阅读说明：本技术 一种浮栅存储器的制备方法和浮栅存储器 (Preparation method of floating gate memory and floating gate memory ) 是由 何永 冯骏 于 2018-08-17 设计创作，主要内容包括：本发明公开了一种浮栅存储器的制备方法和浮栅存储器,该制备方法,包括：提供第一制备结构,第一制备结构包括半导体衬底、设置于半导体衬底一侧的隧穿氧化层、设置于隧穿氧化层远离半导体衬底一侧的第一多晶硅层和多个填充有第一氧化物的第一沟槽,第一多晶硅层被第一沟槽分隔成多段第一子多晶硅层,第一氧化物与第一多晶硅层齐平；刻蚀掉部分第一多晶硅层,以凸出第一氧化物；在第一氧化物及剩余的第一多晶硅层暴露出的表面形成氮化硅层；采用自对准工艺在第一子多晶硅层中形成第二凹槽,使得第一多晶硅层的表面积增大,增加浮栅存储器的耦合率,提高擦写速度；并且,使得第一子多晶硅层中第二凹槽具有较高的一致性,并且降低制造成本。(The invention discloses a preparation method of a floating gate memory and the floating gate memory, wherein the preparation method comprises the following steps: providing a first preparation structure, wherein the first preparation structure comprises a semiconductor substrate, a tunneling oxide layer arranged on one side of the semiconductor substrate, a first polycrystalline silicon layer arranged on one side of the tunneling oxide layer far away from the semiconductor substrate and a plurality of first grooves filled with first oxides, the first polycrystalline silicon layer is divided into a plurality of sections of first sub-polycrystalline silicon layers by the first grooves, and the first oxides are flush with the first polycrystalline silicon layer; etching off part of the first polysilicon layer to protrude the first oxide; forming a silicon nitride layer on the exposed surfaces of the first oxide and the residual first polysilicon layer; forming a second groove in the first sub-polysilicon layer by adopting a self-alignment process, so that the surface area of the first polysilicon layer is increased, the coupling rate of the floating gate memory is increased, and the erasing speed is improved; and the second groove in the first sub-polysilicon layer has higher consistency and the manufacturing cost is reduced.)

1. A preparation method of a floating gate memory is characterized by comprising the following steps:

providing a first preparation structure, wherein the first preparation structure comprises a semiconductor substrate, a tunneling oxide layer arranged on one side of the semiconductor substrate, a first polycrystalline silicon layer arranged on one side of the tunneling oxide layer far away from the semiconductor substrate, and a plurality of first grooves filled with first oxides, the first polycrystalline silicon layer is divided into a plurality of sections of first sub-polycrystalline silicon layers by the first grooves, the first oxides are flush with the first polycrystalline silicon layer, and the depth of each first groove is greater than the thickness of the first polycrystalline silicon layer;

etching off part of the first polysilicon layer to protrude the first oxide;

forming a silicon nitride layer on the exposed surfaces of the first oxide and the rest first polycrystalline silicon layer, wherein the part of the silicon nitride layer positioned on the first sub-polycrystalline silicon layer is provided with a first groove;

and forming a second groove in the first sub-polysilicon layer by adopting a self-alignment process, wherein the second groove is positioned right below the first groove.

2. The method for manufacturing a floating gate memory according to claim 1, wherein forming a second recess in the first sub-polysilicon layer by a self-aligned process comprises:

etching the silicon nitride layer until the part of the silicon nitride layer, which is positioned at the bottom of the first groove, is etched;

and etching the exposed first sub-polysilicon layer by using the rest of the silicon nitride layer or the first oxide and the rest of the silicon nitride layer as masks to form the second groove.

3. The method for manufacturing a floating gate memory according to claim 2, further comprising, after forming a second recess in the first sub-polysilicon layer by a self-aligned process:

removing the residual silicon nitride layer;

etching the first oxide to enable the first oxide to be flush with the tunneling oxide layer;

depositing a gate dielectric film layer on the second surface formed by the first polycrystalline silicon layer and the first oxide;

a second polysilicon layer is deposited over the gate dielectric film layer.

4. The method of manufacturing a floating gate memory according to claim 1, wherein the first trenches are equally spaced.

5. The method of manufacturing a floating gate memory according to claim 1, wherein the method of manufacturing the first manufacturing structure comprises:

forming a semiconductor substrate, a sacrificial oxide layer and a sacrificial silicon nitride layer which are sequentially stacked;

photoetching and etching the sacrificial silicon nitride layer to expose the sacrificial oxide layer at multiple positions of the sacrificial silicon nitride layer;

etching the exposed sacrificial oxide layer and the semiconductor substrate corresponding to the sacrificial oxide layer to enable the semiconductor substrate, the first oxide layer and the sacrificial silicon nitride layer to form a first groove;

filling the first oxide in the first trench so that the first oxide covers the sacrificial silicon nitride layer;

planarizing the first oxide to make the first oxide flush with the sacrificial silicon nitride layer;

removing the sacrificial silicon nitride layer and the sacrificial oxide layer;

depositing a tunneling oxide layer on the surface of the exposed semiconductor substrate;

depositing the first polysilicon layer over the tunneling oxide layer such that the first polysilicon layer covers the first oxide;

and carrying out planarization treatment on the first polysilicon layer to enable the first polysilicon layer to be flush with the first oxide.

6. The method of claim 5, wherein the step of performing photolithography and etching on the sacrificial silicon nitride layer is performed by a hard mask etching process when the sacrificial oxide layer is exposed at a plurality of positions of the sacrificial silicon nitride layer.

7. The method of claim 5, wherein the planarization of the first oxide is performed such that the first oxide is flush with the sacrificial silicon nitride layer using a chemical mechanical polishing process.

8. A floating gate memory, characterized by being prepared by the preparation method of any one of claims 1 to 7.

Technical Field

The embodiment of the invention relates to the technical field of semiconductor devices, in particular to a floating gate memory and a preparation method thereof.

Background

Semiconductor memories are widely used in various electronic products. The floating gate memory is used widely as an important structure of a flash memory device for storing data.

The floating gate type memory generally includes a semiconductor substrate, a tunnel oxide film, a floating gate, a gate dielectric film, and a control gate, which are stacked in this order from bottom to top. The gate dielectric film is usually formed of an ONO film, and in order to improve the coupling ratio of the device, the contact area between the floating gate and the control gate is increased, thereby increasing the capacitance of the ONO layer. The conventional method for increasing the capacitance of the ONO layer is to directly etch the floating gate, form a groove on the floating gate and then deposit the ONO layer.

However, the above method for fabricating the floating gate memory is likely to cause the consistency of the plurality of grooves formed on the floating gate to be poor, and a precise mask plate is required when the floating gate is etched, thereby increasing the fabrication cost.

Disclosure of Invention

The invention provides a preparation method of a floating gate memory and the floating gate memory, aiming at improving the consistency of a plurality of grooves on a floating gate and reducing the preparation cost on the premise of improving the coupling ratio of the floating gate memory.

In a first aspect, an embodiment of the present invention provides a method for manufacturing a floating gate memory, including:

providing a first preparation structure, wherein the first preparation structure comprises a semiconductor substrate, a tunneling oxide layer arranged on one side of the semiconductor substrate, a first polycrystalline silicon layer arranged on one side of the tunneling oxide layer far away from the semiconductor substrate and a plurality of first grooves filled with first oxides, the first polycrystalline silicon layer is divided into a plurality of sections of first sub-polycrystalline silicon layers by the first grooves, the first oxides are flush with the first polycrystalline silicon layer, and the depth of each first groove is greater than the thickness of the first polycrystalline silicon layer;

etching off part of the first polysilicon layer to protrude the first oxide;

forming a silicon nitride layer on the exposed surfaces of the first oxide and the rest first polycrystalline silicon layer, wherein the part of the silicon nitride layer positioned on the first sub-polycrystalline silicon layer is provided with a first groove;

and forming a second groove in the first sub-polysilicon layer by adopting a self-alignment process, wherein the second groove is positioned right below the first groove.

Wherein, the second groove is formed in the first sub-polysilicon layer by adopting a self-alignment process, which comprises the following steps:

etching the silicon nitride layer until the part of the silicon nitride layer, which is positioned at the bottom of the first groove, is etched;

and etching the exposed first sub-polysilicon layer by using the rest silicon nitride layer or the first oxide and the rest silicon nitride layer as masks to form a second groove.

After forming the second groove in the first sub-polysilicon layer by using a self-aligned process, the method further includes:

removing the residual silicon nitride layer;

etching the first oxide to make the first oxide flush with the tunneling oxide layer;

depositing a gate dielectric film layer on the second surface formed by the first polycrystalline silicon layer and the first oxide;

a second polysilicon layer is deposited over the gate dielectric film layer.

Wherein, the intervals between the first grooves are equal.

The manufacturing method of the first preparation structure comprises the following steps:

forming a semiconductor substrate, a sacrificial oxide layer and a sacrificial silicon nitride layer which are sequentially stacked;

photoetching and etching the sacrificial silicon nitride layer to expose the sacrificial oxide layer at multiple positions of the sacrificial silicon nitride layer;

etching the exposed sacrificial oxide layer and the semiconductor substrate corresponding to the sacrificial oxide layer to enable the semiconductor substrate, the first oxide layer and the sacrificial silicon nitride layer to form a first groove;

filling a first oxide in the first trench so that the first oxide covers the sacrificial silicon nitride layer;

carrying out planarization treatment on the first oxide so that the first oxide is flush with the sacrificial silicon nitride layer;

removing the sacrificial silicon nitride layer and the sacrificial oxide layer;

depositing a tunneling oxide layer on the surface of the exposed semiconductor substrate;

depositing a first polysilicon layer above the tunneling oxide layer to cover the first oxide layer;

and carrying out planarization treatment on the first polysilicon layer to enable the first polysilicon layer to be flush with the first oxide.

And photoetching and etching the sacrificial silicon nitride layer to expose the sacrificial oxide layer at multiple positions of the sacrificial silicon nitride layer by using a hard mask etching process.

Wherein the first oxide is planarized such that the first oxide is level with the sacrificial silicon nitride layer using a chemical mechanical polishing process.

In a second aspect, an embodiment of the present invention further provides a floating gate memory, where the floating gate memory is prepared by using the floating gate memory preparation method provided in the first aspect.

The invention provides a first preparation structure, which comprises a semiconductor substrate, a tunneling oxide layer arranged on one side of the semiconductor substrate, a first polycrystalline silicon layer arranged on one side of the tunneling oxide layer far away from the semiconductor substrate and a plurality of first grooves filled with first oxides, wherein the first polycrystalline silicon layer is divided into a plurality of sections of first sub-polycrystalline silicon layers by the first grooves, and the first oxides are flush with the first polycrystalline silicon layer; projecting the first oxide by etching away a portion of the first polysilicon layer; forming a silicon nitride layer on the exposed surfaces of the first oxide and the rest first polycrystalline silicon layer, wherein the part of the silicon nitride layer positioned on the first sub-polycrystalline silicon layer is provided with a first groove; and forming a second groove in the first sub-polysilicon layer under the first groove by using a self-alignment process, so that the surface area of the first polysilicon layer is increased, and when the first polysilicon layer is used as a floating gate, the coupling rate of the floating gate memory can be increased, and the erasing speed is increased; and the second groove positioned right below the first groove is formed in the first sub-polysilicon layer through a self-alignment process, so that the second groove in the first sub-polysilicon layer has higher consistency, and the manufacturing cost is reduced.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a floating gate memory according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a first preparation structure provided in an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a first fabricated structure in which a portion of the first polysilicon layer is etched away according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram illustrating a silicon nitride layer formed on the exposed surface of the first oxide and the remaining first polysilicon layer according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of the first sub-polysilicon layer after forming a second groove therein according to an embodiment of the present invention.

Fig. 6 is a schematic structural diagram illustrating a portion of a silicon nitride layer at the bottom of a first trench after being etched away according to an embodiment of the present invention.

Fig. 7 is a schematic structural diagram illustrating a structure of etching the exposed first sub-polysilicon layer with the remaining silicon nitride layer or the first oxide and the remaining silicon nitride layer as masks to form a second groove according to an embodiment of the present invention.

Fig. 8 is a schematic structural diagram of the structure after removing the remaining silicon nitride according to the embodiment of the present invention.

Fig. 9 is a schematic diagram of a structure in which the first oxide is flush with the tunnel oxide layer after the first oxide is etched away according to an embodiment of the present invention.

Fig. 10 is a schematic structural diagram of a gate dielectric film deposited on the second surface of the first polysilicon layer and the first oxide layer according to the embodiment of the present invention.

Fig. 11 is a schematic structural view of a second polysilicon layer deposited over the gate dielectric film layer according to an embodiment of the present invention.

FIG. 12 is a flow chart for preparing a first preparation structure provided by an embodiment of the present invention.

Fig. 13 to 20 are schematic structural views of a first preparation structure provided in an embodiment of the present invention in each step.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a flowchart of a method for manufacturing a floating gate memory according to an embodiment of the present invention, where the method for manufacturing a floating gate memory includes:

step 110, as shown in fig. 2, providing a first preparation structure, where the first preparation structure includes a semiconductor substrate 10, a tunneling oxide layer 20 disposed on one side of the semiconductor substrate 10, a first polysilicon layer 30 disposed on one side of the tunneling oxide layer 20 away from the semiconductor substrate 10, and a plurality of first trenches 40 filled with first oxides 50, the first polysilicon layer 30 is divided into a plurality of first sub-polysilicon layers 31 by the first trenches 40, the first oxides 50 are flush with the first polysilicon layer 30, and the depth of the first trenches 40 is greater than the thickness of the first polysilicon layer 30;

fig. 2 is a schematic structural diagram of a first preparation structure provided in an embodiment of the present invention. Referring to fig. 2, alternatively, when forming a floating gate memory, the first polysilicon layer 30 may be a floating gate of the floating gate memory. Specifically, the programming and erasing rates of floating gate storage depend mainly on the coupling ratio, i.e., the ratio of the capacitance between the semiconductor substrate 10 and the floating gate to the capacitance between the floating gate and the control gate, which is too high and the faster the programming and erasing speeds.

Step 120, as shown in fig. 3, etching away a portion of the first polysilicon layer 30 to protrude the first oxide 50;

fig. 3 is a schematic structural diagram of a first fabricated structure in which a portion of the first polysilicon layer is etched away according to an embodiment of the present invention. Referring to fig. 3, the first polysilicon layer 30 may be etched by a small amount, and the etched height of each first sub-polysilicon layer 31 is equal, so that the shapes of the grooves formed in the first sub-polysilicon layers 31 may be more consistent.

Step 130, as shown in fig. 4, forming a silicon nitride layer 60 on the exposed surface of the first oxide 50 and the remaining first polysilicon layer 30, wherein a portion of the silicon nitride layer 60 located on the first sub-polysilicon layer 31 has a first groove 61;

fig. 4 is a schematic structural diagram illustrating a silicon nitride layer formed on the exposed surface of the first oxide and the remaining first polysilicon layer according to an embodiment of the present invention. Referring to fig. 4, the silicon nitride layer 60 is uniformly formed on the exposed surfaces of the first oxide 50 and the remaining first polysilicon layer 30, and since a portion of the first polysilicon layer 30 is etched in step 120, the first oxide 50 protrudes relative to the first polysilicon layer 30, so that the silicon nitride layer 60 forms a first groove 61 on the portion of the first sub-polysilicon layer 31.

In step 140, as shown in fig. 5, a self-aligned process is used to form a second recess 32 in the first sub-polysilicon layer 31, wherein the second recess 32 is located right below the first recess 61.

Fig. 5 is a schematic structural diagram of the first sub-polysilicon layer after forming a second groove therein according to an embodiment of the present invention. Referring to fig. 5, after forming the second groove 32 in the first sub-polysilicon layer 31 by using a self-aligned process, the surface area of the surface of the first polysilicon layer 30 on the side away from the semiconductor substrate 10 is increased, while the surface area of the surface of the first polysilicon layer 30 on the side close to the semiconductor substrate 10 is unchanged. When the first polysilicon layer 30 is used as the floating gate of the floating gate memory, the control gate and the floating gate are usually disposed on the surface of the floating gate away from the semiconductor, and the gate dielectric film 70 is disposed between the control gate and the floating gate, so that the surface area of the gate dielectric film 70 is increased, the capacitance between the control gate and the floating gate is increased, and the capacitance between the floating gate and the semiconductor substrate 10 is not changed, thereby increasing the coupling ratio and further increasing the erasing speed of the floating gate memory.

In addition, the self-alignment process is a technology for realizing the automatic alignment of the optical copy printing by using the structural characteristics of elements and devices in the microelectronic technology, the second grooves 32 which are positioned under the first grooves 61 are directly formed in the first sub-polysilicon layer 31 by adopting the process, so that the consistency of the plurality of second grooves 32 is higher, and when the second grooves 32 are formed, no mask plate is needed, the cost for manufacturing the mask plate is saved, and the cost for preparing the floating gate memory is reduced.

Optionally, forming the second groove 32 in the first sub-polysilicon layer 31 by using a self-aligned process includes:

step 141, as shown in fig. 6, etching the silicon nitride layer 60 until the portion of the silicon nitride layer 60 at the bottom of the first groove 61 is etched;

step 142, using the remaining silicon nitride layer 60 or the first oxide 50 and the remaining silicon nitride layer 60 as masks, the exposed first sub-polysilicon layer 31 is etched to form a second groove 32.

Specifically, fig. 6 is a schematic structural diagram illustrating a portion of the silicon nitride layer at the bottom of the first trench after being etched away according to an embodiment of the present invention. Referring to fig. 6, when the silicon nitride layer 60 is etched, the silicon nitride layer 60 can be uniformly etched, and since the silicon nitride layer 60 is uniformly formed on the exposed surfaces of the first oxide 50 and the remaining first polysilicon layer 30, the silicon nitride layer 60 located at the bottom of the first recess 61 is etched, and simultaneously, the silicon nitride located directly above the first oxide 50 and having the same height as the two sidewalls is also etched, that is, after the portion of the silicon nitride layer 60 located at the bottom of the first recess 61 is etched, the silicon nitride is only present on the sidewall portion of the first oxide 50 protruding out of the first polysilicon layer 30, which is specifically referred to fig. 6. There may also be situations where silicon nitride remains over the first oxide 50, not shown in fig. 6.

Then, the remaining silicon nitride layer 60 or the first oxide 50 and the remaining silicon nitride layer 60 are used as masks, the exposed first sub-polysilicon layers 31 are etched, the width of the exposed portion of each first sub-polysilicon layer 31 is equal to that of the corresponding first groove 61, and after etching, a second groove 32 is formed in the exposed portion of each first sub-polysilicon layer 31. Fig. 7 is a schematic structural diagram illustrating a structure of etching the exposed first sub-polysilicon layer with the remaining silicon nitride layer or the first oxide and the remaining silicon nitride layer as masks to form a second groove according to an embodiment of the present invention. If the widths of the first grooves 61 are controlled to be equal when the silicon nitride layer 60 is formed, the widths of the second grooves 32 are also controlled to be equal, so that the second grooves 32 have good shapes and high uniformity. By etching away the portion of the silicon nitride layer 60 located at the bottom of the first groove 61 and etching the first sub-polysilicon layer 31 by using the remaining silicon nitride layer 60 or the first oxide 50 and the remaining silicon nitride layer 60 as masks, a precise mask is not required to be manufactured, and the manufacturing cost of the floating gate memory is saved.

Alternatively, the first trenches 40 are equally spaced.

Specifically, by setting the equal intervals between the first trenches 40, the widths of the first grooves 61 of the silicon nitride layer 60 at the corresponding portions of each sub-polysilicon layer are equal when the silicon oxide layer is formed, and further, the widths of the second grooves 32 are equal when the second grooves 32 are formed in the step 142, so that the second grooves 32 in each first sub-polysilicon layer 31 have higher consistency.

Optionally, after forming the second groove 32 in the first sub-polysilicon layer 31 by using a self-aligned process, the method further includes:

step 150, as shown in fig. 8, removing the remaining silicon nitride layer 60;

specifically, fig. 8 is a schematic structural diagram of the structure after removing the remaining silicon nitride according to the embodiment of the present invention. Referring to fig. 8, after the remaining silicon nitride layer 60 is removed, the first oxide 50 is located between the groove walls of two adjacent second grooves 32 and protrudes from the respective second groove walls.

Step 160, as shown in fig. 9, etching the first oxide 50 to make the first oxide 50 flush with the tunneling oxide layer 20; fig. 9 is a schematic structural diagram of the first oxide 50 being flush with the tunnel oxide layer 20 after the first oxide 50 is etched away according to the embodiment of the present invention.

Step 170, as shown in fig. 10, depositing a gate dielectric film layer 70 on the second surface formed by the first polysilicon layer 30 and the first oxide 50; fig. 10 is a schematic structural diagram of a gate dielectric film deposited on the second surface of the first polysilicon layer and the first oxide layer according to the embodiment of the present invention. The gate dielectric film layer 70 is formed of an oxide nitride oxide film, among others.

Step 180, as shown in fig. 11, a second polysilicon layer 80 is deposited over the gate dielectric film layer 70. Fig. 11 is a schematic diagram of a structure after depositing a second polysilicon layer 80 over the gate dielectric film layer 70 according to an embodiment of the present invention.

Fig. 12 is a flowchart of a first preparation structure, and fig. 13 to 20 are schematic views of the first preparation structure provided in the embodiment of the present invention in respective steps. Referring to fig. 12 to 20, a first preparation structure a method of manufacturing a first preparation structure includes:

step 210, as shown in fig. 13, forming a semiconductor substrate 10, a sacrificial oxide layer 100 and a sacrificial silicon nitride layer 200 which are stacked in sequence; coating a photoresist 300 on the sacrificial silicon nitride layer 200;

step 220, as shown in fig. 14, the sacrificial silicon nitride layer 200 is etched and etched, so that the sacrificial oxide layer 100 is exposed at a plurality of positions of the sacrificial silicon nitride layer 200;

step 230, as shown in fig. 15, etching the exposed sacrificial oxide layer 100 and the semiconductor substrate 10 corresponding to the sacrificial oxide layer to form a first trench 40 in the semiconductor substrate 10, the first oxide layer and the sacrificial silicon nitride layer 200;

step 240, as shown in fig. 16, filling the first trench 40 with a first oxide 50, so that the first oxide 50 covers the sacrificial silicon nitride layer 200;

step 250, as shown in fig. 17, performing a planarization process on the first oxide 50 to make the first oxide 50 flush with the sacrificial silicon nitride layer 200;

step 260, as shown in fig. 18, removing the sacrificial silicon nitride layer 200 and the sacrificial oxide layer 100;

step 270, as shown in fig. 19, depositing a tunnel oxide layer 20 on the exposed surface of the semiconductor substrate 10;

step 280, as shown in fig. 20, depositing a first polysilicon layer 30 over the tunnel oxide layer 20, such that the first polysilicon layer 30 covers the first oxide 50;

step 290, performing a planarization process on the first polysilicon layer 30 to make the first polysilicon layer 30 flush with the first oxide 50, so as to obtain the first preparation structure shown in fig. 1.

Optionally, the sacrificial silicon nitride layer 200 is etched by photolithography, so that a hard mask etching process is used when the sacrificial oxide layer 100 is exposed at a plurality of positions of the sacrificial silicon nitride layer 200.

Specifically, the hard mask is mainly used in the multiple photolithography process, and most of the metal and oxide belong to the hard mask. The hard mask has high temperature resistance, hardly deforms along with the change of the etching thickness, and is convenient to remove.

Optionally, the first oxide 50 is planarized to make the first oxide 50 flush with the sacrificial silicon nitride layer 200 using a chemical mechanical polishing process.

Specifically, chemical mechanical polishing is the smoothing of silicon wafers or other substrate materials during processing by chemical etching and mechanical forces, using equipment and consumables that include: the polishing machine comprises a polishing machine, polishing slurry, a polishing pad, cleaning equipment, polishing end point detection and process control equipment, waste treatment and detection equipment and the like. The method is different from the traditional pure mechanical and pure chemical polishing methods, and the chemical mechanical polishing adopts the comprehensive action of chemistry and machinery, so that the defects of surface damage caused by pure mechanical polishing, low polishing speed, poor surface flatness and polishing consistency and the like easily caused by single-purification chemical polishing are avoided. By adopting the chemical mechanical polishing process, the flatness of the polished surfaces of the first oxide 50 and the sacrificial silicon nitride layer 200 is improved, the consistency is better, and the polishing speed is improved.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.