阅读说明：本技术 电压调整方法、存储器控制电路单元以及存储器存储装置 (Voltage adjusting method, memory control circuit unit and memory storage device ) 是由 林纬 许佑诚 郭才豪 陈思玮 欧沥元 林晓宜 于 2018-08-01 设计创作，主要内容包括：本发明提供一种电压调整方法、存储器控制电路单元以及存储器存储装置。所述方法包括：读取第一物理程序化单元组中的第一物理程序化单元以获得第一数据；根据对应第一数据的第一错误检查与校正码对第一数据进行校正以获得第一校正后数据；读取第一物理程序化单元组中的第二物理程序化单元以获得第二数据；根据第一数据、第一校正后数据以及第二数据将用于读取第一存储单元的第一读取电压调整为第二读取电压。(The invention provides a voltage adjusting method, a memory control circuit unit and a memory storage device. The method comprises the following steps: reading a first physical programming unit in the first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting the first reading voltage for reading the first storage unit to be a second reading voltage according to the first data, the first corrected data and the second data.)

1. A voltage adjustment method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of memory cells, the memory cells are arranged at the intersections of a plurality of word lines and a plurality of bit lines, the word lines comprise first word lines, and a plurality of first memory cells in the memory cells on the first word line form a first physical programming cell group, the voltage adjustment method comprises:

reading a first physical programming cell in the first physical programming cell group to obtain first data;

correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data;

reading at least one second physical programming unit in the first physical programming unit group to obtain second data; and

adjusting a first read voltage for reading the plurality of first memory cells to a second read voltage according to the first data, the first corrected data, and the second data.

2. The voltage adjustment method of claim 1, wherein each of the plurality of memory cells has one of a plurality of memory states, wherein adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage based on the first data, the first corrected data, and the second data comprises:

and performing exclusive-or operation on the first data and the first corrected data to obtain third data, wherein the third data has a plurality of bits, and each bit of the plurality of bits corresponds to one of the plurality of first storage units.

3. The voltage adjustment method according to claim 2, wherein the step of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data further comprises:

when at least one first bit in the bits of the third data is a first value and the storage state of at least one second storage unit in the first storage units corresponding to the first bit is a first storage state in the storage state subdistrict, judging that the second storage unit is positioned in a first error interval in the storage state subdistrict; and

when at least one second bit of the bits of the third data is the first value and the storage state of at least one third storage unit of the first storage units corresponding to the second bit is a second storage state of the storage states, determining that the third storage unit is located in a second error interval in the storage state subdivision diagram.

4. The voltage adjustment method of claim 3, wherein in the storage status distribution map, the first storage status is adjacent to the second storage status, the second storage unit located in the first error interval belongs to the second storage status and the second storage unit is identified as the first storage status according to the first read voltage, and

the third memory cell located in the second error interval belongs to the first memory state and is identified as the second memory state according to the first read voltage.

5. The voltage adjustment method of claim 4, wherein adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data further comprises:

calculating a first number of the second memory cells located in the first error interval;

calculating a second number of the third memory cells located in the second error interval;

when the first number is greater than the second number, adjusting the first read voltage to the second read voltage such that the second read voltage is less than the first read voltage; and

when the first number is smaller than the second number, the first reading voltage is adjusted to the second reading voltage so that the second reading voltage is larger than the first reading voltage.

6. The voltage adjustment method of claim 1, wherein after the step of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data, the method further comprises:

recording the second reading voltage; and

when reading the plurality of first memory cells, reading the first memory cells using the second read voltage.

7. The voltage adjustment method of claim 1, the method further comprising:

correcting the second data according to at least one second error check and correction code corresponding to the second data to obtain at least one second corrected data; and

and adjusting a third read voltage for reading the plurality of first memory cells to a fourth read voltage according to the first data, the second data and the second corrected data.

8. A memory control circuit unit for a rewritable and non-volatile memory module, the rewritable and non-volatile memory module comprising a plurality of memory cells, the memory cells being arranged at intersections of a plurality of word lines and a plurality of bit lines, wherein the plurality of word lines include a first word line, and a plurality of first memory cells of the memory cells on the first word line form a first physical programming cell group, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

a memory interface for electrically connecting to the rewritable nonvolatile memory module; and

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit is configured to read a first physical programming cell in the first set of physical programming cells to obtain first data,

wherein the memory management circuit is further configured to correct the first data according to a first error checking and correcting code corresponding to the first data to obtain first corrected data,

wherein the memory management circuit is further configured to read at least one second physical programming unit in the first set of physical programming units to obtain second data,

wherein the memory management circuit is further configured to adjust a first read voltage for reading the plurality of first memory cells to a second read voltage according to the first data, the first corrected data, and the second data.

9. The memory control circuit unit of claim 8, wherein each of the plurality of memory cells has one of a plurality of memory states, wherein in an operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data,

the memory management circuit is further configured to perform exclusive-or operation on the first data and the first corrected data to obtain third data, where the third data has a plurality of bits and each of the plurality of bits corresponds to one of the plurality of first storage units.

10. The memory control circuit unit of claim 9, wherein in an operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data,

when at least one first bit of the bits of the third data is a first value and the storage state of at least one second storage unit of the first storage units corresponding to the first bit is a first storage state of the storage states, the memory management circuit is further configured to determine that the second storage unit is located in a first error interval in the storage state subdivision diagram, and

when at least one second bit of the bits of the third data is the first value and the storage state of at least one third storage unit of the first storage units corresponding to the second bit is a second storage state of the storage states, the memory management circuit is further configured to determine that the third storage unit is located in a second error interval in the storage state subdivision diagram.

11. The memory control circuit unit of claim 10, wherein in the storage state distribution map, the first storage state is adjacent to the second storage state, the second storage cell located in the first error interval belongs to the second storage state and the second storage cell is identified as the first storage state according to the first read voltage, and

the third memory cell located in the second error interval belongs to the first memory state and is identified as the second memory state according to the first read voltage.

12. The memory control circuit unit of claim 11, wherein in an operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data,

the memory management circuit is further configured to calculate a first number of the second memory cells located in the first error interval,

the memory management circuit is further configured to calculate a second number of the third memory cells located in the second error interval,

when the first number is greater than the second number, the memory management circuit is further configured to adjust the first read voltage to the second read voltage such that the second read voltage is less than the first read voltage, an

When the first number is smaller than the second number, the memory management circuit is further configured to adjust the first read voltage to the second read voltage so that the second read voltage is greater than the first read voltage.

13. The memory control circuit unit of claim 8, wherein after the operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data,

the memory management circuit is further configured to record the second read voltage, an

When reading the plurality of first memory cells, the memory management circuit is further configured to read the first memory cells using the second read voltage.

14. The memory control circuit cell of claim 8, wherein

The memory management circuit is further configured to correct the second data according to at least one second error checking and correcting code corresponding to the second data to obtain at least one second corrected data,

the memory management circuit is further configured to adjust a third read voltage for reading the plurality of first memory cells to a fourth read voltage according to the first data, the second data, and the second corrected data.

15. A memory storage device, comprising:

the connection interface unit is used for electrically connecting to a host system;

the memory module comprises a plurality of memory units, wherein the memory units are arranged at the intersections of a plurality of word lines and a plurality of bit lines, the word lines comprise first word lines, and a plurality of first memory units in the memory units on the first word lines form a first physical programming unit group; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for reading a first physical programming unit in the first physical programming unit group to obtain first data,

wherein the memory control circuit unit is further configured to correct the first data according to a first error checking and correcting code corresponding to the first data to obtain first corrected data,

wherein the memory control circuit unit is further configured to read at least one second physical programming unit in the first physical programming unit group to obtain second data,

wherein the memory control circuit unit is further configured to adjust a first read voltage for reading the plurality of first memory cells to a second read voltage according to the first data, the first corrected data, and the second data.

16. The memory storage device of claim 15, wherein each of the plurality of memory cells has one of a plurality of memory states, wherein in an operation to adjust the first read voltage for reading the plurality of first memory cells to the second read voltage based on the first data, the first corrected data, and the second data,

the memory control circuit unit is further configured to perform an exclusive-or operation on the first data and the first corrected data to obtain third data, where the third data has a plurality of bits and each of the plurality of bits corresponds to one of the plurality of first storage units.

17. The memory storage device of claim 16, wherein in operation to adjust the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data,

when at least one first bit of the bits of the third data is a first value and the state of at least one second memory cell of the first memory cells corresponding to the first bit is a first memory state of the memory states, the memory control circuit unit is further configured to determine that the second memory cell is in a first error interval in a memory state subdivision diagram, and

when at least one second bit of the bits of the third data is the first value and the storage state of at least one third storage unit of the first storage units corresponding to the second bit is a second storage state of the storage states, the memory control circuit unit is further configured to determine that the third storage unit is located in a second error interval in the storage state subdivision diagram.

18. The memory storage device of claim 17, wherein in the storage status distribution map, the first storage status is adjacent to the second storage status, the second storage cell located in the first error interval belongs to the second storage status and the second storage cell is identified as the first storage status according to the first read voltage, and

the third memory cell located in the second error interval belongs to the first memory state and is identified as the second memory state according to the first read voltage.

19. The memory storage device of claim 18, wherein in operation to adjust the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data,

the memory control circuit unit is further used for calculating a first number of the second memory cells located in the first error interval,

the memory control circuit unit is further used for calculating a second number of the third memory cells located in the second error interval,

when the first number is greater than the second number, the memory control circuit unit is further configured to adjust the first read voltage to the second read voltage such that the second read voltage is less than the first read voltage, an

When the first number is smaller than the second number, the memory control circuit unit is further configured to adjust the first reading voltage to the second reading voltage so that the second reading voltage is larger than the first reading voltage.

20. The memory storage device of claim 15, wherein after an operation to adjust the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data,

the memory control circuit unit is further configured to record the second read voltage, an

When reading the plurality of first memory cells, the memory control circuit unit is further configured to read the first memory cells using the second read voltage.

21. The memory storage device of claim 15, wherein

The memory control circuit unit is further used for correcting the second data according to at least one second error checking and correcting code corresponding to the second data to obtain at least one second corrected data, an

The memory control circuit unit is further configured to adjust a third read voltage for reading the plurality of first memory cells to a fourth read voltage according to the first data, the second data, and the second corrected data.

Technical Field

The invention relates to a voltage adjusting method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Generally, when data is read from the rewritable nonvolatile memory module by using a read voltage, the memory management circuit can decode the read data to obtain the data to be read. However, when the decoding fails, the memory management circuit performs a re-Read (Retry-Read) mechanism to retrieve another Read voltage, and reads with the another Read voltage to retrieve the Read data and decode the Read data. The memory management circuit 702 performs the decoding operation according to the retrieved verification bits to obtain another decoded data composed of a plurality of decoded bits. The above-mentioned mechanism of retrieving the read voltage and re-reading can be repeatedly executed until the number of times exceeds the preset number of times.

In particular, through the above re-reading mechanism, an optimal read voltage for reading a plurality of memory cells on the same word line can be found, and the optimal read voltage can be used to read data of the plurality of memory cells and successfully decode the data. It is noted, however, that the optimum read voltage for reading memory cells located on one word line may not be suitable for reading memory cells located on another word line. In other words, the optimum read voltage for reading memory cells located on one word line may not be the optimum read voltage for reading memory cells located on another word line. The order of the re-read voltages used in determining the optimal read voltage for reading on one word line may not be suitable for determining the optimal read voltage for reading on another word line. Generally, therefore, the process of determining the optimum read voltage usually results in a reduction in the performance of the memory controller. Therefore, how to quickly find the optimum reading voltage for reading the memory cell is one of the problems to be solved by those skilled in the art.

Disclosure of Invention

The invention provides a voltage adjusting method, a memory control circuit unit and a memory storage device, which can effectively calculate the optimal reading voltage for reading a storage unit for subsequent reading, thereby improving the probability of successful decoding, reducing the times of re-reading and effectively improving the execution efficiency of a memory controller.

The invention provides a voltage adjusting method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of memory cells, the memory cells are arranged at the intersections of a plurality of word lines and a plurality of bit lines, the word lines comprise a first word line, and a plurality of first memory cells in the memory cells on the first word line form a first physical programming cell group, the voltage adjusting method comprises the following steps: reading a first physical programming cell in the first physical programming cell group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading at least one second physical programming unit in the first physical programming unit group to obtain second data; adjusting a first read voltage for reading the first memory cells to a second read voltage according to the first data, the first corrected data, and the second data.

In an embodiment of the invention, wherein each of the plurality of memory cells has one of a plurality of memory states, wherein the step of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data comprises: and performing exclusive-or operation on the first data and the first corrected data to obtain third data, wherein the third data has a plurality of bits, and each bit of the plurality of bits corresponds to one of the plurality of first storage units.

In an embodiment of the present invention, the adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data, and the second data further includes: when at least one first bit in the bits of the third data is a first value and the storage state of at least one second storage unit in the first storage units corresponding to the first bit is a first storage state in the storage state subdistrict, judging that the second storage unit is positioned in a first error interval in the storage state subdistrict; and when at least one second bit of the bits of the third data is the first numerical value and the storage state of at least one third storage unit of the first storage units corresponding to the second bit is a second storage state of the storage states, determining that the third storage unit is located in a second error interval in the storage state subdivision diagram.

In an embodiment of the invention, wherein in the storage status distribution map, the first storage status is adjacent to the second storage status, the second storage unit located in the first error interval belongs to the second storage status and is identified as the first storage status according to the first read voltage, and the third storage unit located in the second error interval belongs to the first storage status and is identified as the second storage status according to the first read voltage.

In an embodiment of the invention, the adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data and the second data further includes: calculating a first number of the second memory cells located in the first error interval; calculating a second number of the third memory cells located in the second error interval; when the first number is greater than the second number, adjusting the first read voltage to the second read voltage such that the second read voltage is less than the first read voltage; and when the first number is smaller than the second number, adjusting the first reading voltage to the second reading voltage so that the second reading voltage is larger than the first reading voltage.

In an embodiment of the invention, after the step of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data and the second data, the method further includes: recording the second reading voltage; and when reading the plurality of first memory cells, reading the first memory cells using the second read voltage.

In an embodiment of the present invention, the method further includes: correcting the second data according to at least one second error check and correction code corresponding to the second data to obtain at least one second corrected data; and adjusting a third read voltage for reading the plurality of first memory cells to a fourth read voltage according to the first data, the second data and the second corrected data.

The invention provides a memory control circuit unit, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of memory units, the memory units are arranged at the intersections of a plurality of word lines and a plurality of bit lines, the word lines comprise first word lines, and a plurality of first memory units in the memory units on the first word lines form a first physical programming unit group. The memory control circuit unit includes: a host interface, a memory interface, and memory management circuitry. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for executing the following operations: reading a first physical programming cell in the first physical programming cell group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading at least one second physical programming unit in the first physical programming unit group to obtain second data; adjusting a first read voltage for reading the plurality of first memory cells to a second read voltage according to the first data, the first corrected data, and the second data.

In an embodiment of the invention, each of the plurality of memory cells has one of a plurality of memory states, wherein in an operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data and the second data, the memory management circuit is further configured to: performing an exclusive-or operation on the first data and the first corrected data to obtain third data, wherein the third data has a plurality of bits and each of the plurality of bits corresponds to one of the plurality of first storage units.

In an embodiment of the invention, in an operation of adjusting the first read voltage for reading the first memory cells to the second read voltage according to the first data, the first corrected data and the second data, when at least one first bit of the bits of the third data is a first value and a storage state of at least one second memory cell of the first memory cells corresponding to the first bit is a first storage state of the storage states, the memory management circuit is further configured to determine that the second memory cell is located in a first error interval in a storage state histogram, and when at least one second bit of the bits of the third data is the first value and a storage state of at least one third memory cell of the first memory cells corresponding to the second bit is a second storage state of the storage states The memory management circuit is further configured to determine that the third memory cell is in a second error interval in the memory status subdivision diagram.

In an embodiment of the invention, wherein in the storage status distribution map, the first storage status is adjacent to the second storage status, the second storage unit located in the first error interval belongs to the second storage status and is identified as the first storage status according to the first read voltage, and the third storage unit located in the second error interval belongs to the first storage status and is identified as the second storage status according to the first read voltage.

In an embodiment of the invention, in an operation of adjusting the first read voltage for reading the first memory cells to the second read voltage according to the first data, the first corrected data and the second data, the memory management circuit is further configured to: calculating a first number of the second memory cells located in the first error interval; calculating a second number of the third memory cells located in the second error interval; when the first number is greater than the second number, adjusting the first read voltage to the second read voltage such that the second read voltage is less than the first read voltage; and when the first number is smaller than the second number, adjusting the first reading voltage to the second reading voltage so that the second reading voltage is larger than the first reading voltage.

In an embodiment of the invention, after the operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data and the second data, the memory management circuit is further configured to: recording the second read voltage, and reading the first memory cells using the second read voltage when reading the plurality of first memory cells.

In an embodiment of the invention, the memory management circuit is further configured to perform the following operations: correcting the second data according to at least one second error check and correction code corresponding to the second data to obtain at least one second corrected data; and adjusting a third read voltage for reading the plurality of first memory cells to a fourth read voltage according to the first data, the second data and the second corrected data.

The invention provides a memory storage device, which comprises a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of memory cells, wherein the memory cells are arranged at the intersections of a plurality of word lines and a plurality of bit lines, the word lines comprise first word lines, and a plurality of first memory cells in the memory cells on the first word lines form a first physical programming unit group. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing the following operations: reading a first physical programming cell in the first physical programming cell group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading at least one second physical programming unit in the first physical programming unit group to obtain second data; adjusting a first read voltage for reading the plurality of first memory cells to a second read voltage according to the first data, the first corrected data, and the second data.

In an embodiment of the invention, each of the plurality of memory cells has one of a plurality of memory states, wherein in an operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data and the second data, the memory control circuit unit is further configured to perform the following operations: and performing exclusive-or operation on the first data and the first corrected data to obtain third data, wherein the third data has a plurality of bits, and each bit of the plurality of bits corresponds to one of the plurality of first storage units.

In an embodiment of the invention, in an operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data and the second data, the memory control circuit unit is further configured to: when at least one first bit in the bits of the third data is a first value and the storage state of at least one second storage unit in the first storage units corresponding to the first bit is a first storage state in the storage states, determining that the second storage unit is located in a first error interval in a storage state subdivision diagram; and when at least one second bit of the bits of the third data is the first numerical value and the storage state of at least one third storage unit of the first storage units corresponding to the second bit is a second storage state of the storage states, determining that the third storage unit is located in a second error interval in the storage state subdivision diagram.

In an embodiment of the invention, wherein in the storage status distribution map, the first storage status is adjacent to the second storage status, the second storage unit located in the first error interval belongs to the second storage status and is identified as the first storage status according to the first read voltage, and the third storage unit located in the second error interval belongs to the first storage status and is identified as the second storage status according to the first read voltage.

In an embodiment of the invention, in an operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data and the second data, the memory control circuit unit is further configured to: calculating a first number of the second memory cells located in the first error interval; calculating a second number of the third memory cells located in the second error interval; when the first number is greater than the second number, adjusting the first read voltage to the second read voltage such that the second read voltage is less than the first read voltage; and when the first number is smaller than the second number, adjusting the first reading voltage to the second reading voltage so that the second reading voltage is larger than the first reading voltage.

In an embodiment of the invention, after the operation of adjusting the first read voltage for reading the plurality of first memory cells to the second read voltage according to the first data, the first corrected data and the second data, the memory control circuit unit is further configured to perform the following operations: recording the second reading voltage; and when reading the plurality of first memory cells, reading the first memory cells using the second read voltage.

In an embodiment of the invention, the memory control circuit unit is further configured to perform the following operations: correcting the second data according to at least one second error check and correction code corresponding to the second data to obtain at least one second corrected data; and adjusting a third read voltage for reading the plurality of first memory cells to a fourth read voltage according to the first data, the second data and the second corrected data.

Based on the above, the voltage adjustment method, the memory control circuit unit and the memory storage device of the invention can efficiently calculate the optimal read voltage for reading the memory cell for subsequent reading, thereby increasing the probability of successful decoding and reducing the number of times of re-reading, and effectively improving the efficiency of the memory management circuit.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment.

FIG. 6 is a schematic diagram of an array of memory cells according to an example embodiment.

FIG. 7 is a graph illustrating a statistical distribution of gate voltages corresponding to write data stored in an array of memory cells, according to an example embodiment.

FIG. 8 is a diagram illustrating reading data from a memory cell according to an example embodiment.

FIG. 9 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment.

FIG. 10 is a diagram illustrating an example of a physically erased cell in accordance with the present example embodiment.

FIG. 11 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Fig. 12 is a diagram illustrating multi-frame coding according to an exemplary embodiment of the present invention.

FIG. 13 is a diagram illustrating a re-read mechanism, according to an example embodiment.

Fig. 14A to 14C are schematic diagrams illustrating adjusting a read voltage according to a first exemplary embodiment of the invention.

FIGS. 15A-15C are schematic diagrams illustrating adjusting a read voltage according to a second exemplary embodiment of the invention.

FIG. 16 is a flowchart illustrating a voltage regulation method according to an example embodiment.

FIG. 17 is a flowchart illustrating a method for adjusting a read voltage according to the number of memory cells in an error window according to an example embodiment.

Description of the reference numerals

10: memory storage device

11: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: main machine board

201: u disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

2202: memory cell array

2204: word line control circuit

2206: bit line control circuit

2208: row decoder

2210: data input/output buffer

2212: control circuit

502. C1-C8: memory cell

504: bit line

506: word line

508: common source line

512: select gate drain transistor

514: selective gate source transistor

LSB: least significant bit

CSB: middle effective bit

MSB: most significant bit

VA, VA1, VB, VC, VD, VE, VF, VG, 1440-1444: read voltage

1301. 1303, 1305, 1307, 1309: physical programming unit group

702: memory management circuit

704: host interface

706: memory interface

708: error checking and correcting circuit

710: buffer memory

712: power management circuit

801(1) -801 (r): position of

820: encoding data

810(0) -810 (E): physical programming unit

1410. 1420: distribution of

1430: region(s)

G1: physical programming unit group

LP 1-LP 2: lower physical programming unit

MP 2: middle physical programming unit

UP 1-UP 2: physical programming unit

LX1, LX 2: exclusive or data

700. 701, a step of: interval(s)

T1, T2: table form

S1601: reading a first physical programming cell in a first physical programming cell group to obtain first data, wherein the first physical programming cell group is composed of a plurality of first memory cells

S1603: correcting the first data according to the first error check and correction code corresponding to the first data to obtain the first corrected data

S1605: reading a second physical programming cell in the first set of physical programming cells to obtain second data

S1607: adjusting a first read voltage for reading the first memory cell to a second read voltage according to the first data, the first corrected data and the second data

S1609: correcting the second data according to the second error check and correction code corresponding to the second data to obtain second corrected data

S1611: adjusting a third read voltage for reading the first memory cell to a fourth read voltage according to the first data, the second data and the second corrected data

S1701: a step of performing exclusive-or operation on the first data and the first corrected data to obtain third data, wherein the third data has a plurality of bits, and each bit of the plurality of bits corresponds to one of the plurality of first storage units

S1703: a step of determining that the second memory cell is located in the first error interval in the memory state subdivision diagram when at least one first bit of a plurality of bits of the third data is a first value and the memory state of at least one second memory cell of the plurality of first memory cells corresponding to the first bit is a first memory state

S1705: a step of determining that the third memory cell is located in the second error interval in the memory state subdivision diagram when at least one second bit of the bits of the third data is the first value and the memory state of at least one third memory cell of the first memory cells corresponding to the second bit is the second memory state

S1707: calculating a first number of second memory cells located in a first error interval

S1709: calculating a second number of third memory cells in a second error interval

S1711: judging whether the first number is larger or smaller than the second number

S1713: when the first number is larger than the second number, adjusting the first reading voltage to a second reading voltage so that the second reading voltage is smaller than the first reading voltage

S1715: when the first number is smaller than the second number, adjusting the first reading voltage to a second reading voltage so that the second reading voltage is larger than the first reading voltage

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy (iBeacon) memory storage device based on various wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-chip package memory devices (eMCP) 342 to electrically connect the memory module directly to the embedded memory device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the present exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed-I interface standard, the Ultra High Speed-II interface standard, the Ultra High Speed (UHS-I) interface standard, the Memory Stick (MS) interface standard, the Multi-Chip Package (Multi-Chip Package) interface standard, the Multimedia Embedded (media) interface standard, the Multimedia Memory Card (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

The memory cells in the rewritable nonvolatile memory module 406 are arranged in an array. The memory cell array is described below as a two-dimensional array. However, it should be noted that the following exemplary embodiment is only an example of the memory cell array, and in other exemplary embodiments, the configuration of the memory cell array may be adjusted to meet practical requirements.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment. FIG. 6 is a schematic diagram of an array of memory cells according to an example embodiment.

Referring to fig. 5 and fig. 6, the rewritable nonvolatile memory module 406 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, a data input/output buffer 2210 and a control circuit 2212.

In the present exemplary embodiment, the memory cell array 2202 may include a plurality of memory cells 502 for storing data, a plurality of Select Gate Drain (SGD) transistors 512 and a plurality of Select Gate Source (SGS) transistors 514, and a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 (fig. 6) connecting the memory cells. The memory cells 502 are arranged in an array (or stacked) at the intersections of bit lines 504 and word lines 506. When a write command or a read command is received from the memory control circuit unit 404, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the row decoder 2208 and the data input/output buffer 2210 to write data into the memory cell array 2202 or read data from the memory cell array 2202, wherein the word line control circuit 2204 controls the voltage applied to the word line 506, the bit line control circuit 2206 controls the voltage applied to the bit line 504, the row decoder 2208 selects the corresponding bit line according to the row address in the command, and the data input/output buffer 2210 is used for temporarily storing the data.

The memory cells in the rewritable nonvolatile memory module 406 store multiple bits (bits) with a change in threshold voltage. Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to the memory cell" or "programming the memory cell". Each memory cell of the memory cell array 2202 has multiple memory states as the threshold voltage changes. And the reading voltage can judge which storage state the memory cell belongs to, thereby obtaining the bit stored by the memory cell.

FIG. 7 is a graph illustrating a statistical distribution of gate voltages corresponding to write data stored in an array of memory cells, according to an example embodiment.

Referring to fig. 7, taking MLC NAND flash as an example, each memory cell has 4 memory states with different threshold voltages, and the memory states represent bits "11", "10", "00" and "01", respectively. In other words, each memory state includes a Least Significant Bit (LSB) and a Most Significant Bit (MSB). In the present exemplary embodiment, the 1 st bit from the left side in the memory states (i.e., "11", "10", "00", and "01") is the LSB, and the 2 nd bit from the left side is the MSB. Thus, in this example embodiment, each memory cell can store 2 bits. It should be understood that the threshold voltages and their corresponding memory states shown in FIG. 7 are only exemplary. In another exemplary embodiment of the present invention, the correspondence between the threshold voltage and the memory state may be arranged in "11", "10", "01" and "00" or other arrangements as the threshold voltage is larger. In addition, in another exemplary embodiment, it is also possible to define that the 1 st bit from the left side is the MSB and the 2 nd bit from the left side is the LSB.

In an example embodiment where a memory cell can store multiple bits (e.g., MLC or TLC NAND flash memory module), physical program cells belonging to the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, in an MLC NAND flash memory module, the Least Significant Bit (LSB) of a cell belongs to the lower physical programming cell, and the Most Significant Bit (MSB) of the cell belongs to the upper physical programming cell. In an example embodiment, the lower physical program unit is also referred to as a fast page (fast page), and the upper physical program unit is also referred to as a slow page (slow page). In addition, in the TLC NAND flash memory module, the Least Significant Bit (LSB) of a cell belongs to the lower physical programming cell, the middle Significant Bit (CSB) of the cell belongs to the middle physical programming cell, and the Most Significant Bit (MSB) of the cell belongs to the upper physical programming cell.

Fig. 8 is a diagram illustrating reading data from a memory cell according to an example embodiment, which is an example of a mlc nand flash memory.

Referring to FIG. 8, a read operation of the memory cells of the memory cell array 2202 is performed by applying read voltages VA-VC to the control gates to identify data stored in the memory cells by the conductive states of the memory cell channels. A verify bit (VA) is used to indicate whether the memory cell channel is turned on when the read voltage VA is applied; the verification bit (VC) is used for indicating whether the memory cell channel is conducted or not when the reading voltage VC is applied; the Verification Bit (VB) is used to indicate whether the memory cell channel is turned on when the read voltage VB is applied. It is assumed herein that the verify bit is "1" indicating that the corresponding memory cell channel is turned on, and the verify bit is "0" indicating that the corresponding memory cell channel is not turned on. As shown in fig. 8, it is possible to determine which memory state the memory cell is in by verifying the bits (VA) to (VC), and to acquire the stored bit.

FIG. 9 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment.

Referring to fig. 9, for an example of a TLC NAND type flash memory, each memory state includes a least significant Bit LSB of a1 st Bit from the left side, a middle significant Bit (CSB) of a 2 nd Bit from the left side, and a most significant Bit MSB of a 3 rd Bit from the left side. In this example, the memory cell has 8 memory states (i.e., "111", "110", "100", "101", "001", "000", "010", and "011") according to different threshold voltages. The bit stored in the memory cell can be identified by applying the read voltages VA-VG to the control gates.

It should be noted that the arrangement order of the 8 storage states in fig. 9 can be determined by the design of the manufacturer, but is not limited to the arrangement manner of the present example.

In addition, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line in FIG. 6 constitute one or more physical programming cells. For example, if the rewritable nonvolatile memory module 406 is an MLCNAND flash memory module, the memory cells at the intersections of the same word line and the bit lines constitute 2 physical program cells, i.e., an upper physical program cell and a lower physical program cell. An upper physical programming unit and a lower physical programming unit can be collectively referred to as a physical programming unit group. In particular, if the data to be read is located in a lower physical program cell of a physical program cell group, the value of each bit in the lower physical program cell can be identified by the read voltage VA in fig. 8. If the data to be read is located in an upper physical programming cell of a physical programming cell group, the reading voltage VB and the reading voltage VC as shown in fig. 8 can be used to identify the value of each bit in the upper physical programming cell.

Alternatively, if the rewritable nonvolatile memory module 406 is a TLC NAND flash memory module, the memory cells at the intersections of the same word line and the bit lines constitute 3 physical program cells, i.e., an upper physical program cell, a middle physical program cell, and a lower physical program cell. An upper physical programming unit, a middle physical programming unit and a lower physical programming unit can be collectively referred to as a physical programming unit group. In particular, if the data to be read is located in a lower physical program cell of a physical program cell group, the value of each bit in the lower physical program cell can be identified by the read voltage VA in fig. 9. If the data to be read is located in one of the physical program cells in a physical program cell group, the read voltage VB and the read voltage VC as shown in fig. 9 can be used to identify the value of each bit in the physical program cell. If the data to be read is located in an upper physical program cell of a physical program cell group, the read voltage VD, the read voltage VE, the read voltage VF, and the read voltage VG shown in fig. 9 can be used to identify the value of each bit in the upper physical program cell.

In the exemplary embodiment, the physical program cell is a minimum cell to be programmed. That is, the physical programming unit is the smallest unit for writing data. For example, a physical program unit is a physical page (page) or a physical fan (sector). If the physical program units are physical pages, the physical program units usually include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, 8, 16, or a greater or lesser number of physical fans may be included in the data bit region, and the size of each physical fan may also be greater or lesser. On the other hand, the physical erase cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, a physical erase unit is a physical block (block).

FIG. 10 is a diagram illustrating an example of a physically erased cell in accordance with the present example embodiment.

Referring to fig. 10, in the present exemplary embodiment, it is assumed that one physical erase cell is composed of a plurality of physical program cell groups, wherein each physical program cell group includes a lower physical program cell, a middle physical program cell and an upper physical program cell composed of a plurality of memory cells arranged on the same word line. For example, in the physically erased cell, the 0 th physically programmed cell belonging to the lower physically programmed cell, the 1 st physically programmed cell belonging to the middle physically programmed cell, and the 2 nd physically programmed cell belonging to the upper physically programmed cell are considered as one physically programmed cell group. Similarly, the 3 rd, 4 th, and 5 th physical programming cells are considered as a physical programming cell group, and so on, other physical programming cells are divided into a plurality of physical programming cell groups according to the same manner.

FIG. 11 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 11, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706 and an error checking and correcting circuit 708.

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to write, read, and erase data during operation of the memory storage device 10. When the operation of the memory management circuit 702 or any circuit element included in the memory control circuit unit 404 is described below, the operation of the memory control circuit unit 404 is equivalently described.

In the exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 702 may also be stored in a program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware form. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 702 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 704 is electrically connected to the memory management circuit 702 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the exemplary embodiment, host interface 704 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 706 is electrically connected to the memory management circuit 702 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written into the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 wants to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The sequences of instructions are generated by, for example, the memory management circuit 702 and transferred to the rewritable non-volatile memory module 406 via the memory interface 706. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 708 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712.

The buffer memory 710 is electrically connected to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is electrically connected to the memory management circuit 702 and is used for controlling the power of the memory storage device 10.

In the exemplary embodiment, the error checking and correcting circuit 708 can perform single-frame (single-frame) coding on data stored in the same physical program unit, or perform multi-frame (multi-frame) coding on data stored in a plurality of physical program units. The single-frame coding and the multi-frame coding may respectively use at least one of coding algorithms such as a low density parity check code (LDPC), a BCH code, a convolutional code (convolutional code), and a turbo code. Alternatively, in an example embodiment, the multi-frame coding may also employ Reed-solomon (RS) codes or exclusive or (XOR) algorithms. In addition, in another exemplary embodiment, more unlisted coding algorithms may be used, and are not described herein. Depending on the encoding algorithm employed, the error checking and correction circuit 708 may encode the data to be protected to produce a corresponding error correction code and/or error check code. For convenience of explanation, the error correction code and/or the error check code generated through encoding will be collectively referred to as encoded data hereinafter.

Fig. 12 is a diagram illustrating multi-frame coding according to an exemplary embodiment of the present invention.

Referring to fig. 12, taking the example of encoding the data stored in the physical programming units 810(0) to 810(E) to generate the corresponding encoded data 820, at least a portion of the data stored in each of the physical programming units 810(0) to 810(E) can be regarded as a frame. In the multi-frame coding, data in the physical programming units 810(0) to 810(E) are coded according to the position of each bit (or byte). For example, bit b at position 801(1)₁₁、b₂₁、…、b_p1Will be encoded as bit b in the encoded data 820_o1Bit b at position 801(2)₁₂、b₂₂、…、b_p2Will be encoded as bit b in the encoded data 820_o2(ii) a By analogy, bit b at position 801(r)_1r、b_2r、…、b_prWill be encoded as bit b in the encoded data 820_or. Thereafter, the data read from the physical programming units 810(0) -810 (E) may be decoded based on the encoded data 820 in an attempt to correct errors that may exist in the read data.

In addition, in another exemplary embodiment of fig. 12, the data for generating the encoded data 820 may also include redundant bits (redundancy bits) corresponding to data bits (data bits) in the data stored in the physical programming units 810(0) -810 (E). Take the data stored in the physical programming unit 810(0) as an example, wherein the redundant bits are generated by performing single frame encoding on the data bits stored in the physical programming unit 810(0), for example. In the exemplary embodiment, it is assumed that when reading the data in the physical programming unit 810(0), the data read from the physical programming unit 810(0) can be decoded by using the redundancy bits (e.g., the single frame coded data) in the physical programming unit 810(0) for error detection and correction. However, when the decoding using the redundancy bits in the physical programming unit 810(0) fails (e.g., the number of bits in error of the data stored in the decoded physical programming unit 810(0) is greater than a threshold), a Retry-Read mechanism may be used to attempt to Read the correct data from the physical programming unit 810 (0). Details about the re-reading mechanism will be described later. When the correct data cannot be Read from the physical programming units 810(0) by the Retry-Read mechanism, the encoded data 820 and the data of the physical programming units 810(1) to 810(E) can be Read, and decoding is performed according to the encoded data 820 and the data of the physical programming units 810(1) to 810(E) to try to correct errors in the data stored in the physical programming units 810 (0). That is, in the exemplary embodiment, when decoding using the encoded data generated by the single-frame encoding fails and reading using the re-Read (Retry-Read) mechanism fails, the encoded data generated by the multi-frame encoding is decoded instead.

In particular, FIG. 13 is a diagram illustrating a re-read mechanism, according to an example embodiment.

Referring to FIG. 13, taking SLC flash memory as an example, the distributions 1410 and 1420 are used to represent the memory states of the first memory cells, and the distributions 1410 and 1420 represent different memory states. The first memory cells may belong to the same physical programming unit or different physical programming units, and the invention is not limited thereto. It is assumed that when a memory cell belongs to distribution 1410, the memory cell stores a bit "1"; when a memory cell belongs to distribution 1420, it stores a bit "0". When the memory management circuit 702 reads a memory cell with the read voltage 1440, the memory management circuit 702 obtains a verify bit indicating whether the memory cell is turned on. It is assumed that the verification bit is "1" when the memory cell is turned on, and is "0" otherwise, but the invention is not limited thereto. If the verification bit is "1", then memory management circuitry 702 determines that the memory cell belongs to distribution 1410, otherwise distribution 1420. However, distribution 1410 and distribution 1420 overlap in region 1430. That is, there should be several memory cells belonging to distribution 1410 but identified as distribution 1420, and several memory cells belonging to distribution 1420 but identified as distribution 1410.

In this example embodiment, when the memory cells are to be read, the memory management circuit 702 selects a predetermined read voltage (e.g., the read voltage 1441) to read the memory cells to obtain the verification bits of the memory cells. The error checking and correcting circuit 708 performs a decoding operation according to the verification bits of the memory cells to generate a plurality of decoded bits, and the decoded bits may be combined into a decoded data (also referred to as a codeword).

If the decoding fails, it indicates that the memory cells store uncorrectable error bits. If the decoding fails, in the re-reading mechanism, the memory management circuit 702 re-obtains another read voltage, and reads the first memory cells by using the another read voltage (e.g., the read voltage 1442) to re-obtain the verification bits of the memory cells. The memory management circuit 702 performs the decoding operation according to the retrieved verification bits to obtain another decoded data composed of a plurality of decoded bits. In an exemplary embodiment, the ECC circuit 708 determines whether the decoded data is a valid codeword according to the syndrome corresponding to the decoded data. If the decoded data is not a valid codeword, the memory management circuit 702 determines that the decoding fails. If the number of times of retrieving the read voltage does not exceed the predetermined number of times, the memory management circuit 702 retrieves another read voltage (e.g., the read voltage 1443) again, and reads the memory cell according to the retrieved read voltage 1443 to retrieve the verification bit and perform the first decoding operation.

In other words, when there are uncorrectable error bits, some of the verification bits of the memory cells are changed by retrieving the read voltage, thereby giving an opportunity to change the decoding result of the decoding operation. Logically, the re-fetching of the read voltage is to flip (flip) bits of a codeword and re-decode the new codeword. In some cases, codewords that cannot be decoded before flipping (with uncorrectable erroneous bits), may be decoded after flipping. Also, in an exemplary embodiment, the memory management circuit 702 attempts to decode several times until the number of attempts exceeds a predetermined number. However, the present invention does not limit the number of times to the preset number.

It is noted that fig. 13 illustrates an SLC flash memory, but the step of retrieving the read voltage may be applied to MLC or TLC flash memory. As shown in FIG. 8, changing the read voltage VA flips the LSB of a cell, while changing the read voltage VB or VC flips the MSB of a cell. Thus, changing the read voltage VA, VB or VC can change one codeword to another. The result of changing the code word is also applicable to the TLC flash memory of fig. 9. The present invention is not limited to SLC, MLC or TLC flash memory.

Through the above re-reading mechanism, an optimal read voltage for reading a plurality of memory cells on the same word line can be found, and the optimal read voltage can be used to read out data of the plurality of memory cells and successfully decode the data. In particular, the optimal read voltage, such as the read voltage 1440 of FIG. 13, is typically such that the number of memory cells belonging to the distribution 1410 but identified as the distribution 1420 in FIG. 13 is the same as the number of memory cells belonging to the distribution 1420 but identified as the distribution 1410. The optimal read voltage for reading the memory cells can be determined when the rewritable non-volatile memory module 406 is idle (or during a background time), and the determined optimal read voltage can be used for reading the rewritable non-volatile memory module 406 later. It is noted, however, that the optimum read voltage for reading memory cells located on one word line may not be suitable for reading memory cells located on another word line. In other words, the optimum read voltage for reading memory cells located on one word line may not be the optimum read voltage for reading memory cells located on another word line. The order of the re-read voltages used in determining the optimal read voltage for reading on one word line may not be suitable for determining the optimal read voltage for reading on another word line. Therefore, generally, the process of determining the optimum read voltage usually results in a reduction in the performance of the memory management circuit 702.

Based on the above, the voltage adjustment method provided by the present invention can efficiently calculate the optimal read voltage for reading the memory cell for subsequent reading, thereby increasing the probability of successful decoding and reducing the number of re-reading, and effectively improving the performance of the memory management circuit 702.

The voltage adjustment method proposed by the present invention is described in several embodiments below.

[ first embodiment ]

The first exemplary embodiment is described by taking an MLC NAND type flash memory module as an example. Similar to FIG. 8, each memory cell has 4 memory states with different threshold voltages, and these memory states represent "11", "10", "00" and "01", respectively. In fig. 8, the memory management circuit 702 uses the read voltage VA to distinguish between the memory states "10" and "00". The exemplary embodiments of fig. 14A-14C are mainly used for adjusting the read voltage VA to an optimal read voltage. However, the invention is not limited thereto, and in other embodiments, the same method can be applied to adjust the read voltage VB and the read voltage VC in fig. 8 to the optimal read voltage.

Fig. 14A to 14C are schematic diagrams illustrating adjusting a read voltage according to a first exemplary embodiment of the invention.

Referring to FIG. 14A and FIG. 14B, assume that the rewritable nonvolatile memory module 406 has a physical programming cell group G1, as shown in Table T1 in FIG. 14A. The physical programming cell group G1 (also called the first physical programming cell group) has a lower physical programming cell LP1 and an upper physical programming cell UP 1. The physical programming cell group G1 is composed of memory cells C1-C8 (also referred to as first memory cells) located on the same word line (also referred to as a first word line). The LSBs of the memory cells C1-C8 may constitute a lower physical program cell LP1, and the MSBs of the memory cells C1-C8 may constitute an upper physical program cell UP 1.

In the present exemplary embodiment, the memory management circuit 702 first reads the lower physical program cell LP1 (also referred to as the first physical program cell) of the physical program cell group G1 to obtain a first data. As shown in the table T1, the value of the first data read from the lower physical program unit LP1 is, for example, "11100000".

The memory management circuit 702 can correct the first data according to an error checking and correcting code (also referred to as a first error checking and correcting code) corresponding to the first data to obtain first corrected data (not shown). The value of the first corrected data is, for example, "01010111". It should be noted that the first error checking and correcting code is, for example, encoded data generated by single-frame encoding of the lower physical program unit LP 1.

In addition, the memory management circuit 702 reads the upper physical program unit UP1 (also called the second physical program unit) of the physical program unit group G1 to obtain a second data. As shown in Table T1, the value of the second data read from the upper physical programming unit UP1 is, for example, "00100010". Then, the memory management circuit 702 adjusts the read voltage VA (also referred to as a first read voltage) for reading the memory cells C1-C8 to a read voltage VA1 (also referred to as a second read voltage) according to the first data, the first corrected data and the second data. In particular, in the present exemplary embodiment, the adjusted read voltage VA1 is the optimal read voltage for distinguishing between the memory states "10" and "00".

In more detail, in the process of adjusting the read voltage VA to the read voltage VA1, first, the memory management circuit 702 performs an exclusive or (XOR) operation on the first data and the first corrected data to obtain exclusive or data LX1 (also referred to as third data). The exclusive or data LX1 has a value of "10110111", for example, as shown in table T1. Specifically, the exclusive-or data LX1 has 8 bits and each bit corresponds to a memory cell. For example, the 1 st bit of the exclusive OR data LX1 corresponds to the memory cell C1, and the memory cell C1 currently has a memory state of "10"; the 2 nd bit of the XOR data LX1 corresponds to the memory cell C2, and the memory cell C2 currently has a memory state of "10"; the 3 rd bit of the XOR data LX1 corresponds to the memory cell C3, the current memory state of the memory cell C3 is "11", and so on.

In the exclusive-or data LX1, when a bit has a value of "1", the cell corresponding to the bit is in an error interval in the memory status subdivision diagram. More specifically, referring to fig. 14A and 14B, taking the 1 st bit of the exclusive or data LX1 as an example, since the value of the 1 st bit of the exclusive or data LX1 is "1", it indicates that the memory cell C1 actually belongs to the error interval 701 (also referred to as the first error interval) in fig. 14B. The memory cell C1 in the error region 701 belongs to the memory state "00" (also referred to as the second memory state), but the memory cell C1 is identified as the memory state "10" (also referred to as the first memory state) according to the read voltage VA. For another example, taking the 4 th, 6 th, and 8 th bits of the exclusive or data LX1 as an example, the 4 th, 6 th, and 8 th bits of the exclusive or data LX1 have a value of "1", so that the representative memory cell C4, the representative memory cell C6, and the representative memory cell C8 belong to the error interval 700 (also referred to as the second error interval) in fig. 14B. The memory cell C4, the memory cell C6 and the memory cell C8 in the error region 701 actually belong to the memory state "10", but the memory cell C4, the memory cell C6 and the memory cell C8 are identified as the memory state "00" according to the read voltage VA. Herein, the memory cell C1 may be referred to as a "second memory cell", and the memory cells C4, C6 and C8 may be collectively referred to as a "third memory cell".

In addition, since the values of the 2 nd and 5 th bits of the exclusive or data LX1 are "0", it means that the memory cell C2 and the memory cell C5 are not in the error interval. That is, the memory states of the memory cells not in the error interval are correctly recognized according to the read voltage. Since the value of the 3 rd bit of the exclusive OR data LX1 is "1", the representative memory cell C3 belongs to one of the error intervals in the memory status distribution diagram shown in FIG. 8.

Taking the example of adjusting the read voltage VA for distinguishing the memory states "10" and "00" to the optimal read voltage VA1, the memory management circuit 702 first calculates the number of the second memory cells (also referred to as the first number) in the error interval 701. Here, since the second memory cell includes the memory cell C1, the first number is "1".

The memory management circuit 702 also counts the number of the third memory cells (also referred to as a second number) in the error interval 700. Here, since the third memory cell includes the memory cell C4, the memory cell C6, and the memory cell C8, the second number is "3".

Then, the memory management circuit 702 adjusts the read voltage VA to the read voltage VA1 according to the aforementioned first and second quantities. In more detail, in the exemplary embodiments of fig. 14A and 14B, the first number (value "1") is smaller than the second number (value "3"), and the first number can be regarded as the area of the error interval 701 and the second number as the area of the error interval 700 in view of the memory status distribution diagram of fig. 14B. The memory management circuit 702 adjusts the read voltage VA to the read voltage VA1 according to the first number and the second number (or the areas of the error intervals 701 and 700), so that the read voltage VA1 is greater than the read voltage VA. The read voltage VA1 may be X volts from the read voltage VA. In particular, when the memory management circuit 702 then reads the memory cells C1-C8 using the read voltage VA1, the number of memory cells (e.g., "2") in the error window 701 is the same as the number of memory cells (e.g., "2") in the error window 700. In other words, if a read voltage is between two error intervals, the read voltage is the optimal read voltage if the number of memory cells in the two error intervals is the same when the read voltage is used to read the memory cells, and the data read by using the optimal read voltage has a higher probability of successful decoding.

It should be noted that the magnitude of the read voltage adjustment (i.e., the aforementioned X volts) is determined according to the ratio of the first number and the second number. For example, the memory management circuit 702 may store in advance a look-up table of a plurality of ratios of the first number and the second number and the magnitudes of read voltage adjustments corresponding to the ratios, for example. When the memory management circuit obtains the first amount and the second amount by using the read voltage VA, the adjustment magnitude of the read voltage (i.e., the aforementioned X volts) can be known by the aforementioned lookup table. In the present exemplary embodiment, the reading voltage VA may be adjusted to the reading voltage VA1 larger than the reading voltage VA by looking up the table when the first number is smaller than the second number; and when the first number is greater than the second number, the read voltage VA may be adjusted to a read voltage VA1 that is less than the read voltage VA.

However, the present invention is not limited thereto, and in other embodiments, the memory management circuit 702 may not use the lookup table, but directly adjust the read voltage VA to another read voltage VA1 larger than the read voltage VA when the first number is smaller than the second number; and directly adjusting the read voltage VA to another read voltage VA1 smaller than the read voltage VA when the first number is greater than the second number.

In addition, fig. 14C illustrates a case when the first number is larger than the second number, as another example.

In detail, referring to fig. 14C, if the first number (for example, the value is "3") calculated in the above manner is greater than the second number (for example, the value is "1"), the area of the error interval 701 is greater than the area of the error interval 700 as seen from the storage status distribution diagram of fig. 14C. The memory management circuit 702 adjusts the read voltage VA to the read voltage VA1 according to the first number and the second number (or the areas of the error intervals 701 and 700), so that the read voltage VA1 is smaller than the read voltage VA. The read voltage VA1 may be X volts from the read voltage VA. In particular, when the memory management circuit 702 then reads the memory cells C1-C8 using the read voltage VA1, the number of memory cells (e.g., "2") in the error window 701 is the same as the number of memory cells (e.g., "2") in the error window 700.

After determining the optimal read voltage VA1, the memory management circuit 702 can record the read voltage VA1, and then when the memory management circuit 702 is to read the memory cells C1-C8, the memory management circuit 702 can read the memory cells C1-C8 using the read voltage VA1 instead of using the read voltage VA to identify the memory states "10" and "00".

In particular, although the foregoing example is for adjusting the read voltage VA as in FIG. 8. However, the invention is not limited thereto, and in other embodiments, the memory management circuit 702 can also adjust the read voltage for distinguishing the memory states "11" and "10" from an optimal read voltage, or adjust the read voltage for distinguishing the memory states "00" and "01" from an optimal read voltage. For example, similar to the example of fig. 14A to 14C, the memory management circuit 702 may correct the second data according to the second error checking and correcting code (not shown) corresponding to the second data of the physical programming unit UP1 to obtain second corrected data (not shown). Then, the memory management circuit 702 adjusts the read voltage VB or the read voltage VC (collectively referred to as the third read voltage) for reading the memory cells C1-C8 in fig. 8 to the optimal read voltage (referred to as the fourth read voltage) according to the first data, the second data and the second corrected data. After determining the fourth read voltage, the memory management circuit 702 can record the fourth read voltage, and then when the memory management circuit 702 is to read the memory cells C1-C8, the memory management circuit 702 can use the fourth read voltage to read the memory cells C1-C8 so as to identify the memory states "11" and "10" (or the memory states "00" and "01").

[ second embodiment ]

The second exemplary embodiment is described by taking a TLC NAND type flash memory module as an example. Similar to fig. 9, each memory cell has 8 memory states with different threshold voltages, and these memory states represent "111", "110", "100", "101", "001", "000", "010", and "011", respectively. In fig. 9, the memory management circuit 702 uses the read voltage VA to distinguish between the memory states "101" and "001". The exemplary embodiments of fig. 15A-15C are mainly used to adjust the read voltage VA to an optimal read voltage. However, the invention is not limited thereto, and in other embodiments, the same method can be applied to adjust the read voltages VB through VG of fig. 9 to the optimal read voltages, respectively.

FIGS. 15A-15C are schematic diagrams illustrating adjusting a read voltage according to a second exemplary embodiment of the invention.

Referring to FIG. 15A and FIG. 15B, assume that the rewritable nonvolatile memory module 406 has a physical programming cell group G2, as shown in Table T2 in FIG. 15A. The physical programming cell group G2 (also called the first physical programming cell group) has a lower physical programming cell LP2, a middle physical programming cell MP2 and an upper physical programming cell UP 2. The physical programming cell group G2 is composed of memory cells C1-C8 (also referred to as first memory cells) located on the same word line (also referred to as a first word line). The LSBs of the memory cells C1-C8 may constitute a lower physical program cell LP2, the CSBs of the memory cells C1-C8 may constitute a middle physical program cell MP2, and the MSBs of the memory cells C1-C8 may constitute an upper physical program cell UP 2.

In the present exemplary embodiment, the memory management circuit 702 first reads the lower physical program cell LP2 (also referred to as the first physical program cell) of the physical program cell group G2 to obtain a first data. As shown in Table T2, the first data read from the lower physical program cell LP2 has a value of "11101000", for example.

The memory management circuit 702 can correct the first data according to an error checking and correcting code (also referred to as a first error checking and correcting code) corresponding to the first data to obtain first corrected data (not shown). The value of the first corrected data is, for example, "01011111". It should be noted that the first error checking and correcting code is, for example, encoded data generated by single-frame encoding of the lower physical program unit LP 2.

In addition, the memory management circuit 702 reads the middle physical program cell MP2 and the upper physical program cell UP2 (collectively, the second physical program cells) of the physical program cell group G1 to obtain the second data stored in the physical program cells. As shown in the table T2, the data read from the middle physical program unit MP2 has a value of "00100000", and the data read from the upper physical program unit UP2 has a value of "10011101", for example. Then, the memory management circuit 702 adjusts the read voltage VA (also referred to as a first read voltage) for reading the memory cells C1-C8 to a read voltage VA1 (also referred to as a second read voltage) according to the first data, the first corrected data and the second data. In particular, in the present exemplary embodiment, the adjusted read voltage VA1 is the optimal read voltage for distinguishing between the memory states "101" and "001".

In more detail, in the process of adjusting the read voltage VA to the read voltage VA1, first, the memory management circuit 702 performs an exclusive or (XOR) operation on the first data and the first corrected data to obtain exclusive or data LX2 (also referred to as third data). The exclusive or data LX2 has a value of "10110111", for example, as shown in table T2.

In the exclusive-or data LX2, when a bit has a value of "1", the cell corresponding to the bit is in an error interval in the memory status subdivision diagram. More specifically, referring to fig. 15A and fig. 15B, taking the 1 st bit of the exclusive or data LX2 as an example, since the value of the 1 st bit of the exclusive or data LX2 is "1", it indicates that the memory cell C1 actually belongs to the error interval 701 (also referred to as the first error interval) in fig. 15B. The memory cell C1 in the error region 701 belongs to the memory state "001" (also referred to as the second memory state), but the memory cell C1 is identified as the memory state "101" (also referred to as the first memory state) according to the read voltage VA. For another example, taking the 4 th, 6 th, and 8 th bits of the exclusive or data LX2 as an example, the 4 th, 6 th, and 8 th bits of the exclusive or data LX2 have a value of "1", so that the representative memory cell C4, the representative memory cell C6, and the representative memory cell C8 belong to the error interval 700 (also referred to as the second error interval) in fig. 15B. The memory cell C4, the memory cell C6 and the memory cell C8 in the error interval 700 actually belong to the memory state "101", but the memory cell C4, the memory cell C6 and the memory cell C8 are identified as the memory state "001" according to the read voltage VA. Herein, the memory cell C1 may be referred to as a "second memory cell", and the memory cells C4, C6 and C8 may be collectively referred to as a "third memory cell".

In addition, since the values of the 2 nd and 5 th bits of the exclusive or data LX2 are "0", it means that the memory cell C2 and the memory cell C5 are not in the error interval. That is, the memory states of the memory cells not in the error interval are correctly recognized according to the read voltage. Since the value of the 3 rd bit of the exclusive OR data LX2 is "1", the representative memory cell C3 belongs to one of the error intervals in the memory status distribution diagram shown in FIG. 9.

Taking the example of adjusting the read voltage VA for distinguishing the memory states "101" and "001" to the optimal read voltage VA1, the memory management circuit 702 first calculates the number of the second memory cells (also referred to as the first number) in the error interval 701. Here, since the second memory cell includes the memory cell C1, the first number is "1".

The memory management circuit 702 also counts the number of the third memory cells (also referred to as a second number) in the error interval 700. Here, since the third memory cell includes the memory cell C4, the memory cell C6, and the memory cell C8, the second number is "3".

Then, the memory management circuit 702 adjusts the read voltage VA to the read voltage VA1 according to the aforementioned first and second quantities. In more detail, in the exemplary embodiment of fig. 15A and 15B, the first number (value "1") is smaller than the second number (value "3"), and the first number can be regarded as the area of the error interval 701 and the second number as the area of the error interval 700 in view of the memory status distribution diagram of fig. 15B. The memory management circuit 702 adjusts the read voltage VA to the read voltage VA1 according to the first number and the second number (or the areas of the error intervals 701 and 700), so that the read voltage VA1 is greater than the read voltage VA. The read voltage VA1 may be X volts from the read voltage VA. In particular, when the memory management circuit 702 then reads the memory cells C1-C8 using the read voltage VA1, the number of memory cells (e.g., "2") in the error window 701 is the same as the number of memory cells (e.g., "2") in the error window 700. In other words, if a read voltage is between two error intervals, the read voltage is the optimal read voltage if the number of memory cells in the two error intervals is the same when the read voltage is used to read the memory cells, and the data read by using the optimal read voltage has a higher probability of successful decoding.

It should be noted that the magnitude of the read voltage adjustment (i.e., the aforementioned X volts) is determined according to the ratio of the first number and the second number. For example, the memory management circuit 702 may store in advance a look-up table of a plurality of ratios of the first number and the second number and the magnitudes of read voltage adjustments corresponding to the ratios, for example. When the memory management circuit obtains the first amount and the second amount by using the read voltage VA, the adjustment magnitude of the read voltage (i.e., the aforementioned X volts) can be known by the aforementioned lookup table. In the present exemplary embodiment, the reading voltage VA may be adjusted to the reading voltage VA1 larger than the reading voltage VA by looking up the table when the first number is smaller than the second number; and when the first number is greater than the second number, the read voltage VA may be adjusted to a read voltage VA1 that is less than the read voltage VA.

However, the present invention is not limited thereto, and in other embodiments, the memory management circuit 702 may not use the lookup table, but directly adjust the read voltage VA to another read voltage VA1 larger than the read voltage VA when the first number is smaller than the second number; and directly adjusting the read voltage VA to another read voltage VA1 smaller than the read voltage VA when the first number is greater than the second number.

In addition, fig. 15C is another example of the case when the first number is larger than the second number.

In detail, referring to fig. 15C, if the first number (for example, the value is "3") calculated in the above manner is greater than the second number (for example, the value is "1"), the area of the error interval 701 is greater than that of the error interval 700 as seen from the storage status distribution diagram of fig. 15C. The memory management circuit 702 adjusts the read voltage VA to the read voltage VA1 according to the first number and the second number (or the areas of the error intervals 701 and 700), so that the read voltage VA1 is smaller than the read voltage VA. The read voltage VA1 may be X volts from the read voltage VA. In particular, when the memory management circuit 702 then reads the memory cells C1-C8 using the read voltage VA1, the number of memory cells (e.g., "2") in the error window 701 is the same as the number of memory cells (e.g., "2") in the error window 700.

After determining the optimal read voltage VA1, the memory management circuit 702 can record the read voltage VA1, and then when the memory management circuit 702 is to read the memory cells C1-C8, the memory management circuit 702 can read the memory cells C1-C8 using the read voltage VA1 instead of using the read voltage VA to identify the memory states "101" and "001".

In particular, although the foregoing example is for adjusting the read voltage VA as in FIG. 9. However, the invention is not limited thereto, and in other embodiments, the memory management circuit 702 can also adjust the read voltages VB VG to the optimal read voltages respectively. For example, similar to the example of fig. 15A to 15C, the memory management circuit 702 can correct the data of the middle physical program cell MP2 according to the error checking and correcting code (not shown) corresponding to the data of the middle physical program cell MP2 to obtain corrected data (not shown). Then, the memory management circuit 702 adjusts the read voltage VB or the read voltage VC for reading the memory cells C1-C8 in fig. 9 to the optimal read voltage according to the corrected data of the first data, the data of the middle physical program cell MP2, the data of the upper physical program cell UP2, and the data of the middle physical program cell MP 2. Alternatively, the memory management circuit 702 can correct the data of the UP physical programming unit UP2 according to the data of the corresponding UP physical programming unit UP2 and the error checking and correcting code (not shown) corresponding to the data to obtain corrected data (not shown), for example. Then, the memory management circuit 702 adjusts the read voltage VD, the read voltage VE, the read voltage VF, or the read voltage VG for reading the memory cells C1-C8 in fig. 9 to the optimal read voltages respectively according to the corrected data of the first data, the data of the middle physical program cell MP2, the data of the upper physical program cell UP2, and the data of the upper physical program cell UP 2.

FIG. 16 is a flowchart illustrating a voltage regulation method according to an example embodiment.

Referring to fig. 16, in step S1601, the memory management circuit 702 reads a first physical program cell in the first physical program cell group to obtain first data. The first physical programming unit group is composed of a plurality of first memory cells. In step S1603, the memory management circuit 702 corrects the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data. In step S1605, the memory management circuit 702 reads the second physical program unit from the first physical program unit group to obtain the second data. In step S1607, the memory management circuit 702 adjusts a first read voltage for reading the first memory cell to a second read voltage according to the first data, the first corrected data and the second data. In step S1609, the memory management circuit 702 corrects the second data according to the second error check and correction code corresponding to the second data to obtain second corrected data. In step S1611, the memory management circuit 702 adjusts a third read voltage for reading the first memory cell to a fourth read voltage according to the first data, the second data and the second corrected data.

In addition, the memory management circuit 702 can record the second read voltage and the fourth read voltage, and when the memory management circuit 702 is to read the first memory cell later, the memory management circuit 702 reads the first memory cell by using the second read voltage and the fourth read voltage.

FIG. 17 is a flowchart illustrating a method for adjusting a read voltage according to the number of memory cells in an error window according to an example embodiment. The flow of fig. 17 is used to describe step S1607 in fig. 16 in detail.

Referring to fig. 17, in step S1701, the memory management circuit 702 performs an exclusive or operation on the first data and the first corrected data to obtain third data, wherein the third data has a plurality of bits, and each of the plurality of bits corresponds to one of the plurality of first memory cells. In step S1703, when at least a first bit of the bits of the third data is a first value and the storage status of at least a second storage unit of the first storage units corresponding to the first bit is a first storage status, the memory management circuit 702 determines that the second storage unit is located in the first error interval in the storage status subdivision diagram. The second memory cell in the first error interval belongs to the second memory state and is identified as the first memory state based on the first read voltage. In step S1705, when at least a second bit of the bits of the third data is the first value and the storage status of at least a third storage unit of the first storage units corresponding to the second bit is the second storage status, the memory management circuit 702 determines that the third storage unit is located in the second error interval in the storage status subdivision diagram. The third memory cell in the second error interval belongs to the first memory state and is identified as the second memory state according to the first read voltage. In step S1707, the memory management circuit 702 calculates a first number of second memory cells located in the first error section. In step S1709, the memory management circuit 702 calculates a second number of third memory cells located in the second error section. In step S1711, the memory management circuit 702 determines whether the first number is larger or smaller than the second number.

When the first number is greater than the second number, in step S1713, the memory management circuit 702 adjusts the first read voltage to the second read voltage such that the second read voltage is less than the first read voltage.

When the first number is smaller than the second number, in step S1715, the memory management circuit 702 adjusts the first read voltage to the second read voltage so that the second read voltage is greater than the first read voltage.

In summary, the voltage adjustment method, the memory control circuit unit and the memory storage device of the invention can efficiently calculate the optimal read voltage for reading the memory cell for subsequent reading, thereby increasing the probability of successful decoding and reducing the number of re-reading, and effectively improving the performance of the memory management circuit.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.