阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 小柳胜 于 2018-12-14 设计创作，主要内容包括：实施方式提供能够降低制造成本的半导体装置。半导体装置包括第1芯片及第2芯片,第1芯片具有第1基板、第1元件层、设置于第1元件层的焊垫、贯穿第1基板及第1元件层且与焊垫连接的通孔,第2芯片具有第2基板、第2元件层、设置于第2元件层的焊垫、贯穿第2基板与第2元件层且与焊垫连接的通孔,第1芯片的通孔包含第1通孔,第1芯片的焊垫包含与第1通孔连接的第1焊垫,第2芯片的通孔包含第2通孔,第2芯片的焊垫包含与第2通孔连接的第2焊垫及第3焊垫,包含设置于第2元件层中且将第2焊垫与第3焊垫连接的第1配线,第1芯片与第2芯片将第1元件层的上表面及第2元件层的上表面重叠,第1焊垫及第3焊垫经由第1导电体而连接。(Embodiments provide a semiconductor device capable of reducing manufacturing costs. The semiconductor device comprises a1 st chip and a2 nd chip, wherein the 1 st chip comprises a1 st substrate, a1 st element layer, a bonding pad arranged on the 1 st element layer, and a through hole penetrating the 1 st substrate and the 1 st element layer and connected with the bonding pad, the 2 nd chip comprises a2 nd substrate, a2 nd element layer, a bonding pad arranged on the 2 nd element layer, and a through hole penetrating the 2 nd substrate and the 2 nd element layer and connected with the bonding pad, the through hole of the 1 st chip comprises a1 st through hole, the bonding pad of the 1 st chip comprises a1 st bonding pad connected with the 1 st through hole, the through hole of the 2 nd chip comprises a2 nd through hole, the bonding pad of the 2 nd chip comprises a2 nd bonding pad and a3 rd bonding pad connected with the 2 nd through hole, and comprises a1 st wiring arranged in the 2 nd element layer and connecting the 2 nd bonding pad and the 3 rd bonding pad, and the 1 st chip and the 2 nd chip overlap the upper surface of the 1 st element, the 1 st pad and the 3 rd pad are connected through the 1 st conductor.)

1. A semiconductor device includes a1 st chip and a2 nd chip,

the 1 st chip has:

a1 st substrate;

a1 st element layer disposed on an upper surface of the 1 st substrate;

a plurality of pads provided so as to be exposed from the upper surface of the 1 st element layer; and

a plurality of through holes that are provided so as to penetrate the 1 st substrate and the 1 st element layer, each of which is exposed from the lower surface of the 1 st substrate, and is directly connected to a corresponding one of the plurality of pads;

the 2 nd chip has:

a2 nd substrate;

a2 nd element layer disposed on an upper surface of the 2 nd substrate;

a plurality of pads provided so as to be exposed from the upper surface of the 2 nd element layer; and

a plurality of through holes that are provided so as to penetrate the 2 nd substrate and the 2 nd element layer, each of which is exposed from the lower surface of the 2 nd substrate, and is directly connected to a corresponding one of the plurality of pads;

the plurality of vias of the 1 st chip include a1 st via,

the plurality of pads of the 1 st chip include a1 st pad directly connected to the 1 st via,

the plurality of vias of the 2 nd chip include a2 nd via,

the plurality of pads of the 2 nd chip include a2 nd pad and a3 rd pad directly connected to the 2 nd via,

includes a1 st wiring disposed in the 2 nd element layer and connecting the 2 nd pad and the 3 rd pad,

the 1 st chip and the 2 nd chip are overlapped so that the upper surface of the 1 st element layer and the upper surface of the 2 nd element layer face each other,

the 1 st pad and the 3 rd pad are connected via a1 st conductor.

2. The semiconductor device according to claim 1,

the circuit board further comprises an insulator arranged between the 1 st welding pad and the 2 nd welding pad.

3. The semiconductor device according to claim 1 or 2,

the circuit also includes a1 st logic element disposed on the 1 st wiring.

4. The semiconductor device according to claim 1 or 2,

the plurality of vias of the 1 st chip include a3 rd via,

the plurality of pads of the 1 st chip include a4 th pad directly connected to the 3 rd via,

the plurality of vias of the 2 nd chip include a4 th via,

the plurality of pads of the 2 nd chip include a5 th pad directly connected to the 4 th via,

the 4 th pad and the 5 th pad are connected via a2 nd conductor.

5. The semiconductor device according to claim 1 or 2,

the plurality of vias of the 1 st chip include a5 th via,

the plurality of pads of the 1 st chip include a6 th pad directly connected to the 5 th via,

the plurality of vias of the 1 st chip include a6 th via,

the plurality of pads of the 1 st chip include a7 th pad directly connected to the 6 th via,

the plurality of vias of the 2 nd chip include a7 th via,

the plurality of pads of the 2 nd chip include an 8 th pad directly connected to the 7 th via,

the plurality of vias of the 2 nd chip include an 8 th via,

the plurality of pads of the 2 nd chip include a9 th pad directly connected to the 8 th via,

the 6 th pad and the 9 th pad are connected via a3 rd conductor,

the 7 th pad and the 8 th pad are connected via a4 th conductor,

an insulator is disposed between the 6 th pad and the 8 th pad,

an insulator is disposed between the 7 th pad and the 9 th pad,

the 5 th through hole and the 8 th through hole are not provided symmetrically with respect to the facing surface of the 1 st element layer and the 2 nd element layer,

the 6 th through hole and the 7 th through hole are not provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other.

6. The semiconductor device according to claim 5,

the 5 th through hole and the 7 th through hole are provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other,

the 6 th through hole and the 8 th through hole are provided symmetrically with respect to a surface of the 1 st element layer and the 2 nd element layer facing each other.

7. The semiconductor device according to claim 1 or 2,

the plurality of vias of the 1 st chip include a9 th via,

the plurality of pads of the 1 st chip include a10 th pad directly connected to the 9 th via,

the plurality of vias of the 1 st chip include a10 th via,

the plurality of pads of the 1 st chip include an 11 th pad directly connected to the 10 th via,

the plurality of vias of the 2 nd chip include an 11 th via,

the plurality of pads of the 2 nd chip include a12 th pad directly connected to the 11 th via,

the plurality of vias of the 2 nd chip include a12 th via,

the plurality of pads of the 2 nd chip include a13 th pad directly connected to the 12 th via,

the plurality of pads of the 2 nd chip include a14 th pad,

includes a2 nd wiring disposed in the 2 nd element layer and connecting the 13 nd pad and the 14 th pad,

the 10 th pad and the 14 th pad are connected via a5 th conductor,

the 11 th pad and the 12 th pad are connected via a6 th conductor,

an insulator is disposed between the 10 th pad and the 12 th pad,

an insulator is disposed between the 11 th pad and the 13 th pad,

the 9 th through hole and the 12 th through hole are not provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other,

the 10 th through hole and the 11 th through hole are not provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other.

8. The semiconductor device according to claim 7,

the 9 th through hole and the 11 th through hole are provided symmetrically with respect to a surface of the 1 st element layer and the 2 nd element layer facing each other,

the 10 th through hole and the 12 th through hole are provided symmetrically with respect to a surface of the 1 st element layer and the 2 nd element layer facing each other.

9. The semiconductor device according to claim 1 or 2,

the plurality of vias of the 1 st chip include a13 th via,

the plurality of pads of the 1 st chip include a 15 th pad directly connected to the 13 th via,

the plurality of vias of the 1 st chip include a14 th via,

the plurality of pads of the 1 st chip include a 16 th pad directly connected to the 14 th via,

the plurality of pads of the 1 st chip include a 17 th pad,

including a4 th wiring disposed in the 1 st device layer and connecting the 16 th pad and the 17 th pad, the plurality of through holes of the 2 nd chip including a 15 th through hole,

the plurality of pads of the 2 nd chip include an 18 th pad directly connected to the 15 th via,

the plurality of vias of the 2 nd chip include a 16 th via,

the plurality of pads of the 2 nd chip include a 19 th pad directly connected to the 16 th via,

the plurality of pads of the 2 nd chip include a 20 th pad,

includes a5 th wiring disposed in the 2 nd element layer and connecting the 19 th pad and the 20 th pad,

further comprising:

a2 nd logic element disposed on the 4 th wiring;

a3 rd logic element disposed on the 5 th wiring;

the 15 th pad and the 20 th pad are connected via a7 th conductor,

the 17 th pad and the 18 th pad are connected via an 8 th conductor,

an insulator is disposed between the 15 th pad and the 18 th pad,

an insulator is disposed between the 16 th bonding pad and the 19 th bonding pad,

the 13 th through hole and the 16 th through hole are not provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other,

the 14 th through hole and the 15 th through hole are not provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other.

10. The semiconductor device according to claim 9,

the 13 th through hole and the 15 th through hole are provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other,

the 14 th through hole and the 16 th through hole are provided symmetrically with respect to a surface of the 1 st element layer and the 2 nd element layer facing each other.

11. The semiconductor device according to claim 1 or 2,

the plurality of vias of the 1 st chip include a 17 th via,

the plurality of pads of the 1 st chip include a 21 st pad directly connected to the 17 th via,

the plurality of vias of the 1 st chip include an 18 th via,

the plurality of pads of the 1 st chip include a 22 nd pad directly connected to the 18 th via,

the plurality of vias of the 1 st chip include a 19 th via,

the plurality of pads of the 1 st chip include a 23 rd pad directly connected to the 19 th via,

the plurality of vias of the 2 nd chip include a 20 th via,

the plurality of pads of the 2 nd chip include a 24 th pad directly connected to the 20 th via,

the plurality of vias of the 2 nd chip include a 21 st via,

the plurality of pads of the 2 nd chip include a 25 th pad directly connected to the 21 st via,

the plurality of vias of the 2 nd chip include a 22 nd via,

the plurality of pads of the 2 nd chip include a 26 th pad directly connected to the 22 nd via,

the 21 st pad and the 25 th pad are connected via a9 th conductor,

the 22 nd pad and the 26 th pad are connected through a10 th electrical conductor,

the 23 rd pad and the 24 th pad are connected via an 11 th conductor,

an insulator is disposed between the 21 st pad and the 24 th pad,

an insulator is disposed between the 22 nd pad and the 25 th pad,

an insulator is disposed between the 23 rd pad and the 26 th pad,

the 17 th through hole and the 21 st through hole are not provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other,

the 18 th through hole and the 22 nd through hole are not provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other,

the 19 th through hole and the 20 th through hole are not provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other.

12. The semiconductor device according to claim 11,

the 17 th through hole and the 20 th through hole are provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other,

the 18 th through hole and the 21 st through hole are provided symmetrically with respect to a surface of the 1 st element layer and the 2 nd element layer facing each other,

the 19 th through hole and the 22 nd through hole are provided symmetrically with respect to a plane where the 1 st element layer and the 2 nd element layer face each other.

13. The semiconductor device according to claim 1 or 2,

the 1 st element layer and the 2 nd element layer are provided with the same layout pattern.

Technical Field

Background

A NAND type flash memory as a semiconductor device is known.

Disclosure of Invention

Drawings

Fig. 1 is a block diagram for explaining the configuration of the memory system according to embodiment 1.

Fig. 2 is a block diagram for explaining the configuration of the semiconductor device according to embodiment 1.

Fig. 3 is a circuit diagram for explaining signal paths of the core chip of the semiconductor device according to embodiment 1.

Fig. 4 is a block diagram showing an example of the configuration of a core chipset of the semiconductor device according to embodiment 1.

Fig. 5 is a plan view for explaining a layout pattern of a sub chip of the semiconductor device according to embodiment 1.

Fig. 6 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to embodiment 1.

Fig. 7 is a plan view for explaining a layout pattern of a sub chip of the semiconductor device according to embodiment 1.

Fig. 8 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to embodiment 1.

Fig. 9 is a plan view for explaining a layout pattern in the case of stacking sub-chips in the semiconductor device according to embodiment 1.

Fig. 10 is a sectional view for explaining a build-up structure of a core chip set of the semiconductor device according to embodiment 1.

Fig. 11 is a cross-sectional view for explaining a build-up structure of a core chip set of the semiconductor device of the comparative example.

Fig. 12 is a cross-sectional view illustrating a build-up structure of a core chipset of a semiconductor device.

Fig. 13 is a cross-sectional view illustrating a laminated structure of a core chipset of a semiconductor device.

Fig. 14 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to variation 1 of embodiment 1.

Fig. 15 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to variation 1 of embodiment 1.

Fig. 16 is a sectional view for explaining a build-up structure of a core chipset of a semiconductor device according to variation 1 of embodiment 1.

Fig. 17 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to variation 2 of embodiment 1.

Fig. 18 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to variation 2 of embodiment 1.

Fig. 19 is a sectional view for explaining a build-up structure of a core chipset of a semiconductor device according to variation 2 of embodiment 1.

Fig. 20 is a circuit diagram for explaining signal paths of the core chip of the semiconductor device according to embodiment 2.

Fig. 21 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to embodiment 2.

Fig. 22 is a plan view for explaining an example of the wiring pattern of the daughter chip of the semiconductor device according to embodiment 2.

Fig. 23 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to embodiment 2.

Fig. 24 is a plan view for explaining an example of the wiring pattern of the daughter chip of the semiconductor device according to embodiment 2.

Fig. 25 is a sectional view for explaining a build-up structure of a core chip set of the semiconductor device according to embodiment 2.

Fig. 26 is a diagram showing a relationship between pads of the respective sub-chips in a case where 2 sub-chips are stacked in the semiconductor device according to embodiment 2.

Fig. 27 is a cross-sectional view for explaining the flow of signals and power supplies in the build-up structure of the core chip set of the semiconductor device according to embodiment 2.

Fig. 28 is a circuit diagram for explaining signal paths of core chips of a semiconductor device according to a modification of embodiment 2.

Fig. 29 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of a semiconductor device according to a modification of embodiment 2.

Fig. 30 is a plan view for explaining an example of a wiring pattern of a sub-chip of a semiconductor device according to a modification of embodiment 2.

Fig. 31 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of a semiconductor device according to a variation of embodiment 2.

Fig. 32 is a plan view for explaining an example of a wiring pattern of a sub-chip of a semiconductor device according to a modification of embodiment 2.

Fig. 33 is a sectional view for explaining a build-up structure of a core chipset of a semiconductor device according to a variation of embodiment 2.

Fig. 34 is a diagram showing a relationship of pads of each sub-chip in a case where 2 sub-chips are stacked in a semiconductor device according to a modification of embodiment 2.

Fig. 35 is a cross-sectional view for explaining the flow of signals and power supplies in the build-up structure of the core chip group of the semiconductor device according to the variation of embodiment 2.

Fig. 36 is a circuit diagram for explaining signal paths of the core chip of the semiconductor device according to embodiment 3.

Fig. 37 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to embodiment 3.

Fig. 38 is a plan view for explaining an example of the wiring pattern of the daughter chip of the semiconductor device according to embodiment 3.

Fig. 39 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of the semiconductor device according to embodiment 3.

Fig. 40 is a plan view for explaining an example of the wiring pattern of the daughter chip of the semiconductor device according to embodiment 3.

Fig. 41 is a sectional view for explaining a build-up structure of a core chip set of the semiconductor device according to embodiment 3.

Fig. 42 is a diagram showing a relationship of pads of each sub-chip in a case where 2 sub-chips are stacked in the semiconductor device according to embodiment 3.

Fig. 43 is a cross-sectional view for explaining the flow of signals and power supplies in the build-up structure of the core chip set of the semiconductor device according to embodiment 3.

Fig. 44 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of a semiconductor device according to a variation of embodiment 3.

Fig. 45 is a plan view for explaining an example of a wiring pattern of a sub-chip of a semiconductor device according to a variation of embodiment 3.

Fig. 46 is a cross-sectional view for explaining an example of a wiring pattern of a sub-chip of a semiconductor device according to a modification of embodiment 3.

Fig. 47 is a plan view for explaining an example of a wiring pattern of a sub-chip of a semiconductor device according to a variation of embodiment 3.

Fig. 48 is a sectional view for explaining a build-up structure of a core chipset of a semiconductor device according to a variation of embodiment 3.

Fig. 49 is a diagram showing a relationship of pads of each sub-chip in a case where 2 sub-chips are stacked in the semiconductor device according to the variation of embodiment 3.

Fig. 50 is a cross-sectional view for explaining the flow of signals and power supplies in the build-up structure of the core chip set of the semiconductor device according to the variation of embodiment 3.

Embodiments relate to a semiconductor device.