Array substrate, display panel and manufacturing method of array substrate
阅读说明：本技术 一种阵列基板、显示面板和阵列基板的制作方法 (Array substrate, display panel and manufacturing method of array substrate ) 是由 冯雪欢 李永谦 于 2019-09-29 设计创作，主要内容包括：本发明公开了一种阵列基板、显示面板和阵列基板的制作方法,所述阵列基板包括显示区和非显示区,所述非显示区包括栅极驱动电路,所述显示区包括第一薄膜晶体管,所述栅极驱动电路包括第二薄膜晶体管,所述第一薄膜晶体管的栅绝缘层的厚度大于所述第二薄膜晶体管的栅绝缘层的厚度。本发明提供的实施例通过在显示区和非显示区的薄膜晶体管中设置不同厚度的栅绝缘层,能够有效增强栅极驱动电路输出管的驱动能力、减小显示区的寄生电容,减小阵列基板的边框尺寸,提升显示效果,具有广泛的应用前景。(The invention discloses an array substrate, a display panel and a manufacturing method of the array substrate, wherein the array substrate comprises a display area and a non-display area, the non-display area comprises a grid driving circuit, the display area comprises a first thin film transistor, the grid driving circuit comprises a second thin film transistor, and the thickness of a grid insulating layer of the first thin film transistor is larger than that of a grid insulating layer of the second thin film transistor. According to the embodiment of the invention, the gate insulating layers with different thicknesses are arranged in the thin film transistors in the display area and the non-display area, so that the driving capability of an output tube of the gate driving circuit can be effectively enhanced, the parasitic capacitance of the display area is reduced, the frame size of the array substrate is reduced, the display effect is improved, and the wide application prospect is achieved.)
1. An array substrate comprises a display area and a non-display area, wherein the non-display area comprises a gate driving circuit, the array substrate is characterized in that the display area comprises a first thin film transistor, the gate driving circuit comprises a second thin film transistor, and the thickness of a gate insulating layer of the first thin film transistor is larger than that of a gate insulating layer of the second thin film transistor.
2. The array substrate of claim 1, wherein the first thin film transistor is one of a top gate structure and a bottom gate structure, and the second thin film transistor is one of a top gate structure and a bottom gate structure.
3. The array substrate of claim 2, wherein in the case that the first thin film transistor and the second thin film transistor are both of a top gate structure or a bottom gate structure,
the first thin film transistor comprises a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is arranged on the same layer as the first gate insulating layer or the second gate insulating layer.
4. The array substrate of claim 3, wherein the first gate insulating layer and the second gate insulating layer are the same or different materials.
5. The array substrate of claim 3,
the method comprises the following steps:
a substrate;
a light-shielding layer formed on the substrate;
a buffer layer covering the light-shielding layer and the substrate;
a first active layer and a second active layer formed on the buffer layer;
a first gate insulating layer material formed on the first active layer;
a second gate insulating layer material formed on the second active layer and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first active layer constitute the first gate insulating layer and the second gate insulating layer, respectively, and the second gate insulating layer material formed on the second active layer constitutes a gate insulating layer of the second thin film transistor;
forming a grid electrode, a source electrode and a drain electrode of the first thin film transistor and the second thin film transistor; or
A substrate;
a light-shielding layer formed on the substrate;
a buffer layer covering the light-shielding layer and the substrate;
a first gate electrode of the first thin film transistor and a second gate electrode of the second thin film transistor formed on the buffer layer;
a first gate insulating layer material formed on the first gate electrode;
a second gate insulating layer material formed on the second gate electrode and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first gate electrode respectively constitute the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second gate electrode constitutes a gate insulating layer of the second thin film transistor;
and forming an active layer, a source electrode and a drain electrode of the first thin film transistor and the second thin film transistor.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
7. A manufacturing method of an array substrate is characterized by comprising the following steps:
and forming a first thin film transistor in a region corresponding to the display region on the substrate, and forming a second thin film transistor in a region corresponding to the gate drive circuit in the non-display region, wherein the thickness of the gate insulating layer of the first thin film transistor is greater than that of the gate insulating layer of the second thin film transistor.
8. The method of claim 7, wherein forming a first thin film transistor on the substrate in a region corresponding to the display region and forming a second thin film transistor in a region corresponding to the gate driving circuit in the non-display region further comprises:
and forming the first thin film transistor and the second thin film transistor into a top gate structure or a bottom gate structure, wherein the first thin film transistor comprises a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is formed simultaneously with the first gate insulating layer or the second gate insulating layer.
9. The method of manufacturing according to claim 8, wherein forming the first thin film transistor and the second thin film transistor as a top gate structure, wherein the first thin film transistor includes a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and wherein forming the gate insulating layer of the second thin film transistor simultaneously with the second gate insulating layer further comprises:
forming a light-shielding layer on the substrate;
forming a buffer layer covering the light-shielding layer and the substrate;
forming a first active layer and a second active layer on the buffer layer;
forming a first gate insulating layer material only on the first active layer by masking the second active layer using a mask;
and forming a second gate insulating layer material on the second active layer and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first active layer respectively form the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second active layer forms a gate insulating layer of the second thin film transistor.
10. The method of manufacturing according to claim 8, wherein forming the first thin film transistor and the second thin film transistor as a bottom gate structure, wherein the first thin film transistor includes a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and wherein forming the gate insulating layer of the second thin film transistor simultaneously with the second gate insulating layer further comprises:
forming a light-shielding layer on the substrate;
forming a buffer layer covering the light-shielding layer and the substrate;
forming a first gate and a second gate on the buffer layer;
shielding the second grid electrode by using a mask, and forming a first grid insulation layer material on the first grid electrode only;
and forming a second gate insulating layer material on the second gate electrode and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first gate electrode respectively form the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second gate electrode forms a gate insulating layer of the second thin film transistor.
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a manufacturing method of the array substrate.
Background
In the display field, in order to continuously improve the display picture and improve the user experience, narrow-frame display becomes a popular research. The gate driving circuits are disposed on both sides of the display panel to reduce panel defects and cost, but the size of the gate driving circuits is an important factor that restricts the display panel from having a narrow frame.
Disclosure of Invention
In order to solve at least one of the above problems, a first aspect of the present invention provides an array substrate, including a display region and a non-display region, where the non-display region includes a gate driving circuit, where the display region includes a first thin film transistor, the gate driving circuit includes a second thin film transistor, and a gate insulating layer of the first thin film transistor has a thickness greater than a thickness of a gate insulating layer of the second thin film transistor.
Further, the first thin film transistor is one of a top gate structure and a bottom gate structure, and the second thin film transistor is one of a top gate structure and a bottom gate structure.
Further, in the case where the first thin film transistor and the second thin film transistor are both of a top gate structure or a bottom gate structure,
the first thin film transistor comprises a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is arranged on the same layer as the first gate insulating layer or the second gate insulating layer.
Further, the materials of the first gate insulating layer and the second gate insulating layer are the same or different.
Further, in the above-mentioned case,
the method comprises the following steps:
a substrate;
a light-shielding layer formed on the substrate;
a buffer layer covering the light-shielding layer and the substrate;
a first active layer and a second active layer formed on the buffer layer;
a first gate insulating layer material formed on the first active layer;
a second gate insulating layer material formed on the second active layer and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first active layer constitute the first gate insulating layer and the second gate insulating layer, respectively, and the second gate insulating layer material formed on the second active layer constitutes a gate insulating layer of the second thin film transistor;
forming a grid electrode, a source electrode and a drain electrode of the first thin film transistor and the second thin film transistor;
or
A substrate;
a light-shielding layer formed on the substrate;
a buffer layer covering the light-shielding layer and the substrate;
a first gate electrode of the first thin film transistor and a second gate electrode of the second thin film transistor formed on the buffer layer;
a first gate insulating layer material formed on the first gate electrode;
a second gate insulating layer material formed on the second gate electrode and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first gate electrode respectively constitute the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second gate electrode constitutes a gate insulating layer of the second thin film transistor;
and forming an active layer, a source electrode and a drain electrode of the first thin film transistor and the second thin film transistor.
A second aspect of the present invention provides a display panel, including the array substrate of the first aspect.
The third aspect of the present invention provides a method for manufacturing an array substrate, including:
and forming a first thin film transistor in a region corresponding to the display region on the substrate, and forming a second thin film transistor in a region corresponding to the gate drive circuit in the non-display region, wherein the thickness of the gate insulating layer of the first thin film transistor is greater than that of the gate insulating layer of the second thin film transistor.
Further, the forming a first thin film transistor on the substrate in a region corresponding to the display region, and forming a second thin film transistor on the substrate in a region corresponding to the gate driving circuit in the non-display region further includes:
and forming the first thin film transistor and the second thin film transistor into a top gate structure or a bottom gate structure, wherein the first thin film transistor comprises a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is formed simultaneously with the first gate insulating layer or the second gate insulating layer.
Further, forming the first thin film transistor and the second thin film transistor as a top gate structure, wherein the first thin film transistor includes a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is formed simultaneously with the second gate insulating layer includes:
forming a light-shielding layer on the substrate;
forming a buffer layer covering the light-shielding layer and the substrate;
forming a first active layer and a second active layer on the buffer layer;
forming a first gate insulating layer material only on the first active layer by masking the second active layer using a mask;
and forming a second gate insulating layer material on the second active layer and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first active layer respectively form the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second active layer forms a gate insulating layer of the second thin film transistor.
Further, forming the first thin film transistor and the second thin film transistor as a bottom gate structure, wherein the first thin film transistor includes a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is formed simultaneously with the second gate insulating layer includes:
forming a light-shielding layer on the substrate;
forming a buffer layer covering the light-shielding layer and the substrate;
forming a first gate and a second gate on the buffer layer;
shielding the second grid electrode by using a mask, and forming a first grid insulation layer material on the first grid electrode only;
and forming a second gate insulating layer material on the second gate electrode and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first gate electrode respectively form the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second gate electrode forms a gate insulating layer of the second thin film transistor.
The invention has the following beneficial effects:
aiming at the existing problems, the invention provides an array substrate, a display panel and a manufacturing method of the array substrate, and the driving capability of an output tube of a grid driving circuit can be effectively enhanced, the parasitic capacitance of the display area can be reduced, and the frame size of the array substrate can be reduced by arranging the grid insulating layers with different thicknesses in the thin film transistors of the display area and the non-display area, so that the problems in the prior art are solved, the display effect is effectively improved, and the array substrate has wide application prospect.
Drawings
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram illustrating a structure of a display panel in the prior art;
fig. 2 shows a partial circuit diagram of a gate driving circuit in the related art;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 4 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
In view of the above problems, the inventors of the present application have found, as shown in fig. 1, that in the prior art, a display panel 100 includes a non-display region 110 and a display region 120, the non-display region 110 includes a gate driver circuit (GOA), the gate driver circuit includes an output
In view of the above problems, the inventors of the present application have made extensive experiments to propose a solution, and as shown in fig. 3, an embodiment of the present invention provides an array substrate including a display region and a non-display region, the non-display region includes a gate driving circuit, the display region includes a first thin film transistor, the gate driving circuit includes a second thin film transistor, and a thickness of a gate insulating layer of the first thin film transistor is greater than a thickness of a gate insulating layer of the second thin film transistor.
In this embodiment, the structures of the thin film transistors in different areas of the array substrate are adjusted, and the driving capability of the output tube of the gate driving circuit is improved by reducing the thickness of the gate insulating layer of the thin film transistor in the non-display area, so as to reduce the length-width ratio of the gate driving circuit, and simultaneously, the thickness of the gate insulating layer of the thin film transistor in the display area is increased to reduce the driving capability of the thin film transistor so as to enhance the brightness uniformity of the display panel, so that the driving capability of the gate driving circuit is ensured, the volume of the gate driving circuit is reduced, the display effect is improved, and the narrow frame is realized.
It is worth mentioning that, the present application does not limit the structures of the thin film transistors in the display area and the non-display area of the array substrate, and the thin film transistor in the display area may have a top gate structure or a bottom gate structure. In other words, when the thin film transistor in the display area is of a top-gate structure, the thin film transistor in the non-display area may be of a top-gate structure or a bottom-gate structure, and when the thin film transistor in the display area is of a bottom-gate structure, the thin film transistor in the non-display area may be of a top-gate structure or a bottom-gate structure.
In order to simplify the manufacturing steps of the array substrate, in an optional embodiment, in a case that the first thin film transistor and the second thin film transistor are both of a top gate structure, the first thin film transistor includes a first gate insulating layer and a second gate insulating layer, and a gate insulating layer of the second thin film transistor is disposed on the same layer as the first gate insulating layer or the second gate insulating layer.
In this embodiment, the first thin film transistor and the second thin film transistor have the same structure and are both configured as a top gate structure, so that when the array substrate is manufactured, the thin film transistor in the non-display region and the thin film transistor in the display region can be manufactured simultaneously, thereby reducing the manufacturing steps.
As shown in fig. 3, in a specific example, the array substrate 200 includes: a substrate 10, a light-shielding layer formed on the substrate 10, specifically including a first light-shielding layer 111 and a second light-shielding layer 112, a buffer layer 12 covering the light-shielding layer and the substrate 10, and a first active layer 131 and a second active layer 132 formed on the buffer layer 12; a first gate insulating layer material formed on the first active layer 131; a second gate insulating layer material formed on the second active layer 132 and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first active layer 131 respectively constitute the first gate insulating layer 14 and the second gate insulating layer 151, the second gate insulating layer material formed on the second active layer 132 constitutes the gate insulating layer 152 of the second thin film transistor, and the second gate insulating layer 151 and the gate insulating layer 152 of the second thin film transistor are disposed in the same layer; a first gate electrode 161 formed on the second gate insulating layer 151 of the first thin film transistor, a second gate electrode 162 formed on the gate insulating layer 152 of the second thin film transistor, and an interlayer insulating layer 17 covering the first gate electrode 161, the second gate electrode 162, the exposed second gate insulating layer 151 of the first thin film transistor, the gate insulating layer 152 of the second thin film transistor, the first active layer 131, the second active layer 132, and the buffer layer 12; a first source electrode 181 and a first drain electrode 191 of the first thin film transistor, and a second source electrode 182 and a second drain electrode 192 of the second thin film transistor, which are respectively formed on the interlayer insulating layer 17, the first source electrode 181 and the first drain electrode 191 being electrically connected to the corresponding first active layer 131 through a via hole, and the second source electrode 182 and the second drain electrode 192 being electrically connected to the corresponding second active layer 132 through a via hole; and a planarization layer 20 covering the first source electrode 181, the first drain electrode 191, the second source electrode 182, the second drain electrode 192, and the exposed interlayer insulating layer 17.
In this embodiment, when the first gate insulating layer of the first thin film transistor is manufactured, the first gate insulating layer of the first thin film transistor is formed by deposition using a first mask, and the non-display region is covered by the first mask, so that the non-display region is not manufactured in this step; forming a second gate insulating layer of the first thin film transistor and a gate insulating layer of the second thin film transistor by deposition by using a second mask plate, wherein the second mask plate is a mask plate for manufacturing the gate insulating layer and is used for forming the gate insulating layers in the non-display area and the display area respectively; thereby realizing that the thickness of the gate insulating layer of the first thin film transistor is greater than that of the gate insulating layer of the second thin film transistor.
It should be noted that, a second mask may also be used to form the first gate insulating layer of the first thin film transistor and the gate insulating layer of the second thin film transistor by deposition, and then the non-display region is covered by the first mask, and the second gate insulating layer of the first thin film transistor is formed by deposition.
In an alternative embodiment, the materials of the first and second gate insulating layers are the same or different.
In this embodiment, the gate insulating layer of the first thin film transistor is a first gate insulating layer and a second gate insulating layer formed by two preparation processes, and the first gate insulating layer and the second gate insulating layer may be made of the same material, for example, the first gate insulating layer and the second gate insulating layer are both silicon dioxide; the first gate insulating layer and the second gate insulating layer may also be made of different materials, for example, the first gate insulating layer is silicon dioxide, and the second gate insulating layer is silicon nitride. Those skilled in the art should select a suitable insulating medium according to the requirements of practical application, and will not be described in detail herein.
Similar to the previous embodiments, in another alternative embodiment, in the case where the first thin film transistor and the second thin film transistor are both of a bottom gate structure, the first thin film transistor includes a first gate insulating layer and a second gate insulating layer, and the gate insulating layer of the second thin film transistor is disposed in the same layer as the second gate insulating layer.
Specifically, the array substrate includes: a substrate; a light-shielding layer formed on the substrate; a buffer layer covering the light-shielding layer and the substrate; a first gate electrode of the first thin film transistor and a second gate electrode of the second thin film transistor formed on the buffer layer; a first gate insulating layer material formed on the first gate electrode; a second gate insulating layer material formed on the second gate electrode and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first gate electrode respectively constitute the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second gate electrode constitutes a gate insulating layer of the second thin film transistor; and forming an active layer, a source electrode and a drain electrode of the first thin film transistor and the second thin film transistor.
In this embodiment, the first thin film transistor and the second thin film transistor are both of a bottom gate structure, the first thin film transistor includes a first gate insulating layer and a second gate insulating layer, and the second gate insulating layer and the gate insulating layer of the second thin film transistor are disposed on the same layer, so that the number of manufacturing steps of the array substrate is reduced, and the manufacturing cost of the array substrate is reduced.
Corresponding to the array substrate provided in the foregoing embodiments, an embodiment of the present application further provides a manufacturing method of the array substrate, and since the manufacturing method provided in the embodiment of the present application corresponds to the array substrates provided in the foregoing embodiments, the foregoing embodiment is also applicable to the manufacturing method provided in the present embodiment, and is not described in detail in the present embodiment.
As shown in fig. 4, an embodiment of the present application further provides a method for manufacturing the array substrate, including: forming a first thin film transistor on a region of the substrate corresponding to the display region; forming a second thin film transistor in a region corresponding to the gate driving circuit of the non-display region; wherein the thickness of the gate insulating layer of the first thin film transistor is greater than the thickness of the gate insulating layer of the second thin film transistor.
In an alternative embodiment, the forming a first thin film transistor on the substrate in a region corresponding to the display region and forming a second thin film transistor in a region corresponding to the gate driving circuit in the non-display region further includes: and forming the first thin film transistor and the second thin film transistor into a top gate structure or a bottom gate structure, wherein the first thin film transistor comprises a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is formed simultaneously with the first gate insulating layer or the second gate insulating layer.
In the present embodiment, a first gate insulating layer of a first thin film transistor is formed by deposition using a first mask; a second gate insulating layer of the first thin film transistor and a gate insulating layer of the second thin film transistor are formed by deposition using a second mask.
In an alternative embodiment, the first thin film transistor and the second thin film transistor are formed in a top gate structure, wherein the first thin film transistor includes a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is formed simultaneously with the second gate insulating layer including: forming a light-shielding layer on the substrate; forming a buffer layer covering the light-shielding layer and the substrate; forming a first active layer and a second active layer on the buffer layer; forming a first gate insulating layer material only on the first active layer by masking the second active layer using a mask; and forming a second gate insulating layer material on the second active layer and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first active layer respectively form the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second active layer forms a gate insulating layer of the second thin film transistor.
In another alternative embodiment, forming the first thin film transistor and the second thin film transistor as a bottom gate structure, wherein the first thin film transistor includes a first gate insulating layer and a second gate insulating layer on the first gate insulating layer, and the gate insulating layer of the second thin film transistor is formed simultaneously with the second gate insulating layer includes: forming a light-shielding layer on the substrate; forming a buffer layer covering the light-shielding layer and the substrate; forming a first gate and a second gate on the buffer layer; shielding the second grid electrode by using a mask, and forming a first grid insulation layer material on the first grid electrode only; and forming a second gate insulating layer material on the second gate electrode and the first gate insulating layer material, wherein the first gate insulating layer material and the second gate insulating layer material formed on the first gate electrode respectively form the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer material formed on the second gate electrode forms a gate insulating layer of the second thin film transistor.
An embodiment of the present application further provides a display panel including the array substrate. The display device specifically comprises any product or component with a display function, such as a liquid crystal panel, an Organic Light Emitting Diode (OLED) panel, an electronic paper panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
Aiming at the existing problems, the invention provides an array substrate, a display panel and a manufacturing method of the array substrate, and the driving capability of an output tube of a grid driving circuit can be effectively enhanced, the parasitic capacitance of the display area can be reduced, and the frame size of the array substrate can be reduced by arranging the grid insulating layers with different thicknesses in the thin film transistors of the display area and the non-display area, so that the problems in the prior art are solved, the display effect is effectively improved, and the array substrate has wide application prospect.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
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