Magnetic Tunnel Junction (MTJ) integration on the backside of silicon
阅读说明:本技术 硅的背侧上的磁性隧道结(mtj)集成 (Magnetic Tunnel Junction (MTJ) integration on the backside of silicon ) 是由 S·马尼帕特鲁尼 T·戈萨维 I·扬 D·尼科诺夫 于 2019-05-28 设计创作,主要内容包括:本发明公开了一种存储器件,其包括具有正侧和背侧的衬底,其中,第一导线在所述背侧上,并且第二导线位于所述正侧上。晶体管在所述正侧上处于所述第二导线与衬底之间。磁性隧道结(MTJ)在背侧上处于第一导线和衬底之间,其中,所述MTJ的一端通过所述衬底耦合至所述晶体管,并且所述MTJ的相对端连接至所述第一导线,并且其中,所述晶体管进一步连接至所述正侧上的第二导线。(A memory device includes a substrate having a front side and a back side, wherein first conductive lines are on the back side and second conductive lines are on the front side. A transistor is between the second conductive line and a substrate on the front side. A Magnetic Tunnel Junction (MTJ) is between a first conductive line and a substrate on a backside, wherein one end of the MTJ is coupled to the transistor through the substrate and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to a second conductive line on the front side.)
1. A memory device, comprising:
a substrate having a front side and a back side, wherein a first conductive line is on the back side and a second conductive line is on the front side;
a transistor on the positive side and between the second conductive line and the substrate; and
a Magnetic Tunnel Junction (MTJ) on the back side and between the first conductive line and the substrate, wherein one end of the MTJ is coupled to the transistor through the substrate and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.
2. The memory device of claim 1, wherein the MTJ is connected to the drain of the transistor and the source of the transistor is coupled to the second conductive line.
3. The memory device of claim 1 or 2, wherein the MTJ is connected to the drain of the transistor using a through via extending through the substrate from the front side to the back side.
4. The memory device of claim 3, wherein a gate of the transistor is coupled to a word line.
5. The memory device of claim 1 or 2, wherein the first conductive line comprises a bit line and the second conductive line comprises a source line.
6. The memory device of claim 5, wherein the bit lines include a read bit line and a write bit line.
7. The memory device of claim 1 or 2, wherein the memory device comprises a 1T-1MTJ Magnetic Random Access Memory (MRAM).
8. The memory device of claim 1 or 2, wherein the MTJ device comprises an SOT electrode comprising GSHE material.
9. The memory device of claim 8, wherein the GSHE material includes at least one of β -tantalum (β -Ta), β -tungsten (β -W), Pt, Hf, Ir, Bi, and doped Cu.
10. The memory device of claim 8, wherein the MTJ device comprises a free magnetic layer coupled with the SOT electrode, wherein the SOT electrode is coupled to a write bit line; and an opposite end of the MTJ device is coupled to a read bit line.
11. The memory device of claim 10, wherein the material stack comprising the MTJ device further comprises: a tunneling barrier, a fixed magnetic layer, a coupling layer, a Synthetic Antiferromagnet (SAF)/pinning layer, and a top electrode.
12. A memory device, comprising:
a substrate;
a backside of the substrate, comprising:
a read bit line and a write bit line; and
a Magnetic Tunnel Junction (MTJ) device; and
a front side of the substrate comprising:
a source line; and
a transistor controllable by a word line and coupled to the source line.
13. The memory device of claim 12, wherein the MTJ device on the back side comprises an SOT electrode comprising a spin hall effect material and a free magnetic layer in direct contact with the SOT electrode, wherein the SOT electrode defines one end of the MTJ device and is coupled to the write bit line; and a top electrode defines an opposite end of the MTJ device and is coupled to the read bit line.
14. The memory device of claim 12 or 13, wherein one of the drain/source terminals of the transistor on the front side is coupled to the SOT electrode on the back side through a via in the substrate.
15. The memory device of claim 14, wherein the punch-through via is connected to a via pedestal in contact with one end of the MTJ device.
16. The memory device of claim 12 or 13, wherein the memory device comprises a three terminal device, wherein the read bit line and the write bit line on the backside form a first terminal and a second terminal, and the source line forms a third terminal.
17. The memory device of claim 12 or 13, wherein one of the drain/source terminals of the transistor on the front side is coupled to the SOT electrode on the back side through the substrate and the other of the source/drain terminals is coupled to the source line on the front side.
18. The memory device of claim 12 or 13, wherein the word line is coupled to a gate terminal of a transistor.
19. The memory device of claim 12 or 13, wherein the memory device comprises a 1T-1MTJ Magnetic Random Access Memory (MRAM).
20. The memory device of claim 19, wherein the MTJ device comprises an SOT electrode comprising GSHE material.
21. The memory device of claim 20, wherein the GSHE material includes at least one of β -tantalum (β -Ta), β -tungsten (β -W), Pt, Hf, Ir, Bi, and doped Cu.
22. The memory device of claim 20, wherein the MTJ device comprises a free magnetic layer coupled with the SOT electrode, wherein the SOT electrode is coupled to a write bit line; and an opposite end of the MTJ device is coupled to a read bit line.
23. The memory device of claim 22, wherein the material stack comprising the MTJ device further comprises: a tunneling barrier, a fixed magnetic layer, a coupling layer, a Synthetic Antiferromagnet (SAF)/pinning layer, and a top electrode.
24. A method of fabricating an integrated circuit device, the method comprising:
forming a first substrate and a second substrate;
performing front-end processing on the first substrate to form a transistor;
performing backend processing over the transistor to form a first contact and a conductive backend layer on the first substrate;
performing front-end processing on the second substrate to form a Magnetic Tunnel Junction (MTJ);
performing back end processing over the MTJ to form a second contact and a conductive back end layer on the second substrate; and
attaching the MTJ from the second substrate to the first substrate.
25. The method of claim 24, further comprising: coupling one of the drain/source terminals of the transistor on a front side of the first substrate to the MTJ on a back side of the first substrate using a through via in the first substrate.
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit structures, and in particular, to the field of Magnetic Tunnel Junction (MTJ) integration on the back side of silicon.
Background
Scaling of features in integrated circuits has been a driving force behind the ever-growing semiconductor industry for the past decades. Scaling to smaller and smaller features enables the maximum density of functional units to be achieved on the limited chip area of a semiconductor chip. For example, shrinking transistor size allows an increased number of memory devices to be incorporated onto a chip, thereby producing a product with improved functionality. However, the driving of more and more functions is not without problems. The necessity to optimize the performance of each device becomes increasingly important.
Non-volatile embedded memory (e.g., on-chip embedded memory with non-volatility) enables energy and computational efficiency. However, leading edge embedded memory options, such as spin transfer torque magnetoresistive random access memory (STT-MRAM), may suffer from high voltage and high current density issues during programming (writing) of the cell. The density limitation of STT-MRAM can be attributed to the large write switching current and select transistor requirements. In particular, conventional STT-MRAM has cell size limitations due to the need for the drive transistor to provide sufficient spin current. Furthermore, such memories are associated with the large write current (>100 μ Α) and voltage (>0.7V) requirements of conventional Magnetic Tunnel Junction (MTJ) based devices. Specifically, this manifests itself as i) high write error rates or low speed switching (over 20ns) in MRAM based Magnetic Tunnel Junctions (MTJ), and reliability issues due to tunnel currents in the magnetic tunnel junctions.
Thus, significant improvements are still needed in MTJ-based non-volatile memory arrays.
Drawings
FIG. 1 shows a two terminal 1T-1MTJ (magnetic tunnel junction) bit cell for STT-MRAM.
FIG. 2A illustrates an integrated circuit including a 1T-1MTJ MRAM bit cell having a MOBS according to one embodiment of the disclosure.
FIG. 2B illustrates a typical material stack for a 1T-1MTJ bit cell based on GSHE Spin Orbit Torque (SOT) switching according to one embodiment of the present disclosure.
Fig. 2C is a top view of the device of fig. 2B.
Fig. 2D is a sectional view of the SOT electrode showing directions of spin current and charge current determined by SOT in metal.
FIG. 3 illustrates a memory device including a 1T-1MTJ MRAM bit cell with a MOBS in more detail according to one embodiment of the disclosure.
FIG. 4 is a top view of a layout of a cross-sectional view of a 1T-1MTJ MRAM bit cell with a MOBS according to one embodiment of the present disclosure.
FIG. 5 is a cross-sectional view of the 1T-1MTJ MRAM bit cell with the MOBS along line cross-sectional line AA of FIG. 4.
FIG. 6 is a graph of write energy-delay conditions for a 1T-1MTJ MRAM bit cell compared to a conventional MTJ according to one embodiment.
FIG. 7 is a graph of reliable write times for a 1T-1MTJ MRAM bit cell with a MOBS and a conventional MTJ according to one embodiment.
FIG. 8 is a flow chart representing various operations in a method of fabricating a 1T-1MTJ memory device having a MOBS according to embodiments disclosed herein.
Fig. 9A and 9B illustrate a wafer composed of a semiconductor material and including one or more dies having Integrated Circuit (IC) structures formed on a surface of the wafer.
FIG. 10 is a cross-sectional side view of an Integrated Circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a 1T-1MTJ memory device with a MOBS.
FIG. 11 illustrates a computing device according to one implementation of the present disclosure.
Detailed Description
Embodiments of a filter layer for Magnetic Tunnel Junction (MTJ) integration on the back side of silicon are described. In the following description, numerous specific details are set forth, such as specific materials and processing schemes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, have not been described in detail to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. In some instances, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
Certain terminology is also used in the following description for reference purposes only, and thus these terms are not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "bottom," "top," and the like refer to the orientation in which reference is made in the drawings. Terms such as "front," "back," "rear," and "side," describe the orientation and/or position of portions of the component within a consistent but arbitrary frame of reference as may be clearly understood by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
Embodiments described herein may relate to front end of line (FEOL) semiconductor processing and structures. FEOL is the first part of Integrated Circuit (IC) fabrication in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or semiconductor layer. FEOL generally covers all processes up to (but not including) the deposition of metal interconnect layers. The result is typically a wafer with isolated transistors (e.g., without any conductive lines) immediately after the final FEOL operation.
Embodiments described herein may relate to back end of line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring (e.g., one or more metallization layers) on a wafer. The BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the fabrication stage, contacts (pads), interconnect lines, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.
The embodiments described below may be applicable to FEOL processes and structures, BEOL processes and structures, or to both FEOL and BEOL processes and structures. In particular, although exemplary processing schemes may be illustrated using FEOL processing scenarios, such schemes may be equally applicable to BEOL processing. In particular, although exemplary processing schemes may be illustrated using BEOL processing scenarios, such schemes may be equally applicable to FEOL processing.
One or more embodiments of the invention relate to Magnetic Tunnel Junction (MTJ) integration on the back side of silicon. Common applications for such arrays include, but are not limited to, embedded memories, magnetic tunnel junction architectures, MRAM, non-volatile memory, spin hall effect, spin torque memory, and embedded memories using magnetic storage devices.
More specifically, one or more embodiments of MTJ (magnetic tunnel junction) MRAM (magnetic random access memory) bit cells with Metallization (MOBS) on both sides are described. In one embodiment, the bitcell is fabricated on two sides of a substrate having a front side and a back side, with the first conductive line on the back side and the second conductive line on the front side. The transistor is between the second conductor and the substrate on the front side. A Magnetic Tunnel Junction (MTJ) is between the first conductive line and the substrate on the backside, wherein one end of the MTJ is coupled to the transistor through the substrate and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side. In one embodiment, the bit line is a 1T (one transistor) -1MTJ bit cell with Metal (MOBS) on both sides. Embodiments also describe a layout of a 1T-1MTJ bit cell with a MOBS.
To provide context, FIG. 1 shows a two terminal 1T-1MTJ (magnetic tunnel junction) bit
The 1T-
In accordance with one or more embodiments, an improved implementation for MTJ (magnetic tunnel junction) MRAM (magnetic random access memory) is provided that involves a 1T-1MTJ MRAM bit cell with Metal (MOBS) on both sides, as shown in fig. 2A.
FIG. 2A shows an integrated circuit including a 1T-1MTJ
The 1T-
FIG. 2B illustrates an
The MTJ essentially acts as a resistor, wherein the resistance of an electrical path through the MTJ can exist in two resistance states, either "high" or "low," depending on the direction or orientation of magnetization in the free magnetic layer as well as the fixed magnetic layer. In the case where the directions of magnetization in the free magnetic layer and the fixed magnetic layer closest thereto are substantially opposite or antiparallel to each other, a high resistance state exists. In the case where the directions of magnetization in the coupled free magnetic layer and the fixed magnetic layer closest thereto are substantially aligned or parallel to each other, a low resistance state exists. It should be understood that the terms "low" and "high" are relative to each other with respect to the resistance state of the MTJ. In other words, the high resistance state is only detectable more than the low resistance state and vice versa. Thus, with the detectable difference in resistance, the low resistance state and the high resistance state can represent different bits of information (i.e., "0" or "1").
In certain aspects, and in at least some embodiments of the invention, certain terms retain certain definable meanings. For example, a "free" layer magnetic layer is a magnetic layer that stores a calculable variable. A "fixed" magnetic layer is a magnetic layer having a fixed magnetization (magnetically harder than the free magnetic layer). The free layer and the fixed layer may be ferromagnetic layers. In one embodiment, the free layer may be complex and made of two separate magnetic layers with a coupling layer located therebetween. In one embodiment, the fixed layer is complex and made of two magnets with a coupling layer located between them. In yet another embodiment, both the free layer and the fixed layer may be complex. The tunneling barrier material is a material located between the free magnetic layer and the fixed magnetic layer. The SAF/pinning layer allows for cancellation of the dipole field around the free magnetic layer. The coupling layer assists the SAF/pinning layer in pinning the fixed layer and centers the hysteresis loop by overcoming the dipole field between the fixed magnetic layer and the free magnetic layer. In one embodiment, the coupling layer may comprise Ru, Ir, W, or Ta.
A wide range of material combinations may be used for the material stack of the 1T-
Fig. 2C is a
Fig. 2D is a sectional view of the
Wherein the content of the first and second substances,
is the spin Hall injection efficiency as the ratio of the amplitude of the transverse spin current to the lateral charge current, w is the width of the magnet, t is the thickness λ of the GSHE metal electrodesfIs the spin flip length in the GSHE metal, and θ GSHE is the spin hall angle of the GSHE metal relative to the FM1 interface. By passingGiving an injected spin angular momentum that causes spin torque.FIG. 3 illustrates in more detail a memory device including a 1T-1MTJ MRAM bit cell 300 with a MOBS, where like components to those of FIG. 2A have like reference numerals, but are not limited thereto, according to one embodiment of the disclosure. MRAM bit cell 300 is fabricated on both the front side 204 and the back side 206 of
In accordance with the disclosed embodiment, the
In one embodiment, one of the drain/source terminals of the
In one embodiment, to write data to the
FIG. 4 is a top view of a layout of a cross-sectional view of a 1T-1MTJ MRAM bit cell with a MOBS according to one embodiment of the present disclosure. The
FIG. 5 is a cross-sectional view of a 1T-1MTJ MRAM bit cell having a MOBS along line cross-sectional line AA of FIG. 4, wherein like components of FIG. 4 have like reference numerals. The cross-sectional view of the
FIG. 6 is a
wherein R iswriteIs the write resistance of the device (RGSHE or RMTJ-P, RMTJ-AP), "P" is the spin current polarization (PGSHE or PMTJ), μ0Is the vacuum permeability and "e" is the electron charge. The energy at a given delay is proportional to the square of the Gilbert damping. For various GSHE metal electrodes, τ is the change in spin polarization0=MsVe/IcPμBChanges also occur. The combined effect of spin hall polarization, damping and resistivity of the spin hall electrode is plotted in
All cases considered in
(τd<MsVe/IcPμB) (4)
in region 2, the energy is proportional to the delay, which is expressed as:
τd>MsVe/IcPμB (5)
the two regions are separated by an energy minimum at:
τopt=MsVe/IcPμB (6)
wherein a minimum switching energy is obtained for a spin torque device.
The energy-delay trajectory (
FIG. 7 is a
FIG. 8 is a flow chart representing various operations in a method of fabricating a 1T-1MTJ memory device having a MOBS according to embodiments disclosed herein. As previously described, the fabrication techniques of the 1T-1MTJ memory device will be implemented in the context of a MOBS scheme. In some such embodiments, the MOBS scheme may be implemented by forming a first multilayer substrate and a second multilayer substrate comprising a bulk wafer (e.g., bulk silicon) or a semiconductor-on-insulator wafer (e.g., silicon-on-insulator or SOI wafer) (block 800).
Standard front-end processing may then be performed on the first substrate to form as many semiconductor devices (e.g., transistors) as desired (block 802).
Standard back-end processing may then be performed over the transistors to form contacts and as many metal (or otherwise conductive) back-end layers as desired on the first substrate (block 804). In some embodiments, the front side via or contact may be processed very deep, for example, into at least a portion of the substrate below the device layer, as the deep processed via may be used to make through-wafer contact between the drain of the transistor and the MTJ.
Thereafter, standard front end processing may be performed on the second substrate as many semiconductor devices (e.g., MTJs) are formed as desired (block 806). In an embodiment, the SOI electrode of the MTJ is formed in the dielectric layer by a damascene or dual damascene process as is well known in the art. In an embodiment, the SOI electrode may comprise a Giant Spin Hall Effect (GSHE) metal made of beta-tantalum (beta-Ta), beta-tungsten (beta-W), Pt, copper (Cu) doped with an element such as iridium, bismuth, and any of the elements in the 3d, 4d, 5d, and 4f, 5f periodic groups of the periodic table.
In one embodiment, a MTJ material stack is formed on an SOI electrode. In one embodiment, the MTJ material stack and the material layer stack are blanket deposited. The layers of the MTJ stack may be formed by a sputter deposition technique at a deposition rate
Within the range. Such techniques include Physical Vapor Deposition (PVD), especially planar magnetron sputtering, and ion beam deposition. In an embodiment, the MTJ stack may be subjected to an annealing process performed at a temperature between 300 degrees celsius and 400 degrees celsius. In an embodiment, the layers of the material layer stack may be blanket deposited by an evaporation process, an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process, respectively. In an embodiment, the chemical vapor deposition process is augmented by a plasma technique (e.g., RF glow discharge)Strong (plasma enhanced CVD) to improve film density and uniformity. In an embodiment, the uppermost layer of the material layer stack may comprise a top electrode layer which eventually acts as a hard mask.The deposition process may be configured to control the magnetic properties of the magnetic layer. For example, the direction of the magnetic anisotropy of the ferromagnetic material may be set during layer deposition by applying a magnetic field across the substrate. The resulting uniaxial anisotropy is observed as a magnetic easy direction and a magnetic hard direction in the magnetization of the layer. Since the anisotropy axis affects the switching behavior of the material, the deposition system must be able to project a uniform magnetic field, typically in the range of 20-100Oe, across the substrate during deposition. The deposition process is capable of controlling other magnetic properties, such as coercivity and magnetostriction, by selecting the magnetic alloy and deposition conditions. Since the switching field of the patterned bit depends directly on the thickness of the free layer magnet, thickness uniformity and repeatability must meet stringent requirements.
Standard back end processing may then be performed over the MTJ to form contacts and as many metal (or otherwise conductive) back end layers as desired on the second substrate (block 808). For example, a bit line may be patterned on the uppermost surface of the top electrode of the MTJ to complete the formation of the memory cell. In an embodiment, the bit line may include a conductive material such as W, TiN, TaN, or Ru. In an embodiment, the bit lines are formed by using a dual damascene process (not shown) and include a barrier layer such as Ru, Ta, or Ti and a fill metal such as W or Cu.
Thereafter, the MTJ from the second substrate is attached to the first substrate (block 810). In one exemplary process flow, this may be accomplished as follows. The MTJ stack is formed over a transfer layer on a second substrate. Then, a temporary substrate is formed on top of the second substrate. Thereafter, the second substrate is separated from the MTJ stack at the transfer layer. Thereafter, the MTJ stack with the temporary substrate thereon is attached to a first substrate having device layers including transistors formed thereon. The transfer layer of the temporary wafer is then removed, for example by etching.
In one embodiment, the MTJ from the second substrate may be attached to the first substrate prior to back end processing (block 808). In another embodiment, the MTJ may be fabricated on a first substrate and the transistor fabricated on a second substrate. In embodiments where the substrate is a wafer, respective dies from the first wafer and the second wafer may be bonded together. The die may be bonded using any suitable wafer bonding process known to those of ordinary skill in the art.
The transistors in each 1T-1MTJ bit cell with MOBS are connected to word lines and source lines in a manner that will be understood by those skilled in the art. The 1T-1MTJ bit cell with the MOBS can also include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), etc., for operation of the 1T-1MTJ bit cell with the MOBS, as will be understood by those skilled in the art. It should be appreciated that a plurality of 1T-1MTJ bit cells with MOBS are operatively connected to one another to form a memory array (not shown), wherein the memory array may be incorporated into a non-volatile memory device.
Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon, and silicon-on-insulator (SOI) and similar substrates formed of other semiconductor materials. Depending on the manufacturing stage, semiconductor substrates often include transistors, integrated circuits, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not shown, the structures described herein may be fabricated on an underlying lower-level back-end-of-line (BEOL) interconnect layer. For example, in one embodiment, the embedded non-volatile memory structure is formed on a material composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.
Referring to fig. 9A and 9B, a
The embodiments disclosed herein may be used to fabricate a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be fabricated. Furthermore, integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics. The integrated circuit may be coupled to a bus and other components in the system. For example, the processor may be coupled to the memory, chipset, etc. by one or more buses. It is possible to manufacture each of the processors, memories, and chipsets using the approaches disclosed herein.
Fig. 10 is a cross-sectional side view of an Integrated Circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a 1T-1MTJ memory device with a MOBS in accordance with one or more of the embodiments disclosed herein.
Referring to fig. 10, an
In some embodiments,
The
The package-on-
The
The
FIG. 11 illustrates a
Depending on its application, the
The
The processor 1104 of the
The
In other implementations, another component housed within the
In various implementations, the
Thus, embodiments described herein include embedded non-volatile memory structures having 1T-1MTJ memory device elements with MOBSs
The above description of illustrated embodiments of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
These modifications can be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
The following examples relate to other embodiments. Various features of the different embodiments may be combined in various ways, including some features and excluding other features, to accommodate a wide variety of different applications.
Exemplary embodiment 1: a memory device includes a substrate having a front side and a back side, wherein first conductive lines are on the back side and second conductive lines are on the front side. A transistor is between the second conductive line and a substrate on the front side. A Magnetic Tunnel Junction (MTJ) is between a first conductive line and a substrate on a backside, wherein one end of the MTJ is coupled to the transistor through the substrate and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to a second conductive line on the front side.
Exemplary embodiment 2: the memory device of example embodiment 1, wherein an MTJ is connected to the drain of the transistor and the source of the transistor is coupled to the second conductive line.
Exemplary embodiment 3: the memory device of claim 1 or 2, wherein the MTJ is connected to the drain of the transistor using a through via extending through the substrate from the front side to the back side.
Exemplary embodiment 4: the memory device of claim 3, wherein a gate of the transistor is coupled to a word line.
Example embodiment 5 the memory device of claim 1, 2 or 3, wherein the first conductive line comprises a bit line and the second conductive line comprises a source line.
Exemplary embodiment 6: the memory device of claim 5, wherein the bit lines include a read bit line and a write bit line.
Exemplary embodiment 7: the memory device of claim 1, 2, 3, 4, 5, or 6, wherein the memory device comprises a 1T-1MTJ Magnetic Random Access Memory (MRAM).
Exemplary embodiment 8: the memory device of claim 1, 2, 3, 4, 5, 6, or 7, wherein the MTJ device comprises an SOT electrode comprising GSHE material.
Exemplary embodiment 9: the memory device of claim 8, wherein the GSHE material includes at least one of β -tantalum (β -Ta), β -tungsten (β -W), Pt, Hf, Ir, Bi, and doped Cu.
Exemplary embodiment 10: the memory device of claim 1, 2, 3, 4, 5, 6, 7, 8, or 9, wherein the MTJ device comprises a free magnetic layer coupled with the SOT electrode, wherein the SOT electrode is coupled to a write bit line; and an opposite end of the MTJ device is coupled to a read bit line.
Exemplary embodiment 11: the memory device of
Exemplary embodiment 12: a memory device includes a substrate. The backside of the substrate includes read and write bit lines and a Magnetic Tunnel Junction (MTJ) device. The front side of the substrate includes a source line, and a transistor controllable by a word line and coupled to the source line.
Exemplary embodiment 13: the memory device of claim 12, wherein the MTJ device on the back side comprises a write electrode comprising a spin hall effect material and a free magnetic layer in direct contact with an SOT electrode, wherein the SOT electrode defines one end of the MTJ device and is coupled to the write bit line; and a top electrode defines an opposite end of the MTJ device and is coupled to the read bit line.
Exemplary embodiment 14: the memory device of claim 12 or 13, wherein one of the drain/source terminals of the transistor on the front side is coupled to the SOT electrode on the back side through a via in the substrate.
Exemplary embodiment 15: the memory device of claim 14, wherein the through via is connected to a via pedestal in contact with one end of the MTJ device.
Exemplary embodiment 16: the memory device of claim 12, 13, 14 or 15, wherein the memory device comprises a three terminal device, wherein read and write bit lines on the backside form a first terminal and a second terminal, and the source line forms a third terminal.
Exemplary embodiment 17: the memory device of claim 12, 13, 14, 15 or 16, wherein one of the drain/source terminals of the transistor on the positive side is coupled through the substrate to the SOT electrode on the back side and the other of the source/drain terminals is coupled to the source line on the positive side.
Exemplary embodiment 18: the memory device of claim 12, 13, 14, 15, 16, or 17, wherein the word line is coupled to a gate terminal of a transistor.
Exemplary embodiment 19: the memory device of claim 12, 13, 14, 15, 16, 17, or 18, wherein the memory device comprises a 1T-1MTJ Magnetic Random Access Memory (MRAM).
Exemplary embodiment 20: the memory device of claim 12, 13, 14, 15, 16, 17, 18, or 19, wherein the MTJ device comprises an SOT electrode comprising GSHE material.
Exemplary embodiment 21: the memory device of
Exemplary embodiment 22: the memory device of
Exemplary embodiment 23: the memory device of claim 22, wherein the material stack comprising the MTJ device further comprises: a tunneling barrier, a fixed magnetic layer, a coupling layer, a Synthetic Antiferromagnet (SAF)/pinning layer, and a top electrode.
Exemplary embodiment 24: a method of manufacturing an integrated circuit device includes forming a first substrate and a second substrate. Front end processing is performed on the first substrate to form a transistor. Back-end processing is performed over the transistors to form first contacts and conductive back-end layers on the first substrate. Performing front-end processing on the second substrate to form a Magnetic Tunnel Junction (MTJ), performing back-end processing over the MTJ to form a second contact and a conductive back-end layer on the second substrate. Thereafter, the MTJ from the second substrate is attached to the first substrate.
Exemplary embodiment 25: the method of claim 24, further comprising: coupling one of the drain/source terminals of the transistor on the front side of the first substrate to the MTJ on the back side of the first substrate using a through via in the first substrate.
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