Memory device, integrated circuit and method of manufacturing memory device
阅读说明:本技术 存储器装置、集成电路及制造存储器装置的方法 (Memory device, integrated circuit and method of manufacturing memory device ) 是由 陈升照 萧清泰 蔡正原 匡训冲 于 2018-10-12 设计创作,主要内容包括:本发明实施例涉及一种存储器装置、集成电路及制造存储器装置的方法。所述存储器装置包括磁阻式随机存取存储器(MRAM)单元、侧壁间隙壁以及上部内连线。磁阻式随机存取存储器(MRAM)单元设置在衬底上。MRAM单元包括设置在下部电极与上部电极之间的磁性隧道结(MTJ)。侧壁间隙壁沿MRAM单元的相对侧壁排列。上部内连线沿从侧壁间隙壁的第一外边缘连续延伸到侧壁间隙壁的第二外边缘的界面与上部电极的上表面直接接触。(Embodiments of the invention relate to a memory device, an integrated circuit and a method of manufacturing a memory device. The memory device includes a Magnetoresistive Random Access Memory (MRAM) cell, a sidewall spacer, and an upper interconnect. Magnetoresistive Random Access Memory (MRAM) cells are disposed on a substrate. The MRAM cell includes a Magnetic Tunnel Junction (MTJ) disposed between a lower electrode and an upper electrode. Sidewall spacers are arranged along opposing sidewalls of the MRAM cell. The upper interconnect is in direct contact with the upper surface of the upper electrode along an interface extending continuously from the first outer edge of the sidewall spacer to the second outer edge of the sidewall spacer.)
1. A memory device, comprising:
a magnetoresistive random access memory cell disposed on a substrate, wherein the magnetoresistive random access memory cell comprises a magnetic tunnel junction disposed between a lower electrode and an upper electrode;
sidewall spacers arranged along opposing sidewalls of the MRAM cell; and
an upper interconnect directly contacting an upper surface of the upper electrode and an upper surface of the sidewall spacer.
2. The memory device of claim 1, wherein the upper interconnect directly contacts a sidewall of the upper electrode.
3. The memory device of claim 1, further comprising:
a first interlayer dielectric layer comprising a first dielectric material surrounding the MRAM cell and the upper interconnect; and
a second interlevel dielectric layer comprising a second dielectric material disposed over the first interlevel dielectric layer and surrounding the upper interconnect, wherein the first dielectric material is a different material than the second dielectric material.
4. The memory device of claim 3, further comprising:
an interconnect within a logic region and disposed over the substrate, wherein the second interlayer dielectric surrounds the interconnect, and wherein the first interlayer dielectric is not within the logic region.
5. The memory device of claim 1, further comprising:
a first conductive via disposed over the top interconnect; and
a first conductive line disposed over the first conductive via, wherein the first conductive line extends beyond sidewalls of the first conductive via, wherein the first conductive via is laterally aligned between sidewalls of the upper interconnect.
6. An integrated circuit, comprising:
a first dielectric layer disposed over the semiconductor substrate;
a magnetoresistive random access memory cell disposed over the first dielectric layer, wherein the magnetoresistive random access memory cell comprises a magnetic tunnel junction disposed between a bottom electrode and a top electrode;
a first sidewall spacer comprising a first material that contacts an outermost sidewall of the top electrode, wherein a bottom surface of the first sidewall spacer contacts an upper surface of the bottom electrode;
a second sidewall spacer comprising a second material, an inner sidewall of the second material contacting an outermost sidewall of the first sidewall spacer, wherein a bottommost surface of the second sidewall spacer contacts a top surface of the first dielectric layer, and wherein the first material is different from the second material; and
an interconnect contacting the top surface of the top electrode, the first sidewall spacer and the second sidewall spacer.
7. The integrated circuit of claim 6, wherein a bottom surface of the interconnect is defined by an interface extending continuously from a first outermost edge of the second sidewall spacer to a second outermost edge of the second sidewall spacer when viewed in cross-section.
8. A method of manufacturing a memory device, comprising:
forming sidewall spacers around magnetoresistive random access memory cells located in a memory array region, wherein the magnetoresistive random access memory cells comprise a magnetic tunnel junction disposed between a lower electrode and an upper electrode;
forming a first interlayer dielectric layer on the sidewall spacer;
forming a second interlayer dielectric layer over the first interlayer dielectric layer;
forming a dielectric layer over the second interlayer dielectric layer;
performing a first etch process to define a hole directly above the upper electrode, wherein the first etch process removes a portion of the first interlayer dielectric layer, a portion of the second interlayer dielectric layer, a portion of the dielectric layer, and a portion of the sidewall spacer; and
forming an interconnect within the hole, wherein the interconnect directly contacts the top electrode and the sidewall spacer.
9. The method of manufacturing a memory device of claim 8, wherein the sidewall spacer further comprises:
a first sidewall spacer comprising a first material in direct contact with an outer sidewall of the upper electrode;
a second sidewall spacer comprising a second material in direct contact with an outer sidewall of the first sidewall spacer, wherein the first material is different from the second material; and
wherein the first etching process etches more of the first sidewall spacer than the second sidewall spacer, such that the height of the second sidewall spacer is greater than the height of the first sidewall spacer.
10. The method of manufacturing a memory device according to claim 8, further comprising:
forming a second interconnect within a logic region, wherein the second interlayer dielectric layer is disposed over the second interconnect, and wherein the first interlayer dielectric layer is not within the logic region;
forming a first conductive via over the second interconnect; and
a first conductive line is formed over the first conductive via, wherein the first conductive line extends beyond a sidewall of the first conductive via.
Technical Field
Embodiments of the invention relate to a memory device, an integrated circuit and a method of manufacturing a memory device.
Background
Many modern electronic devices contain electronic memory. The electronic memory may be a volatile memory (volatile memory) or a non-volatile memory (non-volatile memory). Non-volatile memories can retain their stored data when power is removed, while volatile memories lose their stored data when power is removed. Magnetoresistive random-access memory (MRAM) is considered a promising candidate for next-generation non-volatile electronic memories due to its advantages over current electronic memories. MRAM is generally faster and has higher endurance than current non-volatile memories, such as flash random-access memory (flash-random-access memory). MRAM typically has similar performance and density, but lower power consumption, than current volatile memories, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).
Disclosure of Invention
According to some embodiments of the present invention, a memory device is provided. The memory device includes a magnetoresistive random access memory cell, a sidewall spacer, and an upper interconnect. The magnetoresistive random access memory cell is disposed on a substrate. The magnetoresistive random access memory cell includes a magnetic tunnel junction disposed between a lower electrode and an upper electrode. Sidewall spacers are arranged along opposing sidewalls of the mram cell. The upper interconnect directly contacts the upper surface of the upper electrode and the upper surface of the sidewall spacer.
According to further embodiments of the present invention, an integrated circuit is provided. The integrated circuit includes a first dielectric layer, a MRAM cell, a first sidewall spacer, a second sidewall spacer, and an interconnect. A first dielectric layer is disposed over the semiconductor substrate. The MRAM cell is disposed on the first dielectric layer. The magnetoresistive random access memory cell includes a magnetic tunnel junction disposed between a bottom electrode and a top electrode. A first sidewall spacer comprising a first material in contact with an outermost sidewall of the top electrode. The bottom surface of the first sidewall spacer contacts the upper surface of the bottom electrode. The second sidewall spacer comprises a second material. The inner sidewall of the second material contacts an outermost sidewall of the first sidewall spacer. The bottommost surface of the second sidewall spacer contacts the top surface of the first dielectric layer. The first material is different from the second material. The interconnect contacts the top surface of the top electrode, the first sidewall spacer and the second sidewall spacer.
According to still further embodiments of the present invention, a method of manufacturing a memory device is provided. The method comprises the following steps: forming sidewall spacers around magnetoresistive random access memory cells located in a memory array region, the magnetoresistive random access memory cells comprising a magnetic tunnel junction disposed between a lower electrode and an upper electrode; forming a first interlayer dielectric layer on the sidewall spacer; forming a second interlayer dielectric layer on the first interlayer dielectric layer; forming a dielectric layer on the second interlayer dielectric layer; performing a first etching process to define a hole right above the upper electrode, the first etching process removing a portion of the first interlayer dielectric layer, a portion of the second interlayer dielectric layer, a portion of the dielectric layer, and a portion of the sidewall spacer; forming an interconnect in the hole, the interconnect directly contacting the top electrode and the sidewall spacer.
Drawings
Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A illustrates a cross-sectional view of a memory device (or referred to as an integrated circuit) including an MRAM cell having a Magnetic Tunneling Junction (MTJ), according to some embodiments of the present disclosure.
Fig. 1B illustrates a top view of a plurality of memory devices including MRAM cells with Magnetic Tunnel Junctions (MTJs), according to some embodiments of the present disclosure.
Fig. 2 illustrates a cross-sectional view of a memory device including an MRAM cell having a Magnetic Tunnel Junction (MTJ), according to some embodiments of the present disclosure.
Fig. 3 illustrates a cross-sectional view of a memory device including a recessed memory region and a logic region, the recessed memory region including two MRAM cells each having a Magnetic Tunnel Junction (MTJ), according to some embodiments of the present disclosure.
Fig. 4-11 illustrate cross-sectional views of methods of forming a memory device including a recessed memory region and a logic region, the recessed memory region including MRAM cells having MTJs, according to some embodiments of the present disclosure.
Figure 12 illustrates, in flow diagram form, a method of forming a memory device including an embedded memory region including MRAM cells with MTJs and a logic region in accordance with some embodiments of the present disclosure.
Detailed Description
The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, for ease of description, spatially relative terms such as "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.
Embedded (embedded) magnetoresistive random-access memory (MRAM) cells are typically disposed in an embedded memory region adjacent to a logic region including transistor devices, such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In the embedded memory region, the MRAM cells are typically located above the substrate within an inter-level dielectric (ILD) structure that surrounds the stacked interconnect layers. The MRAM cell includes a Magnetic Tunnel Junction (MTJ) arranged between a top electrode and a bottom electrode. The bottom electrode is coupled to the stacked interconnect layer by a bottom electrode via, and the top electrode is coupled to the stacked interconnect layer by a top electrode via. Within the logic region, a stacked interconnect layer is coupled to the transistor device and has an interconnect via laterally offset relative to the MRAM cell.
In conventional MRAM cell fabrication, the top electrode via is formed by: an inter-level dielectric (ILD) layer disposed over the top electrode is etched to form a via hole (via hole) in the top electrode. The via is then filled with one or more conductive materials. Next, a photoresist mask is formed over the conductive material and patterned using the photoresist mask to form a top electrode via landing on the top electrode. Subsequently, an overlying metal line is formed within the second ILD layer overlying the top electrode via and over the interconnect via of the logic region.
It is known that after coupling the top electrode via to the overlying metal line, the thickness of the metal line over the MRAM cell in the embedded memory region is less than the thickness of the metal line over the interconnect via in the logic region. The small thickness of the metal lines on the MRAM cells can cause processing problems. For example, the overlying metal lines are typically formed using a damascene process (damascene) that performs a chemical-mechanical planarization (CMP) process after filling trenches in the second ILD layer with a conductive material. However, if the metal lines overlying the MRAM cells are too thin (e.g., less than about 400 angstroms), the CMP process window is small and may cause damage to the top electrode of the MRAM cells.
The present disclosure relates in some embodiments to a method of forming an MRAM cell that directly couples a top electrode of the MRAM cell to an overlying interconnect layer. Directly coupling the top electrode of the MRAM cell to the overlying interconnect layer provides a relatively thick metal line layer (e.g., having a thickness greater than or equal to about 600 angstroms), thereby eliminating potential processing issues related to the thickness of the interconnect layer. This also eliminates the steps and materials used to form the top electrode via, thereby simplifying the fabrication of the MRAM cell and reducing the cost of the MRAM cell. For example, forming the interconnect layer directly on the top electrode can save two photomasks (photomasks) compared to MRAM cells using top electrode vias.
Referring to fig. 1A, a cross-sectional view of a
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FIG. 1B illustrates a top view of some additional embodiments of memory device 100B.
Fig. 2 shows a cross-sectional view of some additional embodiments of a
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Fig. 3 shows a cross-sectional view of a
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Fig. 4-11 illustrate cross-sectional views 400-1100 of methods of forming a memory device including an embedded memory region and a logic region, the embedded memory region including MRAM cells and MTJs, according to some embodiments of the present disclosure. Although the
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In some embodiments, the etch process etches the
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As shown in cross-sectional view 900 of fig. 9, an etch process is performed to etch the third dielectric (704 of fig. 8), the second dielectric (702 of fig. 8), the third ILD layer (602 of fig. 8), the second ILD layer (404 of fig. 8), and the second sidewall spacer layer (402 of fig. 8) and to define the third
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Fig. 12 illustrates a
At 1202, a first interconnect is formed within a first interlayer dielectric (ILD) layer over a substrate. Fig. 4 illustrates a
At 1204, an MRAM cell is formed over the first interconnect within the memory array region, the MRAM cell including a Magnetic Tunnel Junction (MTJ) disposed between a lower electrode and an upper electrode. Fig. 4 illustrates a
At 1206, a sidewall spacer layer is formed over the MRAM cell. Fig. 4 illustrates a
At 1208, a second ILD layer is formed over the sidewall spacer layer. Fig. 4 illustrates a
At 1210, a third ILD layer is formed over the second ILD layer. Fig. 6 illustrates a
At 1212, a dielectric layer is formed over the third ILD layer. Fig. 7 illustrates a
At 1214, openings are formed in the second ILD layer, third ILD layer and dielectric layer directly over the upper electrodes. Fig. 9 illustrates a cut-away view 900 corresponding to some embodiments of
At 1216, a second interconnect is formed within the opening, the interconnect directly contacting the upper electrode. Fig. 10 illustrates a
At 1218, a conductive via is formed within the fourth ILD layer over the second interconnect. Figure 11 illustrates a
Accordingly, in some embodiments, the present disclosure relates to a method of forming an MRAM cell, the method comprising forming an interconnect directly on a top surface of a top electrode of the MRAM cell.
In some embodiments, the present disclosure relates to a memory device. The memory device includes a Magnetoresistive Random Access Memory (MRAM) cell, a sidewall spacer, and an upper interconnect. Magnetoresistive Random Access Memory (MRAM) cells are disposed on a substrate. The MRAM cell includes a Magnetic Tunnel Junction (MTJ) disposed between a lower electrode and an upper electrode. Sidewall spacers are arranged along opposing sidewalls of the MRAM cell. The upper interconnect directly contacts the upper surface of the upper electrode along an interface extending continuously from the first outer edge of the sidewall spacer to the second outer edge of the sidewall spacer.
In the above memory device, the upper interconnect directly contacts a sidewall of the upper electrode.
In the above memory device, the sidewall spacer further includes a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes a first material in direct contact with the outer sidewall of the upper electrode. The second sidewall spacer includes a second material in direct contact with the outer sidewall of the first sidewall spacer and extending over the substrate, wherein the first material is different from the second material.
In the above memory device, when viewed in a cross-sectional view, a bottom surface of the upper interconnect is defined by an interface extending continuously from a first outer edge of the first sidewall spacer to a second outer edge of the first sidewall spacer.
In the above memory device, the second height of the second sidewall spacer is greater than the first height of the first sidewall spacer.
The memory device further comprises a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer includes a first dielectric material surrounding the MRAM cell and the upper interconnect. The second interlayer dielectric layer includes a second dielectric material disposed on the first interlayer dielectric layer and surrounding the upper interconnect, wherein the first dielectric material is a different material than the second dielectric material.
In the memory device, an interconnect is disposed in the logic region and above the substrate, wherein the second interlayer dielectric surrounds the interconnect, and wherein the first interlayer dielectric is not disposed in the logic region.
In the above memory device, the sidewall spacer has a first sidewall and a second sidewall, the first sidewall contacts the first interlayer dielectric layer, and the second sidewall is laterally separated from the first interlayer dielectric layer by the second interlayer dielectric layer.
In the above memory device, a first conductive via and a first conductive line are further included. The first conductive via is disposed over the top interconnect. A first conductive line is disposed over the first conductive via, wherein the first conductive line extends beyond a sidewall of the first conductive via.
In the above memory device, the first conductive via is laterally arranged between sidewalls of the upper interconnect.
In the above memory device, the bottom surface of the upper interconnect includes copper in direct contact with the top surface of the upper electrode, and the top surface of the upper electrode includes tungsten. In some other embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes a first dielectric layer, a Magnetoresistive Random Access Memory (MRAM) cell, a first sidewall spacer, a second sidewall spacer, and an interconnect. A first dielectric layer is disposed over the semiconductor substrate. The MRAM cell is disposed over the first dielectric layer. The MRAM cell includes a Magnetic Tunnel Junction (MTJ) disposed between a bottom electrode and a top electrode. A first sidewall spacer comprising a first material in contact with an outermost sidewall of the top electrode. The bottom surface of the first sidewall spacer contacts the upper surface of the bottom electrode. The second sidewall spacer comprises a second material. The inner sidewall of the second material contacts an outermost sidewall of the first sidewall spacer. The bottommost surface of the second sidewall spacer contacts the top surface of the first dielectric layer. The first material is different from the second material. An interconnect contacts the upper surface of the top electrode along an interface extending from a first outermost edge of the first sidewall spacer to a second outermost edge of the first sidewall spacer.
In the integrated circuit, when viewed in cross-section, the bottom surface of the interconnect is defined by an interface extending continuously from the first outermost edge of the second sidewall spacer to the second outermost edge of the second sidewall spacer.
In the integrated circuit, the second height of the second sidewall spacer is greater than the first height of the first sidewall spacer.
The integrated circuit further comprises a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer includes a third material in direct contact with the outer sidewall of the second sidewall spacer, the upper surface of the second sidewall spacer, and the sidewall of the interconnect. The second interlayer dielectric layer includes a fourth material in direct contact with the sidewalls of the interconnect, the outer sidewalls of the first interlayer dielectric layer, the outer sidewalls of the second sidewall spacers, and the top surface of the first dielectric layer. The third material is different from the fourth material.
In the integrated circuit, a first conductive via and a first conductive line are further included. A first conductive via is disposed over the interconnect, wherein the first conductive via extends laterally within a sidewall of the interconnect. A first conductive line is disposed over the first conductive via, wherein the first conductive line extends laterally beyond a sidewall of the first conductive via.
In yet other embodiments, the present disclosure relates to a method of manufacturing a memory device. The method comprises the following steps: forming sidewall spacers around Magnetoresistive Random Access Memory (MRAM) cells located in a memory array region, the MRAM cells including a Magnetic Tunnel Junction (MTJ) disposed between a lower electrode and an upper electrode; forming a first interlayer dielectric (ILD) layer over the sidewall spacers; forming a second ILD layer over the first ILD layer; forming a dielectric layer over the second ILD layer; performing a first etch process to define a hole directly above the upper electrode, the first etch process removing a portion of the first ILD layer, a portion of the second ILD layer, a portion of the dielectric layer, and a portion of the sidewall spacer; forming an interconnect within the hole, the interconnect directly contacting the upper electrode along an interface extending continuously from a first outer edge of the sidewall spacer to a second outer edge of the sidewall spacer.
In the method of manufacturing a memory device, the sidewall spacers further include a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes a first material in direct contact with the outer sidewall of the upper electrode. The second sidewall spacer includes a second material in direct contact with the outer sidewall of the first sidewall spacer, wherein the first material is different from the second material. Wherein the first etching process etches more of the first sidewall spacer than the second sidewall spacer such that the height of the second sidewall spacer is greater than the height of the first sidewall spacer.
In the above method of manufacturing a memory device, the interface extends continuously from the first outer edge of the first sidewall spacer to the second outer edge of the first sidewall spacer from the perspective of the cross-sectional view.
In the method of manufacturing the memory device, a second interconnect is formed in the logic region, wherein the second interlayer dielectric layer is disposed over the second interconnect and the first interlayer dielectric layer is not located in the logic region. A first conductive via is formed over the second interconnect. And forming a first conductive line over the first conductive via, wherein the first conductive line extends beyond a sidewall of the first conductive via.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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