阅读说明：本技术 阵列基板、显示设备和制造阵列基板的方法 (Array substrate, display apparatus and method of manufacturing array substrate ) 是由 班圣光 曹占锋 王珂 刘清召 董水浪 于 2019-08-20 设计创作，主要内容包括：提供了一种阵列基板。阵列基板包括：具有第一子像素阵列的显示区域；和具有第二子像素阵列的部分透明区域。部分透明区域包括被实质上透明的非发光区域彼此间隔开的多个发光区域。第二子像素阵列限于多个发光区域中。阵列基板还包括位于实质上透明的非发光区域中的多个光传感器和多个第一薄膜晶体管。多个光传感器中的对应一个包括第一极性半导体层、第二极性半导体层和将第一极性半导体层与第二极性半导体层连接的本征半导体层。(An array substrate is provided. The array substrate includes: a display area having a first array of subpixels; and a partially transparent region having a second array of sub-pixels. The partially transparent region includes a plurality of light emitting regions spaced apart from one another by substantially transparent non-light emitting regions. The second array of sub-pixels is limited to a plurality of light emitting areas. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light-emitting region. A corresponding one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer with the second polarity semiconductor layer.)

1. An array substrate, comprising:

a display area including a first array of subpixels; and

a partially transparent region comprising a second array of subpixels;

wherein the partially transparent region comprises a plurality of light emitting regions spaced apart from one another by substantially transparent non-light emitting regions;

the second array of subpixels is limited to the plurality of light emitting areas; and is

The array substrate further comprises a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light-emitting region;

wherein a corresponding one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer with the second polarity semiconductor layer; and is

A corresponding one of the plurality of first thin film transistors includes a first gate electrode, a first active layer, and a first source electrode and a first drain electrode respectively connected to the first active layer.

2. The array substrate of claim 1, wherein the intrinsic semiconductor layer and the first active layer are located at a same layer and comprise a same polysilicon material;

the first polarity semiconductor layer is electrically connected with the first source electrode; and is

The second polarity semiconductor layer includes a metal oxide conductive material doped with an N-type dopant.

3. The array substrate of any one of claims 1 to 2, wherein a corresponding one of the plurality of light emitting areas comprises a plurality of sub-pixels of the second sub-pixel array;

the corresponding one of the plurality of light emitting regions is substantially surrounded by one or more of the plurality of light sensors; and is

A plurality of the plurality of photosensors in the substantially transparent non-emitting region are electrically connected in parallel to a same one of the plurality of first thin film transistors.

4. The array substrate of claim 3, wherein in the plurality of light emitting areas of the display area and the partially transparent area, the array substrate comprises a plurality of second thin film transistors for driving light emission in the display area and the plurality of light emitting areas;

wherein, the array substrate still includes: a passivation layer located on a side of the plurality of photosensors, the plurality of first thin film transistors, and the plurality of second thin film transistors away from the substrate; and

one or more layers located on a side of the passivation layer remote from the substrate and confined in the display region and in the plurality of light emitting regions of the partially transparent region;

wherein the one or more layers are not present in the substantially transparent non-light emitting region.

5. The array substrate of any one of claims 1 to 4, wherein the second polarity semiconductor layer is electrically connected to a bias electrode; and is

The bias electrode, the first source electrode, and the first drain electrode are located at the same layer and comprise the same material.

6. The array substrate according to any one of claims 1 to 3, wherein the array substrate comprises a plurality of second thin film transistors for driving light emission in the display region and the plurality of light emitting regions in the plurality of light emitting regions of the display region and the partially transparent region;

a corresponding one of the plurality of second thin film transistors includes a second gate electrode, a second active layer, and a second source electrode and a second drain electrode respectively connected to the second active layer;

the second active layer, the intrinsic semiconductor layer, and the first active layer are located at the same layer and include the same polysilicon material.

7. The array substrate of claim 6, wherein the second polarity semiconductor layer is electrically connected to a bias electrode; and is

The bias electrode, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located at the same layer and comprise the same material.

8. The array substrate of any one of claims 1 to 7, wherein a plurality of the plurality of photosensors in the substantially transparent non-light emitting region are electrically connected in parallel to the same bias electrode.

9. The array substrate of any one of claims 1 to 8, further comprising: a first light blocking layer substantially surrounding a corresponding one of the plurality of light emitting areas and configured to block at least a portion of light emitted from the corresponding one of the plurality of light emitting areas from being received by an adjacent light sensor located in the substantially transparent non-light emitting area.

10. The array substrate according to any one of claims 1 to 9, further comprising: a second light shielding layer substantially surrounding a corresponding one of the plurality of light sensors and configured to shield the corresponding one of the plurality of light sensors from light emitted from adjacent sub-pixels located in the plurality of light emitting areas.

11. The array substrate of any one of claims 1 to 10, further comprising: a buffer layer between the first active layer and a substrate base plate;

wherein the first active layer and the first polar semiconductor layer directly contact the buffer layer.

12. The array substrate of any one of claims 1 to 11, wherein the first polar semiconductor layer comprises amorphous silicon doped with a P-type dopant; and is

The second polar semiconductor layer includes indium tin oxide.

13. The array substrate of any one of claims 1 to 12, wherein a sub-pixel number density of the first sub-pixel array is higher than a sub-pixel number density of the second sub-pixel array.

14. The array substrate of claim 13, wherein the first array of subpixels comprises a first subpixel of a first color, a first subpixel of a second color, and a first subpixel of a third color;

the second sub-pixel array comprises a second sub-pixel of a first color, a second sub-pixel of a second color and a second sub-pixel of a third color;

a number density of first sub-pixels of the first color is substantially the same as a number density of second sub-pixels of the first color;

a number density of first sub-pixels of the second color is substantially the same as a number density of second sub-pixels of the second color; and is

The number density of the first sub-pixels of the third color is about twice the number density of the second sub-pixels of the third color.

15. A display device comprising the array substrate of any one of claims 1 to 14, and one or more integrated circuits connected to the array substrate.

16. The display device of claim 15, wherein the display device is a self-emissive display device;

a corresponding sub-pixel in the first sub-pixel array includes a self-emitting light emitting element; and is

The corresponding sub-pixel in the second sub-pixel array includes a self-emission light emitting element.

17. The display device according to claim 15, wherein the display device is a liquid crystal display device, comprising:

the array substrate is characterized in that:

an opposite substrate facing the array substrate;

a liquid crystal layer between the array substrate and the opposite substrate; and

a backlight positioned on a side of the array substrate away from the opposite substrate;

wherein the liquid crystal layer is absent from the substantially transparent non-light emitting region.

18. A method of fabricating an array substrate, comprising:

forming a first sub-pixel array in the display area; and

forming a second sub-pixel array in the partially transparent region;

wherein the partially transparent region comprises a plurality of light emitting regions spaced apart from one another by substantially transparent non-light emitting regions;

the second array of subpixels is limited to the plurality of light emitting areas; and is

The method further includes forming a plurality of photosensors in the substantially transparent non-light emitting region and forming a plurality of first thin film transistors;

wherein a corresponding one of the plurality of photosensors is formed to include a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer; and is

A corresponding one of the plurality of first thin film transistors is formed to include a first gate electrode, a first active layer, and a first source electrode and a first drain electrode respectively connected to the first active layer.

19. The method of claim 18, wherein the intrinsic semiconductor layer and the first active layer are formed in the same layer using the same polysilicon material and the same mask;

the first polarity semiconductor layer is electrically connected with the first source electrode; and is

The second polar semiconductor layer is formed using a metal oxide conductive material doped with an N-type dopant.

20. The method of claim 18, comprising:

forming a buffer layer on a substrate;

forming a first amorphous silicon material layer on one side of the buffer layer far away from the substrate base plate;

doping the first amorphous silicon material layer with a P-type dopant;

patterning the first amorphous silicon material layer to form the first polar semiconductor layer;

forming a second amorphous silicon material layer on the buffer layer and one side of the first polarity semiconductor layer far away from the substrate;

crystallizing the second amorphous silicon material layer to form a polycrystalline silicon material layer; and

patterning the polysilicon material layer to form the intrinsic semiconductor layer and the first active layer;

the intrinsic semiconductor layer is formed on one side of the first polarity semiconductor layer far away from the substrate base plate and is in direct contact with the first polarity semiconductor layer.

21. The method of claim 20, further comprising, after forming the intrinsic semiconductor layer and the first active layer:

forming a metal oxide conductive material layer on one side of the intrinsic semiconductor layer far away from the substrate base plate;

doping the metal oxide conductive material layer with the N-type dopant; and

patterning the metal oxide conductive material layer to form the second polarity semiconductor layer.

22. The method of claim 21, further comprising, after forming the second polarity semiconductor layer:

forming a conductive material layer on one side of the second polar semiconductor layer far away from the substrate base plate;

patterning the layer of conductive material to form a bias electrode, the first source electrode, and the first drain electrode;

wherein the bias electrode is electrically connected to the second polarity semiconductor layer.

Technical Field

The present invention relates to a display technology, and more particularly, to an array substrate, a display apparatus, and a method of manufacturing the array substrate.

Background

In recent years, display devices are fabricated to be integrated with a light sensor to implement various functions such as photoelectric sensing, bio-information detection, and human-computer interaction. For example, smart phones typically include a fingerprint sensor to detect and identify a user's fingerprint.

Disclosure of Invention

In one aspect, the present invention provides an array substrate, including: a display area including a first array of subpixels; and a partially transparent region comprising a second array of sub-pixels; wherein the partially transparent region includes a plurality of light emitting regions spaced apart from one another by substantially transparent non-light emitting regions; the second array of sub-pixels is confined to the plurality of light emitting areas; the array substrate further comprises a plurality of light sensors and a plurality of first thin film transistors which are positioned in the non-light-emitting area which is transparent substantially; wherein a corresponding one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer with the second polarity semiconductor layer; and, a corresponding one of the plurality of first thin film transistors includes a first gate electrode, a first active layer, and a first source electrode and a first drain electrode respectively connected to the first active layer.

Optionally, the intrinsic semiconductor layer and the first active layer are located at the same layer and comprise the same polysilicon material; the first polarity semiconductor layer is electrically connected with the first source electrode; and the second polarity semiconductor layer includes a metal oxide conductive material doped with an N-type dopant.

Optionally, the corresponding one of the plurality of light emitting areas comprises a plurality of sub-pixels in a second sub-pixel array; the corresponding one of the plurality of light emitting regions is substantially surrounded by one or more of the plurality of light sensors; and a plurality of the plurality of photosensors in the substantially transparent non-emitting region are electrically connected in parallel to a same one of the plurality of first thin film transistors.

Optionally, in the plurality of light emitting areas of the display area and the partially transparent area, the array substrate includes a plurality of second thin film transistors for driving light emission in the display area and the plurality of light emitting areas; wherein, the array substrate still includes: a passivation layer located on a side of the plurality of photosensors, the plurality of first thin film transistors, and the plurality of second thin film transistors away from the substrate; and one or more layers located on a side of the passivation layer remote from the substrate and confined in the display region and in the plurality of light emitting regions of the partially transparent region; wherein the one or more layers are not present in the substantially transparent non-light emitting region.

Optionally, the second polarity semiconductor layer is electrically connected to the bias electrode; and, the bias electrode, the first source electrode and the first drain electrode are located at the same layer and include the same material.

Optionally, in the plurality of light emitting areas of the display area and the partially transparent area, the array substrate includes a plurality of second thin film transistors for driving light emission in the display area and the plurality of light emitting areas; a corresponding one of the plurality of second thin film transistors includes a second gate electrode, a second active layer, and a second source electrode and a second drain electrode respectively connected to the second active layer; the second active layer, the intrinsic semiconductor layer, and the first active layer are located at the same layer and include the same polysilicon material.

Optionally, the second polarity semiconductor layer is electrically connected to the bias electrode; and, the bias electrode, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located at the same layer and include the same material.

Optionally, a plurality of the plurality of photosensors in the substantially transparent non-light emitting region are electrically connected in parallel to the same bias electrode.

Optionally, the array substrate further includes: a first light blocking layer substantially surrounding a corresponding one of the plurality of light emitting regions and configured to block at least a portion of light emitted from the corresponding one of the plurality of light emitting regions from being received by an adjacent light sensor located in a substantially transparent non-light emitting region.

Optionally, the array substrate further includes: a second light shielding layer substantially surrounding a corresponding one of the plurality of light sensors and configured to shield the corresponding one of the plurality of light sensors from light emitted from adjacent sub-pixels located in the plurality of light emitting areas.

Optionally, the array substrate further includes: a buffer layer between the first active layer and the substrate base plate; wherein the first active layer and the first polar semiconductor layer directly contact the buffer layer.

Optionally, the first polar semiconductor layer comprises amorphous silicon doped with a P-type dopant; and, the second polar semiconductor layer includes indium tin oxide.

Optionally, the number density of sub-pixels of the first sub-pixel array is higher than the number density of sub-pixels of the second sub-pixel array.

Optionally, the first subpixel array comprises a first subpixel of a first color, a first subpixel of a second color, and a first subpixel of a third color; the second sub-pixel comprises a second sub-pixel of the first color, a second sub-pixel of the second color and a second sub-pixel of the third color; the number density of the first sub-pixels of the first color is substantially the same as the number density of the second sub-pixels of the first color; the number density of the first sub-pixels of the second color is substantially the same as the number density of the second sub-pixels of the second color; and the number density of the first sub-pixels of the third color is about twice as large as the number density of the second sub-pixels of the third color.

In another aspect, the present invention provides a display device comprising an array substrate as described herein or manufactured by the method described herein and one or more integrated circuits connected to the array substrate.

Optionally, the display device is a self-emissive display device; a corresponding sub-pixel in the first sub-pixel array includes a self-emission light emitting element; and, the corresponding sub-pixel in the second sub-pixel array includes a self-emission light emitting element.

Optionally, the display device is a liquid crystal display device, comprising: an array substrate; an opposing substrate facing the array substrate; a liquid crystal layer between the array substrate and the opposite substrate; and a backlight positioned on a side of the array substrate away from the opposite substrate; wherein the liquid crystal layer is not present in the substantially transparent non-light emitting region.

In another aspect, the present invention provides a method of manufacturing an array substrate, including: forming a first sub-pixel array in the display area; and forming a second sub-pixel array in the partially transparent region; wherein the partially transparent region includes a plurality of light emitting regions spaced apart from one another by substantially transparent non-light emitting regions; the second array of sub-pixels is confined to the plurality of light emitting areas; and, the method further comprises forming a plurality of photosensors and forming a plurality of first thin film transistors in the substantially transparent non-light emitting region; wherein a corresponding one of the plurality of photosensors is formed to include a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer; and, a corresponding one of the plurality of first thin film transistors is formed to include a first gate electrode, a first active layer, and a first source electrode and a first drain electrode respectively connected to the first active layer.

Alternatively, the intrinsic semiconductor layer and the first active layer are formed in the same layer using the same polysilicon material and the same mask; the first polarity semiconductor layer is electrically connected with the first source electrode; and forming the second polarity semiconductor layer using a metal oxide conductive material doped with an N-type dopant.

Optionally, the method comprises: forming a buffer layer on a substrate; forming a first amorphous silicon material layer on one side of the buffer layer, which is far away from the substrate; doping the first amorphous silicon material layer with a P-type dopant; patterning the first amorphous silicon material layer to form a first polarity semiconductor layer; forming a second amorphous silicon material layer on the buffer layer and one side of the first polarity semiconductor layer far away from the substrate; crystallizing the second amorphous silicon material layer to form a polysilicon material layer; and patterning the polysilicon material layer to form an intrinsic semiconductor layer and a first active layer; the intrinsic semiconductor layer is formed on one side of the first polarity semiconductor layer far away from the substrate base plate and is in direct contact with the first polarity semiconductor layer.

Optionally, after forming the intrinsic semiconductor layer and the first active layer, the method further comprises: forming a metal oxide conductive material layer on one side of the intrinsic semiconductor layer far away from the substrate base plate; doping the metal oxide conductive material layer with an N-type dopant; and patterning the metal oxide conductive material layer to form a second polarity semiconductor layer.

Optionally, after forming the second polarity semiconductor layer, the method further comprises: forming a conductive material layer on one side of the second polar semiconductor layer far away from the substrate base plate; patterning the conductive material layer to form a bias electrode, a first source electrode and a first drain electrode; wherein the bias electrode is electrically connected to the second polar semiconductor layer.

Drawings

The following drawings are merely exemplary for purposes of illustrating various embodiments in accordance with the disclosure and are not intended to limit the scope of the invention.

Fig. 1A is a plan view of an array substrate in some embodiments of the present disclosure.

Fig. 1B is a sectional view taken along line X-X' in fig. 1A.

Fig. 1C is an enlarged view of the region Z1 in fig. 1A.

Fig. 1D is an enlarged view of the region Z2 in fig. 1A.

Fig. 2 is a schematic view illustrating a structure of an array substrate in some embodiments of the present disclosure.

Fig. 3 is a cross-sectional view of the array substrate of fig. 2 taken along line a-a'.

Fig. 4 is a schematic view illustrating a structure of an array substrate in some embodiments of the present disclosure.

Fig. 5 is a cross-sectional view of the array substrate of fig. 4 taken along line B-B'.

Fig. 6A illustrates a structure of a portion of an array substrate in a partially transparent region in some embodiments of the present disclosure.

Fig. 6B is a circuit diagram showing a plurality of photosensors in the substantially transparent non-emitting region electrically connected in parallel to the same one of the plurality of first thin film transistors.

Fig. 7 illustrates a structure of a portion of an array substrate in a partially transparent region in some embodiments of the present disclosure.

Fig. 8 is a cross-sectional view of an array substrate in some embodiments of the present disclosure.

Fig. 9A is a circuit diagram of a corresponding one of a plurality of light sensors in some embodiments according to the present disclosure.

Fig. 9B is a schematic diagram illustrating a structure of a corresponding one of a plurality of light sensors in some embodiments according to the present disclosure.

Fig. 10 is a cross-sectional view of a liquid crystal display device in some embodiments of the present disclosure.

Fig. 11A to 11I illustrate a method of manufacturing an array substrate in some embodiments of the present disclosure.

Detailed Description

The present disclosure will now be described more specifically with reference to the following examples. It is noted that the following description of some embodiments is presented for purposes of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

In the related display device, a notch is generally formed by punching a hole through the display device to mount accessories such as a camera lens and a light sensor for detecting light. The presence of the notch results in a waste of image display area. Driven by aesthetic considerations, full-screen display panels have been developed. However, how to arrange accessories such as a camera and a light sensor in the full-screen display panel remains a problem.

Accordingly, the present disclosure is directed to, among other things, an array substrate, a display apparatus, and a method of manufacturing an array substrate that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes: a display area including a first array of subpixels; and a partially transparent region including a second array of sub-pixels. In some embodiments, the partially transparent region includes a plurality of light emitting regions spaced apart from one another by substantially transparent non-light emitting regions. Optionally, the second array of sub-pixels is limited to the plurality of light emitting areas. Optionally, the array substrate further comprises a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. Optionally, the corresponding one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer with the second polarity semiconductor layer. Optionally, a corresponding one of the plurality of first thin film transistors includes a first gate electrode, a first active layer, and a first source electrode and a first drain electrode respectively connected to the first active layer. Optionally, the intrinsic semiconductor layer and the first active layer are located at the same layer and comprise the same polysilicon material. Optionally, the first polarity semiconductor layer is electrically connected to the first source electrode. Optionally, the second polarity semiconductor layer includes a metal oxide conductive material doped with an N-type dopant.

Fig. 1A is a plan view of an array substrate in some embodiments of the present disclosure. Referring to fig. 1A, in some embodiments, the array substrate includes a display area DA and a partially transparent area PTA adjacent to the display area DA. As used herein, the term "display area" refers to an area of the display substrate where an image is actually displayed. Alternatively, the display area may include both the sub-pixel area and the inter-sub-pixel area. The sub-pixel region refers to a light emitting region of a sub-pixel, such as a region corresponding to a pixel electrode in a liquid crystal display or a region corresponding to a light emitting layer in an organic light emitting display. The inter-subpixel region refers to a region between adjacent subpixel regions, such as a region corresponding to a black matrix in a liquid crystal display or a region corresponding to a pixel defining layer in an organic light emitting display. Optionally, the inter-sub-pixel region is a region between adjacent sub-pixel regions in the same pixel. Optionally, the inter-sub-pixel region is a region between two adjacent sub-pixel regions from two adjacent pixels. As used herein, the term "partially transparent region" refers to a region of the display substrate that partially displays an image and partially does not display an image and allows for the mounting of one or more components that do not emit light. For example, the portion not displaying the image may be configured to arrange a light sensor, for example, a light sensor of a camera. Other non-light emitting components may be arranged in the portion of the partially transparent region where no image is displayed, examples including: a camera lens, a fingerprint sensor, an earpiece, a camera, a distance sensor, an infrared sensor, an audio sensor, an indicator, a button, a knob, or any combination thereof. The partially transparent region allows a full screen display to have no holes in the array substrate or to be punched through the window region. Optionally, the partially transparent region comprises a plurality of image display portions spaced apart by the partially transparent region.

Fig. 1B is a sectional view taken along line X-X' in fig. 1A. Fig. 1C is an enlarged view of the region Z1 in fig. 1A. Fig. 1D is an enlarged view of the region Z2 in fig. 1A. Referring to fig. 1B, 1C, and 1D, the array substrate includes: a display area DA including a first subpixel array Sp 1; and a partially transparent region PTA including a second sub-pixel array Sp 2. In some embodiments, the partially transparent region PTA includes a plurality of light emitting regions LER spaced apart from each other by substantially transparent non-light emitting regions TR. Optionally, the second subpixel array Sp2 is limited to the plurality of light emitting areas LER. Optionally, the array substrate further comprises a plurality of photo sensors PS located in the substantially transparent non-light emitting areas TR.

In the display area DA, as shown in fig. 1A and 1C, the plurality of photo sensors PS are not present, and normal display is performed in the display area DA. In one example, the first subpixel array Sp1 comprises a standard compact C1-C1-C2-C3 array, wherein C1 represents a first color subpixel (e.g., a red subpixel), C2 represents a second color subpixel (e.g., a green subpixel), and C3 represents a third color subpixel (e.g., a blue subpixel). In the partially transparent region PTA, as shown in fig. 1A and 1D, only some of the sub-pixels perform normal display, while the other "sub-pixels" are converted into substantially transparent regions and do not emit light, as indicated by the broken line "sub-pixels" in fig. 1D. To ensure that the gate driver circuits and the chip drivers on the array can satisfactorily drive image display in both the display area DA and the partially transparent area PTA, the display resolution (e.g., pixels per inch) in the display area DA is set to the display resolution in the partially transparent area PTA multiplied by a multiplication factor. Optionally, the multiplication factor is an integer factor (e.g., 2). To ensure satisfactory display results, optionally, the second subpixel array Sp2 includes a C1-C2-C3 array, where C1 represents a first color subpixel (e.g., a red subpixel), C2 represents a second color subpixel (e.g., a green subpixel), and C3 represents a third color subpixel (e.g., a blue subpixel).

Fig. 2 is a schematic view illustrating a structure of an array substrate in some embodiments of the present disclosure. Referring to fig. 1A and 2, the array substrate includes: a display area DA including a first subpixel array Sp 1; and a partially transparent region PTA including a second sub-pixel array Sp 2. In some embodiments, the partially transparent region PTA includes a plurality of light emitting regions LER spaced apart from each other by substantially transparent non-light emitting regions TR. Optionally, the second subpixel array Sp2 is limited to the plurality of light emitting areas LER.

Fig. 3 is a cross-sectional view of the array substrate of fig. 2 taken along line a-a'. Referring to fig. 1 to 3, in some embodiments, the array substrate further includes a plurality of photo sensors PS and a plurality of first thin film transistors TFT1 in the substantially transparent non-light emitting region TR. Alternatively, the corresponding one of the plurality of photo sensors PS includes the first polarity semiconductor layer PSL1, the second polarity semiconductor layer PSL2, and the intrinsic semiconductor layer ISL connecting the first polarity semiconductor layer PSL1 and the second polarity semiconductor layer PSL 2.

Alternatively, a corresponding one of the plurality of first thin film transistors TFT1 includes a first gate electrode G1, a first active layer ACT1, and a first source electrode S1 and a first drain electrode D1 connected to the first active layer ACT1, respectively. Alternatively, the first polar semiconductor layer PSL1 is electrically connected to the first source electrode S1.

Alternatively, the second polarity semiconductor layer PSL2 includes a metal oxide conductive material doped with an N-type dopant. Examples of N-type dopants include group VA elements of the periodic table including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In one example, the second polar semiconductor layer PSL2 includes indium tin oxide doped with an N-type dopant.

Optionally, the first polar semiconductor layer PSL1 includes a semiconductor material doped with a P-type dopant. Examples of P-type dopants include group IIIA elements of the periodic table including boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). In one example, the first polar semiconductor layer PSL1 includes amorphous silicon doped with P-type dopant.

Alternatively, the intrinsic semiconductor layer ISL and the first active layer ACT1 are located at the same layer and include the same polysilicon material. As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, when the intrinsic semiconductor layer ISL and the first active layer ACT1 are formed as a result of one or more steps of the same patterning process performed in the same material layer, they are located in the same layer. In another example, the intrinsic semiconductor layer ISL and the first active layer ACT1 may be formed at the same layer by simultaneously performing the step of forming the intrinsic semiconductor layer ISL and the step of forming the first active layer ACT 1. The term "same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the sectional view.

In some embodiments, and referring to fig. 3, in the plurality of light emitting regions LER of the display area DA and the partially transparent area PTA, the array substrate includes a plurality of second thin film transistors TFT2 for driving light emission in the display area DA and the plurality of light emitting regions LER. Alternatively, a corresponding one of the plurality of second thin film transistors TFT2 includes a second gate electrode G2, a second active layer ACT2, and a second source electrode S2 and a second drain electrode D2 connected to the second active layer ACT2, respectively.

In some embodiments, the array substrate is a self-emissive array substrate that does not require a backlight for image display. Optionally, the array substrate further includes a plurality of light emitting elements LE in the plurality of light emitting regions LER of the display region DA and the partially transparent region PTA. Various suitable light emitting elements can be used in the present display panel. Examples of suitable light-emitting elements include: organic light emitting diodes, quantum dot light emitting diodes, and micro light emitting diodes. Alternatively, the corresponding subpixel in the first subpixel array Sp1 includes one of the plurality of light emitting elements LE, and the corresponding subpixel in the second subpixel array Sp2 includes one of the plurality of light emitting elements LE.

In some embodiments, a corresponding one of the plurality of light emitting elements LE includes an anode AD, a light emitting layer EM, and a cathode CD. The light-emitting layer EM is located between the anode AD and the cathode CD. The anode AD is electrically connected to the second drain electrode D2 of a corresponding one of the plurality of second thin film transistors TFT 2.

Referring to fig. 3, the array substrate includes a substrate base plate 10 and a buffer layer 20 on the substrate base plate 10. The first active layer ACT1, the second active layer ACT2, and the first polarity semiconductor layer PSL1 are located on the side of the buffer layer 20 away from the base substrate 10. Alternatively, the first active layer ACT1 and the first polarity semiconductor layer PSL1 directly contact the buffer layer 20. Alternatively, the intrinsic semiconductor layer ISL is positioned on a side of the first polarity semiconductor layer PSL1 away from the buffer layer 20. The array substrate further includes a gate insulating layer 30 on sides of the first and second active layers ACT1 and ACT2 away from the buffer layer 20. The first gate electrode G1 and the second gate electrode G2 are located on a side of the gate insulating layer 30 away from the base substrate 10. The array substrate further includes an interlayer dielectric layer 40 on the sides of the first and second gate electrodes G1 and G2 away from the substrate base plate 10. The first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 are located on a side of the interlayer dielectric layer 40 away from the base substrate 10. The array substrate further includes a passivation layer 50 on the sides of the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 away from the substrate 10. The anode AD is located on the side of the passivation layer 50 remote from the base substrate 10. The array substrate further includes a pixel defining layer 60 on a side of the passivation layer 50 remote from the substrate base plate 10 for defining a plurality of sub-pixel apertures. The light emitting layer EM is disposed in a corresponding one of the plurality of sub-pixel holes, and the cathode CD is located on a side of the light emitting layer EM away from the anode AD.

In order to facilitate the plurality of photo sensors PS to detect light, in some embodiments, one or more of the pixel defining layer 60, the anode AD, the light emitting layer EM, and the cathode CD are substantially limited in the display area DA and in the plurality of light emitting areas LER of the partially transparent area PTA, and are not present in the substantially transparent non-light emitting areas TR.

In some embodiments, and referring to fig. 3, the array substrate further comprises a bias electrode BE. The second polarity semiconductor layer PSL2 is electrically connected to the bias electrode BE. Alternatively, the bias electrode BE, the first source electrode S1, and the first drain electrode D1 are located at the same layer and include the same material.

In some embodiments, and referring to fig. 3, the second active layer ACT2, the intrinsic semiconductor layer ISL, and the first active layer ACT1 are located at the same layer and comprise the same polysilicon material.

In some embodiments, and referring to fig. 3, the bias electrode BE, the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 are located at the same layer and comprise the same material.

Fig. 4 is a schematic view illustrating a structure of an array substrate in some embodiments of the present disclosure. Fig. 5 is a cross-sectional view of the array substrate of fig. 4 taken along line B-B'. Referring to fig. 4 and 5, in some embodiments, the array substrate further includes: a first light shielding layer LS1 substantially surrounding a corresponding one of the plurality of light-emitting areas LER and configured to shield at least a portion of light emitted from the corresponding one of the plurality of light-emitting areas LER from being received by an adjacent light sensor located in the substantially transparent non-light-emitting area TR. The first light shielding layer LS1 is arranged along the entire boundary between the substantially transparent non-light emitting region TR and the display region DA. Further, the first light shielding layer LS1 is also arranged along all the boundaries between the substantially transparent non-light-emitting areas TR and the plurality of light-emitting areas LER.

In one example, as shown in fig. 5, the first light shielding layer LS1 is located on a side of the passivation layer 50 away from the base substrate 10. Optionally, the height of the first light shielding layer LS1 with respect to the main surface of the passivation layer 50 is equal to or greater than the height of the light emitting layer EM with respect to the main surface of the passivation layer 50. Other suitable designs may be implemented to arrange the first light shielding layer LS 1. In another example, the first light shielding layer LS1 may be disposed on a surface of the interlayer dielectric layer 40, and may protrude in a direction away from the substrate base plate 10. In another example, the first light shielding layer LS1 may be disposed on a surface of the gate insulating layer 30 and may protrude in a direction away from the substrate 10.

Fig. 6A illustrates a structure of a portion of an array substrate in a partially transparent region in some embodiments of the present disclosure. Referring to fig. 6A, a corresponding one of the plurality of light emitting regions LER includes a plurality of sub-pixels, for example, a sub-pixel of a first color (for example, a red sub-pixel), a sub-pixel of a second color (for example, a green sub-pixel), and a sub-pixel of a third color (for example, a blue sub-pixel) in the second sub-pixel array Sp 2. Optionally, the corresponding one of the plurality of light emitting areas LER is substantially surrounded by one or more of the plurality of light sensors PS. As used herein, the term "substantially surrounds" refers to surrounding at least 50% (e.g., at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, and 100%) of the perimeter of a region. For example, at least 60% of a circumference of the corresponding one of the plurality of light emitting areas LER is surrounded by one or more of the plurality of light sensors PS. Referring to fig. 6A, at least 60% of a circumference of the corresponding one of the plurality of light emitting areas LER is surrounded by two light sensors of the plurality of light sensors PS.

In some embodiments, referring to fig. 6A, a plurality of the plurality of photosensors PS located in the substantially transparent non-light emitting region TR are electrically connected in parallel to the same one of the plurality of first thin film transistors TFT 1. Fig. 6A shows that three photosensors corresponding to (e.g., substantially surrounding) four of the plurality of light-emitting areas LER are electrically connected in parallel to the same one of the plurality of first thin-film transistors TFT 1. In one example, the respective first polarity semiconductor layers of three of the plurality of photosensors PS corresponding to four of the plurality of light emitting regions LER are electrically connected in parallel to the first source electrode of the same one of the plurality of first thin film transistors TFT 1. By electrically connecting a plurality of the plurality of photo sensors PS in parallel, the photocurrents from the plurality of photo sensors PS can be uniformly detected, thereby enhancing the signal-to-noise ratio and the sensitivity of light detection.

In some embodiments, and referring to fig. 6A, the plurality of photosensors PS in the plurality of photosensors PS located in the substantially transparent non-light emitting region TR are electrically connected in parallel to the same bias electrode BE. For example, the respective second polarity semiconductor layers of three photosensors PS corresponding to four of the plurality of light emitting regions LER in the plurality of photosensors PS are electrically connected in parallel to the same bias electrode BE.

Fig. 6B is a circuit diagram showing a plurality of photosensors in the substantially transparent non-emitting region electrically connected in parallel to the same one of the plurality of first thin film transistors. Referring to fig. 6B, n photosensors (PS1 to PSn) of the plurality of photosensors PS located in the substantially transparent non-light-emitting region TR are electrically connected in parallel to the same one of the plurality of first thin film transistors TFT 1.

In some embodiments, the array substrate further comprises: a second light shielding layer LS2 substantially surrounding a corresponding one of the plurality of photo sensors PS and configured to shield the corresponding one of the plurality of photo sensors PS from light emitted from an adjacent sub-pixel located in the plurality of light emitting areas LER. Optionally, the second light shielding layer LS2 is disposed in the substantially transparent non-light-emitting area TR. Optionally, the second light shielding layer LS2 is located at a side surface of the corresponding one of the plurality of photo sensors PS.

Optionally, the second light shielding layer LS2 is configured to substantially shield a side surface of the corresponding one of the plurality of light sensors PS from light emitted from an adjacent sub-pixel in the plurality of light-emitting areas LER. Optionally, the second light shielding layer LS2 is configured to completely shield the side surface of the corresponding one of the plurality of light sensors PS from light emitted from the adjacent sub-pixels in the plurality of light-emitting areas LER. Optionally, the second light shielding layer LS2 is configured to substantially shield light emitted from adjacent sub-pixels in the plurality of light emitting areas LER for all side surfaces of the corresponding one of the plurality of photo sensors PS. Optionally, the second light shielding layer LS2 is configured to completely shield light emitted from adjacent sub-pixels in the plurality of light emitting areas LER for all side surfaces of the corresponding one of the plurality of photo sensors PS.

Alternatively, a side of the second light shielding layer LS2 close to the substrate base plate 10 is in direct contact with the first polarity semiconductor layer PSL1 of the corresponding one of the plurality of photo sensors PS. By having the second light shielding layer LS2, the light detection accuracy of the corresponding one of the plurality of photo sensors PS can be significantly improved.

Optionally, the height of the second light shielding layer LS2 with respect to the main surface of the buffer layer 20 is equal to or greater than the height of the second polarity semiconductor layer PSL2 with respect to the main surface of the buffer layer 20. Other suitable designs may be implemented to dispose the second light shielding layer LS 2. In another example, the second light shielding layer LS2 may be disposed on a surface of the buffer layer 20, and may protrude in a direction away from the base substrate 10. In another example, the second light shielding layer LS2 may be disposed on a surface of the gate insulating layer 30 and may protrude in a direction away from the substrate 10. In another example, the second light shielding layer LS2 may be disposed on the surface of the base substrate 10 and may protrude in a direction away from the base substrate 10.

Referring to fig. 8, in some embodiments, the array substrate is an array substrate for a liquid crystal display panel. In some embodiments, the array substrate includes a pixel electrode PE on a side of the passivation layer 50 away from the substrate 10 and electrically connected to the second drain electrode D2 of a corresponding one of the plurality of second thin film transistors TFT 2. Optionally, the array substrate further includes an alignment layer ALG (e.g., a polyimide alignment layer) for aligning liquid crystal molecules to be disposed between the array substrate and the opposite substrate of the display panel having the array substrate. The alignment layer ALG is positioned on the pixel electrode PE and the passivation layer 50 on a side away from the base substrate 10. Alternatively, in order to facilitate the plurality of photo sensors PS to detect light, in some embodiments, the alignment layer ALG is substantially limited in the display region DA and the plurality of light-emitting regions LER of the partially transparent region PTA, and is not present in the substantially transparent non-light-emitting regions TR.

Referring to fig. 2 and 4, in some embodiments, the number density of subpixels of the first subpixel array Sp1 is higher than that of subpixels of the second subpixel array Sp 2. In some embodiments, the first subpixel array Sp1 includes a first subpixel of a first color (e.g., a red subpixel), a first subpixel of a second color (e.g., a green subpixel), and a first subpixel of a third color (e.g., a blue subpixel). Optionally, the second subpixel array Sp2 includes a second subpixel of the first color (e.g., a red subpixel), a second subpixel of the second color (e.g., a green subpixel), and a second subpixel of the third color (e.g., a blue subpixel). Optionally, the number density of the first sub-pixels of the first color is substantially the same as the number density of the second sub-pixels of the first color. Optionally, the number density of the first sub-pixels of the second color is substantially the same as the number density of the second sub-pixels of the second color. Optionally, the number density of the first sub-pixels of the third color is about twice the number density of the second sub-pixels of the third color.

Various suitable photosensors may be utilized in making and using the present array substrate. Examples of suitable light sensors include, but are not limited to: PN photodiode, PIN photodiode, avalanche photodiode, MIM diode junction, MIS diode junction, MOS diode junction, SIS diode junction, and MS diode junction.

Fig. 9A is a circuit diagram of a corresponding one of a plurality of light sensors in some embodiments according to the present disclosure. Referring to fig. 3, 5 to 8, and 9A, in some embodiments, the corresponding one of the plurality of photo sensors PS is electrically connected to the corresponding one of the plurality of first thin film transistors TFT 1. The first source electrode S1 of the corresponding one of the plurality of first thin film transistors TFT1 is electrically connected to the first polarity semiconductor layer PSL1 of the corresponding one of the plurality of photo sensors PS. The first drain electrode D1 of the corresponding one of the plurality of first thin film transistors TFT1 is electrically connected to a read line R, which in turn is also connected to other components (e.g., a digital camera). The second polarity semiconductor layer PSL2 of the corresponding one of the plurality of photo sensors PS is electrically connected to a bias electrode BE configured to supply a bias voltage to the corresponding one of the plurality of photo sensors PS.

Fig. 9B is a schematic diagram illustrating a structure of a corresponding one of a plurality of light sensors in some embodiments according to the present disclosure. Referring to fig. 9B, in some embodiments, the corresponding one of the plurality of photo sensors PS is a PIN photodiode. In some embodiments, the corresponding one of the plurality of photo sensors PS includes a first polarity semiconductor layer PSL1 electrically connected to a connection electrode CE, which in turn is electrically connected to the first source electrode S1 of the corresponding one of the plurality of first thin film transistors TFT 1. The corresponding one of the plurality of photo sensors PS further includes: a second polarity semiconductor layer PSL2 electrically connected to the bias electrode BE; and an intrinsic semiconductor layer ISL connecting the first polarity semiconductor layer PSL1 and the second polarity semiconductor layer PSL 2. As used herein, the term "intrinsic semiconductor layer" refers to a layer that can exhibit current rectification, e.g., a layer that exhibits a conductivity in one bias direction that is substantially different from a conductivity in another bias direction.

Alternatively, the corresponding one of the plurality of photo sensors PS includes a first polarity semiconductor layer PSL1 having the first dopant, a second polarity semiconductor layer PSL2 having the second dopant, and an intrinsic semiconductor layer ISL connecting the first polarity semiconductor layer PSL1 and the second polarity semiconductor layer PSL 2. For example, the first dopant is an N-type dopant, such As a group VA element of the periodic table of elements, including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi); and the second dopant is a P-type dopant, such as a group IIIA element of the periodic table, including boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). Optionally, the corresponding one of the plurality of photo sensors PS is reverse biased. In some embodiments, the corresponding one of the plurality of photo sensors PS is a PN junction having a P + doped semiconductor region as the first polarity semiconductor layer PSL1 and an N + doped semiconductor region as the second polarity semiconductor layer PSL 2. In some embodiments, the corresponding one of the plurality of photo sensors PS is a PIN photodiode having a P + doped semiconductor region as the first polarity semiconductor layer PSL1, an N + doped semiconductor region as the second polarity semiconductor layer PSL2, and an intrinsic semiconductor layer ISL of polycrystalline silicon between the P + doped semiconductor region and the N + doped semiconductor region.

Various suitable materials may be used to fabricate the first light-shielding layer LS1 and the second light-shielding layer LS 2. Examples of materials suitable for making the first and second light shielding layers LS1 and LS2 include, but are not limited to, black light absorbing materials such as black resin materials.

In another aspect, the present disclosure provides a method of manufacturing an array substrate. In some embodiments, the method comprises: forming a first sub-pixel array in the display area; and forming a second sub-pixel array in the partially transparent region. In some embodiments, the partially transparent region includes a plurality of light emitting regions spaced apart from one another by substantially transparent non-light emitting regions. Optionally, the second array of sub-pixels is limited to the plurality of light emitting areas. In some embodiments, the method further comprises forming a plurality of photosensors in the substantially transparent non-light-emitting region and forming a plurality of first thin-film transistors. Optionally, a corresponding one of the plurality of photosensors is formed to include a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer. Alternatively, a corresponding one of the plurality of first thin film transistors is formed to include a first gate electrode, a first active layer, and a first source electrode and a first drain electrode respectively connected to the first active layer. Alternatively, the intrinsic semiconductor layer and the first active layer are formed in the same layer using the same polysilicon material and the same mask. Optionally, the first polarity semiconductor layer is electrically connected to the first source electrode. Alternatively, the second polarity semiconductor layer is formed using a metal oxide conductive material doped with an N-type dopant.

In some embodiments, the method comprises: forming a buffer layer on a substrate; forming a first amorphous silicon material layer on one side of the buffer layer, which is far away from the substrate; doping the first amorphous silicon material layer with a P-type dopant; patterning the first amorphous silicon material layer to form a first polarity semiconductor layer; forming a second amorphous silicon material layer on the buffer layer and one side of the first polarity semiconductor layer far away from the substrate; crystallizing the second amorphous silicon material layer to form a polysilicon material layer; and patterning the polysilicon material layer to form an intrinsic semiconductor layer and a first active layer. Optionally, the intrinsic semiconductor layer is formed on a side of the first polar semiconductor layer away from the substrate base plate and is in direct contact with the first polar semiconductor layer.

In some embodiments, after forming the intrinsic semiconductor layer and the first active layer, the method further comprises: forming a metal oxide conductive material layer on one side of the intrinsic semiconductor layer far away from the substrate base plate; doping the metal oxide conductive material layer with an N-type dopant; and patterning the metal oxide conductive material layer to form a second polarity semiconductor layer.

In some embodiments, after forming the second polarity semiconductor layer, the method further comprises: forming a conductive material layer on one side of the second polar semiconductor layer far away from the substrate base plate; the conductive material layer is patterned to form a bias electrode, a first source electrode, and a first drain electrode. Optionally, the bias electrode is electrically connected to the second polar semiconductor layer.

Fig. 11A to 11I illustrate a method of manufacturing an array substrate in some embodiments of the present disclosure. Referring to fig. 11A, a buffer layer 20 is formed on a base substrate 10. Various suitable insulating materials and various suitable fabrication methods may be used to fabricate buffer layer 20. For example, the insulating material may be deposited on the substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Examples of suitable insulating materials for making the buffer layer include, but are not limited to: si_xO_y、Si_xN_y、Si_xO_yN_zOr a combination thereof. Alternatively, the buffer layer 20 is fabricated to have a thickness in the range of 300nm to 600 nm.

Referring to fig. 11B, a first amorphous silicon material layer asi1 is formed on a side of the buffer layer 20 away from the base substrate 10. The first amorphous silicon material layer asi1 is doped with a P-type dopant. Alternatively, the first amorphous silicon material layer asi1 is fabricated to have a thickness in the range of 30nm to 100 nm.

Referring to fig. 11B and 11C, the first amorphous silicon material layer asi1 is patterned to form a first polarity semiconductor layer PSL 1. A doping process may be performed before the first amorphous silicon material layer asi1 is patterned. Alternatively, the doping process may be performed after the patterning of the first amorphous silicon material layer asi 1.

Referring to fig. 11D, a second amorphous silicon material layer asi2 is formed on the buffer layer 20 and the first polarity semiconductor layer PSL1 on a side away from the base substrate 10. For example, the second amorphous silicon material layer asi2 is crystallized by a laser to form a polycrystalline silicon material layer. Various suitable crystallization methods may be used to crystallize the second amorphous silicon material layer asi 2. Examples of suitable crystallization methods include: excimer Laser Annealing (ELA), Solid Phase Crystallization (SPC), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), and Metal Induced Lateral Crystallization (MILC). Alternatively, the second amorphous silicon material layer asi2 is formed to have a thickness in the range of 30nm to 100 nm.

Referring to fig. 11D and 11E, the polysilicon material layer is then patterned to form an intrinsic semiconductor layer ISL, a first active layer ACT1, and a second active layer ACT 2. The crystallization process may be performed prior to patterning the layer of polysilicon material. Alternatively, the crystallization process may be performed after patterning the polysilicon material layer. The intrinsic semiconductor layer ISL is formed on a side of the first polarity semiconductor layer PSL1 away from the substrate base plate 10, and is in direct contact with the first polarity semiconductor layer PSL 1.

Referring to fig. 11F, a gate insulating layer 30 is formed on the first and second active layers ACT1 and ACT2 on a side away from the substrate 10, a first gate electrode G1 is formed on the gate insulating layer 30 on a side away from the first active layer ACT1, a second gate electrode G2 is formed on the gate insulating layer 30 on a side away from the second active layer ACT2, and an interlayer dielectric layer 40 is formed on the first and second gate electrodes G1 and G2 on a side away from the substrate 10.

Various suitable electrode materials and various suitable fabrication methods may be used to make the gate electrode. For example, the electrode material may be deposited and patterned on the substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Examples of suitable electrode materials for making the gate electrode include, but are not limited to: aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, and the like. Alternatively, the first gate electrode G1 and the second gate electrode G2 are formed to have a thickness in the range of 100nm to 300 nm.

Various suitable insulating materials and various suitable manufacturing methods may be used to fabricate the gate insulating layer 30 and the interlayer dielectric layer 40. For example, the insulating material may be deposited on the substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Examples of suitable insulating materials for making the gate insulating layer 30 and the interlayer dielectric layer 40 include, but are not limited to: si_xO_y、Si_xN_y、Si_xO_yN_zOr a combination thereof. Alternatively, the gate insulating layer 30 is fabricated to have a thickness in the range of 100nm to 500 nm. Alternatively, the interlayer dielectric layer 40 is fabricated to have a thickness in the range of 300nm to 900 nm.

Referring to fig. 11G, a via hole penetrating the interlayer dielectric layer 40 to expose a surface of the intrinsic semiconductor layer ISL is formed, and a metal oxide conductive material layer mol is formed on the intrinsic semiconductor layer ISL and a side of the interlayer dielectric layer 40 away from the substrate base plate 10. The metal oxide conducting material layer is mol doped with N-type dopant. Various suitable metal oxide conductive materials and various suitable manufacturing methods may be used to make the metal oxide conductive material layer mol. For example, the metal oxide conductive material may be deposited on the substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Examples of suitable metal oxide conductive materials for making the metal oxide conductive material layer mol include, but are not limited to, indium tin oxide. Alternatively, the layer of metal oxide conductive material mol is fabricated to have a thickness in the range of 30nm to 100 nm.

Referring to fig. 11G and 11H, the metal oxide conductive material layer mol is then patterned to form the second polarity semiconductor layer PSL 2.

Referring to fig. 11I, a first source electrode S1, a first drain electrode D1, a second source electrode S2, a second drain electrode D2, and a bias electrode BE are formed on a side of the interlayer dielectric layer 40 away from the substrate base plate 10. Various suitable conductive materials may BE used to fabricate the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the bias electrode BE. For example, the electrode material may be deposited on the substrate by sputtering or vapor deposition or solution coating; and patterned. Examples of suitable electrode materials for making the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the bias electrode BE include aluminum, molybdenum, aluminum neodymium (AlNd), copper, molybdenum niobium (MoNb), and alloys thereof. Alternatively, the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the bias electrode BE include a plurality of sub-layers stacked together. In one example, the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the bias electrode BE include a three-layer structure of titanium/aluminum/titanium. Alternatively, each of the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the bias electrode BE is fabricated to have a thickness in the range of 300nm to 900 nm.

Subsequently, a passivation layer 50 is formed on the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, and the bias electrode BE at a side away from the substrate base plate 10. Various suitable insulating materials and various suitable fabrication methods may be used to fabricate the passivation layer 50. For example,the insulating material may be deposited on the substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Examples of suitable insulating materials for fabricating passivation layer 50 include, but are not limited to: si_xO_y、Si_xN_y、Si_xO_yN_zOr a combination thereof. Optionally, the passivation layer 50 is fabricated to have a thickness in the range of 300nm to 900 nm.

In another aspect, the present disclosure provides a display device comprising an array substrate described herein or manufactured by the method described herein and one or more integrated circuits connected with the array substrate. Optionally, the display device comprises a display panel. Optionally, the display panel comprises an array substrate described herein or manufactured by the method described herein, and a counter substrate. Examples of suitable display devices include, but are not limited to: electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, GPS, and the like. Optionally, the display device further comprises one or more integrated circuits connected to the display panel.

In some embodiments, the display device is a self-emissive display device such as an organic light emitting diode display device. The corresponding sub-pixel in the first sub-pixel array includes a self-emitting light emitting element, and the corresponding sub-pixel in the second sub-pixel array includes a self-emitting light emitting element.

In some embodiments, the display device is a liquid crystal display device comprising an array substrate described herein or manufactured by the method described herein, a counter substrate facing the array substrate, a liquid crystal layer between the array substrate and the counter substrate, and a backlight on a side of the array substrate remote from the counter substrate. Fig. 10 is a cross-sectional view of a liquid crystal display device in some embodiments of the present disclosure. Referring to fig. 10, in some embodiments, the display device includes an array substrate AS described herein or manufactured by the method described herein, a counter substrate CS facing the array substrate, a liquid crystal layer LC between the array substrate AS and the counter substrate CS, and a backlight BL at a side of the array substrate AS away from the counter substrate CS. As shown in fig. 10, the liquid crystal layer LC is not present in the substantially transparent non-light emitting region TR.

The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or exemplary embodiments disclosed. The foregoing description is, therefore, to be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in the art. The embodiments were chosen and described in order to explain the principles of the invention and its best mode practical application to enable one skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents, in which all terms are to be interpreted in their broadest reasonable sense unless otherwise indicated. Thus, the terms "invention," "present invention," and the like, do not necessarily limit the scope of the claims to particular embodiments, and references to exemplary embodiments of the invention do not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. Furthermore, these claims may refer to the use of the terms "first," "second," etc. followed by a noun or element. Such terms are to be understood as a meaning and not as a limitation on the number of elements modified by such a meaning unless a specific number is given. Any advantages and benefits described do not necessarily apply to all embodiments of the invention. It will be appreciated by those skilled in the art that changes may be made to the embodiments described without departing from the scope of the invention as defined by the appended claims. Furthermore, no element or component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the appended claims.