阅读说明：本技术 层叠陶瓷电容器及其制造方法 (Multilayer ceramic capacitor and method for manufacturing same ) 是由 柳泽笃博 柴田好规 田原干夫 于 2019-06-12 设计创作，主要内容包括：本发明涉及一种层叠陶瓷电容器,包括：层叠芯片,其中多个电介质层中的每一个和多个内部电极层中的每一个交替地层叠,并且内部电极层交替地露出至两个端面；形成在两个端面上的外部电极；其中：当在两个端面彼此面对的方向上的端缘的长度是EM[μm],并且Mo相对于端缘的主要成分陶瓷的B位元素的浓度是M[atm％]时,满足关系“M≥-0.00002×EM+0.0012”,其中,端缘是在层叠芯片中连接到一个外部电极的内部电极层彼此面对而不夹着连接到另一个外部电极的内部电极层的区域。(The present invention relates to a laminated ceramic capacitor comprising: a laminated chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately laminated, and the internal electrode layers are alternately exposed to both end faces; external electrodes formed on both end faces; wherein: when the length of the end edge in the direction in which the two end faces face each other is EM [ μ M ], and the concentration of the B site element of Mo with respect to the ceramic that is the main component of the end edge is M [ atm% ], the relationship "M ≧ 0.00002 × EM + 0.0012" is satisfied, where the end edge is a region in which the internal electrode layers connected to one external electrode face each other without sandwiching the internal electrode layer connected to the other external electrode in the laminated chip.)

1. A laminated ceramic capacitor comprising:

a laminated chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately laminated and each of the plurality of internal electrode layers is alternately exposed to both end faces of the laminated chip, a main component of the plurality of dielectric layers being ceramic; and

a pair of external electrodes formed on the two end faces;

wherein:

the pair of external electrodes has a structure in which a plating layer is formed on an underlying layer whose main component is a metal or an alloy including at least one of Ni and Cu;

the underlayer comprises Mo; and is

Wherein when the length of the end edge in the direction in which the two end faces face each other is EM [ μ M ], and the concentration of Mo with respect to the B site element of the ceramic which is the main component of the end edge is M [ atm% ], the relationship "M ≧ 0.00002 × EM + 0.0012" is satisfied,

wherein the edge is a region in the laminated chip in which the internal electrode layers connected to one external electrode face each other without sandwiching the internal electrode layer connected to the other external electrode.

2. The laminated ceramic capacitor of claim 1, wherein the plating layer comprises a Sn-plated layer.

3. The laminated ceramic capacitor as claimed in claim 1 or 2, wherein the principal component metal of the bottom layer is Ni.

4. The laminated ceramic capacitor as claimed in any one of claims 1 to 3, wherein a main component of the internal electrode layers is Ni.

5. The laminated ceramic capacitor as claimed in any one of claims 1 to 4, wherein the length EM of the end edge region is less than 60 μm.

6. The laminated ceramic capacitor of any one of claims 1 to 5, wherein the Mo concentration is measured by radiating a laser to the entire end edge in a cross section parallel to the side face of the laminated chip and performing ICP-MS analysis.

7. A method for manufacturing a ceramic laminated capacitor, comprising the steps of:

forming a ceramic laminated structure having a parallelepiped shape in which each of a plurality of ceramic dielectric green sheets and each of a plurality of conductive pastes for forming internal electrodes are alternately laminated, and each of the plurality of conductive pastes is alternately exposed to both end faces of the ceramic laminated structure;

coating a metal paste on the both end faces so as to contact the both end faces, the metal paste including a metal powder whose main component is a metal or an alloy including at least one of Ni and Cu and a Mo source;

forming a laminated chip from the ceramic laminated structure and a primer layer from the metal paste by firing the ceramic laminated structure having the metal paste applied thereto; and

forming external electrodes by plating on the base layer, wherein each of the external electrodes includes a respective base layer and a plating layer,

wherein when the length of the end edge in a direction in which the two end faces face each other is EM [ μ M ], and the concentration of Mo with respect to a B site element of a main component ceramic of the end edge is M [ atm% ], the amount of the Mo source in the metal paste is adjusted so as to satisfy the relationship "M ≧ 0.00002 × EM + 0.0012",

wherein the edge is a region in the laminated chip in which the internal electrode layers connected to one external electrode face each other without sandwiching the internal electrode layer connected to the other external electrode.

Technical Field

Certain aspects of the present invention relate to a laminated ceramic capacitor and a method of manufacturing the laminated ceramic capacitor.

Background

The laminated ceramic capacitor has a laminated structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated, and a pair of external electrodes formed on a surface of the laminated structure and electrically connected to the internal electrode layers led out to the surface. The external electrode has a structure in which the underlying layer is subjected to plating. It is known that hydrogen generated in plating diffuses into the main body and causes IR (insulation resistance) degradation after being adsorbed to the vicinity of the external electrode.

Japanese patent application laid-open No. H01-80011 discloses that hydrogen generated in plating is adsorbed into the internal electrode layers, whereby the insulation resistance of the dielectric layers deteriorates due to reduction caused by hydrogen. And this patent document discloses that the metal Ni (nickel) can be added to suppress adsorption of hydrogen to the internal electrode whose main component is a noble metal. On the other hand, japanese patent application No. 2015-188046 discloses that the thickness of the external electrode on the anode side is high to ensure moisture-resistance reliability.

Disclosure of Invention

However, it is difficult to sufficiently suppress IR degradation.

The purpose of the present invention is to provide a laminated ceramic capacitor and a method for manufacturing a laminated ceramic capacitor, wherein IR degradation can be suppressed.

According to an aspect of the present invention, there is provided a laminated ceramic capacitor including: a laminated chip having a parallelepiped shape in which each of a plurality of dielectric layers, the main component of which is ceramic, and each of a plurality of internal electrode layers are alternately laminated and each of the internal electrode layers is alternately exposed to both end faces of the laminated chip; and a pair of external electrodes formed on both end faces; wherein: the pair of external electrodes has a structure in which a plating layer is formed on a base layer, the main component of the base layer being a metal or an alloy containing at least one of Ni and Cu; the underlayer comprises Mo; and wherein when the length of the end edge in the direction in which the two end faces face each other is EM [ μ M ], and the concentration of the B site element of Mo with respect to the ceramic which is the main component of the end edge is M [ atm% ], a relationship "M ≧ 0.00002 × EM + 0.0012" is satisfied, wherein the end edge is a region in which the internal electrode layers connected to one external electrode face each other without sandwiching the internal electrode layer connected to the other external electrode in the laminated chip.

According to another aspect of the present invention, there is provided a method of manufacturing a ceramic multilayer capacitor, including: forming a ceramic laminated structure having a parallelepiped shape in which each of a plurality of ceramic dielectric green sheets and each of a plurality of conductive pastes for forming internal electrodes are alternately laminated, and each of the plurality of conductive pastes is alternately exposed to both end faces of the ceramic laminated structure; coating a metal paste on both end faces, the metal paste contacting both end faces, the metal paste including a metal powder and a Mo source, the metal powder having a main component of a metal or an alloy including at least one of Ni and Cu; forming a laminated chip from the ceramic laminated structure and a primer layer from the metal paste by firing the ceramic laminated structure on which the metal paste is coated; and, by performing plating on the undercoat layer, external electrodes each including a respective undercoat layer and plating layer are formed, wherein the amount of the Mo source in the metal paste is adjusted so that when the length of the end edge in the direction in which the two end faces face each other is EM [ μ M ], and the concentration of the B site element of Mo with respect to the main component ceramic of the end edge is M [ atm% ], the relationship "M ≧ 0.00002 × EM + 0.0012" is satisfied, where the end edge is a region in which the internal electrode layers connected to one external electrode face each other without sandwiching the internal electrode layer connected to the other external electrode in the laminated chip.

Drawings

Fig. 1 shows a partial perspective view of a laminated ceramic capacitor;

FIG. 2 shows a cross-sectional view taken along line A-A in FIG. 1;

FIG. 3 shows a cross-sectional view taken along line B-B in FIG. 1;

FIG. 4 shows a cross-sectional view of the outer electrode, which is a partial cross-sectional view taken along line A-A in FIG. 1;

FIG. 5 shows equation (1); and is

Fig. 6 shows a method for manufacturing a laminated ceramic capacitor.

Detailed Description

A description will be given of embodiments with reference to the accompanying drawings.