阅读说明：本技术 一种非易失存储器处理方法及装置 (Nonvolatile memory processing method and device ) 是由 马思博 罗啸 陈春晖 王者伟 于 2018-06-25 设计创作，主要内容包括：本发明实施例提供了一种非易失存储器处理方法及装置,该方法包括：获取非易失存储器中的当前擦除脉冲状态；根据所述当前擦除脉冲状态,确定调节电压；确定当前擦除脉冲对应的第一电压；根据所述调节电压和所述第一电压,确定下一擦除脉冲对应的第二电压；在所述下一擦除脉冲中,根据所述第二电压进行擦除操作。本发明实施例中,第二电压是根据当前的对非易失存储器的实际擦除情况确定的,在下一擦除脉冲中根据第二电压进行擦除操作,可以实现对非易失存储器的整个擦除过程中,进行可靠且高效的擦除操作。(The embodiment of the invention provides a nonvolatile memory processing method and a nonvolatile memory processing device, wherein the method comprises the following steps: acquiring a current erasing pulse state in the nonvolatile memory; determining an adjustment voltage according to the current erasing pulse state; determining a first voltage corresponding to a current erasing pulse; determining a second voltage corresponding to the next erasing pulse according to the adjusting voltage and the first voltage; and in the next erasing pulse, erasing operation is carried out according to the second voltage. In the embodiment of the invention, the second voltage is determined according to the current actual erasing condition of the nonvolatile memory, and the erasing operation is carried out according to the second voltage in the next erasing pulse, so that the reliable and efficient erasing operation can be carried out in the whole erasing process of the nonvolatile memory.)

1. A non-volatile memory processing method, the method comprising:

acquiring a current erasing pulse state in the nonvolatile memory;

determining an adjustment voltage according to the current erasing pulse state;

determining a first voltage corresponding to a current erasing pulse;

determining a second voltage corresponding to the next erasing pulse according to the adjusting voltage and the first voltage;

and in the next erasing pulse, erasing operation is carried out according to the second voltage.

2. The method of claim 1, wherein the non-volatile memory corresponds to an initial erase pulse voltage difference;

the step of determining a second voltage corresponding to a next erase pulse according to the adjustment voltage and the first voltage includes:

adjusting the initial erasing pulse voltage difference value according to the adjusting voltage to obtain an actual adjusting voltage difference value;

and determining a second voltage corresponding to the next erasing pulse according to the difference value of the first voltage and the actual adjusting voltage.

3. The method of claim 1, wherein the non-volatile memory corresponds to an initial erase voltage, and an initial erase pulse voltage difference;

the step of determining a second voltage corresponding to a next erase pulse according to the adjustment voltage and the first voltage includes:

determining an initial erase voltage adjustment value according to the adjustment voltage;

and determining a second voltage corresponding to the next erasing pulse according to the first voltage, the initial erasing voltage adjustment value and the initial erasing pulse voltage difference value.

4. The method of claim 1, wherein the current erase pulse state comprises: the step of determining the regulated voltage in dependence upon the current erase pulse state, having issued a first number of erase pulses at the present time, comprises:

determining a first difference between the first number and the second number; the second number is: a number of erase pulses that have been issued in the non-volatile memory at a first time; the first time is earlier than the current time;

if the first difference is smaller than a first threshold value, determining that the regulating voltage is a positive value;

if the first difference is larger than a first threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero;

if the first difference is equal to the first threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.

5. The method of claim 1, wherein the current erase pulse state comprises: determining a third number of erase pulses not sent at the present time, wherein the step of determining the regulated voltage according to the state of the present erase pulses comprises:

determining a second difference between the third number and the fourth number; the third number is: the number of erase pulses not issued in the non-volatile memory at a second time; the second time is earlier than the current time;

if the second difference is larger than a second threshold value, determining that the regulating voltage is a positive value;

if the second difference is smaller than a second threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero;

if the second difference is equal to the second threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.

6. The method of claim 1, wherein the current erase pulse state comprises: determining a fifth number of erase pulses that have been sent at the present time, said determining a regulated voltage based on the state of the present erase pulses comprising:

determining a first ratio of the fifth number to a total number of pulses, the total number of pulses being a preset total number of pulses in the non-volatile memory;

if the first ratio is smaller than a third threshold value, determining that the regulated voltage is a positive value;

if the first ratio is larger than a third threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero;

if the first ratio is equal to the third threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.

7. The method of claim 1, wherein the current erase pulse state comprises: determining the adjustment voltage according to the current erase pulse state, wherein the sixth number of erase pulses not emitted at the current time comprises:

determining a second ratio of the sixth quantity to a total number of pulses, the total number of pulses being a preset total number of pulses in the non-volatile memory;

if the second ratio is larger than a fourth threshold, determining that the regulated voltage is a positive value;

if the second ratio is smaller than a fourth threshold, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero;

if the second ratio is equal to the fourth threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.

8. A non-volatile memory processing apparatus, the apparatus comprising:

the current erasing pulse state acquisition module is used for acquiring the current erasing pulse state in the nonvolatile memory;

the adjusting voltage determining module is used for determining adjusting voltage according to the current erasing pulse state;

the first voltage determining module is used for determining a first voltage corresponding to the current erasing pulse;

the second voltage determining module is used for determining a second voltage corresponding to the next erasing pulse according to the regulating voltage and the first voltage;

and the erasing module is used for erasing operation according to the second voltage in the next erasing pulse.

9. The apparatus of claim 8, wherein the non-volatile memory corresponds to an initial erase pulse voltage difference;

the second voltage determination module includes:

the second voltage determination first submodule is used for adjusting the initial erasing pulse voltage difference value according to the adjusting voltage to obtain an actual adjusting voltage difference value; and determining a second voltage corresponding to the next erasing pulse according to the difference value of the first voltage and the actual adjusting voltage.

10. The apparatus of claim 8, wherein the non-volatile memory corresponds to an initial erase voltage, and an initial erase pulse voltage difference;

the second voltage determination module includes:

the second voltage determination second submodule is used for determining an initial erasing voltage adjustment value according to the adjusting voltage; and determining a second voltage corresponding to the next erasing pulse according to the first voltage, the initial erasing voltage adjustment value and the initial erasing pulse voltage difference value.

11. The apparatus of claim 8, wherein the current erase pulse state comprises: a first number of erase pulses having been issued at a present time, the regulated voltage determination module comprising:

a first regulation voltage determination submodule for determining a first difference between the first number and the second number; the second number is: a number of erase pulses that have been issued in the non-volatile memory at a first time; the first time is earlier than the current time; if the first difference is smaller than a first threshold value, determining that the regulating voltage is a positive value; if the first difference is larger than a first threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the first difference is equal to the first threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.

12. The apparatus of claim 8, wherein the current erase pulse state comprises: a third number of erase pulses not being issued at the present time, the adjustment voltage determination module comprising:

a second regulation voltage determination submodule for determining a second difference between the third number and the fourth number; the third number is: the number of erase pulses not issued in the non-volatile memory at a second time; the second time is earlier than the current time; if the second difference is larger than a second threshold value, determining that the regulating voltage is a positive value; if the second difference is smaller than a second threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the second difference is equal to the second threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.

13. The apparatus of claim 8, wherein the current erase pulse state comprises: a fifth number of erase pulses having been issued at the present time, the adjustment voltage determination module comprising:

a third adjustment voltage determination submodule, configured to determine a first ratio of the fifth number to a total pulse amount, where the total pulse amount is a total pulse amount preset in the nonvolatile memory; if the first ratio is smaller than a third threshold value, determining that the regulated voltage is a positive value; if the first ratio is larger than a third threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the first ratio is equal to the third threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.

14. The apparatus of claim 8, wherein the current erase pulse state comprises: a sixth number of erase pulses not being emitted at the present time, the adjustment voltage determination module comprising:

a fourth adjustment voltage determination submodule, configured to determine a second ratio of the sixth number to a total pulse amount, where the total pulse amount is a total pulse amount preset in the nonvolatile memory; if the second ratio is larger than a fourth threshold, determining that the regulated voltage is a positive value; if the second ratio is smaller than a fourth threshold, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the second ratio is equal to the fourth threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.

Technical Field

The present invention relates to the field of memory processing technologies, and in particular, to a method and an apparatus for processing a nonvolatile memory.

Background

With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, the NAND Memory is composed of a plurality of Memory cells (cells), can realize multiple times of programming, and has large capacity, simple reading and writing, few peripheral devices and low price.

Disclosure of Invention

In view of the above, embodiments of the present invention are proposed to provide a non-volatile memory processing method and apparatus that overcome or at least partially solve the above problems.

According to a first aspect of the present invention, there is provided a non-volatile memory processing method, the method comprising:

acquiring a current erasing pulse state in the nonvolatile memory;

determining an adjustment voltage according to the current erasing pulse state;

determining a first voltage corresponding to a current erasing pulse;

determining a second voltage corresponding to the next erasing pulse according to the adjusting voltage and the first voltage;

and in the next erasing pulse, erasing operation is carried out according to the second voltage.

According to a second aspect of the present invention, there is provided a non-volatile memory processing apparatus, the apparatus comprising:

the current erasing pulse state acquisition module is used for acquiring the current erasing pulse state in the nonvolatile memory;

the adjusting voltage determining module is used for determining adjusting voltage according to the current erasing pulse state;

the first voltage determining module is used for determining a first voltage corresponding to the current erasing pulse;

the second voltage determining module is used for determining a second voltage corresponding to the next erasing pulse according to the regulating voltage and the first voltage;

and the erasing module is used for erasing operation according to the second voltage in the next erasing pulse.

In the embodiment of the invention, the current erasing pulse state in the nonvolatile memory is firstly obtained, the regulating voltage is determined according to the current erasing state, and the first voltage corresponding to the current erasing pulse is determined; then determining a second voltage corresponding to the next erasing pulse according to the current regulating voltage and the first voltage; that is, in the embodiment of the present invention, the second voltage is determined according to the current actual erasing condition of the nonvolatile memory, for example, in one erasing operation, the adjustment voltage may be determined to be a larger value according to the current erasing pulse state, so that the second voltage is much larger than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the erasing efficiency can be improved; in another erasing, the adjusting voltage can be determined to be a negative value according to the current erasing pulse state, so that the second voltage is smaller than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the damage to the memory cell can be reduced, and the reliability of the memory cell is improved; therefore, the reliable and efficient erasing operation can be carried out in the whole erasing process of the nonvolatile memory.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a flow chart of a method for processing a non-volatile memory according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a method for processing a non-volatile memory according to an embodiment of the present invention;

FIG. 3 is a block diagram of a non-volatile memory processing device according to an embodiment of the present invention;

FIG. 4 is a detailed block diagram of a nonvolatile memory processing apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.