阅读说明：本技术 用于磁隧道结的间隔件堆叠件 (Spacer stack for magnetic tunnel junction ) 是由 刘中伟 蓝锦坤 于 2019-03-05 设计创作，主要内容包括：本发明实施例描述形成具有金属化合物层的间隔件的示例性方法。该方法包括：在互连层上方形成磁隧道结(MTJ)结构和在磁隧道结结构和互连层上方沉积第一间隔件层。该方法还包括在第一间隔材料,磁隧道结结构和互连层上方沉积第二间隔件层,其中,第二间隔件层比第一间隔件层薄,并包括金属化合物。此外,该方法还包括：在第二间隔件层上方和MTJ结构之间沉积第三间隔件层。第二间隔件比第一间隔件薄。本发明实施例涉及用于磁隧道结的间隔件堆叠件。(Embodiments describe an exemplary method of forming a spacer having a metal compound layer. The method comprises the following steps: a Magnetic Tunnel Junction (MTJ) structure is formed over the interconnect layer and a first spacer layer is deposited over the MTJ structure and the interconnect layer. The method also includes depositing a second spacer layer over the first spacer material, the magnetic tunnel junction structure, and the interconnect layer, wherein the second spacer layer is thinner than the first spacer layer and comprises a metal compound. In addition, the method further comprises: a third spacer layer is deposited over the second spacer layer and between the MTJ structures. The second spacer is thinner than the first spacer. Embodiments of the invention relate to a spacer stack for a magnetic tunnel junction.)

1. A method for forming a semiconductor structure, comprising:

forming a Magnetic Tunnel Junction (MTJ) structure over the interconnect layer;

depositing a first spacer layer over the magnetic tunnel junction structure and the interconnect layer, wherein the first spacer layer is etched to expose a top electrode of the magnetic tunnel junction structure and the interconnect layer;

depositing a second spacer layer over the first spacer layer, the magnetic tunnel junction structure and the interconnect layer, wherein the second spacer layer is thinner than the first spacer layer and comprises a metal compound; and

the second spacer layer is etched to expose a top electrode of the magnetic tunnel junction structure.

2. The method of claim 1, wherein depositing the second spacer layer comprises:

exposing the first spacer layer, the magnetic tunnel junction structure, and the interconnect layer to an ammonia plasma or a nitrogen plasma;

exposing the first spacer layer, the magnetic tunnel junction structure and the interconnect layer to a trimethylaluminum precursor to form a partially decomposed precursor layer on the first spacer layer, the magnetic tunnel junction structure and the interconnect layer; and

the partially decomposed precursor layer is exposed to ammonia gas or 1-butanol gas to form aluminum nitride or aluminum oxide, respectively.

3. The method of claim 1, wherein the metal compound comprises aluminum oxide, wherein the ratio of aluminum to oxygen is between 1.2 and 2.3, and the dielectric constant is between 7 and 9.5.

4. The method of claim 1, wherein the metal compound comprises aluminum nitride, wherein the ratio of aluminum to nitrogen is between 0.67 and 2.3, and the dielectric constant is between 7 and 9.5.

5. The method of claim 1, wherein the metal compound comprises titanium nitride, titanium oxide, or ruthenium oxide.

6. The method of claim 1, wherein the first spacer layer comprises silicon nitride, silicon carbonitride, or a combination thereof.

7. A semiconductor structure, comprising:

a substrate having transistors, contact layers, and one or more interconnect layers disposed thereon;

one or more Magnetic Tunnel Junction (MTJ) structures located above the one or more interconnect layers, wherein a bottom electrode of the one or more magnetic tunnel junction structures is disposed over a via in a top interconnect layer of the one or more interconnect layers;

a first spacer on each sidewall surface of the one or more magnetic tunnel junction structures;

a metal compound layer over each sidewall surface of the one or more magnetic tunnel junction structures and over the top interconnect layer, wherein the metal compound layer forms a second spacer that is thinner than the first spacer; and

a third spacer on the metal compound layer, wherein the third spacer is thicker than the second spacer and is disposed between the magnetic tunnel junction structures.

8. The semiconductor structure of claim 7, wherein the first spacer, the metal compound layer, and the third spacer form a spacer stack having a thickness of less than 30 nm.

9. The semiconductor structure of claim 7, wherein the metal compound layer comprises an aluminum-based nitride or oxide having a thickness between 5 and 50 angstroms.

10. A semiconductor structure, comprising:

an interconnect layer over the substrate and including lines and vias;

a Magnetic Tunnel Junction (MTJ) structure disposed over a via in the interconnect layer, wherein a bottom electrode of the MTJ structure is in contact with the via in the interconnect layer;

a first spacer on each sidewall surface of the magnetic tunnel junction structure; and

a second spacer over the first spacer and the interconnect layer, wherein the second spacer comprises a metal compound layer.

Technical Field

Embodiments of the invention relate to a spacer stack for a magnetic tunnel junction.

Background

Magnetic Tunnel Junctions (MTJs) are an integral part of Magnetic Random Access Memories (MRAMs). The fabrication process of the MTJ structure may involve various operations such as metal and dielectric deposition, photolithography, etching processes, and the like. The MTJs may be formed between back end of line (BEOL) interconnect layers and separated bilaterally by a spacer stack, which may be formed on sidewalls of each MTJ structure.

Disclosure of Invention

According to some embodiments of the present invention, there is provided a method for forming a semiconductor device, including: forming a Magnetic Tunnel Junction (MTJ) structure over the interconnect layer; depositing a first spacer layer over the magnetic tunnel junction structure and the interconnect layer, wherein the first spacer layer is etched to expose a top electrode of the magnetic tunnel junction structure and the interconnect layer; depositing a second spacer layer over the first spacer layer, the magnetic tunnel junction structure and the interconnect layer, wherein the second spacer layer is thinner than the first spacer layer and comprises a metal compound; and etching the second spacer layer to expose a top electrode of the magnetic tunnel junction structure.

According to further embodiments of the present invention, there is also provided a semiconductor structure including: a substrate having transistors, contact layers, and one or more interconnect layers disposed thereon; one or more Magnetic Tunnel Junction (MTJ) structures located above the one or more interconnect layers, wherein a bottom electrode of the one or more magnetic tunnel junction structures is disposed over a via in a top interconnect layer of the one or more interconnect layers; a first spacer on each sidewall surface of the one or more magnetic tunnel junction structures; a metal compound layer over each sidewall surface of the one or more magnetic tunnel junction structures and over the top interconnect layer, wherein the metal compound layer forms a second spacer that is thinner than the first spacer; and a third spacer on the metal compound layer, wherein the third spacer is thicker than the second spacer and is disposed between the magnetic tunnel junction structures.

There is also provided, in accordance with yet other embodiments of the present invention, a semiconductor structure, including: an interconnect layer over the substrate and including lines and vias; a Magnetic Tunnel Junction (MTJ) structure disposed over a via in the interconnect layer, wherein a bottom electrode of the MTJ structure is in contact with the via in the interconnect layer; a first spacer on each sidewall surface of the magnetic tunnel junction structure; and a second spacer located over the first spacer and the interconnect layer, wherein the second spacer includes a metal compound layer.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flow chart of an exemplary fabrication method for forming a magnetic tunnel junction structure having a spacer stack featuring a metal compound layer, in accordance with some embodiments.

FIG. 2 is a cross-sectional view of an exemplary magnetic tunnel junction layer above an interconnect layer in accordance with some embodiments.

FIG. 3 is a cross-sectional view of a magnetic tunnel junction structure over a via in an interconnect layer after a lithography and etch operation, in accordance with some embodiments.

FIG. 4 is a cross-sectional view of a magnetic tunnel junction structure over an interconnect layer after depositing a first spacer layer in accordance with some embodiments.

Figure 5 is a cross-sectional view of a magnetic tunnel junction structure over an interconnect layer after an etch-back process of a first spacer layer, in accordance with some embodiments.

FIG. 6 is a cross-sectional view of a magnetic tunnel junction structure over an interconnect layer after depositing a metal compound layer, in accordance with some embodiments.

FIG. 7 is a cross-sectional view of a magnetic tunnel junction structure above an interconnect layer after an etch-back process of a metal compound layer, in accordance with some embodiments.

FIG. 8 is a cross-sectional view of a magnetic tunnel junction structure over an interconnect layer after depositing a third spacer layer and a dielectric layer, in accordance with some embodiments.

FIG. 9 is a cross-sectional view of a magnetic tunnel junction structure having a spacer stack over an interconnect layer after a chemical mechanical planarization process in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "about" as used herein denotes a value of a given quantity that may vary based on the particular technology node associated with the subject semiconductor device. The term "about" can indicate a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ± 10%, ± 20% or ± 30% of the value), based on the particular technology node.

The term "nominal" as used herein refers to a desired or target value, and a range of values above and/or below a desired value, of a feature or parameter of a component or process operation set during a design phase of a product or process. The range of values may be due to minor variations in manufacturing processes or tolerances. Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

As used herein, the term "substantially" means that the quantitative value varies within the range of ± 1% to ± 5% of the value.

Magnetic Tunnel Junctions (MTJs) are an integral part of Magnetic Random Access Memories (MRAMs). The fabrication process of the MTJ structure may involve various process operations including metal and dielectric deposition, photolithography, etching operations, and the like. The MTJ stack may be interposed between back end of line (BEOL) interconnect layers and bilaterally separated by a spacer stack formed on sidewalls of each MTJ structure. The spacer stack functions to electrically isolate the MTJ stacks from each other. As MRAM cells shrink from one technology generation (node) to the next, the spacing (e.g., spacing) between adjacent MTJ structures decreases. Therefore, a thinner spacer stack is needed to fill the space between the MTJ structures. Maintaining electrical isolation of MTJ structures in an MRAM cell can be challenging for thinner spacer stacks (e.g., spacer stacks having thicknesses below about 30 nm) when the spacing between the MTJ structures is reduced (e.g., below 92 nm).

Embodiments described herein relate to an exemplary manufacturing method describing formation of a spacer stack. In some embodiments, the thickness of the spacer stack between MTJ structures is below about 30nm (e.g., about 25nm) and the spacer stack pitch is between about 80nm and about 92 nm. In some embodiments, the spacer stack may include a metal compound layer having improved dielectric properties (e.g., electrical isolation properties). The metal compound layer may include aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, ruthenium oxide, or any other suitable material, and may have a thickness of less than about 5nm (e.g., about 3 nm). A metal compound layer may be interposed between layers of silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbide, silicon oxide, or combinations thereof to form a spacer stack on each sidewall surface of the MTJ structure. In some embodiments, the metal compound layer is deposited by thermal atomic layer deposition or plasma assisted atomic layer deposition. According to some embodiments, the spacer stack having the metal compound layer exhibits improved electrical isolation characteristics compared to the spacer stack without the metal compound layer. Thus, the spacer stack with the metal compound layer may be more compact (e.g., thinner).

Fig. 1 is a flow chart of an exemplary method of manufacturing 100, which describes the formation of an MTJ spacer stack with a metal compound layer, in accordance with some embodiments. According to some embodiments, the metal compound layer may be deposited using thermal Atomic Layer Deposition (ALD) or Plasma Enhanced Atomic Layer Deposition (PEALD) at a temperature range of about 150 ℃ to about 400 ℃. The manufacturing method 100 is not limited to the operations described below. Other fabrication operations (e.g., wet cleans, additional lithography and deposition operations, etc.) may be performed between various operations of the fabrication method 100 and may be omitted for clarity only. These manufacturing operations are within the spirit and scope of the present disclosure even if not described.

With reference to fig. 1, the exemplary method of fabricating 100 begins at operation 110 and forms one or more MTJ structures over an interconnect layer. The formation of one or more MTJ structures will be described using fig. 2 and 3 as examples. Fig. 2 is a cross-sectional view of a blanket deposited MTJ layer 200 over one or more interconnect layers 205. The MTJ layer 200 may include a bottom electrode 210, an MTJ stack 215, and a top electrode 220. By way of example and not limitation, MTJ stack 215 may be a multilayer structure including a non-conductive layer interposed between two ferromagnetic layers. For simplicity, the non-conductive and ferromagnetic layers in MTJ stack 215 are not shown in fig. 2. By way of example and not limitation, the non-conductive layer of MTJ stack 215 may include magnesium oxide (MgO), aluminum oxide (AlO)_x) Aluminum oxynitride (AlON), any other suitable material, or a combination thereof. Further, the non-conductive layer may be deposited by Physical Vapor Deposition (PVD). Alternatively, the non-conductive layer may be deposited by other deposition methods, such as plasma enhanced PVD (PEVD), Chemical Vapor Deposition (CVD), Plasma Enhanced CVD (PECVD), ALD, PEALD, or any other suitable deposition method. The ferromagnetic layer of MTJ stack 215 can includeA metal stack having one or more layers comprising iron (Fe), cobalt (Co), ruthenium (Ru), magnesium (Mg), any other suitable material, or a combination thereof. The ferromagnetic layer may be deposited by PVD, PEVD, CVD, PECVD, ALD, PEALD, or any other suitable deposition method. In some embodiments, the combined thickness of the MTJ layers 200 may be about

To about

Within the range of (1).

The top electrode 220 and the bottom electrode 210 are in contact with respective ferromagnetic layers of the MTJ stack 215. By way of example and not limitation, the top electrode 220 may comprise tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), any other suitable material, or a combination thereof. Further, the top electrode 220 may be deposited by a CVD or PVD method. In some embodiments, the top electrode 220 may be a stack comprising TiN and TaN layers. The bottom electrode 210 may comprise TiN, TaN, Ru, copper (Cu), any other suitable material, or a combination thereof. The bottom electrode 210 may also be deposited by CVD or PVD methods. In some embodiments, the top electrode 220 and the bottom electrode 210 may each have between aboutAnd aboutTo the thickness of (d) in between.

In some embodiments, the interconnect layer 205 may be formed prior to forming the MTJ layer 200. According to some embodiments, interconnect layer 205 may be formed over a previously formed interconnect layer, not shown in fig. 2 for simplicity. These previously formed interconnect layers may include, for example, BEOL interconnect layers, mid-line-of-the-line (MOL) layers (e.g., contact interconnects), and Field Effect Transistors (FETs) formed over a substrate (e.g., wafer). By way of example and not limitation, the interconnect layer 205 may be a BEOL layer with several vertical interconnect access lines and lateral lines (also referred to herein as "lines"). Interconnect layer 205 in fig. 2 is shown with vias 225, but for simplicity, no wires are included. For purposes of example, the vias 225 are described as having an interconnect layer 205. However, based on the disclosure herein, the lines are also part of the interconnect layer 205 and are within the spirit and scope of the present disclosure. Further, the number of through-holes 225 shown in fig. 2 is not limiting, and additional through-holes 225 are possible.

According to some embodiments, the vias 225 (and lines) of the interconnect layer 205 may be filled with a metal stack that includes at least a barrier layer 230 and a metal filler 235. The barrier layer 230 may be a single layer or a stack of two or more layers. In some embodiments, the metal filler 235 may be a plated metal or metal alloy. By way of example and not limitation, barrier layer 230 may be a tantalum (TaN)/tantalum (Ta) stack or a cobalt (Co) monolayer deposited by PVD. The metal fill 235 may be electroplated copper or an electroplated copper alloy, such as copper-manganese, copper-ruthenium, or any other suitable material. The lines of vias (e.g., via 225) and interconnect layer 205 are embedded in interlayer dielectric (ILD) layers 240 and 245. In some embodiments, ILD layers 240 and 245 may be silicon oxide or a low-k material having a dielectric constant lower than that of thermally grown silicon oxide (e.g., lower than 3.9). In some embodiments, ILD layers 240 and 245 may be a stack of dielectrics, for example, a low-k dielectric and another dielectric: (i) low-k dielectrics (e.g., carbon-doped silicon oxide) and nitrogen-doped silicon carbide; (ii) low-k dielectrics and oxygen-doped silicon carbide; (iii) a low-k dielectric with silicon nitride; or (iv) a low-k dielectric with silicon oxide. In addition, ILD layers 240 and 245 may be deposited by a high density plasma cvd (hdpcvd) or PECVD process. In some embodiments, ILD layer 240 may be different from ILD layer 245. For example, ILD layer 240 may be carbon doped silicon oxide (SiOC), and ILD layer 245 may be silicon oxide. In some embodiments, etch stop layers 250 and 255 are interposed between ILD layers 240 and 245. By way of example and not limitation, the etch stop layer 250 may comprise silicon carbonitride (SiCN) or aluminum nitride (AlN) and may have a thickness of about

And the combination

To the thickness of (d) in between. The etch stop layer 245 may comprise alumina and may have a thickness of between about

And the combinationTo the thickness of (d) in between. Etch stop layers 250 and 255 are used during the formation of via 225.

The MTJ layers 200 may be patterned using photolithography and etching operations. As a result, one or more MTJ structures may be formed in accordance with operation 110 of method 100. For example, a mask layer (not shown in fig. 2) may be disposed and patterned over the top electrode 220. The mask layer may comprise one or more layers and have an approximate thickness

Of the substrate is described. By way of example and not limitation, the mask layer may include a layer stack having a bottom oxide layer and a top amorphous carbon layer. Any portions of the MTJ layer 200 not covered by the patterned mask layer may be removed during a subsequent etching operation.

As shown in fig. 3, the MTJ structure 300 may be formed from an unetched portion of the MTJ layer 200 above the interconnect layer 205. In some embodiments, the patterned masking layer is aligned with the via 225 of the interconnect layer 205 such that the MTJ structure 300 is formed on top of the via 225, as shown in fig. 3. Thus, each bottom electrode 210 of the MTJ structure 300 may be in electrical and physical contact with a respective via 225 of the underlying interconnect layer 205. Additionally, and as a result of the etching process described above, during formation of MTJ structure 300, a top surface of ILD layer 245 may be recessed relative to a top surface of via 225. After the etching process, the patterned mask layer on top of the MTJ structure 300, not shown in FIG. 3, can be removed with a wet clean process.

According to some embodiments, the pitch P between adjacent MTJ structures 300 may be in a range of about 80nm to about 92nm (e.g., about 82nm), depending on the MRAM layout design. This means that the space between the sidewalls of adjacent (e.g., neighboring) MTJ structures 300 may be less than about 80 nm.

Referring to fig. 1, the method 100 continues with operation 120 and a first spacer is formed on each sidewall of the one or more MTJ structures 300. By way of example, and not limitation, the first spacer formation process may be described using fig. 4 and 5. Referring to fig. 4, a first spacer material 400 may be blanket deposited over MTJ structure 300 and ILD layer 245 to a thickness of aboutAnd the combination

Between (e.g., about)

). In some embodiments, the spacer material 400 may comprise silicon nitride (SiN), silicon carbonitride (SiCN), any suitable material, or combinations thereof. For example, the first spacer material 400 may be a single layer or a stack having a bottom layer of SiN and a top layer of SiCN. In some embodiments, the spacer material 400 may be conformally deposited by an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process at a temperature of about 100 ℃ to about 400 ℃. The process pressure may be between about 0.5 torr and about 10 torr during deposition. The above process pressure ranges are exemplary, and other ranges may be used.

After depositing the first spacer material 400, an anisotropic etch back process may be used to selectively remove the first spacer material 400 from horizontal surfaces of the MTJ structure 300 (e.g., from a top surface of the top electrode 220) and the ILD layer 245. The anisotropic etch-back process (e.g., a directional etch process) may be configured to exhibit a higher removal rate (e.g., at least 2 times or more higher) for the first spacer material 400 on horizontal surfaces than for non-horizontal surfaces, such as sidewall surfaces of the MTJ structure 300. Accordingly, the unetched portions of the first spacer material 400 covering the sidewall surfaces of the MTJ structure 300 may form a first spacer 500, as shown in fig. 5. In some embodiments, the first spacer material 400 is recessed from the top corners of the top electrode 220 due to the anisotropic nature of the etch-back process. Accordingly, as shown in fig. 5, the first spacers 500 do not cover the entire sidewall surface of the top electrode 220.

According to some embodiments, the anisotropic etch-back process may include an ion beam etching process with inductively coupled plasma (RIE-ICP) or a Reactive Ion Etching (RIE) process. In some embodiments, the ion beam etching process may use an ion beam that selectively targets the region where etching is to be performed. The ion beam may be generated from a helium (He), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe) plasma. By way of example and not limitation, the energy of the ion beam during the etching process may be between about 100eV and about 1200 eV. Alternatively, the RIE-ICP process may use an etchant such as tetrafluoromethane (CF)₄) Difluoromethane (CH)₂F₂) Chlorine (Cl)₂) Ar, He, organic gases or combinations thereof.

With reference to fig. 1, the method 100 continues with operation 130 in which a metal compound layer is deposited over the first spacer, the one or more MTJ structures 300, and the top interconnect layer 205. For example, as shown in fig. 6, the metal compound layer 600 may be conformally deposited over the first spacer 500, the MTJ structure 300, and the interconnect layer 205. According to some embodiments, the metallic compound layer 600 may be conformally deposited by a thermal ALD or plasma enhanced ALD process to a thickness between about 5 and about 50 angstroms (e.g., about 30 angstroms). In other words, the metal compound layer 600 thus deposited may be thinner than the first spacer 500. In a thermal ALD process, the deposition temperature may range from about 150 ℃ to about 400 ℃. On the other hand, the deposition temperature of the plasma enhanced process may be lower. For example, the deposition temperature of the plasma enhanced process may be between about 50 ℃ and about 350 ℃ (e.g., 100 ℃, 150 ℃, 200 ℃, 350 ℃, etc.). In some embodiments, the process pressure for thermal and plasma enhanced ALD may be in the range of about 0.5 torr to about 10 torr. The above process pressure ranges are exemplary, and other ranges may be used. According to some embodiments, the metal compound layer 600 may include aluminum nitride (AlN)_x) Aluminum oxide (AlO)_x) Titanium nitride (TiN), titanium oxide (TiO)_x) Ruthenium oxide (RuO)_x) Or any other suitable material. For example, for purposes of example, the metallic compound layer 600 in the method 100 will be described in the context of an aluminum-based layer, such as aluminum nitride and aluminum oxide. Other metal compound layers as described above may be used based on the disclosure herein. These other metal compound layers are within the spirit and scope of the present disclosure.

For the metal compound layer 600 including aluminum nitride or aluminum oxide, Trimethylaluminum (TMA) (Al) may be used₂(CH₃)₆) The precursor serves as the aluminum source for the deposited film. By way of example, and not limitation, the formation of aluminum nitride may be described as follows. First, with ammonia (NH)₃) Thermally pre-treating the first spacer 500, the MTJ structure 300 and the ILD layer 245; for example, a wafer with the MTJ structure 300 and the interconnect layer 205 is exposed to ammonia (NH)₃) A gas. Alternatively, first spacer 500, MTJ structure 300, and ILD layer 245 may be plasma treated. In some embodiments, the plasma may include (i) a mixture of ammonia and helium, hydrogen, or argon; (ii) mixtures of nitrogen with helium, hydrogen or argon. The plasma treatment may be performed at a temperature similar to the deposition temperature (e.g., between about 150 ℃ and about 400 ℃) and at a process pressure similar to the deposition process pressure (e.g., between about 0.5 torr and about 10 torr). As a result of pretreatment (e.g., heat or plasma), amino radicals (NH)₂) May be chemisorbed on the exposed surfaces of the first spacer 500, MTJ structure 300 and ILD layer 245. Unreacted NH can subsequently be removed by purging₃A gas. A TMA soak may then be performed in which the precursor is introduced and chemically reacted with the amino radicals on the exposed surface. As a result of the reaction, the precursor partially decomposes (e.g., releases methyl groups) and attaches itself to amino groups on the surface. Subsequent purging removes any unreacted TMA precursor and by-products of the reaction between the amino radical and the TMA precursor (e.g., methane, CH)₄). Then reintroducing NH₃The gas reacts with the partially decomposed precursor to form aluminum nitride. Subsequent purging removes by-products of the chemical reaction (e.g., methane) and any unreacted NH₃A gas.

The above-described process sequence produces an aluminum nitride film having a thickness in the range of about a thickness depending on the process conditions (e.g., process pressure, temperature, gas and precursor flow, etc.)To about

Within the range of (1). Thus, the deposition process sequence may be repeated as necessary until a desired thickness of the aluminum nitride metal compound layer is achieved (e.g., at about

And the combination

In between).

In some embodiments, post-treatment may be used to densify the deposited aluminum nitride; for example by removing hydrogen. For example, Radio Frequency (RF) NH₃The plasma may be used to remove hydrogen from the aluminum nitride layer. According to some embodiments, the RF power applied to the plasma may be in the range of about 100 watts to about 500 watts. However, the aforementioned RF power ranges should not be considered limiting, and other ranges may be used. By way of example and not limitation, the post-treatment may last up to one minute and may be performed in situ using the deposition process described above. The nitrogen to aluminum ratio (N/Al) of the resulting aluminum nitride layer may be between about 0.67 and about 2.3. Thus, the aluminum atomic percent in the aluminum nitride layer may be from about 40 to about 70 and the nitrogen atomic percent from about 30 to about 60, as measured by X-ray photoelectron spectroscopy (XPS) or other suitable method. Since the aluminum source is TMA (e.g., an organometallic precursor), trace amounts of residual carbon may be found in the aluminum nitride layer. For example, the atomic percent of carbon in the aluminum nitride layer may be in a range of about 1 to about 2. In some embodiments, the treated aluminum nitride can have a dielectric constant of about 7 to about 8 and a density of about 2g/cm when measured by X-ray reflectometry³To about 3g/cm³Within the range of (1). Due to their high dielectric constantElectrical constants and densities, a thin aluminum nitride layer (e.g., less than 50 angstroms) may provide improved electrical isolation compared to layers having lower dielectric constants (e.g., silicon oxide, silicon nitride, silicon carbonitride, etc.).

The deposition of the aluminum oxide metal compound layer is very similar to the process sequence described above for aluminum nitride. However, in the case of alumina deposition, TMA purged NH₃The exposure may be performed with 1-butanol (C)₄H₉OH) in which the partially decomposed TMA precursor may react with 1-butanol to form aluminum-oxygen bonds and eventually alumina. Similarly to the case of aluminum nitride, RF NH is used₃Post-treatment of the plasma may be used to densify the deposited aluminum oxide metal compound layer by removing hydrogen. According to some embodiments, the RF power applied to the plasma may be in the range of about 100 watts to about 500 watts. The aluminum nitride film obtained may have an aluminum to oxygen ratio (Al/O) of about 1.2 to about 2.3. Further, the atomic percent of aluminum may be between about 30 and about 45 and the atomic percent of nitrogen may be between about 55 and about 70 as measured by XPS. By way of example and not limitation, the atomic percent of hydrogen in the plasma treated aluminum oxide film may be in the range of 0 to about 3 as measured by Rutherford Backscattering Spectroscopy (RBS). In some embodiments, the aluminum oxide metal compound layer formed may have a dielectric constant between about 7 and about 9.5 and a density of about 3g/cm as measured by X-ray reflectometry³To about 3.53g/cm³Within the range of (1). Due to their high dielectric constant and density, thin aluminum oxide layers (e.g., less than 50 angstroms) may provide improved electrical isolation compared to layers having lower dielectric constants such as silicon oxide, silicon nitride, silicon carbonitride, and the like.

Referring to fig. 1 and 7, the method 100 continues with operation 140, where an etch-back process may be used to recess the metal compound layer 600 such that a second spacer 600 may be formed on each sidewall of the MTJ structure 300. In some embodiments, the etch-back process will partially remove the metal compound layer 600 located above the top surface of the ILD layer 245 and will expose a portion of the top electrode 220 of the MTJ structure 300, as shown in fig. 7. In some embodiments, the etch-back process of operation 120May be used in operation 140. For example, the etch-back process of operation 140 may use an ion beam etching process or a Reactive Ion Etching (RIE) process with inductively coupled plasma (RIE-ICP). In some embodiments, the ion beam etching process may use an ion beam that selectively targets the region where etching is to be performed. The ion beam may be generated from a helium (He), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe) plasma. By way of example and not limitation, the energy of the ion beam during the etching process may be between about 100eV and about 1200 eV. Alternatively, the RIE-ICP process may use an etchant such as tetrafluoromethane (CF)₄) Difluoromethane (CH)₂F₂) Chlorine Cl₂Ar, He, organic gases or combinations thereof. The etch-back process for forming the first and second spacers (e.g., the first spacer 500 and the second spacer 600) is not limited to the above-described etch-back process. Accordingly, the first and second spacers 500 and 600 may be formed using an alternative etch-back process. Further, in some embodiments, the aluminum nitride or aluminum oxide metallic compound layer 600 may exhibit an approximate ratio of 2: 1 to about 10: 1 (e.g., 2: 1, 5: 1, 8: 1, 10: 1). However, the above selectivity range is not limiting, and higher selectivity ratios are possible (e.g., 50: 1).

In referring to fig. 1, the method 100 continues with operation 150 and forming a third spacer over the second spacer (e.g., the etched metal compound layer 600). Referring to fig. 8, a third spacer 800 may be blanket deposited over the metal compound layer 600. In some embodiments, the third spacer 800 comprises a dielectric material, such as silicon nitride, silicon carbonitride, silicon oxide, carbon doped silicon oxide, or silicon oxide-carbon nitride having a thickness between about 100 angstroms and about 500 angstroms (e.g., about 150 angstroms). Accordingly, in some embodiments, the third spacer 800 may be thicker than the metal compound layer 600 (e.g., the second spacer). As described above, the pitch P between the MTJ structures 300 shown in fig. 1 may be in the range of approximately 80nm and 92 nm. Therefore, after the first and second spacers are formed, the spacing between the MTJ structures 300 will be reduced to less than 80 nm. Accordingly, it is desirable that the third spacer 800 may be deposited using a deposition method having an enhanced gap filling characteristic. By way of example and not limitation, the third spacers 800 may be deposited by PEALD, CVD, ALD, or a deposition method with enhanced gap filling capability such that the third spacers 800 may fill the spaces between the MTJ structures 300, as shown in fig. 8.

According to some embodiments, the first spacer 500, the metal compound layer 600 (second spacer), and the third spacer 800 form a spacer stack, wherein the metal compound layer 600 (second spacer) is thinner than the first spacer 500 and the third spacer 800. Further, the spacer stack may have a thickness of about 30 nm.

In some embodiments, a dielectric layer 805 may be deposited over the third spacer 800. By way of example, and not limitation, dielectric layer 805 may be silicon oxide (SiO) grown with Tetraethoxysilane (TEOS)₂) An interlayer dielectric. Alternatively, dielectric layer 805 may be a low dielectric constant interlayer dielectric; for example, the dielectric constant is lower than 3.9. In some embodiments, the dielectric layer 805 may have a thickness of about

Or a greater thickness. A Chemical Mechanical Planarization (CMP) process may polish the dielectric layer 805 such that a top surface of the top electrode 220 and a top surface of the dielectric layer 805 may be substantially coplanar, as shown in fig. 9. According to some embodiments, additional interconnect layers (not shown in fig. 9) may be formed over the dielectric layer 805 and the planarized surface of the MTJ structure 300, such that the top electrode 220 may be connected to respective vias in the interconnect layers above the MTJ structure 300.

In some embodiments, a spacer stack having a metal compound layer (such as aluminum nitride or aluminum oxide) may exhibit improved dielectric properties compared to a spacer stack limited to a silicon-based layer such as silicon nitride, silicon carbonitride, silicon oxide, carbon-doped silicon oxide, or silicon oxycarbonitride. Thus, the spacer stack with the metal compound layer can be compact (e.g., having less than about

Thickness of) and is suitable for having tight spacing between MTJ structures(e.g., between about 80nm and about 92 nm). In addition, the spacer stack having the metal compound layer exhibits improved etching characteristics. For example, a spacer stack having a metal compound layer may exhibit improved etch resistance and selectivity (e.g., between about 2: 1 and about 10: 1). As a result, the spacer stack having the metal compound layer is not easily damaged by etching during the subsequent etch-back process.

The present disclosure relates to an exemplary manufacturing method for forming a spacer stack having a metal compound layer therein. In some embodiments, the metal layer may improve electrical isolation between adjacent MTJ structures. By way of example and not limitation, the spacer stack can include a 5nm or less (e.g., about 3nm) metal compound layer, which can include aluminum oxide, aluminum nitride, titanium oxide, titanium nitride, ruthenium oxide, or any other suitable material. A metal compound layer may be interposed between layers of silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, silicon oxide, or combinations thereof to form a spacer stack on each sidewall surface of the MTJ structure. In some embodiments, the metal compound layer may be conformally deposited using a thermal atomic layer deposition or a plasma-enhanced atomic layer deposition process. According to some embodiments, the spacer stack having the metal compound layer exhibits improved electrical isolation characteristics, and thus may be more compact (e.g., thinner) than the spacer stack without the metal compound layer.

In some embodiments, a method comprises: a Magnetic Tunnel Junction (MTJ) structure is formed over the interconnect layer. The method further includes depositing a first spacer layer over the magnetic tunnel junction structure and the interconnect layer, wherein the first spacer layer is etched to expose the top electrode of the magnetic tunnel junction structure and the interconnect layer. The method also includes depositing a second spacer layer over the first spacer material, the magnetic tunnel junction structure, and the interconnect layer, wherein the second spacer layer is thinner than the first spacer layer and comprises a metal compound. In addition, the method further comprises: the second spacer layer is etched to expose a top electrode of the magnetic tunnel junction structure.

In some embodiments, a structure comprises: a substrate having a transistor, a contact layer, and one or more interconnect layers disposed on the substrate. The structure also includes one or more Magnetic Tunnel Junction (MTJ) structures located over the one or more interconnect layers. Wherein the bottom electrode of the one or more magnetic tunnel junction structures is disposed over a via in a top interconnect layer of the one or more interconnect layers. The structure also includes a first spacer on each sidewall surface of the one or more magnetic tunnel junction structures and a metal compound layer over each sidewall surface of the one or more magnetic tunnel junction structures and over the top interconnect layer, wherein the metal compound layer forms a second spacer that is thinner than the first spacer. The structure further includes a third spacer on the metal compound layer, wherein the third spacer is thicker than the second spacer and is disposed between the magnetic tunnel junction structures.

In some embodiments, a structure comprises: an interconnect layer over the substrate and including a line and a via, and a Magnetic Tunnel Junction (MTJ) structure disposed over the via in the interconnect layer, wherein a bottom electrode of the magnetic tunnel junction structure is in contact with the via in the interconnect layer. The structure further includes a first spacer located on each sidewall surface of the magnetic tunnel junction structure; and a second spacer located over the first spacer and the interconnect layer, wherein the second spacer includes a metal compound layer.

According to some embodiments of the present invention, there is provided a method for forming a semiconductor device, including: forming a Magnetic Tunnel Junction (MTJ) structure over the interconnect layer; depositing a first spacer layer over the magnetic tunnel junction structure and the interconnect layer, wherein the first spacer layer is etched to expose a top electrode of the magnetic tunnel junction structure and the interconnect layer; depositing a second spacer layer over the first spacer layer, the magnetic tunnel junction structure and the interconnect layer, wherein the second spacer layer is thinner than the first spacer layer and comprises a metal compound; and etching the second spacer layer to expose a top electrode of the magnetic tunnel junction structure.

In the above method, depositing the second spacer layer comprises: exposing the first spacer layer, the magnetic tunnel junction structure, and the interconnect layer to an ammonia plasma or a nitrogen plasma; exposing the first spacer layer, the magnetic tunnel junction structure and the interconnect layer to a trimethylaluminum precursor to form a partially decomposed precursor layer on the first spacer layer, the magnetic tunnel junction structure and the interconnect layer; and exposing the partially decomposed precursor layer to ammonia gas or 1-butanol gas to form aluminum nitride or aluminum oxide, respectively.

In the above method, the metal compound comprises alumina, wherein the ratio of aluminum to oxygen is between 1.2 and 2.3 and the dielectric constant is between 7 and 9.5.

In the above method, the metal compound comprises aluminum nitride, wherein the ratio of aluminum to nitrogen is between 0.67 and 2.3 and the dielectric constant is between 7 and 9.5.

In the above method, the metal compound includes titanium nitride, titanium oxide or ruthenium oxide.

In the above method, the first spacer layer comprises silicon nitride, silicon carbonitride, or a combination thereof.

According to further embodiments of the present invention, there is also provided a semiconductor structure including: a substrate having transistors, contact layers, and one or more interconnect layers disposed thereon; one or more Magnetic Tunnel Junction (MTJ) structures located above the one or more interconnect layers, wherein a bottom electrode of the one or more magnetic tunnel junction structures is disposed over a via in a top interconnect layer of the one or more interconnect layers; a first spacer on each sidewall surface of the one or more magnetic tunnel junction structures; a metal compound layer over each sidewall surface of the one or more magnetic tunnel junction structures and over the top interconnect layer, wherein the metal compound layer forms a second spacer that is thinner than the first spacer; and a third spacer on the metal compound layer, wherein the third spacer is thicker than the second spacer and is disposed between the magnetic tunnel junction structures.

In the above semiconductor structure, the first spacer, the metal compound layer and the third spacer form a spacer stack having a thickness of less than 30 nm.

In the above semiconductor structure, the metal compound layer includes an aluminum-based nitride or an aluminum-based oxide having a thickness of between 5 angstroms and 50 angstroms.

In the above semiconductor structure, the metal compound layer includes an aluminum oxide layer in which a ratio of oxygen to aluminum is between 1.2 and 2.3 and an atomic percent of aluminum is between 30 and 45.

In the above semiconductor structure, the metal compound layer includes titanium oxide, titanium nitride, or ruthenium oxide.

In the above semiconductor structure, the first spacer has a thickness between 30 angstroms and 200 angstroms and comprises silicon nitride, silicon carbonitride or a combination thereof.

In the above semiconductor structure, the third spacer has a thickness of less than 200 angstroms and comprises silicon nitride, silicon carbonitride, silicon oxide, carbon doped silicon oxide, silicon oxycarbonitride, or a combination thereof.

In the above semiconductor structure, further comprising: an interlayer dielectric surrounding the third spacer; and another interconnect layer over the interlayer dielectric and the one or more magnetic tunnel junction structures, wherein a top electrode of the one or more magnetic tunnel junction structures is in contact with a via in the another interconnect layer.

There is also provided, in accordance with yet other embodiments of the present invention, a semiconductor structure, including: an interconnect layer over the substrate and including lines and vias; a Magnetic Tunnel Junction (MTJ) structure disposed over a via in the interconnect layer, wherein a bottom electrode of the MTJ structure is in contact with the via in the interconnect layer; a first spacer on each sidewall surface of the magnetic tunnel junction structure; and a second spacer located over the first spacer and the interconnect layer, wherein the second spacer includes a metal compound layer.

In the above semiconductor structure, a third spacer is further included; and a dielectric layer surrounding the third spacer, wherein a top surface of the dielectric layer is coplanar with a top surface of the third spacer and a top surface of the top electrode of the magnetic tunnel junction structure.

In the above semiconductor structure, a combined thickness of the first spacer, the second spacer, and the third spacer is less than 30 nm.

In the above semiconductor structure, the magnetic tunnel junction structures are spaced apart at a pitch of 80nm to 92 nm.

In the above semiconductor structure, the metal compound layer has a thickness of less than 50 angstroms and includes aluminum oxide, aluminum nitride, titanium oxide, or ruthenium oxide.

In the above semiconductor structure, an additional interconnect layer, a contact layer, and a transistor are interposed between the interconnect layer and the substrate.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.