阅读说明：本技术 存储器装置及其操作方法 (Memory device and operation method thereof ) 是由 俞昌渊 金敏洙 朴贤郁 任琫淳 于 2019-05-14 设计创作，主要内容包括：公开一种存储器装置及其操作方法。所述存储器装置包括单元阵列和页缓冲器电路。单元阵列包括分别连接到第一位线和第二位线的第一单元串和第二单元串。页缓冲器电路被配置为：当对第一单元串和第二单元串的存储器单元执行擦除操作时,将擦除电压施加到第一位线并允许第二位线处于浮置状态。(A memory device and a method of operating the same are disclosed. The memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings connected to first and second bit lines, respectively. The page buffer circuit is configured to: when an erase operation is performed on the memory cells of the first cell string and the second cell string, an erase voltage is applied to the first bit line and the second bit line is allowed to be in a floating state.)

1. A memory device, comprising:

A cell array including first and second cell strings connected to first and second bit lines, respectively; and

a page buffer circuit configured to: when an erase operation is performed on memory cells included in the first cell string and the second cell string, an erase voltage is applied to the first bit line and simultaneously the second bit line is placed in a floating state.

2. The memory device according to claim 1, wherein the page buffer circuit includes:

A first page buffer including a first transistor configured to apply an erase voltage to a first bit line in response to a first control signal; and

A second page buffer configured to prevent an erase voltage from being applied to the second bit line.

3. The memory device according to claim 2, wherein the first page buffer further comprises a second transistor configured to apply a program-inhibit voltage to the first bit line in response to a second control signal,

The second page buffer includes a third transistor configured to apply a program-inhibit voltage to the second bit line in response to a third control signal.

4. The memory device of claim 3, further comprising: a controller configured to control operations of the first and second page buffers using first to third control signals,

Wherein the controller is configured to control the first page buffer to apply the erase voltage to the first bit line using the first control signal and the second control signal,

The first transistor is switched to a conducting state by the first control signal, and the second transistor is switched to a cut-off state by the second control signal.

5. The memory device according to claim 4, wherein the controller is configured to control the second page buffer to place the second bit line in a floating state using a third control signal, wherein the third control signal switches the third transistor to an off state.

6. The memory device of claim 1, wherein the second bit line is coupled to an erase voltage applied to the first bit line.

7. The memory device of claim 1, wherein a length of a first connection line connecting the first bit line to the first cell string is different from a length of a second connection line connecting the second bit line to the second cell string.

8. The memory device of claim 1, wherein the page buffer circuit is further configured to: a precharge operation is performed on the second bit line before the erase voltage is applied to the first bit line.

9. The memory device of claim 8, wherein the precharge operation of the second bit line precharges the second bit line to a negative voltage.

10. A memory device, comprising:

A cell array including first and second cell strings connected to first and second bit lines, respectively;

A first page buffer configured to: applying an erase voltage to the first bit line when an erase operation is performed on memory cells included in the first cell string and the second cell string; and

A second page buffer configured to: when an erase operation is performed, an erase voltage is prevented from being applied to the second bit line.

11. The memory device according to claim 10, wherein the first page buffer comprises:

A first transistor configured to apply an erase voltage to a first bit line in response to a first control signal; and

A second transistor configured to apply a program-inhibit voltage to the first bit line in response to a second control signal,

wherein the second page buffer includes: a third transistor configured to apply a program-inhibit voltage to the second bit line in response to a third control signal.

12. the memory device of claim 11, further comprising: a controller configured to control operations of the first and second page buffers using first to third control signals,

Wherein the controller is configured to: when the erase operation is performed, the third transistor is switched to an off state by adjusting a value of the third control signal.

13. The memory device of claim 12, wherein the controller is further configured to: performing a precharge operation on the second bit line before applying the erase voltage to the first bit line,

The precharge operation of the second bit line includes: the third transistor is switched to an on state using a third control signal.

14. The memory device according to claim 12, wherein the erase operation includes a first period and a second period that are sequentially performed before the first page buffer applies the erase voltage to the first bit line,

wherein, in the first period of time, the controller is configured to: controlling the first transistor and the second transistor to precharge the first bit line to a first precharge voltage, controlling the third transistor to precharge the second bit line to a second precharge voltage,

In the second period, the controller is configured to: the third transistor is controlled to be in a turned-off state to further precharge the second bit line to a negative voltage.

15. The memory device of claim 13, wherein the second bit line is coupled with the first bit line to which the erase voltage is applied.

16. A method of operating a memory device, wherein the memory device includes a controller providing a control signal to a page buffer circuit, and includes first and second cell strings connected to first and second bit lines, respectively, the method comprising:

Receiving, by a controller, an erase command for an erase operation of memory cells included in the first cell string and the second cell string, and providing a control signal in response to the erase command;

Applying an erase voltage from the page buffer circuit to the first bit line in response to a control signal during an erase operation; and

In response to a control signal, the second bit line is placed in a floating state while an erase voltage is applied to the first bit line through the page buffer circuit.

17. The method of claim 16, wherein a length of a first connection line connecting the first bit line to the first cell string is different from a length of a second connection line connecting the second bit line to the second cell string.

18. The method of claim 16, further comprising: a precharge voltage is applied from the page buffer circuit to the second bit line to precharge the second bit line before the erase voltage is applied to the first bit line.

19. The method of claim 16, further comprising: the second bit line is precharged to a negative voltage by the page buffer circuit before the erase voltage is applied to the first bit line.

20. The method of claim 19, wherein precharging the second bit line to a negative voltage through the page buffer circuit comprises:

Applying a first precharge voltage to the first bit line to precharge the first bit line in a first period;

Applying a second precharge voltage to the second bit line to precharge the second bit line in a first period; and

In a second time period after the first time period, the voltage applied to the first bit line is reduced and the second bit line is placed in a floating state.

Technical Field

the inventive concepts herein relate to semiconductor memory devices, and more particularly, to three-dimensional memory devices configured to perform erase operations.

Background

Semiconductor memories may be classified into volatile memory devices in which stored data is lost when power is interrupted, and non-volatile memory devices; in the nonvolatile memory device, stored data is retained even when power is interrupted.

Flash memory, which is an example of a nonvolatile memory, is widely used as a mass storage medium. In view of the increasing demand for highly integrated flash memories, three-dimensional flash memories are being developed.

The integration density of the three-dimensional flash memory can be increased by increasing the number of stacked word lines in the three-dimensional flash memory. However, increasing the number of stacked word lines results in an increased thickness of the flash memory chip. Due to the technical requirements of semiconductor packaging, it is not possible to increase the thickness of flash memory chips continuously. Accordingly, various process technologies are being developed to reduce the thickness of flash memory chips. However, as process technology is used to reduce the chip thickness, it becomes difficult to perform a bulk (bulk) erase operation.

Disclosure of Invention

Embodiments of the inventive concept provide a memory device performing an erase operation using a method other than a bulk erase method and a method of operating the same.

An embodiment of the inventive concept provides a memory device including: a cell array including first and second cell strings connected to first and second bit lines, respectively; and a page buffer circuit configured to: when an erase operation is performed on the memory cells of the first cell string and the second cell string, an erase voltage is applied to the first bit line and simultaneously the second bit line is placed in a floating state.

Embodiments of the inventive concept also provide a memory device, including: a cell array including first and second cell strings connected to first and second bit lines, respectively; a first page buffer configured to: applying an erase voltage to the first bit line when performing an erase operation on memory cells of the first cell string and the second cell string; and a second page buffer configured to: when an erase operation is performed, an erase voltage is prevented from being applied to the second bit line.

Embodiments of the inventive concept also provide a method of operating a memory device, wherein the memory device includes a controller providing a control signal to a page buffer circuit, and includes first and second cell strings connected to first and second bit lines, respectively. The method comprises the following steps: receiving, by a controller, an erase command for an erase operation of memory cells of a first cell string and a second cell string, and providing a control signal in response to the erase command; applying an erase voltage from the page buffer circuit to the first bit line in response to a control signal during an erase operation; and placing the second bit line in a floating state while the erase voltage is applied to the first bit line through the page buffer circuit in response to the control signal.

Drawings

Exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

Fig. 1 illustrates a block diagram of a memory device according to an embodiment of the inventive concept.

FIG. 2 illustrates a block diagram of an example of the memory device of FIG. 1.

Fig. 3 illustrates a circuit diagram of an example of a memory block of the cell array of fig. 2.

fig. 4 is a diagram illustrating an example of a connection structure between the page buffer and the cell string illustrated in fig. 2 and 3, respectively.

Fig. 5 illustrates a table showing an example of bias conditions for an erase operation according to an embodiment of the inventive concept.

Fig. 6 illustrates a circuit diagram of an example of the page buffer of fig. 4.

FIG. 7 illustrates a flow chart of an example of an erase operation of the memory device of FIG. 1.

Fig. 8 illustrates a timing diagram of an example of the erase operation of fig. 7.

Fig. 9A illustrates a top view of a connection structure between a cell string and a bit line according to an embodiment of the inventive concept.

fig. 9B illustrates a perspective view of a connection structure between the cell strings of fig. 9A and bit lines according to an embodiment of the inventive concept.

FIG. 10 illustrates a flow chart of another example of an erase operation of the memory device of FIG. 1.

Fig. 11 illustrates a timing diagram of an example of the erase operation of fig. 10.

FIG. 12 illustrates a flow chart of another example of an erase operation of the memory device of FIG. 1.

Fig. 13 illustrates a timing diagram of an example of the erase operation of fig. 12.

Fig. 14 is a diagram illustrating another example of a connection structure between a page buffer and a cell string.

Fig. 15 illustrates a block diagram of a Solid State Drive (SSD) system provided with a memory device according to an embodiment of the inventive concept.

Detailed Description

Embodiments of the inventive concept will be described more fully with reference to the accompanying drawings.

The embodiments may be described and illustrated in terms of blocks performing a described function or functions, as is conventional in the art of inventive concepts. These blocks, which may be referred to herein as cells or modules, etc., are physically implemented by analog and/or digital circuits (e.g., logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.), and may optionally be driven by firmware and/or software. For example, the circuitry may be implemented in one or more semiconductor chips, or on a substrate support (such as a printed circuit board, etc.). The circuitry making up the blocks may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some of the functions of the blocks and a processor for performing other functions of the blocks. Each block of an embodiment may be physically separated into two or more interactive and discrete blocks without departing from the scope of the inventive concept. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the inventive concept.

fig. 1 illustrates a block diagram of a memory device according to an embodiment of the inventive concept. Referring to fig. 1, a memory device 10 includes a memory device 100 and a memory controller 200. The memory device 100 may perform various operations (e.g., a program operation, a read operation, and an erase operation) based on the command CMD and the address ADDR provided from the memory controller 200.

For example, memory device 100 may comprise a flash memory device, although the inventive concepts are not limited to comprising a flash memory device. The memory device 100 may include at least one of volatile memory (e.g., static RAM, dynamic RAM, or synchronous DRAM) and non-volatile memory (e.g., Read Only Memory (ROM), programmable ROM (prom), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), phase change RAM (pram), magnetic RAM (mram), resistive RAM (rram), or ferroelectric RAM (fram)).

The memory device 100 includes a cell array 110 and peripheral circuitry 101. The cell array 110 may include a plurality of memory blocks, and each memory block may include a plurality of memory cells. Each memory cell may be used to store data.

The peripheral circuit 101 may be connected to the cell array 110 through various signal lines including bit lines BL. The peripheral circuit 101 may be configured to generate various voltages applied to the signal lines and used to control the cell array 110. The voltage supplied from the peripheral circuit 101 may be adjusted to store data into the cell array 110 or erase data stored in the cell array 110. For example, the peripheral circuit 101 may include additional circuits (e.g., a page buffer circuit (not shown) and an address decoder (not shown)) configured to perform various other functions.

The memory controller 200 may send commands CMD and addresses ADDR to the memory device 100 to control the operation of the memory device 100. In some embodiments, memory controller 200 may store data in memory device 100 or may read or erase data stored in memory device 100.

In the case where a command CMD and an address ADDR for an erase operation are sent to the memory device 100, the memory device 100 may perform the erase operation using the peripheral circuit 101. For example, in an erase operation, the memory device 100 may apply an erase voltage to the bit line BL connected to the cell array 110 through the peripheral circuit 101. The erase voltage applied to the bit line BL may be used to erase data stored in the cell array 110.

Alternatively, in the case where a command CMD and an address ADDR for an erase operation are transmitted to the memory device 100, the peripheral circuit 101 may apply an erase voltage to a substrate (not shown) of the cell array 110. The erase voltage applied to the substrate may be used to erase data stored in the cell array 110.

In other words, an erase operation of erasing data from the cell array 110 may be achieved by applying an erase voltage provided from the peripheral circuit 101 to the substrate of the cell array 110 or to the bit line BL connected to the cell array 110. An erase operation of applying an erase voltage to the bit line BL will be described in more detail with reference to the accompanying drawings.

FIG. 2 illustrates a block diagram of an example of the memory device 100 of FIG. 1. Referring to fig. 2, the memory device 100 includes a page buffer circuit 120, an address decoder 130, control logic 140 (which may be characterized as a controller), and a voltage generator 150, in addition to the cell array 110. Together, page buffer circuit 120, address decoder 130, control logic 140, and voltage generator 150 in fig. 2 may be characterized as corresponding to peripheral circuit 101 shown in fig. 1.

The cell array 110 is connected to the address decoder 130 through word lines WL or select lines SSL and GSL. The cell array 110 is connected to a page buffer circuit 120 through a bit line BL. The cell array 110 may include a plurality of cell strings. Each cell string may include a plurality of memory cells. Each or some of the plurality of memory cells may be programmed, erased or read using voltages provided through the bit lines BL or the word lines WL.

The page buffer circuit 120 may apply various voltages to the bit lines BL to perform a program operation or an erase operation on the cell array 110. Page buffer circuit 120 may receive control signals sent from control logic 140 and may operate based on the control signals. The page buffer circuit 120 may receive the first voltage V1 and the second voltage V2 from the voltage generator 150, and may apply a variety of different voltages generated using the first voltage V1 or the second voltage V2 to the bit line BL.

During a program operation, the page buffer circuit 120 may generate a program voltage corresponding to data to be programmed using the first voltage V1, and then may apply the program voltage to the bit line BL. During an erase operation, the page buffer circuit 120 may generate an erase voltage using the second voltage V2, and then may apply the erase voltage to the bit line BL. The first voltage V1 may be lower than the second voltage V2.

The page buffer circuit 120 may include a plurality of page buffers PB1, PB2, …, PBn (hereinafter, may be referred to as page buffers PB1 to PBn). Each of the page buffers PB1 through PBn may be connected to one or more bit lines BL. Each of the page buffers PB1 through PBn is operable in response to a control signal sent from the control logic 140. For example, each of the page buffers PB1 through PBn may receive the first voltage V1 from the voltage generator 150 and may generate various voltages different from the first voltage V1. Each of the page buffers PB1 through PBn may apply various voltages generated from the first voltage V1 to the bit line BL connected to each of the page buffers PB1 through PBn in response to the control signals. The voltage generated by each of the page buffers PB1 through PBn may have a magnitude substantially equal to or similar to that of the first voltage V1.

Some of the page buffers PB1 through PBn may be configured to receive only the first voltage V1, and other of the page buffers PB1 through PBn may be configured to receive both the first voltage V1 and the second voltage V2. In other words, only some of the page buffers PB1 through PBn may include a circuit that receives the second voltage V2. The page buffer configured to receive the second voltage V2 may apply the received second voltage V2 to a bit line BL connected thereto in response to a control signal transmitted from the control logic 140.

The address decoder 130 is connected to the cell array 110 through a plurality of ground selection lines GSL, a plurality of word lines WL, and a plurality of string selection lines SSL. The address decoder 130 may receive an address ADDR from the memory controller 200 and may operate under the control of the control logic 140. The address decoder 130 may decode the received address ADDR and may control the application of the voltage to the word line WL based on the decoded address. For example, during an erase operation, the address decoder 130 may apply a ground voltage to the word line WL of the selected memory block indicated by the address ADDR.

Control logic 140 may receive a command CMD from memory controller 200. The control logic 140 may decode the received command CMD and may control the overall operation of the memory device 100 based on the decoded command. For example, in the case of receiving a command CMD corresponding to an erase operation, the control logic 140 may transmit control signals to the page buffer circuit 120, the address decoder 130, and the voltage generator 150 to control the operation of each of the page buffer circuit 120, the address decoder 130, and the voltage generator 150. The address decoder 130 may apply a ground voltage to the word line WL of the selected memory block in response to the transmitted control signal. The voltage generator 150 may supply the second voltage V2 to the page buffer circuit 120 in response to the transmitted control signal. The page buffer circuit 120 may apply an erase voltage to the bit line BL in response to the transmitted control signal. The erase voltage applied to the bit line BL may be the second voltage V2 provided from the voltage generator 150.

The voltage generator 150 may generate a variety of different voltages for operating the memory device 100 and may provide the generated voltages to various circuits. For example, the voltage generator 150 may be configured to generate the first voltage V1 having a low voltage level and then supply the first voltage V1 to the page buffer circuit 120. The voltage generator 150 may also be configured to generate the second voltage V2 having a high voltage level and then supply the second voltage V2 to the page buffer circuit 120. The magnitude of each of the first voltage V1 and the second voltage V2 may be fixed or changed according to desired circumstances.

Although fig. 2 shows an example in which the voltage generator 150 is configured to supply only the voltage to the page buffer circuit 120, the inventive concept is not limited to this example. For example, the voltage generator 150 may be configured to provide voltages to various circuits, such as the address decoder 130.

Fig. 3 illustrates a circuit diagram of an example of a memory block of the cell array of fig. 2. Referring to fig. 3, the memory block BLK includes a plurality of cell strings CS11, CS12, CS21, and CS 22. The cell strings CS11, CS12, CS21, and CS22 are arranged in a row direction and a column direction to form a plurality of rows and a plurality of columns.

Each of the cell strings CS11, CS12, CS21, and CS22 may include a plurality of cell transistors. For example, each of the cell strings CS11, CS12, CS21, and CS22 may include string selection transistors SST1 and SST2, a plurality of memory cells MC1 to MC6 (i.e., MC1, MC2, MC3, MC4, MC5, and MC6), and a ground selection transistor GST. In some embodiments, each of the plurality of cell transistors included in the cell strings CS11, CS12, CS21, and CS22 may be a Charge Trap Flash (CTF) memory cell.

The memory cells MC1 through MC6 are connected in series and stacked in a height direction, which is perpendicular to a plane defined by a row direction and a column direction (i.e., a top surface of a substrate). The string selection transistors SST1 and SST2 may be connected in series and may be disposed between the memory cells MC1 through MC6 and the bit lines BL1 and BL 2. The ground selection transistor GST may be disposed between the memory cells MC1 through MC6 and the common source line CSL.

the ground selection transistors GST of the cell strings CS11, CS12, CS21, and CS22 are commonly connected to the ground selection line GSL. In some embodiments, the ground select transistors in the same row may be connected to one of a plurality of ground select lines, and the ground select transistors in different rows may be connected to different ones of the plurality of ground select lines. For example, the ground selection transistors GST of the cell strings CS11 and CS12 in the first row may be connected to a first ground selection line, and the ground selection transistors GST of the cell strings CS21 and CS22 in the second row may be connected to a second ground selection line.

In some embodiments, although not shown in the drawings, ground select transistors located at the same level (level) from a substrate (not shown) may be connected to one of a plurality of ground select lines, and ground select transistors located at different levels may be connected to different ones of the plurality of ground select lines.

The memory cells or the ground selection transistors GST located at the same level from the substrate may be commonly connected to one word line of the plurality of word lines, and the memory cells located at different levels may be connected to different word lines of the plurality of word lines. For example, a plurality of memory cells MC1 in the cell strings CS11, CS12, CS21, and CS22 may be commonly connected to the word line WL1, a plurality of memory cells MC2 in the cell strings CS11, CS12, CS21, and CS22 may be commonly connected to the word line WL2, and the remaining memory cells MC3, MC4, MC5, and MC6 may be similarly commonly connected to the word lines WL3, WL4, WL5, and WL6, respectively.

Among the plurality of first string selection transistors SST1 at the same level, a plurality of string selection transistors in the same row may be commonly connected to one of a plurality of string selection lines, and a plurality of string selection transistors in different rows may be connected to different ones of the plurality of string selection lines. For example, the first string selection transistor SST1 of the cell string CS11 and the first string selection transistor SST1 of the cell string CS12 in the first row may be commonly connected to a string selection line SSL1a, and the first string selection transistor SST1 of the cell string CS21 and the first string selection transistor SST1 of the cell string CS22 in the second row may be commonly connected to a string selection line SSL2 a.

Similarly, among the plurality of second string selection transistors SST2 at the same level, a plurality of string selection transistors in the same row may be commonly connected to one of a plurality of string selection lines, and a plurality of string selection transistors in different rows may be connected to different ones of the plurality of string selection lines. For example, the second string selection transistor SST2 of the cell string CS11 and the second string selection transistor SST2 of the cell string CS12 in the first row may be commonly connected to a second string selection line SSL1b, and the second string selection transistor SST2 of the cell string CS21 and the second string selection transistor SST2 of the cell string CS22 in the second row may be commonly connected to a second string selection line SSL2 b.

In some embodiments, to erase data stored in memory cells of the cell strings CS11, CS12, CS21, and CS22, erase voltages may be applied to the first bit line BL1 and the second bit line BL 2. The cell strings CS11, CS12, CS21, and CS22 during the erase operation will be described in more detail with reference to fig. 4 and 5.

It is to be understood that fig. 3 shows an example of the memory block BLK, the number of cell strings may be increased or decreased as necessary, and the number of rows and columns of cell strings depends on the number of cell strings. In addition, the number of the cell transistors MC and the selection transistors GST and SST stacked in the memory block BLK may also be increased or decreased, and thus the memory block BLK may have a height different from that shown in fig. 3. Similarly, the number of lines GSL, WL, and SSL stacked and connected to the cell transistor and the selection transistor may vary according to the number of stacked cell transistors and selection transistors.

Fig. 4 is a diagram illustrating an example of a connection structure between the page buffer and the cell string illustrated in fig. 2 and 3, respectively. Fig. 4 illustrates the first cell string CS11 and the second cell string CS12 of the memory block BLK of the cell array 110. The first cell string CS11 and the second cell string CS12 in this embodiment are connected to respective different bit lines. The first cell string CS11 and the second cell string CS12 may be located adjacent to each other. However, the inventive concept is not limited to that described herein, and in some embodiments, at least one other cell string may be located between the first cell string CS11 and the second cell string CS 12.

Fig. 4 illustrates the first page buffer (PB1)121 and the second page buffer (PB2)122 of the page buffer circuit 120 illustrated in fig. 2. As shown, the first cell string CS11 is connected to the first page buffer 121 through a first bit line BL1, and the second cell string CS12 is connected to the second page buffer 122 through a second bit line BL 2. The first bit line BL1 and the second bit line BL2 may be adjacent to each other. For example, as shown in fig. 3, in the case where the first bit line BL1 and the second bit line BL2 extend in the column direction, the first bit line BL1 and the second bit line BL2 may be spaced apart from each other in the row direction but adjacent to each other. However, the inventive concept is not limited to that described herein, and in some embodiments, at least one other bit line may be located between the first bit line BL1 and the second bit line BL 2.

Each of the first and second cell strings CS11 and CS12 includes a ground selection transistor GST, first through sixth memory cells MC1 through MC6, and first and second string selection transistors SST1 and SST 2. The first and second cell strings CS11 and CS12 are connected to the first and second bit lines BL1 and BL2, respectively, through the second string selection transistor SST 2. A gate electrode of the first string selection transistor SST1 is connected to a first string selection line SSL1, and a gate electrode of the second string selection transistor SST2 is connected to a second string selection line SSL 2. The second string selection line SSL2 may be the topmost one of the plurality of string selection lines.

the gate electrode of each of the first through sixth memory cells MC1 through MC6 is connected to a corresponding one of a plurality of word lines. Each of the first and second cell strings CS11 and CS12 is connected to the common source line CSL through a ground selection transistor GST. The gate electrode of the ground selection transistor GST may be connected to a ground selection line GSL.

The first page buffer 121 receives the first voltage V1 and the second voltage V2. In the first page buffer 121, the received first voltage V1 may be used to apply a low voltage to the first bit line BL 1. For example, the first page buffer 121 may be used to apply a program-inhibit voltage to the first bit line BL 1. In the first page buffer 121, the received second voltage V2 may be used to apply a high voltage to the first bit line BL 1. For example, the first page buffer 121 may be used to apply an erase voltage to the first bit line BL 1.

during a program operation, the first page buffer 121 may set (setup) or precharge the first bit line BL1 using the first voltage V1. During a program operation, the first bit line BL1 may be set to a voltage of 0V or a power supply voltage through the first page buffer 121. During the verify read operation, the first bit line BL1 may be precharged through the first page buffer 121.

During an erase operation, the first page buffer 121 may apply an erase voltage to the first bit line BL 1. For example, the erase voltage may be a high voltage of 10V or higher. In the case where the erase voltage is applied to the first bit line BL1, a gate-induced drain leakage (GIDL) phenomenon may occur in the topmost transistor (e.g., the second string selection transistor SST2) of the first cell string CS 11. As a result of the GIDL phenomenon, holes may be injected into the channel region of the first cell string CS 11. The holes may generate a reverse bias allowing electrons to be depleted from the first through sixth memory cells MC1 through MC6, and the process may be used as an erase operation for the first through sixth memory cells MC1 through MC 6.

Alternatively, in the erase operation, the first page buffer 121 may apply a GIDL voltage for causing a GIDL phenomenon to the first bit line BL1 for a given period of time. For example, the GIDL voltage may be lower than the erase voltage and may be higher than a minimum voltage capable of causing the GIDL phenomenon. In the case where the GIDL voltage is applied to the first bit line BL1, holes may be generated in the topmost transistor (e.g., the second string selection transistor SST2) of the first cell string CS11 and may be injected into the channel region of the first cell string CS 11. The GIDL voltage may be applied to the first bit line BL1 for a predetermined period of time, and then the first page buffer 121 may apply an erase voltage to the first bit line BL 1. The application of the erase voltage may maintain the injection of holes into the channel region of the first cell string CS 11. The holes may generate a reverse bias that allows electrons to be depleted from the first through sixth memory cells MC 1-MC 6, and this process may be used as an erase operation for the first through sixth memory cells MC 1-MC 6.

the second page buffer 122 receives the first voltage V1, but does not receive the second voltage V2. In the second page buffer 122, the first voltage V1 may be used to apply a low voltage to the second bit line BL 2. For example, similar to the first page buffer 121, in the second page buffer 122, the first voltage V1 may be used to apply a program-inhibit voltage to the second bit line BL 2. During a program operation, the second page buffer 122 may set or precharge the second bit line BL2 using the first voltage V1.

When an erase operation is performed on the memory cells included in the second cell string CS12, the second page buffer 122 may operate to allow the second bit line BL2 to be in a floating state. A bit line in a floating state may be understood to mean that the bit line is not electrically connected to another non-floating conductor. In other words, during the erase operation, the second page buffer 122 prevents the erase voltage (e.g., the second voltage V2) from being applied (i.e., connected) to the second bit line BL 2. During an erase operation, if an erase voltage is applied to the first bit line BL1 and the second bit line BL2 is in a floating state, the second bit line BL2 may be electrically coupled with the first bit line BL1, and as a result of the coupling, the voltage of the second bit line BL2 may be increased to the erase voltage. In the case where the voltage of the second bit line BL2 is increased to the erase voltage, a GIDL phenomenon may occur, and such a phenomenon may be used to perform an erase operation on the second cell string CS 12. In this case, electrical coupling (or, as may be used hereinafter, coupling) should be understood to mean: even if the first bit line BL1 and the second bit line BL2 are not physically connected together or are not in contact with each other, at least some of the voltage applied to the first bit line BL1 is transferred to the second bit line BL 2.

In some embodiments, the voltage of the second bit line BL2 increased by coupling may be substantially equal to the erase voltage applied to the first bit line BL 1. In the case where the voltages of the first bit line BL1 and the second bit line BL2 have the same voltage (e.g., an erase voltage), the memory cells connected to each of the plurality of bit lines may be normally erased. For example, memory cells connected to the first bit line BL1 and the second bit line BL2 may be erased to have substantially the same erase state.

In some embodiments, even when the voltage of the second bit line BL2 is increased by the aforementioned coupling, the magnitude of the voltage of the second bit line BL2 may be different from the magnitude of the desired voltage (i.e., the magnitude of the erase voltage applied to the first bit line BL 1). That is, there may be a voltage difference between the first bit line BL1 and the second bit line BL 2. To prevent such a voltage difference, the second bit line BL2 may be precharged in advance. For example, the second bit line BL2 may be precharged to a positive voltage or a negative voltage in advance. This may serve to allow the voltage of the second bit line BL2 increased by coupling to be substantially the same as the voltage of the first bit line BL 1.

As described above, during an erase operation on the cell array 110, the memory device 100 may be configured to apply an erase voltage to the bit line BL through the page buffer circuit 120 and erase data of the memory cells using the GIDL phenomenon. In more detail, the memory apparatus 100 is configured to apply the erase voltage directly to some bit lines of the plurality of bit lines BL through the page buffer circuit 120, but allow other bit lines adjacent to the some bit lines of the plurality of bit lines BL to be in a floating state. In this case, the bit line BL in a floating state may have an increased voltage (e.g., an erase voltage) as a result of coupling between the bit lines BL.

In fig. 3 and 4, each of the plurality of cell strings is illustrated as including a first string selection transistor SST1 and a second string selection transistor SST2, but the inventive concept is not limited to be described herein. For example, each of the plurality of cell strings may be configured to include one string selection transistor, or include three or more string selection transistors. In other words, each of the plurality of cell strings may be combined to one string selection line or three or more string selection lines. For convenience, the following description will refer to an example in which each of the plurality of cell strings is configured to include the first string selection transistor SST1 and the second string selection transistor SST2 as shown in fig. 3 and 4.

Fig. 5 illustrates a table showing an example of bias conditions for an erase operation according to an embodiment of the inventive concept. Referring to fig. 5, during an erase operation, an erase voltage VERS is applied to a bit line BL, and a low voltage Vlow is applied to a second string selection line SSL 2. The ground voltage Vss is applied to the word line WL. The first string selection line SSL1 and the ground selection line GSL are in a floating state.

As shown in fig. 4, the erase voltage VERS may be a voltage directly applied from the second voltage V2 through the first page buffer 121 or a voltage caused by coupling between the plurality of bit lines BL. The erase voltage VERS may be a high voltage of, for example, 10V or higher. The second string selection line SSL2 may be the topmost line of the plurality of string selection lines. That is, in the case where the cell string is configured to have one string selection line, the string selection line may be used as the second string selection line SSL 2. In contrast, in the case where the cell string is configured to have the first string selection line SSL1 and the second string selection line SSL2 as shown in fig. 4, the second string selection line SSL2 may be the topmost string selection line. The low voltage Vlow applied to the second string selection line SSL2 may be a voltage of, for example, 5V or lower.

in the case where the erase voltage VERS and the low voltage Vlow are supplied to the bit line BL and the second string selection line SSL2, respectively, a GIDL phenomenon may occur due to a voltage difference between the bit line BL and the second string selection line SSL 2. In a cell string connected to a bit line BL, the GIDL phenomenon may be used to erase data stored in a memory cell of the cell string.

Fig. 6 illustrates a circuit diagram of an example of the page buffer of fig. 4. The page buffer circuit 120 in fig. 6 includes a first page buffer 121 and a second page buffer 122 (shown in fig. 4). The first page buffer 121 is connected to a first bit line BL1, and the second page buffer 122 is connected to a second bit line BL 2.

The first page buffer 121 includes a first high voltage transistor HTR1, a second high voltage transistor HTR2, and a first low voltage transistor LTR 1. The first high-voltage transistor HTR1 includes two terminals, one of which is connected to the first bit line BL1 and the other of which is connected to a line supplied with the second voltage V2. The operation of the first high voltage transistor HTR1 may be controlled by a second voltage enable signal V2_ en applied to the gate of the first high voltage transistor HTR 1. The first high voltage transistor HTR1 may be turned on or off by the second voltage enable signal V2_ en. For example, the first high voltage transistor HTR1 may be turned on in response to the second voltage enable signal V2_ en being set to logic high, and in this case, the second voltage V2 may be applied to the first bit line BL 1. During an erase operation, the second voltage V2 applied to the first bit line BL1 through the first high-voltage transistor HTR1 may be an erase voltage. The first high voltage transistor HTR1 may be turned off in response to the second voltage enable signal V2_ en being set to logic low, and in this case, the second voltage V2 is not applied to the first bit line BL 1. Since the second voltage V2 applied to the first high voltage transistor HTR1 is a high voltage, the first high voltage transistor HTR1 may be a high voltage transistor.

The second high voltage transistor HTR2 includes two terminals, wherein one of the two terminals is connected to the first bit line BL1, and the other of the two terminals is connected to one of the two terminals of the first low voltage transistor LTR 1. The operation of the second high voltage transistor HTR2 may be controlled by a first bit line selection signal BLSLT1 applied to the gate of the second high voltage transistor HTR 2. The second high voltage transistor HTR2 may be turned on or off by the first bit line selection signal BLSLT 1. For example, the second high voltage transistor HTR2 may be turned on in response to the first bit line selection signal BLSLT1 being set to logic high, and in this case, the voltage transferred from the first low voltage transistor LTR1 may be applied to the first bit line BL 1. During a program operation, a voltage applied to the first bit line BL1 through the second high voltage transistor HTR2 may be a program-inhibited voltage or a ground voltage. The second high voltage transistor HTR2 may be turned off in response to the first bit line selection signal BLSLT1 being set to logic low, and in this case, the voltage transferred from the first low voltage transistor LTR1 is not applied to the first bit line BL 1.

the second high voltage transistor HTR2 may be a high voltage transistor configured to prevent an unexpected high voltage from the first bit line BL1 from being transferred to the first low voltage transistor LTR1, thereby preventing breakdown of the first low voltage transistor LTR 1.

The first low-voltage transistor LTR1 includes two terminals, wherein one of the two terminals is connected to the aforementioned other one of the two terminals of the second high-voltage transistor HTR2, and the other one of the two terminals is connected to a line supplied with the first voltage V1. The operation of the first low voltage transistor LTR1 may be controlled by a first control signal CTRL1 applied to the gate of the first low voltage transistor LTR 1. For example, the first low voltage transistor LTR1 may control the magnitude of the first voltage V1 transmitted to the second high voltage transistor HTR2 based on the first control signal CTRL 1.

Alternatively, the first low voltage transistor LTR1 may be turned on or off by the first control signal CTRL 1. For example, the first low voltage transistor LTR1 may be turned on in response to the first control signal CTRL1 being set to logic high, and in this case, the first low voltage transistor LTR1 may be used to transfer the first voltage V1 to the second high voltage transistor HTR 2. Since the first voltage V1 transmitted to the first low voltage transistor LTR1 is a low voltage, the first low voltage transistor LTR1 may be a low voltage transistor.

The second page buffer 122 includes a third high voltage transistor HTR3 and a second low voltage transistor LTR 2. The third high voltage transistor HTR3 includes two terminals, wherein one of the two terminals is connected to the second bit line BL2, and the other of the two terminals is connected to one of the two terminals of the second low voltage transistor LTR 2. The operation of the third high voltage transistor HTR3 may be controlled by a second bit line selection signal BLSLT2 applied to the gate of the third high voltage transistor HTR 3. For example, the third high voltage transistor HTR3 may be turned on or off by the second bit line selection signal BLSLT 2. The third high voltage transistor HTR3 may be turned on in response to the second bit line selection signal BLSLT2 being set to logic high, and in this case, the voltage transferred from the second low voltage transistor LTR2 may be applied to the second bit line BL 2. During a program operation, a voltage applied to the second bit line BL2 through the third high voltage transistor HTR3 may be a program-inhibited voltage or a ground voltage. The third high voltage transistor HTR3 may be turned off in response to the second bit line selection signal BLSLT2 being set to logic low, and in this case, the voltage transferred from the second low voltage transistor LTR2 is not applied to the second bit line BL 2. During the erase operation, the third high voltage transistor HTR3 may be turned off (turned off) to allow the second bit line BL2 to be in a floating state. In other words, the second page buffer 122 (or, in general, the page buffer circuit 120) may be characterized as being configured to put the second bit line BL2 in a floating state.

the third high voltage transistor HTR3 may be a high voltage transistor configured to prevent an unexpected high voltage from the second bit line BL2 from being transmitted to the second low voltage transistor LTR2, thereby preventing breakdown of the second low voltage transistor LTR 2.

The second low-voltage transistor LTR2 includes two terminals, wherein one of the two terminals is connected to the aforementioned other one of the two terminals of the third high-voltage transistor HTR3, and the other one of the two terminals is connected to a line supplied with the first voltage V1. The operation of the second low voltage transistor LTR2 may be controlled by a second control signal CTRL2 applied to the gate of the second low voltage transistor LTR 2. For example, the second low voltage transistor LTR2 may control the magnitude of the first voltage V1 transmitted to the third high voltage transistor HTR3 based on the second control signal CTRL 2.

In some embodiments, the magnitude of the voltage transferred from the first low voltage transistor LTR1 to the second high voltage transistor HTR2 according to the first control signal CTRL1 may be different from the magnitude of the voltage transferred from the second low voltage transistor LTR2 to the third high voltage transistor HTR3 according to the second control signal CTRL 2.

the second low voltage transistor LTR2 may be turned on or off by a second control signal CTRL 2. For example, the second low voltage transistor LTR2 may be turned on in response to the second control signal CTRL2 being set to logic high, and in this case, the second low voltage transistor LTR2 may be used to transfer the first voltage V1 to the third high voltage transistor HTR 3. Since the first voltage V1 transmitted to the second low voltage transistor LTR2 is a low voltage, the second low voltage transistor LTR2 may be a low voltage transistor.

the control signals V2_ en, BLSLT1, CTRL1, BLSLT2, and CTRL2 supplied to the first and second page buffers 121 and 122 may be transmitted from the control logic 140 of fig. 2. The control logic 140 may control the first and second page buffers 121 and 122 using the control signals V2_ en, BLSLT1, CTRL1, BLSLT2, and CTRL 2.

As shown in fig. 6, the second page buffer 122 has no transistor available for supplying the second voltage V2 to the second bit line BL 2. Therefore, if it is necessary to increase the voltage of the second bit line BL2 to the erase voltage, the voltage of the second bit line BL2 may be increased to the erase voltage using the coupling with the first bit line BL 1. In other words, according to some embodiments of the inventive concept, even when the second page buffer 122 does not include a transistor capable of applying an erase voltage to the second bit line BL2, the voltage of the second bit line BL2 may be raised to the erase voltage, and thus, an erase operation may be effectively performed on a cell string connected to the second bit line BL 2. Accordingly, the circuit area of the page buffer circuit 120 can be reduced and the erase operation can be achieved using the bit line BL.

FIG. 7 illustrates a flow chart of an example of an erase operation of the memory device of FIG. 1. Referring to fig. 7, in step S101, the memory device 100 receives an erase command CMD from the memory controller 200. In step S102, the memory device 100 applies an erase voltage to a first bit line BL1 (such as the bit line BL1 shown in fig. 4) based on the erase command CMD. With the erase voltage applied to the first bit line BL1, the memory cells of the cell string connected to the first bit line BL1 are directly erased by the erase voltage. In step S103, the second bit line BL2 (such as the bit line BL2 shown in fig. 4) is electrically floated. The first bit line BL1 and the second bit line BL2 may be adjacent to each other. In some embodiments, at least one other bit line may be located between the first bit line BL1 and the second bit line BL 2. In the case where the second bit line BL2 is in a floating state and an erase voltage is applied to the first bit line BL1 at the same time, the second bit line BL2 may be coupled with the first bit line BL1 to which the erase voltage is applied. As a result of the coupling, the voltage of the second bit line BL2 may be raised to the erase voltage. In the case where the erase voltage of the second bit line BL2 is transferred to the cell string, the memory cells of the cell string connected to the second bit line BL2 may also be effectively erased.

Fig. 8 illustrates a timing diagram of an example of the erase operation of fig. 7. The timing chart of fig. 8 is described below with reference to the page buffer circuit 120 shown in fig. 6. Referring to fig. 8, the erase operation may be divided into a first erase period tier 1 from time t1 to time t2, a second erase period tier 2 from time t2 to time t3, and a third erase period tier 3 from time t3 to time t 4.

The first erase period tier 1 as shown in fig. 8 is a period for setting the voltages of the first and second bit lines BL1 and BL2 to the erase voltage VERS. In other words, the first erase period tERS1 is a set period of time for the erase operation. In the first erase period tERS1, the second voltage V2 is changed from the start voltage Vs to the erase voltage VERS. For example, the start voltage Vs may be 0V. The second voltage enable signal V2_ en changes from logic low to logic high. Accordingly, the first high voltage transistor HTR1 of the first page buffer 121 is turned on to allow the second voltage V2 to be applied to the first bit line BL 1.

In the first erase period tERS1, the first and second bit line selection signals BLSLT1 and BLSLT2 are set to logic low. Accordingly, the second high voltage transistor HTR2 of the first page buffer 121 and the third high voltage transistor HTR3 of the second page buffer 122 are turned off to prevent the first voltage V1 from being supplied to the first bit line BL1 and the second bit line BL 2. In the first erase period tERS1, the voltage of the first bit line BL1 is changed from the start voltage Vs to the first erase voltage VERS1 according to the second voltage V2. As indicated by "Couple-up" in FIG. 8, second bit line BL2 may be coupled with first bit line BL1, where "Couple-up" indicates a rise by the coupling voltage. As a result of the coupling, the voltage of the second bit line BL2 may be changed from the start voltage Vs to the second erase voltage VERS 2.

The second erase period tier 2 is a period in which the erase operation is performed using the erase voltage VERS set during the first erase period tier 1. In other words, the second erase period tERS2 is an execution period of the erase operation. During the second erase period tier 2, the voltage levels of the second voltage V2, the control signals V2_ en, BLSLT1, BLSLT2, and the first and second bit lines BL1 and BL2 are maintained at the same respective levels as the last stage of the first erase period tier 1. In other words, during the second erase period tier 2, the second bit line BL2 is in a floating state.

The third erase period tier 3 is a period in which the bias voltage for the erase operation is reduced to the start state of the first erase period tier 1. In other words, the third erase period tERS3 is a recovery period of the erase operation. In the third erase period tERS3, the second voltage V2 decreases. As a result of the decrease of the second voltage V2 or the interruption of the supply, the first bit line BL1 may be discharged. In the case where the first bit line BL1 is discharged, the second bit line BL2 coupled thereto may be discharged. In the third erase period tERS3, the second voltage enable signal V2_ en may be set to one of a logic low and a logic high.

As shown in fig. 8, the erase operation including the first to third erase periods tier 1 to tier 3 may be performed to erase data stored in memory cells of a cell string connected to the first and second bit lines BL1 and BL 2.

Fig. 9A and 9B are diagrams illustrating a connection structure between a cell string and a bit line according to an embodiment of the inventive concept. In detail, fig. 9A is a plan view illustrating the first and second bit lines BL1 and BL2 extending in the column direction and the cell strings CS11, CS12, CS21, and CS22 disposed under the first and second bit lines BL1 and BL2, and fig. 9B is a perspective view schematically illustrating the structure of fig. 9A.

Referring to fig. 9A, the first bit line BL1 is connected to the first cell string CS11 through a connection line CL11, and is connected to the second cell string CS21 through a connection line CL 12. One end of the connection line CL11 is connected to the first node n1 of the first bit line BL1, and one end of the connection line CL12 is connected to the second node n2 of the first bit line BL 1.

the second bit line BL2 is connected to the first cell string CS12 through a connection line CL21, and is connected to the second cell string CS22 through a connection line CL 22. One end of the connection line CL21 is connected to the third node n3 of the second bit line BL2, and one end of the connection line CL22 is connected to the fourth node n4 of the second bit line BL 2.

When considered for the column direction, in order to increase the integration density of the cell array 110 or to improve the efficiency of the arrangement of the cell strings, the positions of the cell strings CS11 and CS21 connected to the first bit line BL1 are different from the positions of the cell strings CS12 and CS22 connected to the second bit line BL 2. As shown in fig. 9A, the first cell string CS11 is located at the first row (row1), and the first cell string CS12 is located at the second row (row 2). The second cell string CS21 is located in the third row (row3), and the second cell string CS22 is located in the fourth row (row 4). That is, the positions of the cell strings CS11 and CS21 connected to the first bit line BL1 are offset from the positions of the cell strings CS12 and CS22 connected to the second bit line BL2 by a length smaller than the distance between the cell string CS11 and the cell string CS21 in the column direction.

Referring to fig. 9B, the first bit line BL1 is connected to the first and second cell strings CS11 and CS21 through connection lines CL11 and CL12, respectively, and the second bit line BL2 is connected to the first and second cell strings CS12 and CS22 through connection lines CL21 and CL22, respectively. In this case, each of the cell strings CS11, CS12, CS21, and CS22 extends in the height direction.

In the case where the cell strings CS11, CS21, CS12, and CS22 are provided as shown in fig. 9A and 9B, the connection lines CL11 and CL12 are longer than the connection lines CL21 and CL 22. Since the connection lines CL11 and CL12 are longer than the connection lines CL21 and CL22, the resistances of the connection lines CL11 and CL12 may be higher than the resistances of the connection lines CL21 and CL 22. Accordingly, the magnitude of the voltage transferred to the first and second cell strings CS11 and CS21 through the first bit line BL1 may be lower than the magnitude of the voltage transferred to the first and second cell strings CS12 and CS22 through the second bit line BL 2. Accordingly, the memory cells included in the first and second cell strings CS11 and CS21 may be used as slow cells (slow cells), and the memory cells included in the first and second cell strings CS12 and CS22 may be used as fast cells (fast cells).

During an erase operation, a first page buffer 121 such as shown in fig. 6 may apply a first erase voltage VERS1 to a first bit line BL 1. Since the second bit line BL2 is electrically coupled with the first bit line BL1 applied with the first erase voltage VERS1, the voltage of the second bit line BL2 may be increased to the second erase voltage VERS 2.

In some embodiments, the second erase voltage VERS2 may be lower than the first erase voltage VERS 1. In the case where the connection lines CL11 and CL12 have lengths substantially equal to the lengths of the connection lines CL21 and CL22 and the second erase voltage VERS2 is lower than the first erase voltage VERS1, the difference between the first erase voltage VERS1 and the second erase voltage VERS2 may cause inconsistency in the electrical or data state of the erased memory cells. However, as shown in fig. 9A and 9B, in the case where the connection lines CL11 and CL12 are longer than the connection lines CL21 and CL22, even if the first erase voltage VERS1 is higher than the second erase voltage VERS2, the difference between the voltages transmitted to the cell strings CS11, CS21, CS12, and CS22 through the connection lines CL11 to CL22 may be reduced. That is, the arrangement of the cell strings CS11, CS21, CS12, and CS22 shown in fig. 9A and 9B may reduce the variation in magnitude between the erase voltages applied to the cell strings CS11, CS21, CS12, and CS 22.

The page buffer connected to the long connection lines (e.g., the connection lines CL11 and CL12 of fig. 9A and 9B) through the bit lines may include a high voltage transistor (e.g., the first high voltage transistor HTR1 of the first page buffer 121 of fig. 6) to which an erase voltage (i.e., the second voltage V2) may be applied. On the other hand, the page buffer connected to the short connection line (e.g., the connection lines CL21 and CL22 of fig. 9A and 9B) through the bit line may not include a high voltage transistor (e.g., the first high voltage transistor HTR1) to which the erase voltage (i.e., the second voltage V2) may be applied. That is, the second voltage V2 may be directly used as an erase voltage for a cell string including a memory cell serving as a slow cell, and a voltage provided by coupling between bit lines may be used as an erase voltage for another cell string including a memory cell serving as a fast cell.

FIG. 10 illustrates a flow chart of another example of an erase operation of the memory device of FIG. 1. In step S111, the memory device 100 applies a precharge voltage to the second bit line BL2 to precharge the second bit line BL 2. The precharge voltage may be a voltage generated from the first voltage V1. For example, the second page buffer 122 as shown in fig. 4 and 6 may apply a precharge voltage. In step S112, the memory device 100 applies an erase voltage to the first bit line BL 1. For example, the first page buffer 121 as shown in fig. 4 and 6 may apply an erase voltage. With the erase voltage applied to the first bit line BL1, memory cells of a cell string connected to the first bit line BL1 may be directly erased by the erase voltage applied to the first bit line BL 1. In step S113, the second bit line BL2 is electrically floated. With the second bit line BL2 in a floating state, the second bit line BL2 may be coupled with the first bit line BL1 applied with an erase voltage. As a result of the coupling, the voltage of the second bit line BL2 may be increased to the erase voltage. In the case where the erase voltage of the second bit line BL2 is transferred to the cell string, the memory cells of the cell string connected to the second bit line BL2 may also be effectively erased.

Fig. 11 illustrates a timing diagram of an example of the erase operation of fig. 10. Referring to fig. 11, the erase operation is divided into a precharge period tPC from time t1 to time t2, a first erase period tier 1 from time t2 to time t3, a second erase period tier 2 from time t3 to time t4, and a third erase period tier 3 from time t4 to time t 5.

In the case where the voltage of the second bit line BL2 is determined by being coupled with the first bit line BL1 applied with the erase voltage, there may be a difference in voltage level between the first bit line BL1 and the second bit line BL 2. For example, the erase voltage of the second bit line BL2 may be lower than the erase voltage of the first bit line BL 1. To reduce such a difference between the erase voltages, the second bit line BL2 is precharged to the precharge voltage Vpre in the precharge period tPC.

In the precharge period tPC, the first voltage V1, the second bit line selection signal BLSLT2, and the second control signal CTRL2 are supplied to the second page buffer 122 shown in fig. 6. For example, the first voltage V1 supplied to the second page buffer 122 may be the specific voltage VP, and the second bit line selection signal BLSLT2 and the second control signal CTRL2 may be set to logic high. The second page buffer 122 generates the precharge voltage Vpre from the first voltage V1 in response to the second control signal CTRL 2. The second page buffer 122 applies the precharge voltage Vpre to the second bit line BL2 in response to the second bit line selection signal BLSLT 2. Accordingly, the second bit line BL2 may be precharged to the precharge voltage Vpre. For example, the magnitude of the precharge voltage Vpre may be substantially equal to the difference between the first erase voltage VERS1 and the second erase voltage VERS2 when the second bit line BL2 is not precharged.

The operations in the first to third erase periods tier 1 to 3 may be similar to those in the first to third erase periods tier 1 to tier 3 of fig. 8, and thus, a detailed description thereof will be omitted. In the first erase period tier 1, the second voltage V2 may be set to the erase voltage VERS, and thus, the voltage of the first bit line BL1 may be set to the first erase voltage VERS 1. Due to the coupling between the first bit line BL1 and the second bit line BL2, the voltage of the second bit line BL2 in the precharge state may be set to the second erase voltage VERS 2. In this case, the first erase voltage VERS1 may be substantially equal to the second erase voltage VERS 2. Next, an erase operation is performed in the second erase period tier 2, and a bias voltage for the erase operation is reduced in the third erase period tier 3.

As shown in fig. 11, to perform an erase operation, the memory device 100 may apply the precharge voltage Vpre to the second bit line BL2 before applying the first erase voltage VERS1 to the first bit line BL 1. This may allow the erase voltages VERS1 and VERS2 applied to the first bit line BL1 and the second bit line BL2, respectively, to have substantially the same level.

Fig. 11 illustrates an example in which a precharge operation is performed to reduce a difference between the erase voltage VERS1 and the erase voltage VERS2, but the inventive concept is not limited to what is described. For example, the magnitude of the precharge voltage Vpre may be changed differently. For example, the magnitude of the precharge voltage Vpre may be greater than the difference between the first erase voltage VERS1 and the second erase voltage VERS2 when the second bit line BL2 is not precharged. In this case, the second erase voltage VERS2 generated by the coupling may be higher than the first erase voltage VERS1 of the first bit line BL 1. Further, in the case where the first voltage V1 is a negative voltage, the second bit line BL2 may be precharged to the negative voltage. That is, the precharge voltage Vpre may become a negative voltage.

FIG. 12 illustrates a flow chart of another example of an erase operation of the memory device of FIG. 1. In step S121, the memory device 100 applies a first precharge voltage to the first bit line BL1 during a first period of time to precharge the first bit line BL 1. For example, the first page buffer 121 as shown in fig. 4 and 6 may apply the first precharge voltage. In step S122, the memory device 100 applies a second precharge voltage to the second bit line BL2 during a first period of time to precharge the second bit line BL 2. For example, the second page buffer 122 as shown in fig. 4 and 6 may apply the second precharge voltage. For example, the second precharge voltage may be lower than the first precharge voltage.

In step S123, the memory device 100 reduces the magnitude of the voltage applied to the first bit line BL1 and allows the second bit line BL2 to be in a floating state during the second period. For example, the memory device 100 may decrease the magnitude of the voltage supplied to the first bit line BL1 from the first precharge voltage to the ground voltage Vss, and may stop supplying the voltage to the second bit line BL 2. In the case where the voltage of the first bit line BL1 is lowered from the first precharge voltage to the ground voltage Vss and the supply of the second precharge voltage to the second bit line BL2 is stopped, the coupling allows the second bit line BL2 to have a voltage lowered by the difference between the first precharge voltage and the ground voltage Vss. In this case, the voltage of the second bit line BL2 may decrease from the second precharge voltage to a negative voltage due to the voltage decrease caused by the coupling. In other words, due to the coupling, the second bit line BL2 may be precharged to a negative voltage.

in step S124, the memory device 100 applies an erase voltage to the first bit line BL 1. With the erase voltage applied to the first bit line BL1, memory cells of a cell string connected to the first bit line BL1 are directly erased by the erase voltage applied to the first bit line BL 1. In step S125, the second bit line BL2 is electrically floated. With the second bit line BL2 in a floating state, the second bit line BL2 may be coupled with the first bit line BL1 applied with an erase voltage. As a result of the coupling, the voltage of the second bit line BL2 may be increased to the erase voltage. In the case where the erase voltage of the second bit line BL2 is transferred to the cell string, the memory cells of the cell string connected to the second bit line BL2 may also be effectively erased.

Fig. 13 illustrates a timing diagram of an example of the erase operation of fig. 12. Referring to fig. 13, the erase operation is divided into a first period T1 from time T1 to time T2, a second period T2 from time T2 to time T3, a first erase period tier 1 from T3 to time T4, a second erase period tier 2 from time T4 to time T5, and a third erase period tier 3 from time T5 to time T6.

In the case where the voltage of the second bit line BL2 is determined by being coupled with the first bit line BL1 applied with the erase voltage, there may be a difference in voltage level between the first bit line BL1 and the second bit line BL 2. In a particular case, the erase voltage of the second bit line BL2 may be higher than the erase voltage of the first bit line BL 1. In order to reduce the difference between the erase voltages, the second bit line BL2 may be negatively precharged to the negative precharge voltage Vnpre in the first and second periods T1 and T2. In other words, the second bit line BL2 may be precharged to a voltage lower than the start voltage Vs or the ground voltage Vss.

In the first period T1, the second voltage V2 and the second voltage enable signal V2_ en are supplied to the first page buffer 121 as shown in fig. 4 and 6. For example, the second voltage V2 may be a second specific voltage VP2 lower than the erase voltage VERS, and the second voltage enable signal V2_ en may be set to logic high. The first page buffer 121 applies the first precharge voltage Vpre1 to the first bit line BL1 in response to the second voltage enable signal V2_ en. Here, the first precharge voltage Vpre1 may be substantially the same as the second specific voltage VP 2. Accordingly, the first bit line BL1 may be precharged to the first precharge voltage Vpre 1.

In the first period T1, the first voltage V1, the second bit line selection signal BLSLT2, and the second control signal CTRL2 are supplied to the second page buffer 122. For example, the first voltage V1 may be the first specific voltage VP1, and the second bit line selection signal BLSLT2 and the second control signal CTRL2 may be set to logic high. The second page buffer 122 generates the second precharge voltage Vpre2 from the first specific voltage VP1 in response to the second control signal CTRL 2. The second page buffer 122 applies the second precharge voltage Vpre2 to the second bit line BL2 in response to the second bit line selection signal BLSLT 2. Accordingly, the second bit line BL2 may be precharged to the second precharge voltage Vpre 2.

In the second period T2, the magnitude of the second voltage V2 supplied to the first page buffer 121 is reduced to the third specific voltage VP3, and the logic high state of the second voltage enable signal V2_ en is maintained. For example, the third specific voltage VP3 may be the ground voltage Vss or the start voltage Vs. Accordingly, the voltage of the first bit line BL1 is lowered from the first precharge voltage Vpre1 to the third precharge voltage Vpre 3. In this case, the third precharge voltage Vpre3 may be substantially equal to the third specific voltage VP 3. The difference in magnitude between the second specific voltage VP2 and the third specific voltage VP3 may be substantially equal to a change RA in the voltage of the second bit line BL2 (e.g., from the second precharge voltage Vpre2 to the negative precharge voltage Vnpre) caused by coupling as indicated by "Couple-down" in fig. 13, wherein "Couple-down" indicates a drop by the coupling voltage.

in the second period T2, the supply of the voltage to be supplied to the second bit line BL2 is stopped. In other words, the second bit line BL2 may be in a floating state. For example, the second bit line selection signal BLSLT2 provided to the second page buffer 122 may be set to logic low.

In the case where the voltage supplied to the first bit line BL1 is lowered from the first precharge voltage Vpre1 to the third precharge voltage Vpre3 and the supply of the second precharge voltage Vpre2 to the second bit line BL2 is stopped, the second bit line BL2 coupled to the first bit line BL1 may be precharged to a negative voltage due to a change in the voltage of the first bit line BL 1. In other words, the voltage of the second bit line BL2 may be reduced from the second precharge voltage Vpre2 to the negative precharge voltage Vnpre by the reduced magnitude RA caused by the coupling.

The operations in the first to third erase periods tier 1 to 3 may be similar to those in the first to third erase periods tier 1 to tier 3 of fig. 8, and thus, a detailed description thereof will be omitted. In the first erase period tier 1, the second voltage V2 may be set to the erase voltage VERS, and thus, the voltage of the first bit line BL1 may be set to the first erase voltage VERS 1. Due to the coupling between the first bit line BL1 and the second bit line BL2, the voltage of the second bit line BL2 precharged to a negative voltage may be set to the second erase voltage VERS 2. In this case, the first erase voltage VERS1 may be substantially equal to the second erase voltage VERS 2.

Next, an erase operation is performed in the second erase period tier 2, and a bias voltage for the erase operation is reduced in the third erase period tier 3.

As shown in fig. 13, to perform an erase operation, the memory device 100 may precharge the second bit line BL2 to a negative voltage before applying the first erase voltage VERS1 to the first bit line BL 1. This may allow the erase voltage VERS1 of the first bit line BL1 and the erase voltage VERS2 of the second bit line BL2 to have substantially the same level.

The negative precharge method is not limited to the method of fig. 13, and various methods may be used to precharge the second bit line BL2 to a negative voltage. For example, the first voltage V1 instead of the second voltage V2 may be used to lower the voltage of the first bit line BL1 to the third precharge voltage Vpre 3.

Fig. 14 is a diagram illustrating another example of a connection structure between a page buffer and a cell string. Referring to fig. 14, the page buffer circuit 120 of this embodiment includes a first page buffer (PB1)121, a second page buffer (PB2)122, and a third page buffer (PB3) 123. The first page buffer 121 is connected to the first cell string CS11 through a first bit line BL1, the second page buffer 122 is connected to the second cell string CS12 through a second bit line BL2, and the third page buffer 123 is connected to the third cell string CS13 through a third bit line BL 3.

During an erase operation, the first page buffer 121 may be configured to receive the second voltage V2 and apply an erase voltage generated using the received second voltage V2 to the first bit line BL 1. In the case where the second bit line BL2 and the third bit line BL3 are in a floating state, the voltages of the second bit line BL2 and the third bit line BL3 may increase to an erase voltage caused by coupling.

As shown in fig. 14, during an erase operation of the memory device 100, an erase voltage applied to the first bit line BL1 may be used to increase the voltages of the second BL2 and the third bit line BL3 to respective erase voltages. In other words, a single bit line to which the erase voltage is applied may be coupled with a plurality of bit lines to increase the voltage of each bit line to the erase voltage.

Fig. 15 illustrates a block diagram of a Solid State Drive (SSD) system provided with a memory device according to an embodiment of the inventive concept. Referring to fig. 15, the SSD system 1000 may include a host 1100 and an SSD 1200.

The SSD 1200 may exchange a signal SIG with the host 1100 through the signal connector 1201, and may be supplied with power PWR through the power supply connector 1202. SSD 1200 includes an SSD controller 1210, a plurality of flash memories (NVM)1221, 1222 … 122n (hereinafter, may be referred to as flash memories 1221 to 122n), an auxiliary power source 1230, and a buffer memory 1240. In some embodiments, each of the flash memories 1221 to 122n may be provided as a separate chip or a separate package.

The SSD controller 1210 may control the flash memories 1221 to 122n in response to a signal SIG received from the host 1100. The flash memories 1221 to 122n may operate under the control of the SSD controller 1210. The auxiliary power source 1230 may be connected to the host 1100 through the power connector 1202. In some embodiments, each of the flash memories 1221 to 122n may include one of the plurality of page buffers described with reference to fig. 1 to 14. The page buffer may be used to perform an erase operation on each of the flash memories 1221 to 122 n.

The auxiliary power source 1230 may be charged by power PWR from the host 1100. In the presence of difficulties associated with the supply of power PWR from host 1100, secondary power source 1230 may supply power to other components in SSD 1200.

According to some embodiments of the inventive concept, there may be provided a three-dimensional nonvolatile memory device that performs an erase operation using a method other than a bulk erase method and is configured to have a reduced chip area.

Although exemplary embodiments of the inventive concept have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.