阅读说明：本技术 非易失性存储器装置、其操作方法及包括其的存储器系统 (Nonvolatile memory device, method of operating the same, and memory system including the same ) 是由 池承九 郑容日 于 2020-09-24 设计创作，主要内容包括：本公开涉及一种非易失性存储器装置,该非易失性存储器装置包括存储器单元阵列和控制单元。存储器单元阵列包括联接到多个字线的多个存储器区域。多个存储器区域包括分别联接到上字线和下字线的第一存储器区域和第二存储器区域。在接收第一数据和第二数据之后,控制单元对第一存储器区域执行第一编程操作以存储第一数据,并且对第二存储器区域执行第二编程操作以存储第二数据。(The present disclosure relates to a nonvolatile memory device including a memory cell array and a control unit. The memory cell array includes a plurality of memory regions coupled to a plurality of word lines. The plurality of memory regions includes a first memory region and a second memory region coupled to an upper word line and a lower word line, respectively. After receiving the first data and the second data, the control unit performs a first program operation on the first memory area to store the first data and performs a second program operation on the second memory area to store the second data.)

1. A non-volatile memory device, comprising:

a memory cell array including a plurality of memory regions coupled to a plurality of word lines, the plurality of memory regions including a first memory region and a second memory region coupled to an upper word line and a lower word line, respectively; and

control logic to, after receiving first data and second data, perform a first programming operation on the first memory area to store the first data and perform a second programming operation on the second memory area to store the second data.

2. The non-volatile memory device of claim 1, wherein the control logic further performs a verify operation that identifies data that has been stored in memory cells of the second memory region coupled to the lower word line prior to performing the second programming operation.

3. The non-volatile memory device of claim 1, wherein the control logic further performs the first programming operation and the second programming operation in response to a merge program command provided with the first data and the second data.

4. The non-volatile memory device of claim 1, wherein the control logic further stores the first data as a first least significant bit into a first memory cell in the first memory region and stores the second data as a more significant bit than a second least significant bit into a second memory cell that is in the second memory region coupled to the lower word line and that already stores the second least significant bit.

5. The non-volatile memory device of claim 1, wherein the lower word line and the upper word line are adjacent to each other.

6. The non-volatile memory device of claim 1, wherein the lower word line is closer to a source line than the upper word line.

7. A memory system, comprising:

a non-volatile memory device including a plurality of memory regions coupled to a plurality of word lines, the plurality of memory regions including a first memory region and a second memory region coupled to a first word line and a second word line, respectively; and

a controller to provide first data and second data to the non-volatile memory device at a time to store the first data in the first memory area and to store the second data in the second memory area.

8. The memory system of claim 7, wherein the non-volatile memory device, after receiving the first data and the second data, performs a first programming operation that stores the first data into the first memory area and a second programming operation that stores the second data into the second memory area.

9. The memory system of claim 8, wherein the non-volatile memory device further performs a verify operation that identifies data already stored in the second memory region prior to performing the second programming operation.

10. The memory system of claim 8, wherein the controller further provides a merge program command to the non-volatile memory device with the first data and the second data, and

wherein the non-volatile memory device performs the first programming operation and the second programming operation in response to the merged program command.

11. The memory system of claim 7, wherein the first memory region includes a first memory cell storing the first data, the first data including a first least significant bit, and

wherein the second memory region includes a second memory cell storing the second data, the second data including more significant bits than a second least significant bit already stored in the second memory cell.

12. The memory system of claim 7, wherein the second word line and the first word line are adjacent to each other.

13. The memory system of claim 7, wherein the second word line is closer to a source line than the first word line.

14. The memory system of claim 7, wherein the first memory area and the second memory area are disposed in a common plane.

15. The memory system of claim 7, wherein the non-volatile memory device is a first non-volatile memory device, the memory system further comprises a second non-volatile memory device, and

wherein the controller further provides the first data and the second data to the first non-volatile memory device at a time, and then provides third data and fourth data to the second non-volatile memory device at a time, such that the first non-volatile memory device and the second non-volatile memory device operate in a parallel manner.

16. A method of operating a non-volatile memory device, the method of operation comprising:

receiving the first data and the second data at a time;

performing a first program operation on a first memory region to store the first data, the first memory region being coupled to an upper word line; and is

Performing a second programming operation on a second memory region to store the second data, the second memory region being coupled to a lower word line.

17. The method of operation of claim 16, further comprising: performing a verify operation that identifies data that has been stored in memory cells of the second memory region that are coupled to the lower word line before performing the second programming operation.

18. The method of operation of claim 16, further comprising: a consolidated program command provided with the first data and the second data is received.

19. The operating method of claim 16, wherein the first data is stored as a first least significant bit in a first memory cell of the first memory region coupled to the upper word line, and

wherein the second data is stored as a more significant bit than a second least significant bit in a second memory cell that is located in the second memory region coupled to a lower word line and that already stores the second least significant bit.

20. The operating method according to claim 16, wherein the lower word line and the upper word line are adjacent to each other.

Technical Field

Various embodiments relate to a memory system, and more particularly, to a memory system including a non-volatile memory device.

Background

The memory system may be configured to store data provided by the host device in response to a write request from the host device. Further, the memory system may be configured to provide the stored data to the host device in response to a read request from the host device. The host device is an electronic device capable of processing data, and may include a computer, a digital camera, or a mobile phone. The memory system may be installed in the host device or may be detachably coupled to the host device.

Disclosure of Invention

Embodiments of the present disclosure provide a nonvolatile memory device having improved sequential writing performance, an operating method of the nonvolatile memory device, and a memory system including the nonvolatile memory device.

In an embodiment, a non-volatile memory device may include a memory cell array and a control unit. The memory cell array may include a plurality of memory regions coupled to a plurality of word lines. The plurality of memory regions may include a first memory region and a second memory region coupled to an upper word line and a lower word line, respectively. After receiving the first data and the second data, the control unit may perform a first program operation on the first memory area to store the first data and a second program operation on the second memory area to store the second data.

In an embodiment, a memory system may include a non-volatile memory device and a controller. The non-volatile memory device may include a plurality of memory regions coupled to a plurality of word lines. The plurality of memory regions may include a first memory region and a second memory region coupled to a first word line and a second word line, respectively. The controller may provide the first data and the second data to the non-volatile memory device at a time to store the first data in the first memory region and the second data in the second memory region.

In an embodiment, a method of operating a non-volatile memory device may include: receiving the first data and the second data at a time; performing a first program operation on a first memory region to store first data, the first memory region being coupled to an upper word line; a second program operation is performed on a second memory region coupled to the lower word line to store second data.

Drawings

FIG. 1 is a block diagram illustrating a memory system according to an embodiment.

Fig. 2A and 2B are diagrams illustrating a detailed configuration of a memory block.

Fig. 3 is a diagram illustrating a programming method according to an embodiment.

Fig. 4A and 4B are tables each showing a programming order for a plurality of word lines according to an embodiment.

FIG. 5 is a timing diagram of a programming operation for a non-volatile memory device, according to an embodiment.

Fig. 6A and 6B are tables each showing a programming order for a plurality of word lines according to an embodiment.

FIG. 7 is a timing diagram of a programming operation for a non-volatile memory device, according to an embodiment.

FIG. 8 is a flow diagram illustrating a method of operation of the non-volatile memory device of FIG. 1, according to an embodiment.

Fig. 9 is a diagram illustrating a data processing system including a Solid State Drive (SSD), according to an embodiment.

FIG. 10 is a diagram illustrating a data processing system including a memory system, according to an embodiment.

FIG. 11 is a diagram illustrating a data processing system including a memory system, according to an embodiment.

Fig. 12 is a diagram illustrating a network system including a memory system according to an embodiment.

Fig. 13 is a block diagram illustrating a nonvolatile memory device included in a memory system according to an embodiment.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, embodiments of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments of the disclosure to those skilled in the art.

The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

As used herein, the term "and/or" includes at least one of the associated listed items. It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms and vice versa, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements, and do not preclude the presence or addition of one or more other elements.

Hereinafter, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a memory system 100 according to an embodiment.

The memory system 100 may be configured to store data provided by an external host device (not shown) in response to a write request from the host device. Further, the memory system 100 may be configured to provide stored data to a host device in response to a read request from the host device.

The memory system 100 may be configured as a Personal Computer Memory Card International Association (PCMCIA) card, a Compact Flash (CF) card, a smart media card, a memory stick, various multimedia cards (e.g., MMC, eMMC, RS-MMC, and micro-MMC), a Secure Digital (SD) card (e.g., SD, mini-SD, and micro-SD), a Universal Flash (UFS), or a Solid State Drive (SSD).

The memory system 100 may include a controller (e.g., a memory controller) 110 and non-volatile memory devices NVM 1-NVM 4. Memory controller 110 may be implemented as a hardware controller as well as a firmware and software controller. For example, memory controller 110 may be implemented as a controller (e.g., controller 1210 in FIG. 9) to provide an interface between memory system 100 and a host (e.g., host device 1100 in FIG. 9) through any one of the following protocols, such as: secure digital, Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (emmc), Personal Computer Memory Card International Association (PCMCIA), Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), serial SCSI (sas), Peripheral Component Interconnect (PCI), PCI express (PCI-E), and universal flash memory (UFS).

The controller 110 may control the overall operation of the memory system 100. The controller 110 may control the nonvolatile memory devices NVM 1-NVM 4 in response to instructions from a host device to perform foreground operations. The foreground operations may include the following operations: in response to instructions from the host device, i.e., write requests and read requests, data is written to the nonvolatile memory devices NVM 1-NVM 4 and read from the nonvolatile memory devices NVM 1-NVM 4.

Further, the controller 110 may control the nonvolatile memory devices NVM 1-NVM 4 to perform background operations independently of the host device. Background operations may be performed to improve the performance of the memory system 100 and extend the life of the memory system 100. The background operations may include one or more of wear leveling operations, garbage collection operations, erase operations, read reclamation operations, and refresh operations for the non-volatile memory devices NVM 1-NVM 4. Similar to foreground operations, background operations may include operations to write data into non-volatile memory devices NVM 1-NVM 4 and to read data from non-volatile memory devices NVM 1-NVM 4.

The controller 110 may control the merged programming operation of the non-volatile memory device NVM 1. As will be described later, the merged programming operation of the nonvolatile memory device NVM1 may be the following operations: the first data DT1 and the second data DT2 to be stored into the memory areas MRa and MRb, respectively, are received from the controller 110 at a time, and the first data DT1 and the second data DT2 are successively programmed into the memory areas MRa and MRb, respectively. The memory regions MRa and MRb to be subjected to the merged program operation may be coupled to adjacent word lines. The controller 110 may control the non-volatile memory devices NVM 1-NVM 4 to perform a merged programming operation in a parallel manner. Therefore, according to the embodiments, interference between the memory regions MRa and MRb may be minimized and performance of sequential writing may be improved due to the merged program operation.

For a merged program operation of the non-volatile memory device NVM1, the controller 110 may provide the first data DT1 and the second data DT2 to the non-volatile memory device NVM1 at a time. Providing the first data DT1 and the second data DT2 at a time may indicate that the first data DT1 and the second data DT2 are provided by merging program commands, instead of providing the first data DT1 and the second data DT2 by respective program commands. Providing the first data DT1 and the second data DT2 at a time may indicate: prior to programming any one of the first data DT1 and the second data DT2, the first data DT1 and the second data DT2 are provided together, instead of indicating: one of the first data DT1 and the second data DT2 is provided, and then the other of the first data DT1 and the second data DT2 is provided after the programming of the one of the first data DT1 and the second data DT2 has been completed.

The merged program command may include addresses indicating the memory regions MRa and MRb.

In an embodiment, the controller 110 may control the non-volatile memory device NVM1 through a first program command and a second program command that are separate from each other to perform a first program operation and a second program operation, respectively. The controller 110 may control the non-volatile memory device NVM1 to perform one of the first program operation and the second program operation, instead of performing both the first program operation and the second program operation, in response to the first program command or the second program command.

The memory region MRa may be coupled to a first word line (e.g., an upper word line), and the memory region MRb may be coupled to a second word line (e.g., a lower word line), where the lower word line is adjacent to the upper word line. The first data DT1 may include the least significant bit to be stored into the memory area MRa. The second data DT2 may include more significant bits than the least significant bits already stored in the memory area MRb.

The nonvolatile memory devices NVM 1-NVM 4 may store data provided from the controller 110 according to the control of the controller 110, and may read the stored data to provide the read data to the controller 110.

The nonvolatile memory devices NVM 1-NVM 4 may share input/output lines configured to receive commands and data provided from the controller 110. That is, the nonvolatile memory devices NVM 1-NVM 4 may be coupled to the same input/output lines. Thus, after completing the data transfer to any one of the non-volatile memory devices NVM 1-NVM 4, the controller 110 may begin transferring data to another one of the non-volatile memory devices NVM 1-NVM 4.

The nonvolatile memory device NVM1 may include a memory cell array MCAR and a control unit CTRL. The control unit (or control logic) CTRL may control the overall operation of the non-volatile memory device NVM 1. In an embodiment, the control logic CTRL may be implemented as control circuitry to control the operation of the non-volatile memory device NVM 1. For example, control logic CTRL may control one or more components (e.g., row decoder 320, column decoder 340, data read/write block 330, and voltage generator 350 in fig. 13) in non-volatile memory device NMV1 to perform read operations, program operations, and erase operations on selected regions in memory cell array MCAR.

The memory cell array MCAR may include memory blocks MB1 through MBk. The memory block may be a unit in which the nonvolatile memory device NVM1 performs an erase operation, but embodiments of the present disclosure are not limited thereto. For example, the memory block may be a unit of memory different from a unit in which the erase operation is performed.

Memory block MB1 may include memory regions MRa and MRb. As described above, the memory regions MRa and MRb may be coupled to adjacent upper and lower word lines, respectively. Of any two word lines coupled to memory block MB1, one word line closer to the source line may be referred to as a lower word line, and the other word line may be referred to as an upper word line.

The memory region MRa may be configured by a plurality of memory cells coupled to the upper word line, and the memory region MRb may be configured by a plurality of memory cells coupled to the lower word line.

The control unit CTRL may receive the first data DT1 and the second data DT2 at a time from the controller 110, and may perform a merged programming operation on the memory regions MRa and MRb. The merged program operation may include a first program operation on the first data DT1 and a second program operation on the second data DT 2.

After having finished receiving all the first data DT1 and the second data DT2, the control unit CTRL may perform a first program operation of storing the first data DT1 as a least significant bit into the memory region MRa. The control unit CTRL may perform a second programming operation that stores the second data DT2 as a more significant bit than the least significant bit, which has been stored in the memory area MRb, into the memory area MRb.

Before performing the second programming operation, the control unit CTRL may further perform a verification operation that identifies data that has been stored in the memory area MRb.

Each of the nonvolatile memory devices NVM 2-NVM 4 may be configured and operate in substantially the same manner as the nonvolatile memory device NVM 1.

Each of the non-volatile memory devices NVM 1-NVM 4 may include a flash memory device such as NAND flash or NOR flash, ferroelectric random access memory (FeRAM), Phase Change Random Access Memory (PCRAM), Magnetic Random Access Memory (MRAM), or resistive random access memory (ReRAM).

Each of the non-volatile memory devices NVM 1-NVM 4 may include one or more planes, one or more memory chips, one or more memory dies, or one or more memory packages.

Although fig. 1 shows that the memory system 100 includes four nonvolatile memory devices NVM 1-NVM 4, the number of nonvolatile memory devices included in the memory system 100 is not limited thereto.

Similar to the set of non-volatile memory devices NVM 1-NVM 4, the memory system 100 may also further include another set of non-volatile memory devices sharing input/output lines. Similar to the way the set of non-volatile memory devices NVM 1-NVM 4 are controlled, the controller 110 may also control such another set of non-volatile memory devices to perform a merged programming operation in a parallel manner.

Fig. 2A and 2B are diagrams illustrating a detailed configuration of the storage block MB 1. Each of the memory blocks MB1 through MBk shown in fig. 1 may be configured in substantially the same manner as the configuration shown in fig. 2A and 2B.

Referring to fig. 2A, the memory block MB1 may be coupled to a plurality of word lines WL1 to WLn arranged in parallel between a source select line SSL and a drain select line DSL. The memory block MB1 may include a plurality of strings ST1 through STm. Bit lines BL 1-BLm may be coupled to strings ST 1-STm, respectively. The source lines SL may be commonly coupled to the strings ST1 to STm. The strings ST1 to STm may be configured in substantially the same manner as each other, and thus the string ST1 coupled to the bit line BL1 will be exemplarily described.

The string ST1 may include a source select transistor SST1, a plurality of memory cells MC11 through MCn1, and a drain select transistor DST1 coupled in series with one another between a source line SL and a bit line BL 1.

The source select transistor SST1 may be coupled at its source to a source line SL. The drain select transistor DST1 may be coupled at its drain to a bit line BL 1. The memory cells MC11 through MCn1 may be coupled in series with each other between the source select transistor SST1 and the drain select transistor DST 1. The source selection transistors SST to SSTm respectively included in the strings ST1 to STm may be coupled to a source selection line SSL at their gates. The drain select transistors DST1 to DSTm may be coupled to the drain select line DSL at their gates. The memory cells MC 11-MC 1m and MCn 1-MCnm may be coupled at their gates to word lines WL 1-WLn, respectively. Memory cells coupled to the same word line among the memory cells MC11 through MC1m and MCn1 through MCnm may be programmed at the same time during a program operation. Memory cells coupled to the same word line may be included in the same memory region. Word lines WL1 to WLn may correspond to different memory regions, respectively.

One or more bits may be stored in each of the memory cells MC11 through MC1m and MCn1 through MCnm.

Between any two adjacent word lines (e.g., word lines WL1 and WL2) among the word lines WL1 to WLn, the lower word line may be the word line WL1 closer to the source line SL, and the upper word line may be the word line WL2 farther from the source line SL.

Referring to fig. 2B, the memory block MB1 may include strings ST11 to ST1m and ST21 to ST2 m. Each of the strings ST11 to ST1m and strings ST21 to ST2m may extend in the vertical direction (i.e., in the Z direction). In the memory block MB1, "m" strings may be arranged in the row direction (i.e., the X direction). Although fig. 2B shows that two strings are arranged in the column direction (i.e., Y direction), three or more strings may be arranged in the column direction (Y direction).

The strings ST11 to ST1m and ST21 to ST2m may be configured identically to each other. For example, the string ST11 may include a source select transistor SST, memory cells MC1 through MCn, and a drain select transistor DST coupled in series to each other between a source line SL and a bit line BL 1. The source select transistor SST may be coupled to a source line SL at a source thereof. The drain select transistor DST may be coupled at its drain to a bit line BL 1. The memory cells MC11 through MCn1 may be coupled in series with each other between the source selection transistor SST and the drain selection transistor DST.

The source selection transistors respectively included in the strings arranged in the same row (i.e., the strings arranged in the X direction) may be coupled to the same source selection line at their gates. For example, the source select transistors of strings ST 11-ST 1m arranged in the first row may be coupled at their gates to a first source select line SSL 1. The source select transistors of strings ST 21-ST 2m arranged in the second row may be coupled at their gates to a second source select line SSL 2. In an embodiment, the source select transistors in strings ST 11-ST 1m and strings ST 21-ST 2m may be commonly coupled to a single source select line.

Drain select transistors respectively included in strings arranged in the same row may be coupled to the same drain select line at their gates. For example, the drain select transistors of the strings ST11 to ST1m arranged in the first row may be coupled at their gates to a first drain select line DSL 1. The drain select transistors of the strings ST21 to ST2m arranged in the second row may be coupled at their gates to a second drain select line DSL 2.

Strings arranged in the same column (i.e., strings arranged in the Y direction) may be coupled to the same bit line. For example, the strings ST11 and ST21 arranged in the first column may be coupled to the bit line BL 1. The strings ST1m and ST2m arranged in the mth column may be coupled to the bit line BLm.

Memory cells arranged at the same level in the vertical direction (i.e., in the same XY plane) may be coupled to the same word line at their gates. For example, memory cells arranged in the same position in the vertical direction as the memory cell MC1 in the strings ST11 to ST1m and strings ST21 to ST2m may be coupled to the word line WL 1. Memory cells arranged in the same position in the vertical direction as the memory cell MC2 in the strings ST11 to ST1m and strings ST21 to ST2m may be coupled to the word line WL 2.

Memory cells arranged in the same row and coupled to the same word line may configure a single memory region to be simultaneously programmed during a programming operation. For example, memory cells arranged in a first row and coupled to word line WL1 may configure memory region MR 11. Memory cells arranged in a second row and coupled to word line WL1 may configure memory region MR 12.

Although memory regions MR11 and MR12 are shown in fig. 2B to lie in the same XY plane, memory regions MR11 and MR12 may be respectively arranged in different XZ planes. That is, each word line may be coupled to multiple memory regions arranged in different XZ planes, where the number of XZ planes is the number of rows.

Among any two adjacent word lines (e.g., the word lines WL1 and WL2) among the word lines WL1 to WLn, a word line (e.g., the word line WL1) closer to the source line SL than another word line (e.g., the word line WL2) may be referred to as a lower word line, and the another word line may be referred to as an upper word line.

Fig. 3 is a diagram illustrating a programming method according to an embodiment. FIG. 3 shows threshold voltage distributions of memory cells belonging to states S1-S3, respectively. The horizontal axis "VTH" may represent the threshold voltage of the memory cell. The vertical axis "#" may represent the number of memory cells for a threshold voltage.

Referring to FIG. 3, in the initial erased state S1, the memory cells may belong to threshold voltage distribution D1. The memory cells belonging to threshold voltage distribution D1 may be memory cells to be programmed simultaneously. The memory cells belonging to threshold voltage distribution D1 may be memory cells coupled to a common word line. The memory cells belonging to threshold voltage distribution D1 may configure the memory region.

When the first program operation PR1 is performed on the memory cells in the memory region, the state may be changed from the erased state S1 to the state S2. The first program operation PR1 may be an operation of programming Least Significant Bit (LSB) data into a memory cell. The first program operation PR1 may be performed by a combined program command or by a separate first program command.

In state S2, the memory cells may belong to threshold voltage distributions D11 and D12. The memory cells belonging to the threshold voltage distribution D11 may store LSB data "1". The memory cells belonging to the threshold voltage distribution D12 may store LSB data "0". For example, the threshold voltage of the memory cell MC32 may rise such that the memory cell MC32 belongs to the threshold voltage distribution D12, and thus it may be determined that the memory cell MC32 stores LSB data "0". The threshold voltage of the memory cell MC31 may be maintained such that the memory cell MC31 belongs to the threshold voltage distribution D11, and thus it may be determined that the memory cell MC31 stores LSB data "1".

When the second program operation PR2 is performed on the memory cell, the state may be changed from the state S2 to the state S3. The second program operation PR2 may be an operation of programming a Central Significant Bit (CSB) data and a Most Significant Bit (MSB) data into memory cells. The second program operation PR2 may be performed by a combined program command or by a separate second program command.

In state S3, the memory cells may belong to threshold voltage distributions D21-D28. The memory cells belonging to the threshold voltage distributions D21 to D28 may store "111", "101", "001", "011", "010", "110", "100", and "000" as MSB, CSB, and LSB data, respectively. The threshold voltage distributions D21-D24 may be subdivided from the threshold voltage distribution D11. The threshold voltage distributions D25-D28 may be subdivided from the threshold voltage distribution D12. For example, the threshold voltage of the memory cell MC34 may rise such that the memory cell MC34 belongs to the threshold voltage distribution D28, and thus it may be determined that the memory cell MC34 stores data "000". For example, the threshold voltage of memory cell MC33 may rise such that memory cell MC33 belongs to threshold voltage distribution D23, and thus it may be determined that memory cell MC33 stores data "001".

Both memory cell MC33 and memory cell MC34 may store data "00" as MSB data and CSB data, and may belong to different threshold voltage distributions D23 and D28 according to whether memory cell MC33 and memory cell MC34 store data "1" or data "0" as LSB data. Therefore, before the MSB data and the CSB data are programmed into the memory cell (i.e., before the second program operation PR2 is performed on the memory cell), a verification operation may be performed that checks whether data "1" or data "0" is stored in the memory cell as LSB data.

As shown in FIG. 3, a first program operation PR1 and a second program operation PR2 may be performed to store 3 bits of data into each memory cell. In an embodiment, in order to finally store k bits of data into each memory cell, the first program operation PR1 may be performed as described above to store Least Significant Bit (LSB) data into each memory cell, and the second program operation PR2 may be performed to store remaining more significant bit (i.e., more significant bit than LSB) data into each memory cell. The second program operation PR2 may be performed to divide the two threshold voltage distributions D11 and D12 into "2" in total^{^}k "threshold voltage distributions.

Fig. 4A and 4B are tables each showing a programming order for a plurality of word lines according to an embodiment.

Referring to fig. 4A, the first and second program operations PR1 and PR2 may be performed according to a predetermined program sequence in consideration of interference effects that may occur between adjacent word lines while data is being programmed. The numbers shown in the table of fig. 4A may represent a programming sequence.

For example, first, a first programming operation PR1 may be performed on one or more memory cells coupled to word line WL 1. Second, a first programming operation PR1 may be performed on one or more memory cells coupled to word line WL 2. Third, a second programming operation PR2 may be performed on one or more memory cells coupled to word line WL 1. Fourth, the first programming operation PR1 may be performed on one or more memory cells coupled to word line WL 3. Fifth, a second programming operation PR2 may be performed on one or more memory cells coupled to the word line WL 2. As such, the first program operation PR1 may be applied to the upper word line (e.g., the (i +1) th word line) before the second program operation PR2 is applied to the lower word line (e.g., the ith word line).

Referring to fig. 4B, when 8 memory regions MR1 through MR8 are coupled to each word line, the first and second program operations PR1 and PR2 may be performed according to a predetermined program sequence to minimize a disturb effect. The first memory regions MR1 respectively coupled to the word lines may be memory regions arranged in the same plane (e.g., the first common XZ plane of fig. 2B). Likewise, the second memory regions MR2 respectively coupled to the word lines may be memory regions arranged in a second common XZ plane. The first common XZ plane and the second common XZ plane may be arranged in the Y direction of fig. 2B and disposed adjacent to each other. The same is true of the third through eighth memory regions MR3 through MR 8.

Although eight memory regions MR 1-MR 8 are coupled to each word line in the embodiment shown in fig. 4B, a program operation may be performed on a different number of memory regions in a similar manner according to an embodiment.

From the first to eighth, the first program operation PR1 may be sequentially performed on the first to eighth memory regions MR1 to MR8 corresponding to the word line WL 1. For example, the first program operation PR1 may be sequentially performed on the first through eighth memory regions MR1 through MR8 coupled to the word line WL 1.

Ninth, the first program operation PR1 may be performed on the first memory region MR1 corresponding to the word line WL 2. Tenth, the second program operation PR2 may be performed on the first memory region MR1 corresponding to the word line WL 1. Such operations for the word line WL2 and the word line WL1 may be repeated in the same manner for the second memory region MR2 through the eighth memory region MR 8.

Twenty-fifth, the first program operation PR1 may be performed on the first memory region MR1 corresponding to the word line WL 3. Twenty-sixth, the second program operation PR2 may be performed on the first memory region MR1 corresponding to the word line WL 2. Such operations for the word line WL3 and the word line WL2 may be repeated in the same manner for the second memory region MR2 through the eighth memory region MR 8.

When memory regions MR 1-MR 8 in different planes are coupled to each word line, in each plane, a first program operation PR1 may be performed on the upper word line first, before performing a second program operation PR2 on the lower word line. For example, a first one of the first memory regions MR1, MR1, may be coupled to a word line WL1, and a second one of the first memory regions MR1, MR1, may be coupled to a word line WL2, the word line WL1 being closer to the source line than the word line WL 2. In this case, the first program operation PR1 may be performed on memory cells in a second one of the first memory regions MR1 that is coupled to the word line WL2, MR1, before the second program operation PR2 is performed on memory cells in a first one of the first memory regions MR1 that is coupled to the word line WL1, MR 1.

Fig. 5 is a timing diagram of performing a first program operation PR1 and a second program operation PR2 on the non-volatile memory devices NVM 1-NVM 4 according to an embodiment.

Referring to fig. 5, the controller 110 may control the nonvolatile memory devices NVM1 through NVM4 in a parallel manner to perform a first program operation PR1 and a second program operation PR2 for storing sequential data. The controller 110 may apply the programming sequence described with reference to fig. 4A or 4B to each of the non-volatile memory devices NVM 1-NVM 4. However, the controller 110 may control each of the first and second program operations PR1 and PR2 through a separate first program command C1 and a separate second program command C2. In other words, the controller 110 may control the first and second program operations PR1 and PR2 using the first and second program commands C1 and C2, respectively, which are two different program commands.

The controller 110 may sequentially provide the first program command C1 and the first data DT1 to the nonvolatile memory devices NVM1 to NVM 4. The first data DT1 may be LSB data to be stored in a memory region coupled to the upper word line (WLi + 1). In response to the first program command C1, each of the non-volatile memory devices NVM 1-NVM 4 may perform a first program operation PR1 for the upper word line (WLi +1) to store first data DT 1.

After the first data DT1 is completely provided to the non-volatile memory devices NVM 1-NVM 4, the controller 110 may sequentially provide the second program command C2 and the second data DT2 to the non-volatile memory devices NVM 1-NVM 4. The second data DT2 may be remaining data (e.g., CSB data and MSB data) to be stored in a memory region coupled to the lower word line WLi. In response to the second program command C2, each of the non-volatile memory devices NVM 1-NVM 4 may perform a verify operation VRF, where the verify operation VRF identifies first data (e.g., LSB data) that has been stored in the memory region coupled to the lower word line WLi. Then, each of the non-volatile memory devices NVM 1-NVM 4 may perform a second program operation PR2 for the lower word line WLi to store second data DT 2.

Through such a programming scheme, the controller 110 can quickly store sequential data while minimizing interference effects. However, because each of the non-volatile memory devices NVM 1-NVM 4 individually performs the first program operation PR1 and the second program operation PR2, each of the non-volatile memory devices NVM 1-NVM 4 may wait for an amount of latency WTIME between ending the first operation PR1 and beginning to receive the second program command C2.

Fig. 6A and 6B are tables each showing a programming order for a plurality of word lines according to an embodiment.

Referring to fig. 6A, nonvolatile memory devices NVM 1-NVM 4 may perform a merged programming operation to further improve the performance of sequential writes. For example, first, a first program operation PR1 may be performed on the word line WL 1. Then, a first merged programming operation may be performed, which includes a first programming operation PR1 to the word line WL2 and a second programming operation PR2 to the word line WL 1. Then, a second merged programming operation may be performed, which includes a first programming operation PR1 to the word line WL3 and a second programming operation PR2 to the word line WL 2. Here, the programming sequence described with reference to FIG. 4A may be maintained in view of disturb effects.

For example, the merged program operation CPR on word line WL2 and word line WL1 will be described in more detail. The controller 110 may provide the merged program command C3 to the non-volatile memory device together with the first data DT1 and the second data DT2 at a time. The first data DT1 may be LSB data to be stored in a memory region coupled to the word line WL 2. The second data DT2 may be remaining data (e.g., CSB data and MSB data) to be stored in a memory region coupled to the word line WL 1.

The control unit CTRL of the non-volatile memory device may perform a merged program operation CPR in response to the merged program command C3. The control unit CTRL may perform a first program operation PR1 on the word line WL2 in order to store the first data DT1, a verify operation VRF on the word line WL1, and a second program operation PR2 on the word line WL1 in order to store the second data DT 2.

Referring to FIG. 6B, each word line may be coupled to eight memory regions MR 1-MR 8. In the embodiment shown in FIG. 6B, multiple merged programming operations may be performed according to the programming sequence described with reference to FIG. 4B. For example, the first merged program operation may be performed by performing a first program operation PR1 on a second one of the first memory regions MR1 coupled to the word line WL2 among the first memory regions MR1, performing a verify operation VRF on a first one of the first memory regions MR1 coupled to the word line WL1 among the first memory regions MR1, and performing a second program operation PR2 on a first one of the first memory regions MR1 of the first memory region MR 1. The second merge programming operation may be performed by performing a first program operation PR1 (or a third program operation to store the first data DT1) on a second one of the second memory regions MR2 coupled to the word line WL2 in the second memory region MR2, performing a verify operation VRF (or a second verify operation) on a first one of the second memory regions MR2 coupled to the word line WL1 in the second memory region MR2, and performing a second program operation PR2 (or a fourth program operation to store the second data DT2) on a first one of the second memory regions MR2 in the second memory region MR 2.

Fig. 7 is a timing diagram of a merged program operation CPR of non-volatile memory devices NVM 1-NVM 4, according to an embodiment.

Referring to fig. 7, to store sequential data, the controller 110 may control the non-volatile memory devices NVM 1-NVM 4 to perform a merge programming operation CPR in a parallel manner. Each of the nonvolatile memory devices NVM 1-NVM 4 may perform the first program operation PR1 and the second program operation PR2 according to the program sequence described with reference to fig. 6A or 6B.

The controller 110 may sequentially provide the merged program command C3, the first data DT1, and the second data DT2 to the nonvolatile memory devices NVM 1-NVM 4. The first data DT1 may be LSB data to be stored in a memory region coupled to the upper word line (WLi + 1). The second data DT2 may be remaining data (e.g., CSB data and MSB data) to be stored in a memory region coupled to the lower word line WLi.

In response to the merged program command C3, each of the non-volatile memory devices NVM 1-NVM 4 may sequentially perform a first program operation PR1 for the upper word line (WLi +1), a verify operation VRF for the lower word line WLi, and a second program operation PR2 for the lower word line WLi.

Accordingly, as shown in fig. 7, the latency WTIME (refer to fig. 5) may be removed, and thus the performance of sequential writing may be further improved while minimizing interference between memory regions. For example, the memory system according to the embodiment shown in fig. 7 performs the first program operation PR1 for the first word line, the verify operation VRF for the second word line closer to the source line than the first word line, and the second program operation PR2 for the second word line using a single merged program command C3, instead of performing the first program operation PR1 and the verify operation VRF/second program operation PR2 using two separate commands C1 and C2, respectively. When the memory system according to the embodiment of fig. 7 performs the sequential write operation on the nonvolatile memory devices NMV1 through NMV4, a given time interval (e.g., the wait time WTIME in fig. 5) between the end of performing the first program operation PR1 and the start of performing the verify operation VRF/the second program operation PR2 may be removed for each of the nonvolatile memory devices NVM1 through NVM 4. Thus, the duration of the total time interval for performing sequential write operations to the non-volatile memory devices NVM 1-NVM 4 may be reduced compared to the memory system according to the embodiment of fig. 5. In addition, as the number of non-volatile memory devices increases, the efficiency of performing sequential write operations to a plurality of non-volatile memory devices by the memory system according to the embodiment of fig. 7 may not be significantly reduced as compared to the memory system according to the embodiment of fig. 5.

Fig. 8 is a flow chart illustrating a method of operation of a non-volatile memory device (e.g., non-volatile memory device NVM1 in fig. 1) according to an embodiment.

Referring to fig. 8, in step S110, the nonvolatile memory device NVM1 may receive the first data DT1 and the second data DT2 at a time from the controller 110.

In step S120, after receiving the first data DT1 and the second data DT2, the control unit CTRL may perform a first program operation on the memory region MRa coupled to the upper word line to store the first data DT 1.

In step S130, the control unit CTRL may perform a verify operation on the memory region MRb coupled to the lower word line. The control unit CTRL may identify the data that has been stored in the memory area MRb by means of a verification operation.

In step S140, the control unit CTRL may perform a second program operation on the memory region MRb coupled to the lower word line to store the second data DT 2. The control unit CTRL may perform a second program operation, which subdivides the threshold voltage distribution of the memory cells coupled to the lower word line, by referring to data identified through the verify operation. In an embodiment, in response to a single consolidated program command instead of two or more separate commands, the control unit CTRK may perform a first program operation on the memory region MRa, a verify operation on the memory region MRb, and a second program operation on the memory region MRb.

Fig. 9 is a diagram illustrating a data processing system 1000 including a Solid State Drive (SSD)1200 according to an embodiment. Referring to fig. 9, the data processing system 1000 may include a host device 1100 and an SSD 1200.

SSD1200 may include a controller 1210, a buffer memory device 1220, a plurality of non-volatile memory devices 1231-123 n, a power source 1240, a signal connector 1250, and a power connector 1260.

Controller 1210 may control the general operation of SSD 1200. The controller 1210 may be configured in the same manner as the controller 110 shown in fig. 1.

The controller 1210 may include a host interface unit 1211, a control unit 1212, a random access memory 1213, an Error Correction Code (ECC) unit 1214, and a memory interface unit 1215.

The host interface unit 1211 may exchange a signal SGL with the host device 1100 through the signal connector 1250. The signal SGL may include commands, addresses, data, and the like. The host interface unit 1211 may interface the host device 1100 and the SSD1200 according to a protocol of the host device 1100. For example, the host interface unit 1211 may communicate with the host device 1100 through any one of standard interface protocols such as: secure digital, Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (emmc), Personal Computer Memory Card International Association (PCMCIA), Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), serial SCSI (sas), Peripheral Component Interconnect (PCI), PCI express (PCI-E), and universal flash memory (UFS).

The control unit 1212 may analyze and process a signal SGL received from the host device 1100. The control unit 1212 may control the operation of the internal functional blocks according to firmware or software for driving the SSD 1200. The random access memory 1213 may be used as a working memory for driving such firmware or software.

ECC unit 1214 may generate parity data for data to be transmitted to at least one of non-volatile memory devices 1231-123 n. The generated parity data may be stored in the nonvolatile memory devices 1231 to 123n together with the data. The ECC unit 1214 may detect an error of data read from at least one of the nonvolatile memory devices 1231 through 123n based on the parity data. If the detected error is within a correctable range, ECC unit 1214 may correct the detected error.

The memory interface unit 1215 may provide control signals such as commands and addresses to at least one of the nonvolatile memory devices 1231 to 123n according to the control of the control unit 1212. Further, the memory interface unit 1215 may exchange data with at least one of the nonvolatile memory devices 1231 to 123n according to the control of the control unit 1212. For example, the memory interface unit 1215 may provide data stored in the buffer memory device 1220 to at least one of the non-volatile memory devices 1231 through 123n, or provide data read from at least one of the non-volatile memory devices 1231 through 123n to the buffer memory device 1220.

The buffer memory device 1220 may temporarily store data to be stored in at least one of the non-volatile memory devices 1231 through 123 n. Further, the buffer memory device 1220 may temporarily store data read from at least one of the non-volatile memory devices 1231 through 123 n. The data temporarily stored in the buffer memory device 1220 may be transferred to the host device 1100 or at least one of the nonvolatile memory devices 1231 through 123n according to the control of the controller 1210.

The nonvolatile memory devices 1231 to 123n may be used as storage media of the SSD 1200. Non-volatile memory devices 1231 through 123n may be coupled to controller 1210 through a plurality of channels CH1 through CHn, respectively. One or more non-volatile memory devices may be coupled to one channel. The non-volatile memory devices coupled to each channel may be coupled to the same signal bus and data bus. Each of the nonvolatile memory devices 1231 to 123n can be configured in the same manner as the nonvolatile memory device NVM1 shown in fig. 1.

The power supply 1240 may provide power PWR input through the power connector 1260 to the inside of the SSD 1200. The power supply 1240 may include an auxiliary power supply 1241. When a sudden power down occurs, auxiliary power supply 1241 may provide power to allow SSD1200 to terminate normally. The auxiliary power supply 1241 may include a large-capacity capacitor.

The signal connector 1250 may be configured by various types of connectors according to an interface scheme between the host device 1100 and the SSD 1200.

The power connector 1260 may be configured by various types of connectors according to a power supply scheme of the host device 1100.

Fig. 10 is a diagram illustrating a data processing system 2000 including a memory system 2200 according to an embodiment. Referring to fig. 10, the data processing system 2000 may include a host device 2100 and a memory system 2200.

The host device 2100 may be configured in a board form such as a printed circuit board. Although not shown, the host device 2100 may include internal functional blocks for performing functions of the host device.

The host device 2100 may include a connection terminal 2110 such as a socket, slot, or connector. The memory system 2200 may be mounted to the connection terminal 2110.

The memory system 2200 may be configured in a board form such as a printed circuit board. The memory system 2200 may be referred to as a memory module or a memory card. The memory system 2200 may include a controller 2210, a buffer memory device 2220, nonvolatile memory devices 2231 and 2232, a Power Management Integrated Circuit (PMIC)2240, and a connection terminal 2250.

The controller 2210 may control the general operation of the memory system 2200. The controller 2210 may be configured in the same manner as the controller 1210 shown in fig. 9.

The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memory devices 2231 and 2232. Further, the buffer memory device 2220 may temporarily store data read from the nonvolatile memory devices 2231 and 2232. Data temporarily stored in the buffer memory device 2220 may be transferred to the host device 2100 or the nonvolatile memory devices 2231 and 2232 according to the control of the controller 2210.

The nonvolatile memory devices 2231 and 2232 may be used as storage media of the memory system 2200.

The PMIC 2240 may supply power input through the connection terminal 2250 to the inside of the memory system 2200. The PMIC 2240 may manage power of the memory system 2200 according to control of the controller 2210.

The connection terminal 2250 may be coupled to the connection terminal 2110 of the host device 2100. Signals such as commands, addresses, data, and the like, and power can be transmitted between the host device 2100 and the memory system 2200 through the connection terminal 2250. The connection terminal 2250 may be configured in various types according to an interface scheme between the host device 2100 and the memory system 2200. The connection terminal 2250 may be provided on either side of the memory system 2200.

Fig. 11 is a diagram illustrating a data processing system 3000 including a memory system 3200 according to an embodiment. Referring to fig. 11, a data processing system 3000 may include a host device 3100 and a memory system 3200.

The host device 3100 may be configured in a board form such as a printed circuit board. Although not shown, the host device 3100 may include internal functional blocks for performing functions of the host device.

The memory system 3200 may be configured in the form of a surface mount package. Memory system 3200 can be mounted to host device 3100 via solder balls 3250. Memory system 3200 can include a controller 3210, a cache device 3220, and a non-volatile memory device 3230.

The controller 3210 may control the general operation of the memory system 3200. The controller 3210 may be configured in the same manner as the controller 1210 shown in fig. 9.

The buffer memory device 3220 may temporarily store data to be stored in the non-volatile memory device 3230. Further, the buffer memory device 3220 may temporarily store data read from the non-volatile memory device 3230. The data temporarily stored in the buffer memory device 3220 may be transmitted to the host device 3100 or the nonvolatile memory device 3230 according to control of the controller 3210.

Nonvolatile memory device 3230 can be used as a storage medium for memory system 3200.

Fig. 12 is a diagram illustrating a network system 4000 including a memory system 4200 according to an embodiment. Referring to fig. 12, a network system 4000 may include a server system 4300 and a plurality of client systems 4410-4430 coupled by a network 4500.

The server system 4300 may service data in response to requests from a plurality of client systems 4410-4430. For example, server system 4300 may store data provided from multiple client systems 4410-4430. As another example, the server system 4300 may provide data to a plurality of client systems 4410-4430.

Server system 4300 may include host device 4100 and memory system 4200. The memory system 4200 may be configured by the memory system 100 shown in fig. 1, the SSD1200 shown in fig. 9, the memory system 2200 shown in fig. 10, or the memory system 3200 shown in fig. 11.

Fig. 13 is a block diagram illustrating a nonvolatile memory device 300 included in a memory system according to an embodiment. Referring to fig. 13, the nonvolatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read/write block 330, a column decoder 340, a voltage generator 350, and control logic 360.

The memory cell array 310 may include memory cells MC arranged at regions where word lines WL1 to WLm and bit lines BL1 to BLn intersect each other. The memory cell array 310 may be configured in the same manner as the memory cell array MCAR shown in fig. 1.

Row decoder 320 may be coupled with memory cell array 310 by word lines WL1 through WLm. The row decoder 320 may operate according to the control of the control logic 360. The row decoder 320 may decode an address provided from an external device (not shown). The row decoder 320 may select and drive word lines WL1 to WLm based on the decoding result. For example, the row decoder 320 may provide the word line voltage provided from the voltage generator 350 to the word lines WL1 to WLm.

The data read/write block 330 may be coupled with the memory cell array 310 through bit lines BL1 through BLn. The data read/write block 330 may include read/write circuits RW1 to RWn corresponding to the bit lines BL1 to BLn, respectively. The data read/write block 330 may operate according to the control of the control logic 360. The data read/write block 330 may operate as a write driver or a sense amplifier depending on the mode of operation. For example, in a write operation, the data read/write block 330 may operate as a write driver that stores data supplied from an external device in the memory cell array 310. For another example, in a read operation, the data read/write block 330 may operate as a sense amplifier that reads out data from the memory cell array 310.

Column decoder 340 may operate according to control of control logic 360. The column decoder 340 may decode an address provided from an external device. The column decoder 340 may couple the read/write circuits RW1 to RWn in the data read/write block 330 corresponding to the bit lines BL1 to BLn, respectively, with data input/output lines or data input/output buffers based on the decoding result.

The voltage generator 350 may generate a voltage to be used in an internal operation of the nonvolatile memory device 300. The voltage generated by the voltage generator 350 may be applied to the memory cells of the memory cell array 310. For example, a program voltage generated in a program operation may be applied to a word line of a memory cell on which the program operation is to be performed. For another example, an erase voltage generated in an erase operation may be applied to a well region of a memory cell on which the erase operation is to be performed. For another example, a read voltage generated in a read operation may be applied to a word line of a memory cell on which the read operation is to be performed.

The control logic 360 may control the general operation of the non-volatile memory device 300 based on control signals provided from an external device. For example, the control logic 360 may control operations of the non-volatile memory device 300, such as read operations, write operations, and erase operations of the non-volatile memory device 300. The control logic 360 may be configured in the same way as the control unit CTRL shown in fig. 1.

While certain embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples. Accordingly, the nonvolatile memory device, the operating method of the nonvolatile memory device, and the memory system including the nonvolatile memory device should not be limited based on the described embodiments. Rather, the non-volatile memory devices, methods of operating non-volatile memory devices, and memory systems including the same described herein should be limited only by the claims as understood when taken in conjunction with the above description and accompanying drawings.