阅读说明：本技术 制造铁电随机存取存储器的方法 (Method for manufacturing ferroelectric random access memory ) 是由 孙山 于 2016-07-18 设计创作，主要内容包括：涉及制造铁电随机存取存储器的方法。描述了F-RAM单元的结构和制造方法。F-RAM单元包括形成在预先图案化的阻挡结构之上和形成有预先图案化的阻挡结构的铁电电容器,预先图案化的阻挡结构具有平坦化/化学和/或机械抛光的顶表面。预先图案化的阻挡结构包括具有在阻氧层上的底部电极层的结构的多个阻氧层。底部电极层形成在其上形成的铁电电容器的底部电极的至少一部分。(To a method of fabricating a ferroelectric random access memory. Structures and fabrication methods of F-RAM cells are described. The F-RAM cell includes a ferroelectric capacitor formed over and with a pre-patterned barrier structure having a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes a plurality of oxygen barrier layers having a structure of a bottom electrode layer on the oxygen barrier layers. The bottom electrode layer forms at least a portion of a bottom electrode of a ferroelectric capacitor formed thereon.)

1. A memory device, comprising:

a barrier layer comprising a patterned barrier structure, wherein the patterned barrier structure comprises a barrier layer disposed at a barrier to oxygen (O)₂) A first electrode layer over the layer; and

A patterned ferroelectric stack disposed at least partially over the patterned barrier structure, wherein the patterned ferroelectric stack comprises a second electrode layer disposed over a ferroelectric layer,

Wherein the first electrode layer of the patterned barrier structure, the ferroelectric layer of the patterned ferroelectric stack, and the second electrode layer form a ferroelectric capacitor.

2. The memory device of claim 1, wherein the barrier layer is disposed over the first contact and the first dielectric layer.

3. The memory device of claim 1, wherein the patterned ferroelectric stack further comprises a transition layer comprising at least one of iridium and iridium oxide disposed below the ferroelectric layer, wherein the transition layer comprises a thickness in a range of approximately 5nm to 30nm, and wherein a ratio of the thickness of the transition layer to the thickness of the first electrode layer is 1: 12.

4. The memory device of claim 1, wherein the barrier layer further comprises at least one first hydrogen-blocking structure comprising a silicon nitride layer, the at least one first hydrogen-blocking structure being arranged in contact with at least one sidewall of the patterned barrier structure.

5. The memory device of claim 4, wherein the barrier layer comprises a planarized top surface exposing a top surface of the patterned barrier structure and the at least one first hydrogen-blocking structure.

6. the memory device of claim 1, wherein the first electrode layer comprises at least one of iridium (Ir) and platinum (Pt).

7. the memory device of claim 1, wherein the oxygen barrier layer comprises a plurality of layers, and wherein the plurality of layers comprises a first oxygen barrier layer comprising titanium nitride (TiN) and a second oxygen barrier layer comprising titanium aluminum nitride (TiAlN) disposed over the first oxygen barrier layer.

8. The memory device of claim 1, wherein the oxygen barrier layer comprises titanium aluminum oxynitride (TiAlO)_xN_y) Layer of, wherein the TiAlO_xN_yThe layer is oxygen rich near a top surface of the oxygen barrier layer and nitrogen rich near a bottom surface of the oxygen barrier layer.

9. The memory device of claim 4, wherein the at least one first hydrogen-blocking layer comprises a plurality of layers, wherein the plurality of layers comprises at least a silicon nitride layer disposed over an aluminum oxide layer.

10. The memory device of claim 4, further comprising:

A second hydrogen-blocking layer comprising at least one of TiN and TiAlN disposed over the ferroelectric capacitor;

A second dielectric layer disposed over the second hydrogen-blocking layer; and

a second contact extending from a planarized top surface of the second dielectric layer to the second electrode layer of the ferroelectric capacitor.

11. The memory device of claim 3, wherein the first electrode layer of the patterned barrier structure has a first length (L1) and the transition layer of the patterned ferroelectric stack has a second length (L2), and wherein L2 is greater than L1.

12. The memory device of claim 3, wherein the first electrode layer of the patterned barrier structure has a first length (L1) and the transition layer of the patterned ferroelectric stack has a second length (L2), wherein L2 is approximately equal to L1.

13. A device, comprising:

A first dielectric layer disposed over a substrate to encapsulate at least a portion of a complementary metal-oxide-semiconductor (CMOS) circuit formed on the substrate;

A pre-patterned barrier structure disposed over the first dielectric layer, wherein the pre-patterned barrier structure comprises a plurality of Bottom Electrodes (BEs)/oxygen barriers (Os)₂) Structure and multiple hydrogen (H) barriers₂) Structures, wherein each BE/oxygen barrier structure comprises a Bottom Electrode (BE) layer formed over an oxygen barrier layer, and wherein each BE/oxygen barrier structure is formed between two adjacent hydrogen barrier structures, and wherein the pre-patterned barrier structures comprise a planarized common surface that exposes top surfaces of the plurality of BE/oxygen barrier structures; and

A patterned ferroelectric stack disposed over a corresponding BE/oxygen blocking structure to form a ferroelectric capacitor.

14. the device of claim 13, wherein the patterned ferroelectric stack comprises a Top Electrode (TE) layer over a ferroelectric layer and a Bottom Electrode (BE) transition layer, and wherein the patterned BE transition layer and the BE layer thereunder form a bottom electrode of the ferroelectric capacitor.

15. The device of claim 13, wherein each of the plurality of hydrogen-blocking structures is in communication with the plurality of BE/os₂At least one sidewall of one of the structures is in contact.

16. The device of claim 14, wherein each of the patterned BE transition layers has a second length (L2) and the BE layers below the patterned BE transition layers have a first length (L1), and wherein L2 is greater than L1.

17. The device of claim 14, wherein each of the patterned BE transition layers has a second length (L2) and the BE layers below the patterned BE transition layers have a first length (L1), and wherein L2 is approximately the same as L1.

18. A device, comprising:

a first dielectric layer disposed over a substrate to encapsulate at least a portion of a complementary metal-oxide-semiconductor (CMOS) circuit formed on the substrate;

A barrier layer comprising a patterned barrier structure, a Local Interconnect (LI), and a landing pad, wherein the patterned barrier structure, the LI, and the landing pad each comprise a material disposed at a barrier oxygen (O)₂) A first electrode layer over the layer; and

a patterned ferroelectric stack disposed at least partially over the patterned barrier structure, wherein the patterned ferroelectric stack comprises a second electrode layer disposed over a ferroelectric layer, and wherein the first electrode layer of the patterned barrier structure, the ferroelectric layer of the patterned ferroelectric stack, and the second electrode layer form a ferroelectric capacitor.

19. The device of claim 18, further comprising:

A second dielectric layer disposed over the barrier layer to encapsulate the ferroelectric capacitor, the LI, and the landing pad;

A plurality of first contacts disposed at least partially within the first dielectric layer connecting one of the patterned blocking structure and the landing pad to the CMOS circuitry; and

A plurality of second contacts disposed at least partially within the second dielectric layer connecting one of the ferroelectric capacitor, the LI, and the landing pad to a metallization layer.

20. The device of claim 18, wherein the patterned ferroelectric stack further comprises a transition layer comprising at least one of iridium and iridium oxide disposed below the ferroelectric layer, wherein the transition layer comprises a thickness in a range of approximately 5nm to 30nm, and wherein a ratio of the thickness of the transition layer to the thickness of the first electrode layer of the patterned barrier structure is 1: 12.

Technical Field

The present disclosure relates generally to semiconductor devices, and more particularly to ferroelectric random access memory (F-RAM) devices including embedded or integrally formed ferroelectric capacitors and complementary metal-oxide-semiconductor (CMOS) transistors and methods for fabricating the same.

background

Ferroelectric random access memory (F-RAM) is considered to be non-volatile (NV) memory and may include a grid or array of storage elements or cells, each storage element or cell including an NV element, such as at least one ferroelectric capacitor. The F-RAM circuit may also include one or more associated transistors that select cells and control reading or writing to NV elements.

When an external electric field is applied across the ferroelectric material of the ferroelectric capacitor in the cell, the dipoles in the material align with the electric field direction. After the electric field is removed, the dipoles maintain their polarization state. Data is stored in each data storage cell as one of two possible electrical polarization states in the cell. For example, in a one transistor-one capacitor (1T1C) cell, a "1" may be encoded using negative remanent polarization and a "0" encoded using positive remanent polarization, or vice versa.

SUMMARY

a non-volatile memory cell including a complementary metal-oxide-semiconductor (CMOS) transistor and an embedded ferroelectric capacitor formed according to the method of the present disclosure minimizes changes to the CMOS process flow, reduces the cost of manufacturing a ferroelectric random access memory (F-RAM), reduces defect density, and enables tighter design rules.

in one embodiment, the method includes forming a contact extending through a first dielectric layer on a surface of a substrate. A blocking structure is formed on the contact. In general, forming the barrier structure includes: (i) depositing a bottom electrode layer over the oxygen barrier layer and over the first dielectric layer and the top surface of the contact; (ii) patterning both the bottom electrode and the oxygen barrier layer to form a barrier structure over the contact; (iii) (iii) depositing a second dielectric layer over the patterned barrier layer and the first dielectric layer, and (iv) planarizing the second dielectric layer to expose a top surface of the barrier structure. A ferroelectric stack (ferroelectric stack) is deposited on the barrier structure. The ferroelectric stack includes a bottom electrode transition layer deposited over the barrier structure, a ferroelectric layer on the bottom electrode layer, and a top electrode on the ferroelectric layer. Finally, the ferroelectric stack is patterned to form a ferroelectric capacitor having a bottom electrode layer with a barrier structure, wherein the barrier layer is conductive and the bottom electrode of the ferroelectric capacitor is electrically coupled to the contact through the barrier layer.

in another embodiment, forming the barrier structure further comprises using hydrogen (H) barrier prior to depositing the second dielectric layer₂) A layer encapsulates the patterned bottom electrode and barrier layer, and planarizing the second dielectric layer includes removing the hydrogen-blocking layer on the top surface of the barrier structure to expose the patterned barrier layer.

Optionally, patterning the bottom electrode and the barrier layer may include patterning the bottom electrode and the barrier layer to simultaneously form a Local Interconnect (LI) and a landing pad (landing pad).

The present disclosure also includes the following:

1) A method, comprising:

Forming a pre-patterned barrier structure over a first dielectric layer, comprising:

Disposing oxygen (O) barrier over the first dielectric layer₂) A layer;

Disposing a Bottom Electrode (BE) layer over the oxygen barrier layer;

Patterning the BE layer and the oxygen barrier layer to form at least one BE/oxygen barrier structure;

A first hydrogen (H) barrier disposed over the at least one BE/oxygen barrier structure₂) A layer; and

Planarizing the first hydrogen-blocking layer to form a planarized top surface of the pre-patterned barrier structure, wherein a top surface of the at least one BE/oxygen-blocking structure is exposed;

Forming a ferroelectric stack (ferroelectric stack) over the pre-patterned barrier structure; and

Patterning the ferroelectric stack to form a ferroelectric capacitor having each of the at least one BE/oxygen blocking structure.

2) The method of 1), wherein forming the ferroelectric stack over the pre-patterned barrier structure comprises:

A Bottom Electrode (BE) transition layer is disposed over a planarized top surface of the pre-patterned barrier structure, a ferroelectric layer is disposed over the BE transition layer, and a top electrode layer is disposed over the ferroelectric layer.

3) The method of 1), wherein disposing the oxygen barrier layer comprises:

Disposing a first oxygen barrier layer comprising titanium nitride (TiN); and

A second oxygen barrier layer comprising titanium aluminum nitride (TiAlN) is disposed over the first oxygen barrier layer.

4) The method of 1), wherein the oxygen barrier layer comprises titanium aluminum oxynitride (TiAlO)_xN_y) Layer of, wherein the TiAlO_xN_yThe layer is oxygen rich near a top surface of the oxygen barrier layer and nitrogen rich near a bottom surface of the oxygen barrier layer.

5) The method of 1), wherein the BE layer comprises at least one of iridium (Ir) or platinum (Pt).

6) The method of 1), wherein the first hydrogen barrier layer comprises a plurality of layers, the disposing the first hydrogen barrier layer comprising:

Disposing alumina (Al) over the at least one BE/oxygen barrier structure₂O₃) A layer; and

in the Al₂O₃A silicon nitride layer is disposed over the layer.

7) The method of 1), wherein forming the pre-patterned barrier structure further comprises:

Disposing a second dielectric layer over the first hydrogen-blocking layer; and

removing a portion of the second dielectric layer while planarizing the first hydrogen-blocking layer, wherein the portion of the second dielectric layer and a portion of the first hydrogen-blocking layer disposed over a top surface of the at least one BE/oxygen-blocking structure are removed.

8) the method of 1), wherein the BE transition layer comprises a thickness in a range of approximately 5nm to 30nm, the BE transition layer further comprises at least one of iridium or iridium oxide, and wherein a ratio of the thickness of the BE transition layer to the thickness of the BE layer is 1: 12.

9) The method of 1), wherein patterning the ferroelectric stack to form the ferroelectric capacitor with each of the at least one BE/oxygen barrier structures further comprises:

Aligning a patterned BE transition layer of the ferroelectric stack with a pre-patterned BE layer of the at least one BE/oxygen blocking structure such that the patterned BE transition layer is in direct contact with the pre-patterned BE layer, collectively forming a Bottom Electrode (BE) of the ferroelectric capacitor.

10) The method of claim 9), wherein the at least one pre-patterned BE layer of the BE/oxygen barrier structure comprises a first length (L1) and the patterned BE transition layer of the ferroelectric stack comprises a second length (L2), wherein L2 is greater than L1.

11) The method of 9), wherein the pre-patterned BE layer of the at least one BE/oxygen-blocking structure comprises a first length (L1) and the patterned BE transition layer of the ferroelectric stack comprises a second length (L2), wherein L2 is approximately equal to L1.

12) The method of 1), further comprising:

Forming a plurality of first contacts extending through the first dielectric layer to a surface of a substrate, wherein the pre-patterned blocking structure is disposed over the plurality of first contacts and a top surface of the first dielectric layer.

13) The method of 12), wherein forming the pre-patterned barrier structure further comprises:

Forming a Local Interconnect (LI) and a landing pad over the plurality of first contacts and a top surface of the first dielectric layer, wherein the LI and the landing pad comprise a structure similar to the at least one BE/oxygen blocking structure that includes the BE layer over the oxygen blocking layer, and wherein the landing pad and the at least one BE/oxygen blocking structure are electrically coupled with each of their respective contacts.

14) The method of 13), further comprising:

Disposing a second hydrogen-blocking layer comprising at least one of TiN or TiAlN to encapsulate the LI, the landing pad, and the at least one ferroelectric capacitor;

disposing a third dielectric layer over the second hydrogen-blocking layer; and

Forming a plurality of second contacts extending from a planarized top surface of the third dielectric layer to at least one of the LI, the landing pads, or the top electrode layer of the at least one ferroelectric capacitor.

15) A method, comprising:

Disposing a first dielectric layer over a substrate to encapsulate at least a portion of a complementary metal-oxide-semiconductor (CMOS) circuit formed on the substrate;

Forming a pre-patterned barrier structure over the first dielectric layer, wherein the pre-patterned barrier structure comprises a plurality of Bottom Electrodes (BEs)/oxygen barriers (Os)₂) Structure and multiple hydrogen (H) barriers₂) Structures, wherein each BE/oxygen barrier structure comprises a Bottom Electrode (BE) layer deposited over an oxygen barrier layer, and wherein each BE/oxygen barrier structure is formed between two adjacent hydrogen barrier structures; and

Depositing and patterning a ferroelectric stack over the pre-patterned barrier structure to form a ferroelectric capacitor having each of the plurality of BE/oxygen barrier structures.

16) The method of 15), wherein depositing and patterning the ferroelectric stack comprises:

Depositing a Top Electrode (TE) layer over the ferroelectric layer and the Bottom Electrode (BE) transition layer; and

patterning the TE layer, the ferroelectric layer, and the BE transition layer such that each patterned BE transition layer is aligned with the BE layer of one of the plurality of BE/oxygen blocking structures,

wherein each of the patterned BE transition layers and the BE layer thereunder form a bottom electrode of the ferroelectric capacitor.

17) The method of 16), wherein each of the patterned BE transition layers comprises a second length (L2), the BE layer thereunder comprises a first length (L1), and wherein L2 is greater than L1.

18) the method of 16), wherein each of the patterned BE transition layers comprises a second length (L2), the BE layer thereunder comprises a first length (L1), and wherein L2 is substantially the same as L1.

19) A method, comprising:

Forming a contact extending through a first dielectric layer on a surface of a substrate to a diffusion region of a metal-oxide-semiconductor (MOS) transistor formed in the surface of the substrate;

Depositing oxygen (O) barrier over the first dielectric layer and the top surface of the contact₂) A layer;

depositing a bottom electrode layer over the oxygen barrier layer;

patterning the oxygen barrier layer and bottom electrode layer to form an oxygen barrier structure over the contact;

Using hydrogen (H)₂) Layer packaging the oxygen barrier structure;

Depositing a second dielectric layer over the hydrogen-blocking layer;

planarizing the second dielectric layer and the hydrogen-blocking layer to expose a top surface of the oxygen-blocking structure;

depositing a ferroelectric stack over the oxygen-barrier structure, the ferroelectric stack comprising a bottom electrode transition layer deposited on a pre-patterned bottom electrode layer of the oxygen-barrier structure, a ferroelectric layer on the bottom electrode transition layer, and a top electrode on the ferroelectric layer; and

patterning the ferroelectric stack to form a ferroelectric capacitor having the oxygen-blocking structure, wherein the patterned bottom electrode transition layer and the pre-patterned bottom electrode layer form a bottom electrode of the ferroelectric capacitor, wherein the bottom electrode is electrically coupled to the contact through the pre-patterned oxygen-blocking layer.

20) The method of 19), wherein patterning the oxygen barrier layer comprises patterning the oxygen barrier layer to simultaneously form a Local Interconnect (LI) and a landing pad, and wherein packaging the oxygen barrier structure comprises packaging the LI and the landing pad using the hydrogen barrier layer.