阅读说明：本技术 一种用于sram的读写优化电路 (A kind of read-write optimization circuit for SRAM ) 是由 陈依雅 张捷 刘雯 于 2019-08-19 设计创作，主要内容包括：本发明提供一种用于SRAM的读写优化电路,选择模块、读操作控制模块、写操作控制模块以及SRAM存储单元；其中选择模块包含由栅极和漏极交叉互联的两个PMOS管组成的若干钳位电路；选择模块的一端与写操作控制模块连接,另一端与读操作控制模块连接；每一个钳位电路连接一个SRAM存储单元。本发明在选择模块中加入一个由两个栅极与漏极交叉互联的PMOS管组成的钳位电路；可以有效防止SRAM存储单在读取过程中内部节点数据翻转,有效提升SRAM的良率,同时可以提高写入读出速度。(The present invention provides a kind of read-write optimization circuit for SRAM, selecting module, read operation control module, write operation control module and SRAM memory cell；Wherein selecting module includes several clamp circuits being made of grid and the two cross interconnected PMOS tube that drain；One end of selecting module is connect with write operation control module, and the other end is connect with read operation control module；Each clamp circuit connects a SRAM memory cell.The clamp circuit being made of two grids and the cross interconnected PMOS tube that drains is added in the present invention in selecting module；The SRAM storage singly internal node Data flipping in reading process can be effectively prevented, effectively promote the yield of SRAM, while write-in reading speed can be improved.)

1. a kind of read-write for SRAM optimizes circuit, which is characterized in that include at least:

Selecting module, read operation control module, write operation control module and SRAM memory cell；

Wherein the selecting module includes several clamp circuits being made of grid and the two cross interconnected PMOS tube that drain；Institute The one end for stating selecting module is connect with the write operation control module, and the other end is connect with the read operation control module；It is described Each clamp circuit connects a SRAM memory cell.

2. the read-write according to claim 1 for SRAM optimizes circuit, it is characterised in that: in each clamp circuit The source electrodes of described two PMOS tube be all connected with supply voltage, and the drain electrode of two PMOS tube is separately connected bit line BP and position Line BN.

3. the read-write according to claim 2 for SRAM optimizes circuit, it is characterised in that: each clamp circuit connects A global pre-charge circuit is connect, which is formed by first to third PMOS tube, and described first to third The grid of PMOS tube connects global precharge control logic signal jointly；Wherein, first PMOS tube and the second PMOS tube Source electrode connects power vd D, and drain electrode is separately connected the source electrode and drain electrode of third PMOS tube；The source of the third PMOS tube, drain electrode It is connect respectively with bit line BP, bit line BN.

4. the read-write according to claim 3 for SRAM optimizes circuit, it is characterised in that: each clamp circuit Bit line BP and bit line BN is separately connected a transfer tube circuit.

5. the read-write according to claim 4 for SRAM optimizes circuit, it is characterised in that: one transfer tube circuit Including a NMOS tube interconnected and a PMOS tube, the bit line BP and bit line BN are connect respectively in the NMOS tube and PMOS At the connecting pin of pipe.

6. optimizing circuit for the read-write of SRAM according to claim 1 or 5, it is characterised in that: the read operation control Module includes the control signal generating circuit of sensitive amplifier circuit and sensitive amplifier circuit.

7. the read-write according to claim 6 for SRAM optimizes circuit, it is characterised in that: the sensitive amplifier circuit packet Include analog computing amplifier；The control signal generating circuit of the sensitive amplifier circuit by several metal-oxide-semiconductors, combinational logic gate, post Storage and latch composition.

8. the read-write according to claim 1 for SRAM optimizes circuit, it is characterised in that: the write operation control module It is made of several logic circuits, is sent to bit line BP and bit line BN for converting input data into two opposite signals.

9. the read-write according to claim 1 for SRAM optimizes circuit, it is characterised in that: in each clamp circuit The PMOS tube it is suitable with the size of described first in global precharge module to third PMOS tube, order-of-magnitude agreement.

10. the read-write according to claim 1 for SRAM optimizes circuit, it is characterised in that: the SRAM memory cell It is made of the four, the 5th PMOS tube and first to fourth NMOS tube.

11. the read-write according to claim 10 for SRAM optimizes circuit, it is characterised in that: the SRAM memory cell In the source electrode of the four, the 5th PMOS tube connect supply voltage jointly, the grid of the 4th PMOS tube, the first NMOS tube Grid, the drain electrode of the 5th PMOS tube, the drain electrode of the second NMOS tube and the drain electrode of the 4th NMOS tube are connected with each other；Described 4th The drain electrode of PMOS tube, the drain electrode of the first NMOS tube, the drain electrode of third NMOS tube, the grid of the 5th PMOS tube and the second NMOS tube Grid be connected with each other；The source electrode of the third NMOS tube connects bit line BN；The source electrode of 4th NMOS tube connects bit line BP； The grid of 4th NMOS tube connect wordline with the grid of the third NMOS tube jointly.

Technical field

The present invention relates to chip design fields, optimize circuit more particularly to a kind of read-write for SRAM.

Background technique

Summary of the invention

In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of read-write optimizations for SRAM Circuit, for solving the problems, such as that the storage information of the corresponding bit cell of prior art neutrality line is easy to happen overturning.

In order to achieve the above objects and other related objects, the present invention provides a kind of read-write optimization circuit for SRAM, until It less include: selecting module, read operation control module, write operation control module and SRAM memory cell；The wherein selection mould Block includes several clamp circuits being made of grid and the two cross interconnected PMOS tube that drain；One end of the selecting module with The write operation control module connection, the other end are connect with the read operation control module；Each clamp circuit connection One SRAM memory cell.

Preferably, the source electrode of described two PMOS tube in each clamp circuit is all connected with supply voltage, and should The drain electrode of two PMOS tube is separately connected bit line BP and bit line BN.

Preferably, each clamp circuit connects a global pre-charge circuit, and the overall situation and charging circuit are by first It is formed to third PMOS tube, described first to third PMOS tube grid connects the global precharge control logic letter of precharge jointly Number；Wherein, first PMOS tube connects power vd D with the source electrode of the second PMOS tube, and drain electrode is separately connected third PMOS tube Source electrode and drain electrode；The source of the third PMOS tube, drain electrode are connect with bit line BP, bit line BN respectively.

Preferably, the bit line BP and bit line BN of each clamp circuit are separately connected a transfer tube circuit.

Preferably, one transfer tube circuit includes a NMOS tube and a PMOS tube interconnected, institute's rheme Line BP and bit line BN is connect respectively at the connecting pin of the NMOS tube and PMOS tube.

Preferably, the read operation control module includes the control signal production of sensitive amplifier circuit and sensitive amplifier circuit Raw circuit.

Preferably, the sensitive amplifier circuit includes analog computing amplifier；The control signal of the sensitive amplifier circuit Generation circuit is made of several metal-oxide-semiconductors, combinational logic gate, register and latch.

Preferably, the write operation control module is made of several logic circuits, for converting input data into two Opposite signal is sent to bit line BP and bit line BN.

Preferably, described first in the PMOS tube in each clamp circuit and global precharge module is to the The size of three PMOS tube is suitable, order-of-magnitude agreement.

Preferably, the SRAM memory cell is made of the four, the 5th PMOS tube and first to fourth NMOS tube.

Preferably, the source electrode of the four, the 5th PMOS tube in the SRAM memory cell connects supply voltage jointly, institute State the grid, the grid of the first NMOS tube, the drain electrode of the 5th PMOS tube, the drain electrode and the 4th of the second NMOS tube of the 4th PMOS tube The drain electrode of NMOS tube is connected with each other；The drain electrode of 4th PMOS tube, the drain electrode of the first NMOS tube, the drain electrode of third NMOS tube, The grid of 5th PMOS tube and the grid of the second NMOS tube are connected with each other；The source electrode of the third NMOS tube connects bit line BN； The source electrode of 4th NMOS tube connects bit line BP；The grid of 4th NMOS tube and the grid of the third NMOS tube are common Connect wordline.

As described above, the read-write for SRAM of the invention optimizes circuit, have the advantages that the present invention is selecting The clamp circuit being made of two grids and the cross interconnected PMOS tube that drains is added in module；SRAM can be effectively prevented The singly internal node Data flipping in reading process is stored, the yield of SRAM is effectively promoted, while it is fast that write-in reading can be improved Degree.

Detailed description of the invention

The six transistor memory unit circuits and global pre-charge circuit that Fig. 1 is shown as in the SRAM module for reading and writing of the prior art show It is intended to；

Fig. 2 is first shown as the frame construction drawing of the read-write optimization circuit for SRAM of the invention；

Fig. 3 is shown as selecting module internal circuit schematic diagram of the present invention；

Fig. 4 is shown as the circuit diagram that clamp circuit of the invention is connect with SRAM memory cell；

Fig. 5 is shown with the read-write for SRAM of the invention and optimizes circuit and using the emulation of read-write optimization circuit Comparative result.

Specific embodiment

Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from Various modifications or alterations are carried out under spirit of the invention.

Fig. 2 is please referred to Fig. 5.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its Assembly layout kenel may also be increasingly complex.

As shown in Fig. 2, the frame construction drawing present invention that Fig. 2 is shown as the read-write optimization circuit for SRAM of the invention mentions Optimize circuit for a kind of read-write for SRAM, the circuit includes: selecting module (MUX), read operation control in the present embodiment Module (RDBLK), write operation control module (WTBLK) and SRAM memory cell；Wherein the selecting module (MUX) include by Several clamp circuits of grid and two PMOS tube for draining cross interconnected composition；One end of the selecting module (MUX) and institute Write operation control module (WTBLK) connection is stated, the other end is connect with the read operation control module (WTBLK)；It is described each Clamp circuit connects a SRAM memory cell.That is, in Fig. 2, comprising several in each described selecting module A clamp circuit, wherein each clamp circuit includes two PMOS tube, as shown in figure 3, Fig. 3 is shown as in selecting module of the present invention Portion's circuit diagram, the grid of two PMOS tube (C1, C2) in each clamp circuit and cross interconnected, the Yi Jisuo that drains The grid for stating PMOS tube C1 connects the drain electrode of the PMOS tube C2, and the drain electrode pole of the PMOS tube C1 connects the PMOS tube C2's Grid.As shown in Fig. 2, each described clamp circuit connects a SRAM memory cell.

As shown in figure 3, the present invention is further, described two PMOS tube (C1, C2) in each clamp circuit Source electrode is all connected with supply voltage VDD, and the drain electrode of two PMOS tube is separately connected bit line BP and bit line BN.

Further, each clamp circuit in Fig. 3 connects a global pre-charge circuit (on Fig. 3 to the present invention Circuit in square dotted line frame), bit line is pre-charged to supply voltage before read-write operation starts；The overall situation pre-charge circuit is by One forms to third PMOS tube, and described first to third PMOS tube grid connects global precharge control logic signal jointly； Wherein, first PMOS tube connects power vd D with the source electrode of the second PMOS tube (above overall situation pre-charge circuit described in Fig. 3 Two PMOS tube be the first, second PMOS tube), drain electrode is separately connected the source electrode and drain electrode of third PMOS tube, that is, described The source electrode and drain electrode of the drain electrode connection third PMOS tube of first, second PMOS tube；The source of the third PMOS tube, drain electrode respectively with Bit line BP, bit line BN connection (PMOS tube below overall situation pre-charge circuit described in Fig. 3 is the third PMOS tube).

In the present embodiment, the bit line BP and bit line BN of each clamp circuit are separately connected a transfer tube circuit (position The circuit of the leftmost side and the rightmost side is the transfer tube circuit in Fig. 3).It selects for bit line to be separately connected in read/write operation To read operation control module and write operation control module.As shown in figure 3, a transfer tube circuit described in the present embodiment includes phase The NMOS tube and a PMOS tube to connect, the bit line BP and bit line BN meet the company in the NMOS tube and PMOS tube respectively It connects at end.That is, the NMOS tube and PMOS tube in one transfer tube circuit are end to end, the bit line BP and bit line BN are connected between the NMOS tube and the connecting pin of PMOS tube.The transfer tube circuit is in read/write operation Bit line is respectively connected to the read operation control module (RDBLK) and the write operation control module (WTBLK) by selection.

In the present invention further, the read operation control module (RDBLK) includes sensitive amplifier circuit and sensitive puts The control signal generating circuit of big circuit.This module amplifies two signals on bit line BP, BN simultaneously by sensitive amplifier circuit Be converted to output signal Q.Wherein, the sensitive amplifier circuit includes analog computing amplifier, that is, the sensitive amplifier circuit It can be realized by all kinds of analog computing amplifiers；The control signal generating circuit of the sensitive amplifier circuit by several metal-oxide-semiconductors, Combinational logic gate, register and latch composition.

In the present embodiment, the write operation control module (WTBLK) is made of several logic circuits, is used for input data It is converted into two opposite signals and is sent to bit line BP and bit line BN.The SRAM memory cell is finally written.It is heretofore described The PMOS tube in each clamp circuit and first, second, third PMOS tube in the global precharge module Size is suitable, order-of-magnitude agreement.

When read operation, clamp circuit can effectively avoid the Data flipping of internal node, enhance in 6 transistor memory unit of SRAM The stability of portion's node can also increase the potential difference between bit line to guarantee the correctness of storing data, improve and read speed Degree；When write operation, clamp circuit can guarantee that bit line one end is permanent high, to improve writing speed.Global pre-charge circuit is being read Bit line is pre-charged to supply voltage before starting by write operation, the data reset that will be stored on last operation bit line, for next time Operation is prepared.

Since each clamp circuit of the invention is also connected with the SRAM memory cell, the SRAM storage is single Member is made of the four, the 5th PMOS tube and first to fourth NMOS tube in the present embodiment.As shown in figure 4, Fig. 4 is shown as this hair The circuit diagram that bright clamp circuit is connect with SRAM memory cell.Wherein, the described 4th in the SRAM memory cell PMOS tube P4, the 5th PMOS tube P5 source electrode meet supply voltage VDD, grid, the first NMOS of the 4th PMOS tube P4 jointly The grid of pipe N1, the drain electrode of the 5th PMOS tube P5, the drain electrode of the second NMOS tube N2 and the drain electrode of the 4th NMOS tube N4 mutually interconnect It connects；The drain electrode of the 4th PMOS tube P4, the drain electrode of the first NMOS tube N1, the drain electrode of third NMOS tube N3, the 5th PMOS tube P5 Grid and the second NMOS tube N2 grid be connected with each other；The source electrode of the third NMOS tube N3 connects bit line BN；Described The source electrode of four NMOS tube N4 connects bit line BP；The grid of the 4th NMOS tube N4 and the grid of the third NMOS tube N3 are common Connect wordline WL.(due to including several clamp circuits in the optimization circuit of the invention, each clamp circuit It is connect with a SRAM memory cell, and each clamp circuit connects the global pre-charge circuit, such as Fig. 4 institute Show, therefore composition includes the array an of clamp circuit, a SRAM memory cell and a global pre-charge circuit, it is described Bit line BP and bit line BN also forming array BP0, BN0；BN1, BP1 ...).

Before read-write operation starts, as shown in figure 3, global pre-charge circuit in selecting module (MUX) is by all positions Line is pre-charged to supply voltage.When read operation, such as Fig. 4, by taking the circuit of secondary series in the array as an example, it is assumed that internal node P It deposits " 1 ", N deposits " 0 ".Global pre-charge circuit disconnects, the NMOS transfer tube conducting of certain row, position in the wordline WL control array chosen Line BN1 is discharged to VSS by transmission NMOS tube and pull-down NMOS pipe, and the decline of BN1 voltage generates potential difference with BN1, by sensitive Amplifier reads data.If adjacent SRAM memory cell has opposite data, adjacent bit lines BN0 current potential is that 1, BN1 current potential is 0, potential difference is maximum in the coupled capacitor of adjacent bit lines, and BN0 is caused to charge on BN1, and the internal node N for keeping BN1 connected is easier to It is flipped, the data being stored at internal node P and N is caused to have the risk being written over.

The addition of clamp circuit is it is possible to prevente effectively from above reading overturns risk, since BP1, BN1 are respectively connected to clamper Grid and cross interconnected one of the grid of PMOS tube that drains in circuit, when BN1 current potential drops to PMOS tube threshold voltage vt, PMOS tube C2 conducting, the bit line BP1 being connected with drain electrode are pulled to supply voltage, and internal node current potential P is also set to height, and P passes through Inverter controlling N is set low, and ensure that the stabilization of internal node current potential N.In addition, the substrate of metal-oxide-semiconductor leaks in advanced process node Electricity increases, when BN1 reads " 0 ", BP1 also due to electric leakage brings the slow decline of voltage, due to clamp circuit BP1 clamped it is supreme Level is increasing the voltage difference between two bit lines in read operation, can be improved the speed and correctness for reading data.Due to Clamp circuit is made of two grids and the cross interconnected PMOS tube that drains, and similarly, if internal node P is deposited " 0 ", N deposits " 1 ", Then reading data course neutrality line BN1 will be clamped to high level.

When write operation, input data is converted to two by several combinational logic circuits by write operation control module (WTBLK) A opposite signal WP/WN, and opposite signal is sent to by bit line BP/BN by selecting unit (MUX).Assuming that BN1 writes at end in Fig. 4 1, BP1 end is write 0, BP1 control clamp circuit C1 and is opened, and clamps bit line BN1 to high level, deposits to improve data write-in SRAM The speed of storage unit.

Compared with prior art, the present invention increases in selecting module by two grids and the cross interconnected PMOS tube that drains Circuit-clamp circuit of composition.This technological improvement effectively eliminates the defect of SRAM read/write circuit in the prior art, can be effective It prevents the current potential of SRAM memory cell internal node from overturning, ensure that the correctness of its storing data, and then ensure that SRAM's Yield.Simultaneously, moreover it is possible to effectively improve write-in reading speed.Moreover, its simple possible, without to circuit structure and domain cloth Office carries out excessive change, and for design upgrading, compatibility and economy are all fairly good.

The read-write for SRAM of the invention, which is shown with, refering to Fig. 5, Fig. 5 optimizes circuit and not using read-write optimization electricity The simulation result on road compares.Fig. 5 compared the bit-line voltage under the read/write circuit read operation of optimization front and back.Before optimization, " 0 " behaviour is read The bit line BP2 electric discharge of work causes voltage to decline, and should maintain the bit line BN2 of high level originally due to shadows such as coupled capacitor, electric leakages Ringing voltage can also decline.If the clock duration long enough of read operation, bit line BN2 can be discharged to always low potential, at this time inherently SRAM memory cell internal node Data flipping is caused, the validity for reading data next time is influenced.After optimization, from simulation result It can be seen that after bit line BP drops to certain voltage, clamp circuit is opened by the PMOS tube that bit line BP is controlled, at this time bit line BN by It is pulled to high potential in the connection so far drain electrode of PMOS tube, SRAM memory cell internal node N is pulled to high level, surely Determine SRAM memory cell internal node P, successfully avoids the Data flipping of SRAM memory cell internal node.

In conclusion the present invention is added one by two grids and the cross interconnected PMOS tube group that drains in selecting module At clamp circuit；The SRAM storage singly internal node Data flipping in reading process, effectively promotion SRAM can be effectively prevented Yield, while write-in reading speed can be improved.So the present invention effectively overcomes various shortcoming in the prior art and has High industrial utilization value.

The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as At all equivalent modifications or change, should be covered by the claims of the present invention.