阅读说明：本技术 一种具有自偏置pmos的横向沟槽型igbt及其制备方法 (A kind of lateral trench type IGBT and preparation method thereof with automatic biasing PMOS ) 是由 张金平 赵阳 罗君轶 刘竞秀 李泽宏 张波 于 2019-08-29 设计创作，主要内容包括：本发明属于功率半导体器件技术领域,涉及一种具有自偏置PMOS的横向沟槽型IGBT及其制备方法。本发明在LIGBT器件结构的基础上,加入载流子存储层,增强电导调制效应,减小器件导通压降；用分离栅包裹栅极的侧面,减小密勒电容,降低关断时间,减小关断损耗,改善正向导通压降与关断损耗的折中；同时能够减少器件的栅电荷,降低了驱动损耗；优化了电流下降速率(di/dt)与导通损耗(Eon)的折衷特性；正向导通时自偏置MOSFET的自开启,钳位电荷存储区电压,减小饱和电流,优化短路安全工作区；关断初期自偏置MOSFET开启,加快抽取漂移区的过剩载流子,减少关断损耗；槽栅左侧埋层能辅助耐压,增加阻断电压；薄的栅氧化层能够降低器件的阈值电压,减小闩锁电流密度。(The invention belongs to power semiconductor device technology fields, are related to a kind of lateral trench type IGBT and preparation method thereof with automatic biasing PMOS.Carrier accumulation layer is added on the basis of LIGBT device architecture in the present invention, enhances conductivity modulation effect, reduces break-over of device pressure drop；With the side of separate gate package grid, reduce Miller capacitance, reduce the turn-off time, reduce turn-off power loss, improves the compromise of forward conduction voltage drop and turn-off power loss；The grid charge that device can be reduced simultaneously, reduces drive loss；Optimize the compromise characteristic of current fall rate (di/dt) Yu conduction loss (Eon)；The unlatching certainly of automatic biasing MOSFET, clamper electric charge storage region voltage reduce saturation current when forward conduction, optimize short-circuit safety operation area；Shutdown initial stage automatic biasing MOSFET is opened, and is accelerated the excess carriers for extracting drift region, is reduced turn-off power loss；Buried layer can assist pressure resistance on the left of slot grid, increase blocking voltage；Thin gate oxide can reduce the threshold voltage of device, reduce latch-up current density.)

1. a kind of lateral trench type IGBT with automatic biasing PMOS, including the second conduction type half set gradually from bottom to top Conductor substrate (1), spacer medium layer (2), the first conductive type semiconductor drift region (3)；With three-dimensional cartesian coordinate system to device Three-dimensional be defined: define device transverse direction be x-axis direction, device vertical direction is y-axis direction, device longitudinal direction side It is z-axis direction to i.e. third dimension direction；Along the z-axis direction, the upper layer both ends of the first conductive type semiconductor drift region (3) are set respectively It is equipped with collector structure and emitter structure；The collector structure includes the first conductive type semiconductor buffer area (4), insertion It is arranged in the second conductive type semiconductor collecting zone (5) on first conductive type semiconductor buffer area (4) upper layer and positioned at second First metallization collector (6) of conductive type semiconductor collecting zone (5) upper surface, the second conductive type semiconductor current collection Area (5) is located at the first side of conductive type semiconductor buffer area (4) upper layer far from emitter structure, and the second conduction type half The upper surface of conductor collecting zone (5) is flushed with the upper surface of the first conductive type semiconductor buffer area (4)；The emitter structure Including the first conductive type semiconductor electric charge storage region (15), it is located at table on the first conductive type semiconductor electric charge storage region (15) The second conductive type semiconductor base area (7) in face, be disposed in parallel in second conductive type semiconductor base area (7) upper surface first Conductive type semiconductor emitter region (8) and the second conductive type semiconductor emitter region (9), the first conductive type semiconductor emitter region (8) and the upper surface of the second conductive type semiconductor emitter region (9) has the first metallization emitter (10), and described first is conductive Type semiconductor emitter region (8) and the second conductive type semiconductor emitter region (9) are to be set side by side along the x-axis direction；Along x-axis side To emitter structure is located at the one end on the upper layer of the first conductive type semiconductor drift region (3)；It is characterized by:

Along the x-axis direction, the side of emitter structure is equipped with first groove grid structure, and first groove grid structure includes the second emitter (12) and setting the second emitter (12) side wall and bottom wall the first gate dielectric layer (11)；It is set inside the second emitter (12) Second groove structure is set, including first gate electrode (14) and the second gate medium in first gate electrode (14) side wall and bottom wall is set Layer (13), second groove structure are contacted with emitter structure；Along the x-axis direction, the first conductive type semiconductor drift region (3) is upper The other end relative to emitter structure of layer has the second conductive type semiconductor doping contacted with first groove grid structure The first conductive type semiconductor doped region on second conductive type semiconductor doped region (18) upper layer is arranged in area (18), insertion (17), second conductive type semiconductor doped region of the insertion setting on first conductive type semiconductor doped region (17) upper layer (16), the second conductive type semiconductor doped region (16) and the first conductive type semiconductor doped region (17) are respectively positioned on far from current collection One end of pole structure；Third metallization emitter (19) is provided with above second conductive type semiconductor doped region (16)；It is described Thickness of the thickness of the second gate dielectric layer (13) side wall less than the first gate dielectric layer (11) side wall；First conductive type semiconductor electricity The doping concentration of lotus memory block (15) is greater than the doping concentration of the first conductive type semiconductor drift region (3)；Second conduction type The doping concentration in semiconductor doping area (16) is higher than the doping concentration of the first conductive type semiconductor doped region (17)；First is conductive Type semiconductor doped region (17) doping concentration is higher than the doping concentration of the first conductive type semiconductor drift region (3)；Second leads Electric type semiconductor buried layer area (18) doping concentration is higher than the doping concentration of the first conductive type semiconductor drift region (3).

2. a kind of lateral trench type IGBT with automatic biasing PMOS according to claim 1, it is characterised in that: second Conductive type semiconductor base area (8) upper surface is provided with third gate dielectric layer (131), and third gate dielectric layer (131) extends along z-axis To the top of the first conductive type semiconductor electric charge storage region (15) and the first conductive type semiconductor emitter region (8)；Third grid The second gate electrode (141) are provided with above dielectric layer (131)；Second gate electrode (141) extends lengthwise into the first conduction type half The top of conductor charge memory block (15) and the first conductive type semiconductor emitter region (8).

3. a kind of lateral trench type IGBT with automatic biasing PMOS according to claim 2, it is characterised in that: by first The side with the emitter structure in z-axis direction along the x-axis direction is arranged in trench gate structure, and first groove grid structure is along z-axis side It is contacted to the first conductive type semiconductor emitter region (8) and the second conductive type semiconductor emitter region (9), and first groove grid The combination of structure and the first conductive type semiconductor emitter region (8) and the second conductive type semiconductor emitter region (9) is in device table It is rectangle on the top view in face, the depth of first groove grid structure is greater than the first conductive type semiconductor electric charge storage region (15) Junction depth, first groove grid structure includes the second emitter (12) and by the second emitter (12) and the first conductive type semiconductor The first gate dielectric layer (11) of drift region (3) and emitter structure isolation；Second groove structure setting is in second along the z-axis direction Emitter (12) is internal, and the depth of second groove structure is greater than the junction depth of the second conductive type semiconductor base area (7), second groove Structure include first gate electrode (14) and first gate electrode (14) is isolated with the second emitter (12) and emitter structure Two gate dielectric layers (13).

4. according to claim 1 to a kind of lateral trench type IGBT with automatic biasing PMOS described in 3, it is characterised in that: the It is internal that two gate dielectric layers (13) and first gate electrode (14) extend to the second emitter (12) along the x-axis direction, and remote along the z-axis direction Side from the first conductive type semiconductor buffer area (4) extends up to cellular boundary；Second gate dielectric layer (13) is in x-axis direction It is contacted with the first conductive type semiconductor emitter region (8)；First gate electrode (14) passes through the second gate dielectric layer (13) and the second hair Emitter-base bandgap grading (12) isolation.

5. a kind of lateral trench type IGBT with automatic biasing PMOS according to claim 4, it is characterised in that: first The first conductive type semiconductor between conductive type semiconductor doped region (20) and the first conductive type semiconductor buffer area (4) The second conductive type semiconductor buried layer (20) is additionally provided in drift region (3)；It mixes second conductive type semiconductor buried layer (20) Miscellaneous concentration is greater than the doping concentration of the first conductive type semiconductor drift region (3)；Second conductive type semiconductor buried layer (20) Vertical direction depth of the vertical direction depth less than the first gate dielectric layer (11).

6. a kind of lateral trench type IGBT with automatic biasing PMOS according to claim 5, it is characterised in that: will be along z The second emitter (12) that axis direction width is greater than second conductive type semiconductor doped region (16) width is led to x-axis direction first Electric type semiconductor doped region (17) side extends to half cellular boundary of contact；；The second emitter (12) side wall after extension and Bottom is provided with the first gate dielectric layer (11)；In the z-axis direction of the second conductive type semiconductor emitter region (9) close to first grid electricity The first conductive type semiconductor emitter region (81) is arranged in the side of pole (14)；First conductive type semiconductor emitter region (81) and the Two gate dielectric layers (13), the second conductive type semiconductor base area (7) and the first metallization emitter (10) contact.

7. a kind of lateral trench type IGBT with automatic biasing PMOS according to claim 6, it is characterised in that: by first Interlaced the first conductive type semiconductor doped region (21) and second is set along the x-axis direction in conduction type drift region (3) Conductive type semiconductor doped region (22)；First conductive type semiconductor doped region (21) and the doping of the second conductive type semiconductor The doping concentration in area (22) is higher than the doping concentration of the first conductive type semiconductor drift region (3)；First conductive type semiconductor The lower surface of doped region (22) is lower than the lower surface of the first conductive type semiconductor buffer area (4).

8. a kind of lateral trench type IGBT with automatic biasing PMOS according to claim 7, it is characterised in that: first The x-axis direction of gate dielectric layer (11) is provided with third dielectric layer (111), third medium with respect to the other side of first gate electrode (14) Layer (111) extends in z-axis direction to be in contact with the first gate oxide (11)；The vertical direction following table of third dielectric layer (111) The position in face is higher than the position of the vertical direction lower surface in the second conductive type semiconductor buried layer area (18)；Third dielectric layer (111) it is internally provided with the 4th emitter (121), the 4th emitter (121) extends to and the second emitter (12) to z-axis direction It is in contact.

9. a kind of lateral trench type IGBT with automatic biasing PMOS according to claim 8, it is characterised in that: first leads Electric type semiconductor is N-type semiconductor, and the second conductive type semiconductor is P-type semiconductor；Or first conductive type semiconductor For P-type semiconductor, the second conductive type semiconductor is N-type semiconductor.

10. a kind of preparation method of the lateral trench type IGBT with automatic biasing PMOS, comprising the following steps:

Step 1: selection backing bottom is the second conductive type semiconductor substrate zone (1), dielectric layer is spacer medium layer (2), top layer For the substrate of the first conductive type semiconductor drift region (3)；

Step 2: growing one layer of pre- oxygen in surface of semiconductor chip, partly led by photoetching, ion implanting in the first conduction type afterwards The second conductive type impurity is injected on body drift region (3) and is annealed, and the second conductive type semiconductor buried layer (18) is formed；Pass through again Photoetching, ion implanting inject the first conductive type impurity on the first conductive type semiconductor drift region (3) and anneal, and form the One conductive type semiconductor charge storage layer (15)；

Step 3: injecting the first conductive type impurity on the second conductive type semiconductor buried layer (18) and anneal, form first and lead Electric type semiconductor doped region (17)；

Step 4: injecting the second conductive type impurity at the first conductive type semiconductor doped region (17) and anneal, form the Two conductive type semiconductor doped regions (16)

Step 5: growing one layer of pre- oxygen in surface of semiconductor chip, partly led by photoetching, ion implanting in the first conduction type afterwards The second conductive type impurity is injected in volume charge accumulation layer (15) and is annealed, and the second conductive type semiconductor base area (7) is formed；

Step 6: growing one layer of pre- oxygen in surface of semiconductor chip, partly led by photoetching, ion implanting in the first conduction type afterwards Body drift region (3) injects the first conductive type impurity and anneals, and forms the first conductive type semiconductor buffer area (4).

Step 7: depositing protective layer in device surface, groove is formed by lithography and etching technique；

Step 8: complete first groove structure is formed by oxidation, deposit and etching technics；

Step 9: depositing low stress protective layer in device surface, groove is formed in first groove by lithography and etching technique；

Step 10: complete second groove structure is formed by oxidation, deposit and etching technics；

Step 11: the low stress protective layer deposited when removing etching second trenches；

Step 12: rectangular on the second conductive type semiconductor base area (7) by photoetching, the first conductive type impurity of ion implanting At the first conductive type semiconductor emitter region (8), level is then formed in by photoetching, the second conductive type impurity of ion implanting The second conductive type semiconductor emitter region (9) that direction and the first conductive type semiconductor emitter region (8) are arranged side by side；

Step 13: through photoetching, the second conductive type impurity of ion implanting above the first conductive type semiconductor buffer area (4) The second conductive type semiconductor collecting zone (5) is formed, and is annealed；

Step 14: depositing metal in device surface, and using photoetching, etching technics in the first conductive type semiconductor emitter region (8) and the second conductive type semiconductor emitter region (9) upper surface forms emitter metal (10)；In the second conductive type semiconductor Collecting zone (5) upper surface forms collector electrode metal (6)；It is formed and is emitted in the second conductive type semiconductor doped region (16) upper surface Pole metal (19).

Technical field

The invention belongs to power semiconductor technologies fields, and in particular to a kind of lateral trench type insulated gate bipolar transistor.

Background technique

Insulated gate bipolar transistor (IGBT) is a kind of widely used power electronic devices, possesses input impedance height, The characteristics of driving circuit is simple and current density is big, saturation pressure reduces.And transversal I GBT device is developed on the basis of IGBT The horizontal integrating power device come, the input impedance that it combines IGBT device structure is high, driving power is small, conduction voltage drop is low, A variety of advantages such as switching speed is fast, voltage blocking capability is strong, and important application is obtained in horizontal integrating devices field.

As the continuous improvement of the integrated level of horizontal semiconductor device and characteristic size constantly reduce, close device is arranged It is increasingly severe by the interaction of substrate between device so that using traditional bulk silicon technological production integrated circuit can It is substantially reduced by property and performance, is increasingly not suitable with the needs of industrial application.So SOI technology gradually becomes production at present laterally Device includes the mainstream technology of transversal I GBT.SOI technology will be pushed up silicon using buried oxide layer and be kept apart with following silicon substrate, push up Making devices on silicon, so that cannot be coupled, while can be generated with suppression device substrate by substrate between device and device Ghost effect, buried oxide layer can also assist transversal I GBT pressure-resistant in forward blocking, greatly improve the performance of device, mention High device reliability.

Fig. 1 is the half cellular structural schematic diagram of trench gate transversal I GBT of the tradition based on SOI.Device in forward blocking, Drift region base area mutually exhausts, and depletion layer bears high voltage, while the buried layer of silicon dioxide of SOI assists pressure resistance；Device is just To when conducting, parasitic pnp transistor is opened, while injecting base current to pnp transistor by MOS channel, makes pnp transistor Work generates big injection effect in amplification region, conductance modulation occurs, reduces conduction voltage drop, conductance modulation is stronger, and conduction voltage drop is got over It is low；And due to big injection effect, turn-off speed when device turns off is slow, has serious current tail phenomenon, can make in use At biggish turn-off power loss.Obviously, it is desirable to make transversal I GBT obtain lower conduction voltage drop and switching loss, to mention Rise its performance.

Transversal I GBT works in high current high power field, and while reducing conduction voltage drop, it is special to need to pay close attention to its short circuit Property, saturation current density is reduced, to improve shorted devices reliability, protection device will not be damaged because electric current is excessive.For this purpose, The structure of transversal I GBT device need to be changed, so that current potential will not be lifted to very high below base area in high collector voltage Value improve the short circuits of device so that the saturation current for flowing through emitter is limited in a lower value.

Summary of the invention

The present invention provides a kind of lateral trench type IGBT and preparation method thereof with automatic biasing PMOS.Compared to biography The two-dimensional structure of system, present invention adds the slot grid structures of carrier accumulation layer to play carrier memory action, optimizes drift Area's Carrier Profile, enhancing conductivity modulation effect and reduction break-over of device pressure drop；Grid is wrapped up with the separate gate of sending and receiving emitter-base bandgap grading Side reduces the turn-off time so that the largely coupling of suppressor grid and drift region, reduces Miller capacitance, reduces Turn-off power loss improves the compromise of forward conduction voltage drop and turn-off power loss；The grid charge that device can be reduced simultaneously, is easy to drive, Reduce the requirement to driving circuit ability；Reduce drive loss；Optimize current fall rate di/dt and conduction loss Eon Compromise characteristic；Automatic biasing MOSFET can be collectively formed with gate oxide and emitter in interlocking PNP layers for slot grid side, just To automatic biasing MOSFET when conducting carrier accumulation layer voltage can be made to be clamped, reduce saturation current, improve short circuit from opening Reliability；It is opened in shutdown initial stage automatic biasing MOSFET, accelerates the excess carriers for extracting drift region, reduce the turn-off time, subtract Few turn-off power loss.With buried layer on the left of time slot grid can in forward blocking it is pressure-resistant, increase blocking voltage, while can allow higher The doping concentration of carrier accumulation layer reduces conduction voltage drop；The thick oxide layer of slot grid longitudinal direction can reduce the turn-off time, subtract Few turn-off power loss, improves the compromise of forward conduction and turn-off power loss；Thin gate oxide can reduce the threshold voltage of device, subtract Small latch-up current density.

The present invention adopts the following technical scheme that realization:

The present invention provides a kind of lateral insulated gate bipolar transistor, including the second conduction type set gradually from bottom to top Semiconductor substrate 1, spacer medium layer 2, the first conductive type semiconductor drift region 3；With three-dimensional cartesian coordinate system to the three of device Dimension direction be defined: define device transverse direction be x-axis direction, device vertical direction be y-axis direction, device longitudinal direction i.e. Third dimension direction is z-axis direction；Along the z-axis direction, the upper layer both ends of the first conductive type semiconductor drift region 3 are respectively arranged with collection Electrode structure and emitter structure；The collector structure includes the first conductive type semiconductor buffer area 4, and insertion setting is the It the second conductive type semiconductor collecting zone 5 on one conductive type semiconductor buffer area, 4 upper layer and is partly led positioned at the second conduction type First metallization collector 6 of 5 upper surface of body collecting zone, it is conductive that the second conductive type semiconductor collecting zone 5 is located at first Side of 4 upper layer of type semiconductor buffer area far from emitter structure, and the upper surface of the second conductive type semiconductor collecting zone 5 It is flushed with the upper surface of the first conductive type semiconductor buffer area 4；The emitter structure includes the first conductive type semiconductor Electric charge storage region 15, the second conductive type semiconductor base area positioned at 15 upper surface of the first conductive type semiconductor electric charge storage region 7, the first conductive type semiconductor emitter region 8 and second for being disposed in parallel in 7 upper surface of the second conductive type semiconductor base area is led Electric type semiconductor emitter region 9, the first conductive type semiconductor emitter region 8 and the second conductive type semiconductor emitter region 9 it is upper Surface has the first metallization emitter 10, the first conductive type semiconductor emitter region 8 and the second conductive type semiconductor Emitter region 9 is to be set side by side along the x-axis direction；Along the x-axis direction, emitter structure is located at the first conductive type semiconductor drift region 3 Upper layer one end；It is characterized by:

Along the x-axis direction, the side of emitter structure is equipped with first groove grid structure, and first groove grid structure includes the second hair Emitter-base bandgap grading 12 and the first gate dielectric layer 11 that 12 side wall of the second emitter and bottom wall are set；Is arranged inside the second emitter 12 Two groove structures, including first gate electrode 14 and the second gate dielectric layer 13 that 14 side wall of first gate electrode and bottom wall is arranged in, Two groove structures are contacted with emitter structure；Along the x-axis direction, the upper layer of the first conductive type semiconductor drift region 3 relative to There is the other end of emitter structure the second conductive type semiconductor doped region 18 contacted with first groove grid structure, insertion to set It sets and is arranged in the first conductive type semiconductor doped region 17 on 18 upper layer of the second conductive type semiconductor doped region, insertion first The second conductive type semiconductor doped region 16 on 17 upper layer of conductive type semiconductor doped region, the doping of the second conductive type semiconductor Area 16 and the first conductive type semiconductor doped region 17 are respectively positioned on one end far from collector structure；Second conductive type semiconductor Third metallization emitter 19 is provided with above doped region 16；The thickness of second gate dielectric layer, 13 side wall is situated between less than the first grid The thickness of 11 side wall of matter layer；The doping concentration of first conductive type semiconductor electric charge storage region 15 is greater than the first conduction type and partly leads The doping concentration of body drift region 3；The doping concentration of second conductive type semiconductor doped region 16 is higher than the first conduction type and partly leads The doping concentration of body doped region 17；First conductive type semiconductor doped region, 17 doping concentration is higher than the first conductive type semiconductor The doping concentration of drift region 3；Second conductive type semiconductor buried layer area, 18 doping concentration is floated higher than the first conductive type semiconductor Move the doping concentration in area 3.

It is situated between further, third grid can also be arranged in 8 upper surface of the second conductive type semiconductor base area in the present invention Matter layer 131, third gate dielectric layer 131 extend to the first conductive type semiconductor electric charge storage region 15 and the first conductive-type along z-axis The top in type semiconductor emission area 8；The second gate electrode 141 is provided with above third gate dielectric layer 131；Second gate electrode 141 is vertical To the top for extending to the first conductive type semiconductor electric charge storage region 15 and the first conductive type semiconductor emitter region 8.

Further, first groove grid structure can also be arranged in the hair with z-axis direction along the x-axis direction in the present invention The side of emitter structure, first groove grid structure is conductive with the first conductive type semiconductor emitter region 8 and second along the z-axis direction Type semiconductor emitter region 9 contacts, and first groove grid structure and the first conductive type semiconductor emitter region 8 and the second conductive-type The combination in type semiconductor emission area 9 is rectangle on the top view of device surface, and the depth of first groove grid structure is greater than the The junction depth of one conductive type semiconductor electric charge storage region 15, first groove grid structure include the second emitter 12 and emit second The first gate dielectric layer 11 that pole 12 is isolated with the first conductive type semiconductor drift region 3 and emitter structure；Second groove structure It is arranged in inside the second emitter 12 along the z-axis direction, the depth of second groove structure is greater than the second conductive type semiconductor base The junction depth in area 7, second groove structure include first gate electrode 14 and by first gate electrode 14 and the second emitter 12 and emitter Second gate dielectric layer 13 of structure isolation

Further, the second gate dielectric layer 13 and first gate electrode 14 can also be extended along the x-axis direction in the present invention Cellular is extended up to far from the side of the first conductive type semiconductor buffer area 4 to inside the second emitter 12, and to z-axis direction Boundary；Second gate dielectric layer 13 is contacted with the first conductive type semiconductor emitter region 8 in the horizontal direction；First gate electrode 14 passes through Second gate dielectric layer 13 is isolated with the second emitter 12.

Further, can also be by the first conductive type semiconductor doped region 20 and the first conduction type half in the present invention The second conductive type semiconductor buried layer 20 is additionally provided in the first conductive type semiconductor drift region 3 between conductor buffer area 4； The doping concentration of second conductive type semiconductor buried layer 20 is greater than the doping concentration of the first conductive type semiconductor drift region 3；The Vertical direction depth of the vertical direction depth of two conductive type semiconductor buried layers 20 less than the first gate dielectric layer 11.

Further, in the present invention the second conductive type semiconductor doped region can also will be greater than by width along the z-axis direction Second emitter 12 of 16 width extends to half cellular side of contact to 17 side of the first conductive type semiconductor of x-axis direction doped region Boundary；12 side wall of the second emitter and bottom after extension are provided with the first gate dielectric layer 11；It is sent out in the second conductive type semiconductor That penetrates area 9 is arranged the first conductive type semiconductor emitter region 81 close to the side of first gate electrode 14 along the z-axis direction；First is conductive Type semiconductor emitter region 81 and the second gate dielectric layer 13, the second conductive type semiconductor base area 7 and the first metallization emitter 10 contacts.

Further, will can also be arranged along the x-axis direction in the first conduction type drift region 3 in the present invention interlaced The first conductive type semiconductor doped region 21 and the second conductive type semiconductor doped region 22；First conductive type semiconductor is mixed The doping concentration of miscellaneous area 21 and the second conductive type semiconductor doped region 22 is higher than mixing for the first conductive type semiconductor drift region 3 Miscellaneous concentration；The lower surface of first conductive type semiconductor doped region 22 is lower than the following table of the first conductive type semiconductor buffer area 4 Face.

Further, the first gate dielectric layer 11 is provided with respect to the other side of first gate electrode 14 along the x-axis direction Three dielectric layers 111, third dielectric layer 111 are extended in longitudinal direction and are in contact with the first gate oxide 11；Third dielectric layer 111 Vertical direction lower surface be higher than the second conductive type semiconductor buried layer area 18 vertical direction lower surface；Third dielectric layer 111 It is internally provided with the 4th emitter 121, the 4th emitter 121 is extended to longitudinal direction and is in contact with the second emitter 12.

Further, can also be N-type semiconductor, the second conduction type by the first conductive type semiconductor in the present invention Semiconductor is P-type semiconductor；Or first conductive type semiconductor be P-type semiconductor, the second conductive type semiconductor is N-type half Conductor.

Further, the semiconductor material of IGBT device uses Si, SiC, GaAs or GaN, trench fill in the present invention Material uses polycrystalline Si, SiC, GaAs or GaN, and not same material group can also be used using same material in each section It closes.

The present invention also provides a kind of production methods of lateral trench type insulated gate bipolar transistor, comprising the following steps:

Step 1: selection backing bottom is the second conductive type semiconductor substrate zone 1, dielectric layer is spacer medium layer 2, top layer For the substrate of the first conductive type semiconductor drift region 3；

Step 2: one layer of pre- oxygen is grown in surface of semiconductor chip, afterwards by photoetching, ion implanting in the first conduction type The second conductive type impurity is injected in drift semiconductor area 3 and is annealed, and the second conductive type semiconductor buried layer 18 is formed；Pass through again Photoetching, ion implanting inject the first conductive type impurity and are annealed on the first conductive type semiconductor drift region 3, form first Conductive type semiconductor charge storage layer 15；

Step 3: injecting the first conductive type impurity on the second conductive type semiconductor buried layer 18 and anneal, form first Conductive type semiconductor doped region 17；

Step 4: injecting the second conductive type impurity at the first conductive type semiconductor doped region 17 and anneal, formed Second conductive type semiconductor doped region 16

Step 5: one layer of pre- oxygen is grown in surface of semiconductor chip, afterwards by photoetching, ion implanting in the first conduction type The second conductive type impurity is injected on semiconductor charge storage layer 15 and is annealed, and the second conductive type semiconductor base area 7 is formed；

Step 6: one layer of pre- oxygen is grown in surface of semiconductor chip, afterwards by photoetching, ion implanting in the first conduction type Drift semiconductor area 3 injects the first conductive type impurity and anneals, and forms the first conductive type semiconductor buffer area 4.

Step 7: depositing protective layer in device surface, groove is formed by lithography and etching technique；

Step 8: complete first groove structure is formed by oxidation, deposit and etching technics；

Step 9: depositing low stress protective layer in device surface, ditch is formed in first groove by lithography and etching technique Slot；

Step 10: complete second groove structure is formed by oxidation, deposit and etching technics；

Step 11: the low stress protective layer deposited when removing etching second trenches；

Step 12: through photoetching, the first conductive type impurity of ion implanting above the second conductive type semiconductor base area 7 The first conductive type semiconductor emitter region 8 is formed, level is then formed in by photoetching, the second conductive type impurity of ion implanting The second conductive type semiconductor emitter region 9 that direction and the first conductive type semiconductor emitter region 8 are arranged side by side；

Step 13: through photoetching, the second conductive type impurity of ion implanting on the first conductive type semiconductor buffer area 4 It is rectangular at the second conductive type semiconductor collecting zone 5, and anneal；

Step 14: depositing metal in device surface, and emitted using photoetching, etching technics in the first conductive type semiconductor Area 8 and 9 upper surface of the second conductive type semiconductor emitter region form emitter metal 10；In the second conductive type semiconductor current collection 5 upper surface of area forms collector electrode metal 6；Emitter metal 19 is formed in 16 upper surface of the second conductive type semiconductor doped region.

It is prepared into lateral trench type insulated gate bipolar transistor of the present invention.

Details are as follows for original design intention of the invention:

The present invention proposes a kind of lateral insulated gate bipolar transistor, compared to traditional two-dimensional structure, present invention adds The slot grid structure of carrier accumulation layer plays carrier memory action, optimizes drift region carrier distribution, enhances conductance modulation Effect and reduction break-over of device pressure drop；The side that grid is wrapped up with the separate gate of sending and receiving emitter-base bandgap grading, thus largely suppressor The coupling of pole and drift region reduces Miller capacitance, reduces the turn-off time, reduces turn-off power loss, improves forward conduction voltage drop With the compromise of turn-off power loss；The grid charge that device can be reduced simultaneously, is easy to drive, and reduces the requirement to driving circuit ability； Reduce drive loss；Optimize the compromise characteristic of current fall rate (di/dt) Yu conduction loss (Eon)；Slot grid side Staggeredly automatic biasing MOSFET can be collectively formed with gate oxide and emitter for PNP layers, the automatic biasing MOSFET in forward conduction Carrier accumulation layer voltage can be made to be clamped, reduce saturation current, improve short circuits from opening；Shutdown initial stage from It biases MOSFET to open, accelerates the excess carriers for extracting drift region, reduce the turn-off time, reduce turn-off power loss.With time slot grid Left side buried layer can be pressure-resistant in forward blocking, increases blocking voltage, while can allow the doping of higher carrier accumulation layer Concentration reduces conduction voltage drop；The thick oxide layer of slot grid longitudinal direction can reduce the turn-off time, reduce turn-off power loss, improve just To the compromise of conducting and turn-off power loss；Thin gate oxide can reduce the threshold voltage of device, reduce latch-up current density.

Compared with prior art, the beneficial effects of the present invention are:

Compared with prior art, it the invention has the benefit that optimizing drift region carrier distribution, reduces laterally absolutely The forward conduction voltage drop of edge grid bipolar transistor；The Miller capacitance for reducing device, reduces the turn-off time, reduces shutdown damage Consumption；Grid charge needed for reducing the unlatching of device, is easy to drive；Conductive path when forward conduction is increased, by carrier The current potential clamper of accumulation layer, reduces saturation current density, improves the short circuits of device；Automatic biasing MOSFET when shutdown It opens, accelerates the excess carriers for extracting drift region, reduce the turn-off time, reduce turn-off power loss.When increasing shutdown Conductive path quickly extracts the excess carriers of drift region, reduces turn-off power loss, optimizes forward conduction voltage drop and shutdown is damaged Compromise between consumption；Increase forward blocking voltage；The threshold voltage for reducing device reduces latch-up current density.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of traditional groove-shaped transversal I GBT device based on SOI.

Fig. 2 is the structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Fig. 3 is the two dimensional cross-section structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Fig. 4 is the two dimensional cross-section structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Fig. 5 is the structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Fig. 6 is the structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Fig. 7 is the structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Fig. 8 is the structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Fig. 9 is the two dimensional cross-section structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Figure 10 is the structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Figure 11 is the two dimensional cross-section structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Figure 12 is the structural schematic diagram of transversal I GBT device provided in an embodiment of the present invention.

Figure 13 is two of the structure after transversal I GBT device manufacture method etching first groove provided in an embodiment of the present invention Tie up diagrammatic cross-section.

Figure 14 is that transversal I GBT device manufacture method provided in an embodiment of the present invention grows oxide layer 11 in first groove The two dimensional cross-section schematic diagram of structure afterwards.

Figure 15 is transversal I GBT device manufacture method provided in an embodiment of the present invention depositing polysilicon 12 in oxide layer 11 The two dimensional cross-section schematic diagram of structure afterwards.

Figure 16 is transversal I GBT device manufacture method provided in an embodiment of the present invention etched portions polycrystalline on polysilicon 12 The oxide layer 11 of silicon 12 and etched sidewall, the two dimensional cross-section schematic diagram of the structure after forming second groove.

Figure 17 is that transversal I GBT device manufacture method provided in an embodiment of the present invention grows oxide layer 13 in second groove The two dimensional cross-section schematic diagram of structure afterwards.

Figure 18 is transversal I GBT device manufacture method provided in an embodiment of the present invention depositing polysilicon 14 in oxide layer 13 The two dimensional cross-section schematic diagram of structure afterwards.

Figure 19 is that transversal I GBT device manufacture method ion implanting provided in an embodiment of the present invention forms N-type emitter region 8 and P The two dimensional cross-section schematic diagram of structure after type emitter region 9.

Figure 20 is after transversal I GBT device manufacture method ion implanting provided in an embodiment of the present invention forms p-type collecting zone 5 Structure two dimensional cross-section schematic diagram.

Fig. 1 is into Figure 20: 1 is P type substrate, and 2 be silica separation layer, and 3 be the drift region N, and 4 be the buffer area N, and 5 be p-type Collecting zone, 6 be the first metallization collector, and 7 be p-type base area, and 8 be N-type emitter region, and 9 be p-type emitter region, and 10 be the first metal Change emitter, 11 be the first silicon dioxide layer, and 12 be the second emitter, and 13 be the second silicon dioxide layer, and 14 be polysilicon gate electricity Pole, 15 be N-type carrier accumulation layer, and 16 be P-doped zone, and 17 be N-doped zone, and 18 be p type buried layer area, and 19 be third metal Change emitter, 20 be p type buried layer area, and 21 be N-doped zone, and 22 be P-doped zone, and 81 be N-type emitter region, and 111 be the three or two Silicon oxide layer, 121 be the 4th polysilicon emitter, and 131 be third gate oxide, and 141 be the second polygate electrodes.

Specific embodiment

In order to enable one of ordinary skill in the art can more understand the present invention program and principle, with reference to the accompanying drawing and have Body embodiment is described in detail.The contents of the present invention are not limited to any specific embodiment, and also not representing is most preferred embodiment, General substitution well-known to those skilled in the art is also encompassed within the scope of the invention.