阅读说明：本技术 一种具有超快恢复特性的复合二极管结构及其制造方法 (A kind of compound diode structure and its manufacturing method with Ultrafast recovery characteristic ) 是由 饶祖刚 王民安 项建辉 郑科峰 于 2019-08-07 设计创作，主要内容包括：本发明公开了一种具有超快恢复特性的复合二极管结构及其制造方法,该二极管包括N+衬底,位于N+衬底背面的金属化阴极和位于N+衬底正面的N型外延层；所述N型外延层上设置有一组向N型外延层内延伸的P区,所述P区在硅片有源区的N型外延层上均匀分布；相邻P区之间的N型外延层表面设置有一层采用等离子体轰击方式形成的缺陷层,所述P区和缺陷层上设置有一层肖特基势垒金属,肖特基势垒金属上设置有金属化阳极。该器件结构及其制造方法简单且易于实现,能够获得更快的恢复时间,降低器件的开关功耗,可以用于制造具有超快恢复特性的复合二极管(MPS)领域。(The invention discloses a kind of compound diode structure and its manufacturing method with Ultrafast recovery characteristic, which includes N+ substrate, positioned at the metallization cathode of N+ substrate back and positioned at the N-type epitaxy layer of N+ substrate face；One group of area P extended into N-type epitaxy layer is provided in the N-type epitaxy layer, the area P is uniformly distributed in the N-type epitaxy layer of silicon wafer active area；N-type epitaxy layer surface between the adjacent area P is provided with the defect layer that floor using plasma bombardment mode is formed, and is provided with a floor Schottky barrier metal in the area P and defect layer, is provided with metallization anode in Schottky barrier metal.The device architecture and its manufacturing method are simple and are easily achieved, and can obtain faster recovery time, reduce the switching power loss of device, can be used for manufacturing the field compound diode (MPS) with Ultrafast recovery characteristic.)

1. a kind of compound diode structure with Ultrafast recovery characteristic, including N+ substrate (109) are located at N+ substrate (109) and carry on the back The metallization cathode (108) in face and be located at N+ substrate (109) positive N-type epitaxy layer (100)；It is characterized by: outside the N-type Prolong and be provided with one group of area P (103) extended into N-type epitaxy layer (100) on floor (100), the area P (103) is in N-type epitaxy layer (100) it is uniformly distributed on；N-type epitaxy layer (100) surface between the adjacent area P (103) is provided with a floor using plasma and bangs The defect layer (105) that the mode of hitting is formed is provided with a floor Schottky barrier metal on the area P (103) and defect layer (105) (106), Schottky gesture is provided between the defect layer (105) on the Schottky barrier metal (106) and N-type epitaxy layer (100) Knot (111) is built, metallization anode (107) is provided in Schottky barrier metal (106).

2. as described in claim 1 with the compound diode structure of Ultrafast recovery characteristic, it is characterised in that: the chip point For intermediate active area (1) and positioned at the termination environment (2) of active area (1) surrounding, the area P (103) is arranged in active area (1) It is interior.

3. as described in claim 1 with the compound diode structure of Ultrafast recovery characteristic, it is characterised in that: the area P (103) surface is also equipped with the defect layer (105) that one layer of using plasma bombardment mode is formed.

4. as described in claim 1 with the compound diode structure of Ultrafast recovery characteristic, it is characterised in that: the Schottky For the material that barrier metal (106) uses for aluminium, nickel or nickel platinum, the metallization anode (107) can be with Schottky barrier metal (106) it is same metal, other metals can also be used.

5. a kind of compound diode manufacturing method with Ultrafast recovery characteristic, it is characterised in that:

The following steps are included: 1) formed absolutely on the surface of N-type epitaxy layer (100) by thermal oxide or chemical vapor deposition method Edge dielectric layer (101)；

2) by photoetching and wet-etching technology, on the insulating medium layer (101) of active area (1) selective etching go out one group it is uniform The doping window (102) that distribution is spaced apart from each other again；

3) using ion implantation technology by doping window (102) carry out p type impurity doping, then by heat treatment process at Reason, so that one group of area P (103) extended into N-type epitaxy layer (100) is formed on N-type epitaxy layer (100), meanwhile, heat treatment Technique also grows a floor and insulating medium layer (101) the same or different area P insulating medium layer on the area P (103) surface (110)；

4) pass through the area the P insulating medium layer (110) and phase in the area P (103) in photoetching and wet-etching technology removal active area (1) Insulating medium layer (101) between the adjacent area P (103) in N-type epitaxy layer (100), to form metal contact hole on chip (104)；

5) using plasma bombardment mode etches contact hole (104), in the area P (103) and the adjacent area P (103) of active area (1) Between N-type epitaxy layer (100) surface formed defect layer (105)；Or outside the N-type between the adjacent area P (103) of active area (1) Prolong layer (100) surface and forms defect layer (105)；

6) one layer of aluminium, nickel or nickel platinum alloy are deposited as Schottky by sputtering or evaporation technology on defect layer (105) Barrier metal (106), and the defect layer above Schottky barrier metal (106) and N-type epitaxy layer (100) is made by heat treatment (105) upper portion carries out alloy and forms schottky barrier junction (111), and the downside of schottky barrier junction retains a part of defect Layer (105)；

7) aluminium, titanium, nickel or silver metal are deposited or evaporated in chip surface form metallization anode (107)；

8) N+ substrate (109) relative to N-type epitaxy layer (100) another side by sputter or evaporation titanium nickeline, nickeline or Person's titanium nickel and vanadium silver metal forms metallization cathode (108).

Technical field

The present invention relates to power semiconductor field more particularly to a kind of compound diodes with Ultrafast recovery characteristic Structure and its manufacturing method.

Background technique

In diode family, there is P-type semiconductor to contact the PN junction diode to be formed or its extension with N-type semiconductor Fast recovery diode out, the Schottky barrier diode for also thering is metal and semiconductor contact to be formed, usual PN junction diode with The increase of drift region thickness, higher pressure resistance can be obtained, but pressure drop is higher when device forward conduction, device shutdown recovery Time is longer, has higher conducting power consumption and switching power loss so as to cause device.It is compound by mixing platinum, gold doping introducing deep energy level Center can shorten the recovery time of PN junction diode device, but often production line is difficult to compatible heavy metal technique, manufacturing process Become complicated.And Schottky diode has faster switching speed and lower forward voltage drop, thus there is lower conducting Power consumption and switching power loss, but since the limitation of Schottky barrier causes device pressure resistance to be difficult to improve, its usual pressure resistance is no more than 200V。

Summary of the invention

An object of the present invention is to provide a kind of compound diode structure with Ultrafast recovery characteristic, solves existing device Part is while with high voltage, the problem of further shortening recovery time, improve switching speed, reduce switching power loss.This is specially It is sharp described after forming contact hole, the surface silicon of the N-type epitaxy layer between the area P in contact hole and the adjacent area P is carved by dry method Etching off falls, but still has the area P of certain depth remaining, forms the contact hole of the defective layer in surface carved, and forms potential barrier gold later Belong to, this structure can further decrease the recovery time of device, so that further lifting switch speed, reduces switching power loss.

It is a further object of the present invention to provide a kind of manufacturing method of compound diode structure with Ultrafast recovery characteristic, It, can be mutually compatible with prior art while realizing device architecture of the present invention.

The technical solution adopted by the present invention to solve the technical problems is:

A kind of compound diode structure with Ultrafast recovery characteristic, including N+ substrate, positioned at the metal of N+ substrate back Change cathode and the N-type epitaxy layer positioned at N+ substrate face；One group is provided in the N-type epitaxy layer to extend into N-type epitaxy layer The area P, the area P is uniformly distributed in N-type epitaxy layer；N-type epitaxy layer surface between the adjacent area P is provided with floor use etc. Gas ions bombard the defect layer that mode is formed, and are provided with a floor Schottky barrier metal, the Xiao Te in the area P and defect layer Defect interlayer on base barrier metal and N-type epitaxy layer is provided with schottky barrier junction, is provided with gold in Schottky barrier metal Categoryization anode.

Further, the chip is divided into the active area of centre and the terminal positioned at active area surrounding, and the area the P setting exists In active area.

For convenience of processing, the surface in the area P is also equipped with the defect layer that floor using plasma bombardment mode is formed.

For the material that the Schottky barrier metal uses for aluminium, nickel or nickel platinum alloy, the metallization anode can be with Xiao Special base barrier metal is same metal, can also use other metals.

The invention also discloses a kind of compound diode manufacturing method with Ultrafast recovery characteristic,

The following steps are included:

1) insulating medium layer is formed by thermal oxide or chemical vapor deposition method on the surface of N-type epitaxy layer；

2) by photoetching and wet-etching technology, selective etching goes out one group and is uniformly distributed on the insulating medium layer of active area The doping window being spaced apart from each other again；

3) using ion implantation technology by doping window carry out p type impurity doping, then by heat treatment process at Reason, so that one group of area P extended into N-type epitaxy layer is formed in N-type epitaxy layer, meanwhile, heat treatment process is also on the area P surface Grow a floor and the same or different area the P insulating medium layer of insulating medium layer；

4) by the area the P insulating medium layer in the area P in photoetching and wet-etching technology removal active area and between the adjacent area P Insulating medium layer in N-type epitaxy layer, to form metal contact hole on chip；

5) using plasma bombardment mode etches contact hole, while the N-type between the area P of active area and the adjacent area P Epi-layer surface forms defect layer；Or only the N-type epitaxy layer surface between the adjacent area P of active area forms defect layer；

6) one layer of aluminium, nickel or nickel platinum alloy are deposited as Schottky by sputtering or evaporation technology on defect layer Barrier metal, and Schottky barrier metal and the upper portion of the defect layer above N-type epitaxy layer are closed by heat treatment Gold forms schottky barrier junction, and the downside of schottky barrier junction retains a part of defect layer；

7) aluminium, titanium, nickel or silver metal are deposited or evaporated in chip surface form metallization anode；Metallizing anode can be with It is same metal with Schottky barrier metal, can also be different；

8) pass through sputtering or evaporation titanium nickeline, nickeline or titanium nickel relative to the another side of N-type epitaxy layer in N+ substrate Vanadium silver metal forms metallization cathode.

Beneficial effects of the present invention: the present invention is after contact hole is formed, by plasma bombardment mode in the area P and adjacent Defect layer is formed in N-type epitaxy layer between the area P, achievees the effect that introduce defect layer on the downside of schottky barrier junction, so as to To enhance the carrier capture rate of device when off, shorten the effect of device recovery time, so that the speed of recovery is improved, from And further lifting switch speed, reduce the power consumption of switch.Meanwhile it and can be obtained more by depth adjustment to a certain extent The excellent area P depth and spacing obtain to optimize the area accounting of PN junction diode and Schottky diode to a certain extent Smaller recovery time.In order to easy to process, while defect can also be introduced in N-type epitaxy layer between the area P, in the area P It is also introduced into defect layer.Process of the invention is simply easily achieved, also mutually compatible with common MPS diode processing technology, Equipment change is few, and processing cost is low.

Below with reference to drawings and examples, the present invention is described in detail.

Detailed description of the invention

Fig. 1 is top view of the invention.

Fig. 2 is to process the schematic diagram of insulating medium layer on N-type epitaxy layer surface in the present invention.

Fig. 3 is the schematic diagram for opening up doping window in the present invention on insulating medium layer.

Fig. 4 is to form the schematic diagram in the area P in active area in the present invention.

Fig. 5 is that the schematic diagram after contact hole is formed is etched in the present invention.

Fig. 6 a is the signal for forming the defective floor in surface in the present invention in N-type epitaxy layer between the adjacent area P of contact hole Figure.

Fig. 6 b is the formation defective floor in surface in the N-type epitaxy layer in the present invention in the area contact hole P between the adjacent area P The schematic diagram by quarter contact hole.

Fig. 7 a is the schematic diagram that Fig. 6 a forms Schottky barrier metal on the contact hole carved.

Fig. 7 b is the schematic diagram that Fig. 6 b forms Schottky barrier metal on the contact hole carved.

Fig. 7 c is the schematic diagram of the partial enlargement of A in Fig. 7 a.

Fig. 7 d is the schematic diagram of the partial enlargement of B in Fig. 7 b.

Fig. 8 a is the schematic diagram that Fig. 7 a forms metallization anode in chip surface.

Fig. 8 b is the schematic diagram that Fig. 7 b forms metallization anode in chip surface.

Fig. 9 a is the schematic diagram that Fig. 8 a forms metallization cathode in chip back.

Fig. 9 b is the schematic diagram that Fig. 8 b forms metallization cathode in chip back.

Specific embodiment