阅读说明：本技术 阵列基板和显示面板 (Array substrate and display panel ) 是由 房耸 井晓静 于 2021-08-16 设计创作，主要内容包括：一种阵列基板,包括多个呈矩阵排布的像素,各像素包括第一子像素和第二子像素,第一子像素包括第一晶体管和与第一晶体管连接的第一像素电极,第二子像素包括第二晶体管和与第二晶体管连接的第二像素电极,阵列基板还包括多条第一数据线和多条第二数据线；多个像素的奇数行中,奇数位中各像素的第一晶体管和第二晶体管均电性连接第一数据线；偶数位中各像素的第一晶体管和第二晶体管均电性连接第二数据线；多个像素的偶数行中,奇数位中各像素的第一晶体管和第二晶体管均电性连接第二数据线；偶数位中各像素的第一晶体管和第二晶体管均电性连接第一数据线。本发明提供的阵列基板能达到2dot inversion的效果,并降低功耗。本发明还涉及一种显示面板。(An array substrate comprises a plurality of pixels arranged in a matrix, each pixel comprises a first sub-pixel and a second sub-pixel, the first sub-pixel comprises a first transistor and a first pixel electrode connected with the first transistor, the second sub-pixel comprises a second transistor and a second pixel electrode connected with the second transistor, and the array substrate further comprises a plurality of first data lines and a plurality of second data lines; in the odd-numbered rows of the pixels, the first transistor and the second transistor of each pixel in the odd-numbered bits are electrically connected with the first data line; the first transistor and the second transistor of each pixel in the even-numbered positions are both electrically connected with the second data line; in even rows of the plurality of pixels, the first transistor and the second transistor of each pixel in the odd bits are electrically connected with the second data line; the first transistor and the second transistor of each pixel in the even-numbered positions are both electrically connected with the first data line. The array substrate provided by the invention can achieve the effect of 2dot inversion and reduce the power consumption. The invention also relates to a display panel.)

1. An array substrate, comprising a plurality of pixels (12) arranged in a matrix, wherein each pixel (12) comprises a first sub-pixel (121) and a second sub-pixel (122), the first sub-pixel (121) comprises a first transistor (1211) and a first pixel electrode (1212), the first transistor (1211) is connected with the first pixel electrode (1212), the second sub-pixel (122) comprises a second transistor (1221) and a second pixel electrode (1222), the second transistor (1221) is connected with the second pixel electrode (1222), and the array substrate comprises a substrate (11) and a plurality of first data lines (13) and a plurality of second data lines (14) arranged on the substrate (11);

in odd rows of the plurality of pixels (12), the first transistor (1211) and the second transistor (1221) of each of the pixels (12) located in odd bits are electrically connected to the first data line (13), respectively; the first transistor (1211) and the second transistor (1221) of each pixel (12) in even-numbered bits are electrically connected to the second data line (14), respectively;

in even rows of the plurality of pixels (12), the first transistor (1211) and the second transistor (1221) of each of the pixels (12) located in odd numbers are electrically connected to the second data line (14), respectively; the first transistor (1211) and the second transistor (1221) of each pixel (12) of even-numbered bits are electrically connected to the first data line (13), respectively.

2. The array substrate of claim 1, further comprising a plurality of touch signal lines (15), wherein each touch signal line (15) is respectively located between the adjacent first data line (13) and the second data line (14).

3. The array substrate according to claim 2, wherein the touch signal line (15) is routed between two adjacent pixels (12).

4. The array substrate of claim 3, wherein the touch signal line (15) is disposed on the same layer as the first data line (13) and the second data line (14).

5. The array substrate of claim 4, further comprising a common electrode (18), wherein the common electrode (18) is spaced apart from the first pixel electrode (1212) and the second pixel electrode (1222) up and down.

6. The array substrate of claim 5, wherein the first pixel electrode (1212) is disposed in a same layer as a source (1211a) and a drain (1211b) of the first transistor (1211); the second pixel electrode (1222) is disposed at the same layer as the source (1211a) and the drain (1211b) of the second transistor (1221).

7. The array substrate of claim 5, wherein the array substrate comprises a first insulating layer (19) covering the first transistor (1211) and the second transistor (1221) and a second insulating layer (21) covering the first insulating layer (19), wherein the common electrode (18) is disposed on the first insulating layer (19), and wherein the first pixel electrode (1212) and the second pixel electrode (1222) are disposed on the second insulating layer (21).

8. The array substrate of claim 7, further comprising a contact hole (101), wherein the contact hole (101) penetrates through the first insulating layer (19) and the second insulating layer (21), and the first pixel electrode (1212) and the second pixel electrode (1222) are electrically connected to the first transistor (1211) and the second transistor (1221) through the contact hole (101), respectively.

9. The array substrate according to claim 5, wherein a routing area (11a) is provided between each pixel in an odd-numbered row and each pixel (12) in an adjacent even-numbered row, the first data line (13), the second data line (14) and the touch signal line (15) all pass through the routing area (11a), and a region of the common electrode (18) corresponding to the routing area (11a) is provided with a groove.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.

Technical Field

The invention relates to the technical field of displays, in particular to an array substrate and a display panel.

Background

Currently, touch display panels generally include an on-cell touch display panel and an in-cell touch display panel. The embedded touch display panel is widely welcomed by the advantages of small thickness, high signal-to-noise ratio, good process compatibility and the like.

However, the embedded (in cell) touch display panel increases the number of peripheral circuits because the data lines and the touch lines are connected to the driving circuit. In addition, the conventional embedded (in-cell) touch display panel adopts a dual gate architecture, which results in large power consumption of the data lines and poor electromagnetic interference resistance of the product. Meanwhile, the conventional embedded (in-cell) touch display panel uses different layers of metal wires as touch wires, which increases the manufacturing difficulty and is not beneficial to cost reduction, and the existence of the touch wires can also reduce the opening area of pixels (pixels).

Disclosure of Invention

In view of this, the invention provides an array substrate, which not only achieves the effect of 2dot inversion, but also reduces the power consumption of the product and improves the anti-electromagnetic interference capability of the product.

An array substrate comprises a plurality of pixels arranged in a matrix, wherein each pixel comprises a first sub-pixel and a second sub-pixel, the first sub-pixel comprises a first transistor and a first pixel electrode, the first transistor is connected with the first pixel electrode, the second sub-pixel comprises a second transistor and a second pixel electrode, the second transistor is connected with the second pixel electrode, and the array substrate comprises a substrate and a plurality of first data lines and a plurality of second data lines which are arranged on the substrate;

in the odd-numbered rows of the plurality of pixels, the first transistor and the second transistor of each pixel at the odd-numbered bits are electrically connected to the first data line, respectively; the first transistor and the second transistor of each pixel of the even number position are respectively and electrically connected with the second data line;

in even rows of the plurality of pixels, the first transistor and the second transistor of each pixel at odd bits are respectively electrically connected with the second data line; the first transistor and the second transistor of each pixel of even-numbered bits are electrically connected to the first data line, respectively.

In an embodiment of the invention, the array substrate further includes a plurality of touch signal lines, and each of the touch signal lines is located between the adjacent first data line and the second data line.

In an embodiment of the invention, the touch signal line is routed between two adjacent pixels.

In an embodiment of the invention, the touch signal line is disposed on the same layer as the first data line and the second data line.

In an embodiment of the present invention, the array substrate further includes a common electrode, and the common electrode, the first pixel electrode, and the second pixel electrode are spaced from each other up and down.

In an embodiment of the invention, the first pixel electrode and the source and the drain of the first transistor are disposed in the same layer; the second pixel electrode is disposed in the same layer as the source and the drain of the second transistor.

In an embodiment of the present invention, the array substrate includes a first insulating layer covering the first transistor and the second transistor, and a second insulating layer covering the first insulating layer, the common electrode is disposed on the first insulating layer, and the first pixel electrode and the second pixel electrode are disposed on the second insulating layer.

In an embodiment of the invention, the array substrate further includes a contact hole, the contact hole penetrates through the first insulating layer and the second insulating layer, and the first pixel electrode and the second pixel electrode are electrically connected to the first transistor and the second transistor through the contact hole, respectively.

In an embodiment of the present invention, a wiring area is provided between each pixel in an odd-numbered row and each pixel in an adjacent even-numbered row, the first data line, the second data line, and the touch signal line all pass through the wiring area, and a groove is provided in a region of the common electrode located in the wiring area.

The invention also provides a display panel comprising the array substrate.

In the array substrate, in the odd-numbered rows of the plurality of pixels, the first transistor and the second transistor of each pixel at the odd-numbered position are respectively and electrically connected with the first data line; the first transistor and the second transistor of each pixel of the even number position are respectively and electrically connected with the second data line; in even rows of the plurality of pixels, the first transistor and the second transistor of each pixel at odd bits are respectively electrically connected with the second data line; the first transistor and the second transistor of each pixel of even-numbered bits are electrically connected to the first data line, respectively. Therefore, when voltages with opposite polarities are input to the adjacent first data line and the second data line, the polarities of the adjacent two first pixel electrodes are opposite; the polarities of the voltages applied to the two adjacent second pixel electrodes are opposite; the polarity of the voltage applied by the first pixel electrode is the same as that of the voltage applied by the second pixel electrode. The polarity of the first data line or the polarity of the second data line are kept consistent in the same frame, so that the effect of 2dot inversion is achieved, the power consumption of the product is reduced, and the anti-electromagnetic interference capability of the product is improved.

Drawings

Fig. 1 is a schematic partial cross-sectional view of an array substrate according to the present invention.

Fig. 2 is a partially enlarged schematic structural view of the array substrate shown in fig. 1.

Fig. 3 is a partially enlarged schematic structural view of the array substrate shown in fig. 1.

Fig. 4 is a schematic partial cross-sectional view of a display panel according to a first embodiment of the invention.

Fig. 5 is a schematic partial cross-sectional view of a display panel according to a second embodiment of the invention.

Detailed Description

In order to facilitate understanding of those skilled in the art, the present application provides a specific implementation process of the technical solution provided by the present application through the following embodiments.

First embodiment

Fig. 1 is a schematic partial cross-sectional structure view of an array substrate according to a first embodiment of the present invention, fig. 2 is a schematic partial enlarged structure view of the array substrate shown in fig. 1, fig. 3 is a schematic partial enlarged structure view of the array substrate shown in fig. 1, and fig. 4 is a schematic partial cross-sectional structure view of a display panel according to the first embodiment of the present invention, as shown in fig. 1 to 4, the first embodiment of the present invention provides an array substrate 10: the array substrate 10 comprises a plurality of pixels 12 arranged in a matrix, each pixel 12 comprises a first sub-pixel 121 and a second sub-pixel 122, the first sub-pixel 121 comprises a first transistor 1211 and a first pixel electrode 1212, the first transistor 1211 is connected with the first pixel electrode 1212, the second sub-pixel 122 comprises a second transistor 1221 and a second pixel electrode 1222, the second transistor 1221 is connected with the second pixel electrode 1222, and the array substrate 10 comprises a substrate 11 and a plurality of first data lines 13 and a plurality of second data lines 14 arranged on the substrate 11;

in the odd-numbered rows of the pixels 12, the first transistor 1211 and the second transistor 1221 of each pixel 12 located at an odd number are electrically connected to the first data line 13, respectively; the first transistor 1211 and the second transistor 1221 of each pixel 12 in the even-numbered bits are electrically connected to the second data line 14, respectively;

in the even-numbered rows of the pixels 12, the first transistor 1211 and the second transistor 1221 of each of the pixels 12 located in the odd-numbered rows are electrically connected to the second data line 14, respectively; the first transistor 1211 and the second transistor 1221 of each pixel 12 in the even-numbered bits are electrically connected to the first data line 13, respectively.

In the array substrate 10 of the present invention, as shown in fig. 1 to 3, in the odd-numbered rows of the pixels 12, the first transistor 1211 and the second transistor 1221 of each pixel 12 located at an odd-numbered position are electrically connected to the first data line 13 respectively; the first transistor 1211 and the second transistor 1221 of each pixel 12 in the even-numbered bits are electrically connected to the second data line 14, respectively; in the even-numbered rows of the pixels 12, the first transistor 1211 and the second transistor 1221 of each of the pixels 12 located in the odd-numbered rows are electrically connected to the second data line 14, respectively; the first transistor 1211 and the second transistor 1221 of each pixel 12 in the even-numbered bits are electrically connected to the first data line 13, respectively. Therefore, when voltages with opposite polarities are input to the adjacent first data line 13 and the second data line 14, the polarities of the adjacent first pixel electrodes 1212 are opposite; the polarities of the voltages applied to the adjacent second pixel electrodes 1222 are opposite; the polarity of the voltage applied to the first pixel electrode 1212 and the second pixel electrode 1222 is the same. The polarities of the first data line 13 or the second data line 14 are kept consistent in the same frame, so that the effect of 2dot inversion is achieved, the power consumption of a product is reduced, and the anti-electromagnetic interference capability of the product is improved.

Further, the material of the first data line 13 and the second data line 14 is a metal material, such as copper (Ag), silver (Ag), or aluminum (Al).

Further, the array substrate 10 further includes a plurality of touch signal lines 15, and each touch signal line 15 is respectively located between the adjacent first data line 13 and the second data line 14. In the present embodiment, the touch signal line 15 is made of a metal material, such as copper (Ag), silver (Ag), or aluminum (Al).

Further, the touch signal line 15 is disposed on the same layer as the first data line 13 and the second data line 14. In the embodiment, the touch signal line 15, the first data line 13 and the second data line 14 are in the same layer and made of the same material, and therefore, the touch signal line 15, the first data line 13 and the second data line 14 are formed by patterning (the patterning includes processes of coating photoresist, mask exposure, development, etching and the like) the same conductive film, so that the manufacturing process of the array substrate 10 is simplified, the cost is effectively reduced, and the product competitiveness is improved.

Further, the touch signal line 15 is routed between two adjacent pixels 12. In the present embodiment, the trace direction of the touch signal line 15 is the same as that of the first data line 13 and the second data line 14.

Further, as shown in fig. 1, the array substrate 10 further includes a plurality of first gate lines 16 and a plurality of second gate lines 17, the first gate lines 16 and the second gate lines 17 are respectively located at upper and lower sides of the pixels 12, the first transistor 1211 is located at a side close to the first gate line 16, and the second transistor 1221 is located at a side close to the second gate line 17. The first gate line 16 is electrically connected to the first transistor 1211, and the second gate line 17 is electrically connected to the second transistor 1221.

Further, as shown in fig. 1 to 3, the length direction of the first gate line 16 and the second gate line 17 is a first direction; the length directions of the touch signal line 15, the first data line 13 and the second data line 14 are the second direction, and the first direction and the second direction are mutually crossed. In the first direction, since the first data line 13 passes between the first subpixel 121 and the second subpixel 122 in the same pixel 12; the second data line 14 passes through a space between the first sub-pixel 121 and the second sub-pixel 122 in another pixel 12, and the touch signal line 15 passes through a space between two adjacent pixels 12; in the second direction, the touch signal line 15, the first data line 13, and the second data line 14 are disposed at an interval. Therefore, even if the first data line 13 is connected to the first pixel electrode 1212 and the second pixel electrode 1222 in the same pixel 12, the second data line 14 is connected to the first pixel electrode 1212 and the second pixel electrode 1222 in another pixel 12, and the touch signal line 15 is connected to the touch electrode; short circuit does not occur, so that the effect of 2dot inversion can be realized.

Further, as shown in fig. 1, 2 and 4, the array substrate 10 further includes a common electrode 18, and the common electrode 18 is spaced from the first pixel electrode 1212 and the second pixel electrode 1222 up and down. In this embodiment, a third insulating layer 22 is disposed on the first pixel electrode 1212, the second pixel electrode 1222, the first transistor 1211, and the second transistor 1221, and the common electrode 18 is disposed on the third insulating layer 22. In addition, the plurality of first sub-pixels 121 or the plurality of second sub-pixels 122 are provided with a corresponding common electrode 18, and the common electrodes 18 are electrically connected through the common electrode 18 lines, respectively. For example, the common electrode 18 may be disposed for each pixel 12, the common electrode 18 may be disposed for a plurality of pixels 12, or a corresponding common electrode 18 may be disposed for each first sub-pixel 121 or each second sub-pixel 122.

Further, the first pixel electrode 1212 is disposed in the same layer as the source 1211a and the drain 1211b of the first transistor 1211; the second pixel electrode 1222 is disposed at the same layer as the source 1211a and the drain 1211b of the second transistor 1221. In this embodiment, the first pixel electrode 1212 is disposed in the same layer as the source 1211a and the drain 1211b of the first transistor 1211; the second pixel electrode 1222 is disposed at the same layer as the source 1211a and the drain 1211b of the second transistor 1221, and therefore, the contact hole 101 for electrically connecting the first pixel electrode 1212 and the first transistor 1211 or electrically connecting the second pixel electrode 1222 and the second transistor 1221 is not required.

Furthermore, a wiring area 11a is formed between each pixel 12 in the odd-numbered row and each pixel 12 in the adjacent even-numbered row, the first data line 13, the second data line 14 and the touch signal line 15 all pass through the wiring area 11a, and a groove (not shown) is formed in a region of the common electrode 18 in the wiring area 11 a. In the embodiment, the routing area 11a extends along the first direction, and since the first data line 13 and the second data line 14 in the routing area 11a are close to the touch signal line 15, under the influence of the electric field, the position of the common electrode 18 corresponding to the routing area 11a needs to be dug into a groove, and the opening of the groove faces the touch signal line 15, the first data line 13 or the second data line 14, so as to reduce the coupling capacitance. Wherein the position of the groove corresponds to the black matrix pattern 323 of the display panel.

The invention further relates to a display panel comprising the array substrate 10.

Further, the display panel further includes a touch electrode electrically connected to the touch signal line 15. The touch driving signal is supplied to the touch electrode through the touch signal line 15, and the touch sensing signal is received, thereby recognizing the touch position.

Further, the touch electrode may also be formed by the common electrode 18, and correspondingly, the touch signal line 15 may also be formed by the common electrode 18, based on which, in the touch stage, the touch signal line 15 provides a touch driving signal to the touch electrode and receives a touch feedback signal; in the display stage, the touch signal line 15 provides a common signal to the touch electrode, and provides a signal required by the common electrode 18 during display. When the touch electrode is reused as the common electrode 18 and the touch signal line 15 is reused as the common electrode 18, the thickness of the array substrate 10 is reduced, and when the array substrate 10 is applied to a touch display panel, the thickness of the touch display panel is reduced.

Further, the touch electrode may include a plurality of touch sub-electrodes for a plurality of pixels 12 on the array substrate 10. In the present embodiment, each pixel 12 may be provided with a touch sub-electrode; or, a touch sub-electrode may be disposed in a part of the pixels 12, and no touch sub-electrode may be disposed in a part of the pixels 12. In addition, one touch electrode is electrically connected to a plurality of touch signal lines 15.

Further, the display panel includes an array substrate 10 and a color filter substrate 30 which are oppositely disposed, and a liquid crystal layer 40 disposed between the array substrate 10 and the color filter substrate 30. The array substrate 10 and the color film substrate 30 are adhered together by frame sealing glue, so that the liquid crystal layer 40 is limited in the area enclosed by the frame sealing glue.

Further, the color filter substrate 30 further includes a substrate 31 and a color filter layer 32 disposed on the substrate 31, where the color filter layer 32 includes a red photoresist unit 321, a green photoresist unit 322, and a blue photoresist unit 323. The red photoresist units 321, the green photoresist units 322, and the blue photoresist units are periodically arranged along a first direction, and the red photoresist units 321, the green photoresist units 322, and the blue photoresist units are arranged in rows along a second direction. Meanwhile, the red photoresist unit 321, the green photoresist unit 322 and the blue photoresist unit are respectively aligned with the first sub-pixel 121 or the second sub-pixel 122 on the array substrate 10 one by one, and projections of the aligned sub-pixels on the substrate 31 along the thickness direction of the display panel are overlapped.

Further, in order to avoid crosstalk between light emitted from two adjacent first sub-pixels 121, two adjacent second sub-pixels 122, or between the first sub-pixels 121 and the second sub-pixels 122, the color film substrate 30 may further include a Black Matrix pattern 323(Black Matrix, abbreviated as BM). For example, the black matrix pattern 323 includes a plurality of parallel first light-shielding bars and a plurality of parallel second light-shielding bars, and a plurality of grids formed by the plurality of first light-shielding bars and the plurality of second light-shielding bars, where an area formed by each grid is an area where one first sub-pixel 121 or one second sub-pixel 122 is located. In this embodiment, the orthographic projections of the first data lines 13, the second data lines 14 and the touch signal lines 15 on the color film substrate 30 are located on the first light-shielding strips and/or the second light-shielding strips.

Further, the color filter substrate 30 further includes a planarization layer 33, and the planarization layer 33 is disposed on the color filter layer 32 and is close to the liquid crystal layer 40.

Second embodiment

Fig. 1 is a schematic partial cross-sectional structure of an array substrate according to the present invention, fig. 2 is a schematic partial enlarged structure of the array substrate shown in fig. 1, fig. 3 is a schematic partial enlarged structure of the array substrate shown in fig. 1, and fig. 5 is a schematic partial cross-sectional structure of a display panel according to a second embodiment of the present invention, referring to fig. 1 to 3 and 5, the array substrate according to the second embodiment of the present invention is substantially the same as the array substrate according to the first embodiment, except that in this embodiment, the relative positions of a common electrode, a first pixel electrode, and a second pixel electrode are different.

Further, the array substrate 10 further includes a common electrode 18, and the common electrode 18 is spaced from the first pixel electrode 1212 and the second pixel electrode 1222 vertically. In the present embodiment, the plurality of first sub-pixels 121 or the plurality of second sub-pixels 122 are provided with a corresponding common electrode 18, and the common electrodes 18 are electrically connected through the common electrode 18 line respectively. For example, the common electrode 18 may be disposed for each pixel 12, the common electrode 18 may be disposed for a plurality of pixels 12, or a corresponding common electrode 18 may be disposed for each first sub-pixel 121 or each second sub-pixel 122.

Further, the array substrate 10 includes a first insulating layer 19 covering the first and second transistors 1211 and 1221 and a second insulating layer 21 covering the first insulating layer 19, the common electrode 18 is disposed on the first insulating layer 19, and the first and second pixel electrodes 1212 and 1222 are disposed on the second insulating layer 21.

Further, the array substrate 10 further includes a contact hole 101, the contact hole 101 penetrates through the first insulating layer 19 and the second insulating layer 21, and the first pixel electrode 1212 and the second pixel electrode 1222 are electrically connected to the first transistor 1211 and the second transistor 1221 through the contact hole 101, respectively.

For other structures of the array substrate 10, please refer to the first embodiment, which will not be described herein.

Third embodiment

The array substrate provided by the third embodiment of the present invention is substantially the same as the array substrate in the first embodiment, except that in this embodiment, the relative positions of the touch signal line, the first data line and the second data line are different.

Further, the touch signal line 15, the first data line 13, and the second data line 14 are disposed at different layers, that is, the touch signal line 15, the first data line 13, and the second data line 14 are formed by patterning different conductive films, respectively. In the present embodiment, the touch signal line 15 may be in the same layer as any metal layer except the first data line 13 and the second data line 14, for example, the touch signal line 15 may be in the same layer as the gate 34. Since the touch signal line 15 and the first data line 13 or the second data line 14 are disposed at different layers, the influence of an electric field between the touch signal line 15 and the first data line 13 or the second data line 14 can be reduced; moreover, when the orthographic projection of the touch signal line 15 on the substrate 11 is overlapped with the orthographic projection of the first data line 13 or the second data line 14 on the substrate 11, the aperture ratio can be improved.

Further, the touch signal line 15 coincides with an orthographic projection of the first data line 13 or the second data line 14 on the array substrate 10.

For other structures of the array substrate 10, please refer to the first embodiment, which will not be described herein.

In this document, the terms of upper, lower, left, right, front, rear and the like are used to define the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the sake of clarity and convenience in technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It is also to be understood that the terms "first" and "second," etc., are used herein for descriptive purposes only and are not to be construed as limiting in number or order.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.