阅读说明：本技术 显示装置及其阵列基板 (Display device and array substrate thereof ) 是由 檀小芳 宋志伟 袁继旺 何伟 于 2021-08-03 设计创作，主要内容包括：本申请实施例公开了一种显示装置及其阵列基板,其中,阵列基板包括绝缘层、钝化层以及导电层。所述钝化层设置于所述绝缘层的一侧,其朝向所述绝缘层的一侧开设有容纳槽。所述导电层容置于所述容纳槽中,其两侧面分别与所述绝缘层和所述钝化层接触。所述导电层包括相互电连接的源极、漏极以及导电块,所述导电块上开设有多个通孔,所述通孔的两侧开口分别朝向所述绝缘层和所述钝化层,所述通孔的内侧面呈平滑曲面。所述绝缘层在烘烤加工过程中产生的气体可通过所述通孔排出阵列基板,解决了现有技术中阵列基板容易产生鼓包的技术问题,提高了屏幕模组的阵列基板加工的良品率,降低了屏幕模组的生产成本。(The embodiment of the application discloses a display device and an array substrate thereof, wherein the array substrate comprises an insulating layer, a passivation layer and a conducting layer. The passivation layer is arranged on one side of the insulating layer, and an accommodating groove is formed in one side of the passivation layer, which faces the insulating layer. The conducting layer is accommodated in the accommodating groove, and two side faces of the conducting layer are respectively contacted with the insulating layer and the passivation layer. The conducting layer comprises a source electrode, a drain electrode and a conducting block which are electrically connected with each other, a plurality of through holes are formed in the conducting block, openings on two sides of each through hole respectively face the insulating layer and the passivation layer, and the inner side surfaces of the through holes are smooth curved surfaces. The gas accessible that the insulating layer produced in the baking course of working through-hole discharge array substrate has solved the technical problem that array substrate easily produces the swell among the prior art, has improved the yields of the array substrate processing of screen module, has reduced the manufacturing cost of screen module.)

1. An array substrate, comprising:

an insulating layer;

the passivation layer is arranged on one side of the insulating layer, and an accommodating groove is formed in one side of the passivation layer, which faces the insulating layer;

the conducting layer is accommodated in the accommodating groove, and two side faces of the conducting layer are respectively contacted with the insulating layer and the passivation layer; the conducting layer comprises a source electrode, a drain electrode and a conducting block which are electrically connected with each other, a plurality of through holes are formed in the conducting block, openings on two sides of each through hole respectively face the insulating layer and the passivation layer, and the inner side surfaces of the through holes are smooth curved surfaces.

2. The array substrate of claim 1, wherein the through holes are arranged in a multi-column rectangular array on the conductive block.

3. The array substrate of claim 1, wherein the through holes are arranged in a multi-turn annular array on the conductive block.

4. The array substrate of any of claims 1 to 3, wherein the minimum distance between the edges of two through holes is not less than 100 μm.

5. The array substrate of any of claims 1 to 3, wherein the through holes comprise circular holes, and the diameter of the through holes is between 100 microns and 150 microns.

6. The array substrate of any of claims 1 to 3, wherein the through holes comprise rounded rectangular holes, and the length of the long side of the through holes is between 100 and 150 microns.

7. The array substrate of claim 1, wherein the through-hole comprises a plurality of nested holes, the nested holes comprising a central annular hole and a peripheral annular hole surrounding the central annular hole.

8. The array substrate of claim 7, wherein the central annular hole and the peripheral annular hole divide the conductive block into a plurality of annular portions nested with each other, and a connecting rib is disposed between two adjacent annular portions.

9. The array substrate of claim 7, wherein the through-hole further comprises a circular hole disposed around the nested hole.

10. The array substrate of claim 1, wherein the opening of the via hole on the side facing the insulating layer is a first opening, the opening of the via hole on the side facing the passivation layer is a second opening, and a diameter of the first opening is larger than a diameter of the second opening.

11. A display device comprising the array substrate according to any one of claims 1 to 10.

Technical Field

The application relates to the field of display, in particular to a display device and an array substrate thereof.

Background

With the development of display screen technology, more and more electronic devices use various screen modules. However, in the current process of manufacturing the screen module, the array substrate needs to be baked at a high temperature. During the baking process, the array substrate generates volatile gas. If the volatile gas cannot be discharged out of the array substrate in time, the array substrate may bulge, which may cause product abnormality.

Disclosure of Invention

The embodiment of the application provides a display device and an array substrate thereof, which can solve the technical problem that the array substrate is easy to bulge in the prior art.

The embodiment of the application provides an array substrate, which comprises an insulating layer, a passivation layer and a conducting layer. The passivation layer is arranged on one side of the insulating layer, and an accommodating groove is formed in one side of the passivation layer, which faces the insulating layer; the conducting layer is accommodated in the accommodating groove, and two side faces of the conducting layer are respectively contacted with the insulating layer and the passivation layer; the conducting layer comprises a source electrode, a drain electrode and a conducting block which are electrically connected with each other, a plurality of through holes are formed in the conducting block, openings on two sides of each through hole respectively face the insulating layer and the passivation layer, and the inner side surfaces of the through holes are smooth curved surfaces.

Optionally, in some embodiments of the present application, the through holes are arranged in a multi-column rectangular array on the conductive block.

Optionally, in some embodiments of the present application, the through holes are arranged in a multi-turn annular array on the conductive block.

Optionally, in some embodiments of the present application, a minimum distance between two edges of the through hole is not less than 100 micrometers.

Optionally, in some embodiments of the present application, the through holes comprise circular holes, and the diameter of the through holes is between 100 micrometers and 150 micrometers.

Optionally, in some embodiments of the present application, the through-hole comprises a rounded rectangular hole, and the length of the long side of the through-hole is between 100 micrometers and 150 micrometers.

Optionally, in some embodiments of the present application, the through-hole comprises a multi-layer nested hole, the nested hole comprising a central annular hole and a peripheral annular hole surrounding the central annular hole.

Optionally, in some embodiments of the present application, the central annular hole and the peripheral annular hole divide the conductive block into a plurality of annular portions nested with each other, and a connecting rib is disposed between two adjacent annular portions.

Optionally, in some embodiments of the present application, the through hole further includes a circular hole disposed around the nesting hole.

Optionally, in some embodiments of the present application, an opening of the through hole facing the insulating layer is a first opening, an opening of the through hole facing the passivation layer is a second opening, and a diameter of the first opening is larger than a diameter of the second opening.

Correspondingly, the embodiment of the application also provides a display device, which comprises the array substrate.

In the embodiment of the application, through set up a plurality of through-holes on the conducting block of array substrate's conducting layer, with the gas outgoing array substrate that the insulating layer produced in the baking process, solved among the prior art array substrate and produced the technical problem of swell easily, improved the yields of the array substrate processing of screen module, reduced the manufacturing cost of screen module. Meanwhile, the inner side surface of the through hole is a smooth curved surface, so that the problem of point discharge caused by sharp corners at the edge of the through hole can be avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of a screen module of the display device shown in fig. 1 of the present application.

Fig. 3 is a schematic structural diagram of a peripheral region of the array substrate of the screen module shown in fig. 2 of the present application.

Fig. 4 is a schematic structural diagram of an operable area of the array substrate of the screen module shown in fig. 2 of the present application.

Fig. 5 is a partial structural schematic diagram of an embodiment of the array substrate shown in fig. 3-4 of the present application.

Fig. 6 is a partial structural schematic view of another embodiment of the array substrate shown in fig. 3-4 of the present application.

Fig. 7 is a top view of a first embodiment of a conductive block of the array substrate shown in fig. 3-4 of the present application.

Fig. 8 is a partial structural diagram of a second embodiment of the conductive block of the array substrate shown in fig. 3-4 of the present application.

Fig. 9 is a partial structural diagram of a third embodiment of a conductive block of the array substrate shown in fig. 3 to 4 of the present application.

Fig. 10 is a top view of a fourth embodiment of a conductive block of the array substrate shown in fig. 3-4.

Fig. 11 is a top view of a fifth embodiment of a conductive block of the array substrate shown in fig. 3-4 of the present application.

Fig. 12 is a cross-sectional view of the array substrate shown in fig. 11 of the present application.

Fig. 13 is a plan view of a sixth embodiment of a conductive block of the array substrate shown in fig. 3 to 4 of the present application.

Fig. 14 is a cross-sectional view of the array substrate shown in fig. 13 of the present application.

Fig. 15 is a plan view of a seventh embodiment of a conductive block of the array substrate shown in fig. 3 to 4 of the present application.

Description of reference numerals:

1. a housing; 2. a screen module; 21. an array substrate; 22. a control unit; 100. a light transmitting layer; 200. a buffer layer; 300. an insulating layer; 400. a passivation layer; 500. a conductive layer; 600. a gate layer; 700. an isolation layer; 800. an IGZO layer; 900. a light-shielding layer; 410. accommodating grooves; 510. a source electrode; 520. a drain electrode; 530. a conductive block; 531. a through hole; 5311. a first opening; 5312. a second opening; 5313. a circular hole; 5314. an elliptical hole; 5315. a round-corner rectangular hole; 5316. a rounded square hole; 5317. embedding a sleeve hole; 5318. an annular portion; 5319. connecting ribs; 53171. a central annular aperture; 53172. a peripheral annular aperture.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.

The embodiment of the application provides a display device and an array substrate 21 thereof. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.

The present application provides a display device that can be mounted in various products having a display function. For example, the electronic product may be a smart terminal, a notebook computer, a photographing apparatus, a wearable apparatus, an electronic scale, a vehicle-mounted display, a television, and the like.

Referring to fig. 1 and 2, the display device includes a housing 1 and a screen module 2 installed in the housing 1, the screen module 2 includes an array substrate 21 and a control unit 22 electrically connected to the array substrate 21, and the control unit 22 is used for controlling the array substrate 21 to display. The screen module 2 can be various types of screen modules, and in the embodiment, an Indium Gallium Zinc Oxide (IGZO) screen module is taken as an example for description.

Referring to fig. 3 and 4, the array substrate 21 includes a light-transmitting layer 100, a buffer layer 200, an insulating layer 300, a passivation layer 400, a conductive layer 500, a gate layer 600, an isolation layer 700, an IGZO layer 800, and a light-shielding layer 900.

In the peripheral region of the array substrate 21, the light-transmitting layer 100, the buffer layer 200, the insulating layer 300, and the passivation layer 400 are sequentially stacked, one side of the passivation layer 400 facing the insulating layer 300 is provided with an accommodating groove 410, the accommodating groove 410 accommodates the conductive layer 500, and two side surfaces of the conductive layer 500 are respectively in contact with the insulating layer 300 and the passivation layer 400.

In the operable region of the array substrate 21, the light transmissive layer 100, the buffer layer 200, the insulating layer 300, and the passivation layer 400 are sequentially stacked, and the light shielding layer 900 is disposed in the buffer layer 200 and attached to the light transmissive layer 100. The gate layer 600, the isolation layer 700, and the IGZO layer 800 are sequentially stacked and disposed in the insulating layer 300. Wherein, IGZO layer 800 is also attached to the buffer layer.

The transparent layer 100 is generally made of a wear-resistant and scratch-resistant transparent material such as glass, and is disposed on the outermost layer of the array substrate 21 for protecting the array substrate 21 and transmitting video signals generated in the array substrate 21.

The buffer layer 200 is generally made of a material such as a silicon nitride compound or a silicon oxy compound to separate the light-shielding layer 900 from the IGZO layer 800.

The insulating layer 300 is generally made of an organic photoresist material such as polyimide, so as to ensure that the flatness and surface roughness of the surface of the array substrate 21 away from the light-transmitting layer 100 meet high requirements, and serve as a base material for carrying electronic elements and circuits in the conductive layer 500, the gate layer 600, the isolation layer 700, and the IGZO layer 800.

The passivation layer 400 is generally made of a material such as silicon nitride or silicon oxide to isolate the conductive layer 500 from the outside and to provide a certain insulation against oxygen and water.

The gate layer 600 is typically made of a conductive metal material and mainly includes a gate electrode located in the operable region of the array substrate 21.

The isolation layer 700 is typically made of a material such as a silicon nitride compound or a silicon oxide compound to separate the gate layer 600 and the IGZO layer 800.

The IGZO layer 800 is generally made of IGZO, and mainly includes a thin film liquid crystal tube for driving a screen within an operable area of the array substrate 21.

The light-shielding layer 900 is generally made of an opaque metal material, and may also be made of an opaque organic insulating material such as resin, and an opaque inorganic insulating material such as chrome molybdenum oxide, and is mainly used for shielding light, preventing a display area from being reduced, and improving display quality.

The conductive layer 500 is generally made of a conductive material, and includes a source electrode 510, a drain electrode 520, and a conductive bump 530 electrically connected to each other. The source electrode 510 and the drain electrode 520 are located in an operable region of the array substrate 21, wherein a plurality of source electrode protrusions are further disposed on a surface of the source electrode 510 attached to the insulating layer 300, and the source electrode protrusions are attached to and connected to the IGZO layer 800 and the light-shielding layer 900. A plurality of drain protrusions are further disposed on the surface of the drain 520 attached to the insulating layer 300, and the drain protrusions extend through the insulating layer 300 toward the light-transmitting layer 100 and are attached to the IGZO layer 800.

Referring to fig. 5, the conductive block 530 is located in the peripheral region of the array substrate 21, and has a thickness and a height greater than those of the source 510 and the drain 520, and other elements and circuits located on the conductive layer 500, and is mainly used for measuring electrical properties of the circuit or measuring impedance of the circuit. The conductive block 530 is provided with a plurality of through holes 531, and the inner side surfaces of the through holes 531 are smooth curved surfaces, so that the problem of point discharge generated at the edges of the through holes 531 due to sharp corners is avoided. The two sides of the through hole 531 are opened towards the insulating layer 300 and the passivation layer 400, respectively, wherein the opening of the through hole 531 towards the insulating layer 300 is a first opening 5311, and the opening of the through hole 531 towards the passivation layer 400 is a second opening 5312.

In the process of manufacturing the array substrate, the insulating layer 300 is generally formed on the buffer layer 200, the conductive layer 500 is mounted on the insulating layer 300, and the passivation layer 400 is formed. The passivation layer 400 is formed at 285-295 deg.c, and the insulating layer 300 generates a large amount of volatile gas by baking at high temperature. Since the buffer layer 200 and the passivation layer 400 are made of a material such as a silicon nitride compound or a silicon oxy compound, and have many fine pores in their inner structures, volatile gas can be emitted from the fine pores in the contact region of the insulating layer 300 with the buffer layer 200 and the passivation layer 400. In the contact area between the insulating layer 300 and the conductive bump 530, the volatile gas can be emitted from the through hole 531 and the micro-apertures of the passivation layer 400. The problem that the array substrate bulges due to the fact that a large amount of volatile gas is gathered between the insulating layer 300 and the conducting block 530 can be avoided, the yield of the array substrate 21 is improved, production efficiency is improved, and production cost is reduced.

Referring to fig. 6, in some embodiments of the present invention, the diameter of the first opening 5311 is larger than the diameter of the second opening 5312 to increase the gas discharging speed and increase the gas discharging efficiency.

In an embodiment of the present application, please refer to fig. 7 to 10 in combination, the through holes 531 may include circular holes 5313, elliptical holes 5314, rounded rectangular holes 5315, nesting holes 5317, and combinations thereof. The major axis length of the elliptical holes 5314 is between 100 microns and 150 microns, and the major axis length of the rounded rectangular holes 5315 is between 100 microns and 150 microns, so that gas cannot be smoothly discharged due to too small aperture, and the performance of the conductive block 530 is prevented from being influenced due to too large aperture. Meanwhile, as can be seen from the long axis length of the elliptical holes 5314, the diameter of the circular holes 5313 is between 100 microns and 150 microns; from the above-mentioned long sides of the rounded rectangular aperture 5315, the rounded rectangular aperture 5316 has a side length of 100 to 150 μm.

In some embodiments of the present application, please continue to refer to fig. 7, the through hole 531 only includes circular holes 5313, and the circular holes 5313 are arranged in a multi-turn circular array. The circular hole 5313 is easy to machine and has a small air resistance, and it is easier to discharge gas. Meanwhile, the through holes 531 are arranged more densely in a multi-circle annular array, the area of the holes in unit area is relatively larger, and the gas discharge efficiency is improved.

In other embodiments of the present application, please refer to fig. 10 in combination, the through holes 531 only include rounded square holes 5316, and the rounded square holes 5316 are arranged in a multi-column rectangular array. The open area of the rounded square holes 5316 is larger than that of the circular holes 5313 per unit area, so that the gas discharge efficiency can be higher. Meanwhile, the through holes 531 are arranged more uniformly in a multi-column rectangular array, and are easier to machine and mold. Meanwhile, the through holes 531 arranged in a multi-row rectangular array can be processed in rows, so that the processing and forming time of the through holes 531 can be greatly shortened, and the yield in unit time is improved. Moreover, in practical applications, the screen module 2 generally has a rectangular structure, so the conductive blocks 530 also have a corresponding rectangular structure, and are arranged in a multi-column rectangular array and are more adaptive to the rectangular structure of the conductive blocks 530.

In the above embodiment, the minimum distance between the edges of the two through holes 531 is not less than 100 μm. In embodiments where through holes 531 are circular holes 5313, the hole pitch of two circular holes 5313 is between 200 microns and 250 microns; in embodiments where the through holes 531 are rounded square holes 5316, the hole pitch of the two rounded square holes 5316 is also between 200 microns and 250 microns. The distance between the two through holes 531 is the distance between the centers of the two through holes 531, and when the minimum distance between the edges of the two through holes 531 is less than 100 micrometers, the through holes 531 are arranged too densely, so that the difficulty in processing the through holes 531 is greatly improved, and the normal functions of the conductive block 530 are affected. When the hole pitch between the two through holes 531 is greater than 250 μm, the arrangement of the holes is too sparse, resulting in too low exhaust efficiency.

In some embodiments of the present application, please refer to fig. 11 and 12 in combination, the through hole 531 includes a plurality of nesting holes 5317, the nesting holes 5317 include a central annular hole 53171 and a plurality of peripheral annular holes 53172 surrounding the central annular hole 53171, and the central annular hole 53171 and the peripheral annular holes 53172 divide the conductive block 530 into a plurality of annular portions 5318 nested in each other. The minimum distance between the outer edge of the central annular aperture 53171 and the adjacent peripheral annular aperture 53172 is greater than 100 microns, in this embodiment 100 microns. The minimum distance between the edges of two adjacent peripheral annular holes 53172 is also not less than 100 microns, and in this embodiment is 100 microns. The area of the single-layer nested holes 5317 is larger than that of the single circular hole 5313 and the single round-angle rectangular hole 5315, so that the volatile gas generated when the insulating layer 300 is baked can be discharged in time. Meanwhile, the number of the nesting holes 5317 is smaller than that of the circular holes 5313 and the round-corner rectangular holes 5315, the processing time is shorter, and the cost is lower.

In the present embodiment, please refer to fig. 13 and 14, a connecting rib 5319 is disposed between two adjacent annular portions 5318. The tie ribs 5319 are located in the central annular aperture 53171 and the peripheral annular aperture 53172 and have a thickness no greater than the thickness of each annular portion 5318 itself. When the thickness of the connecting ribs 5319 is equal to the thickness of each annular portion 5318, it divides the central annular hole 53171 and the peripheral annular hole 53172 into a plurality of fan-shaped regions. The annular portions 5318 are not connected to each other due to the centered annular hole 53171 and the peripheral annular hole 53172. Resulting in difficulty in mounting the conductive bumps 530 on the insulating layer 300 after the process is completed. In this embodiment, the connecting ribs 5319 are arranged to successfully connect the annular portions 5318 that are not connected to each other into a whole, so that the difficulty in mounting the conductive block 530 is reduced, and the coaxiality between the annular portions 5318 is improved.

In the present embodiment, referring to fig. 15, the through hole 531 includes a circular hole 5313 surrounding the nesting hole 5317 in addition to the multi-layer nesting hole 5317. In practical applications, the screen module 2 is generally rectangular, and the conductive block 530 is also rectangular accordingly. If the through hole 531 includes only the multi-layer nesting holes 5317, there are no open areas at the four corners of the conductive block 530. In this embodiment, the circular holes 5313 are further formed around the nesting holes 5317, so that the four corners of the conductive block 530 are also provided with the through holes 531, and the situation that the volatile gas is deposited at the four corners of the conductive block 530 to cause the four corners of the conductive block 530 to bulge is avoided.

The display device and the array substrate 21 thereof provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments above is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.