阅读说明：本技术 半导体存储装置及快闪存储器运行方法 (Semiconductor memory device and flash memory operation method ) 是由 须藤直昭 于 2020-05-26 设计创作，主要内容包括：本发明提供一种快闪存储器等半导体存储装置及快闪存储器运行方法,所述半导体存储装置,其可自动解除深度省电模式。本发明的半导体存储装置包含：标准命令I/F电路及DPD控制器,通过外部电源电压而运行；以及内部电路,通过从电压供给节点供给的内部电压而运行。DPD控制器在对标准命令I/F电路输入了标准命令时,检测是否为DPD模式,在检测到DPD模式的情况下,使内部电路从DPD模式恢复。在内部电路恢复后,执行标准命令。(The invention provides a semiconductor storage device such as a flash memory and a flash memory operation method, wherein the semiconductor storage device can automatically release a deep power saving mode. The semiconductor memory device of the present invention includes: a standard command I/F circuit and a DPD controller operated by an external power supply voltage; and an internal circuit operated by an internal voltage supplied from the voltage supply node. The DPD controller detects whether the DPD mode is present when a standard command is input to the standard command I/F circuit, and restores the internal circuit from the DPD mode when the DPD mode is detected. After the internal circuitry is restored, the standard command is executed.)

1. A flash memory operation method, comprising:

detecting whether the normal command is a deep power saving mode in which power supply to a specific circuit is blocked when a normal command including reading, programming, or erasing is input;

a step of releasing a deep power saving mode when the deep power saving mode is detected; and

executing the standard command after the specific circuit is recovered.

2. The flash memory operation method of claim 1,

in the case where the deep power saving mode is not detected, the input standard command is executed without releasing the deep power saving mode.

3. The flash memory operation method of claim 1,

the step of deactivating restores the particular circuit selected according to the type of standard command.

4. The flash memory operation method of claim 1,

the step of releasing comprises: turning on a switching transistor connected between a power supply voltage and the specific circuit.

5. The flash memory operation method of claim 1,

the deep power saving mode jumps from the standby mode and further reduces the power consumption of the standby mode.

6. A semiconductor memory device, comprising:

a peripheral circuit;

a detection unit that detects whether or not a deep power saving mode is a mode in which power supply to one or more specific circuits of the peripheral circuits is blocked when a standard command including read, program, or erase is externally input;

a release unit that releases the deep power saving mode when the deep power saving mode is detected; and

and an execution unit configured to execute the standard command after the specific circuit is restored.

7. The semiconductor memory device according to claim 6,

in a case where the deep power saving mode is not detected, the standard command is executed without releasing the deep power saving mode by the release means.

8. The semiconductor memory device according to claim 6,

the release section restores a specific circuit selected according to the kind of the standard command.

9. The semiconductor memory device according to claim 6,

the release unit includes a plurality of switching transistors respectively connected between an external power supply voltage and a plurality of specific circuits, and turns on any one of the plurality of transistors.

10. The semiconductor storage device according to any one of claims 6 to 9,

the semiconductor memory device is a flash memory.

Technical Field

The present invention relates to a semiconductor memory device such as a flash memory and a flash memory operation method, and more particularly, to an operation in a standby mode or a deep power saving mode.

Background

A NAND (Not AND, NAND) type flash memory (flash memory) can be read or programmed in units of pages AND erased in units of blocks. The flash memory disclosed in patent document 1 includes: in a standby-by mode and a normal operation mode, different power supply voltages are supplied to a page buffer/read out circuit, thereby reducing power consumption in the standby mode.

[ Prior art documents ]

[ patent document ]

[ patent document 1] Japanese patent application laid-open No. 2006-252748

Disclosure of Invention

[ problems to be solved by the invention ]

The flash memory has an active mode for reading, programming, erasing, etc. in response to a command from a user, and a standby mode for accepting a command from a user. In the standby mode, the operation of the internal circuit is restricted so that the power consumption is not more than a certain level, but when a command is input from the user, the command must be immediately responded to. Therefore, even in the standby mode, a shoot-through current (off-leak current) is generated in a volatile circuit such as a logic circuit or a register (register), the shoot-through current increases with the reduction in the size of the element, and when an internal power supply voltage is used, the internal power supply voltage detection circuit must be operated to consume a certain amount of power. That is, it is difficult to reduce the current consumption in the standby mode.

In order to further reduce power consumption in the standby mode, a deep power-down mode (hereinafter referred to as a DPD mode) may be mounted depending on the flash memory. In the DPD mode, power supply to a part of internal circuits used in the standby mode is stopped, and a power leakage current is reduced. The DPD mode is entered into the mode by a DPD start command, for example, and is recovered from the mode by a DPD release command. While recovery from the DPD mode requires a certain time to normally operate the shutdown circuit, it has an advantage that power consumption can be significantly reduced.

Fig. 1A shows an example of an operation waveform when a NAND flash memory having a Serial Peripheral Interface (SPI) function jumps to a DPD mode. In the standby mode, the flash memory is selected by setting the chip select signal/CS to low level, and a dpd command is input from the data input terminal DI in synchronization with a clock signal during this period (B9 h). Flash memory at time T when a certain period tDP has elapsed since the DPD command was input_DPDJump to DPD mode, block to specialThe internal circuit of (2) supplies a voltage. Time T_DPDIn the previous period, the current of the standby mode is consumed, and the time T_DPDIn the subsequent period, the current of the DPD mode is consumed.

Fig. 1B shows an example of an operating waveform when the DPD mode is restored. In the standby mode, the flash memory is selected by setting the chip select signal/CS to low level, and a DPD release command for releasing the DPD mode is inputted from the data input terminal DI in synchronization with the clock signal during this period (ABh). The flash memory supplies power to the internal circuit that is turned off during the period of tRES from the input of the DPD release command, and at time T_STAnd the state of the internal circuit is recovered to be in normal operation. At time T_STPreviously, consuming the current of DPD mode at time T_STThereafter, the current of the standby mode is consumed.

Fig. 2 is an internal block diagram of a NAND-type flash memory supporting a DPD mode. The flash memory 10 includes a DPD controller 20, a memory cell array (memory cell array)30, a row decoder 40, a page buffer/readout circuit 50, peripheral circuits 60, and a high voltage circuit 70. An external power supply voltage (e.g., 3.3V) VCC is supplied to the flash memory 10, and the DPD controller 20 operates directly using the external power supply voltage VCC. A P-channel Metal Oxide Semiconductor (PMOS) transistor P is connected between the external power supply voltage VCC and the internal circuit, and a DPD enable signal DPDEN is applied to a gate of the transistor P. In the active mode and the standby mode, the DPD controller 20 generates a DPD enable signal DPDEN of an L level to turn on the transistor P. Thus, the internal voltage VDD is supplied to each internal circuit via the voltage supply node INTVDD. In the DPD mode, the DPD controller 20 generates a DPD enable signal DPDEN of H level to turn off the transistor P. Thus, the supply of the external power supply voltage VCC is stopped, and the operation of the internal circuit is stopped.

In the case of releasing the DPD mode, as shown in fig. 1B, the user inputs a DPD release command from the outside (ABh). In response to the input of the DPD release command, the DPD controller 20 transits the DPD enable signal DPDEN to L level, turns on the transistor P, and starts to supply power from the external power supply voltage VCC to the internal circuits. Thus, the internal circuit is restored to an operable state after the period tRES.

As described above, in the conventional flash memory, in order to use the DPD mode, the user must input not only the DPD command but also the DPD release command, and there is a problem that the DPD mode cannot be used in the flash memory controller which does not support the DPD command and the DPD release command.

The present invention has been made to solve the above conventional problems, and an object of the present invention is to provide a semiconductor memory device capable of releasing a deep power saving mode without requiring a dedicated command for releasing the deep power saving mode.

[ means for solving problems ]

The operation method of the flash memory comprises the following steps: detecting whether the normal command is a deep power saving mode in which power supply to a specific circuit is blocked when a normal command including reading, programming, or erasing is input; a step of releasing a deep power saving mode when the deep power saving mode is detected; and executing the standard command after the specific circuit is restored.

In one embodiment of the flash memory according to the present invention, when the deep power saving mode is not detected, the input standard command is executed without releasing the deep power saving mode. In one embodiment of the flash memory according to the present invention, the step of releasing restores a specific circuit selected according to a kind of the standard command. In one embodiment of the flash memory of the present invention, the releasing step comprises: turning on a switching transistor connected between a power supply voltage and the specific circuit. In one embodiment of the flash memory of the present invention, the deep power saving mode jumps from the standby mode, and further reduces the power consumption of the standby mode.

The semiconductor memory device of the present invention includes: a peripheral circuit; a detection unit that detects whether or not a deep power saving mode is a mode in which power supply to one or more specific circuits of the peripheral circuits is blocked when a standard command including read, program, or erase is externally input; a release unit that releases the deep power saving mode when the deep power saving mode is detected; and an execution unit that executes the standard command after the specific circuit is restored.

In one embodiment of the semiconductor memory device according to the present invention, when the deep power saving mode is not detected, the release means does not release the deep power saving mode and executes the standard command. In one embodiment of the semiconductor memory device of the present invention, the release unit restores a specific circuit selected according to a type of the standard command. In one embodiment of the semiconductor memory device of the present invention, the release means includes a plurality of switching transistors respectively connected between an external power supply voltage and a plurality of specific circuits, and the release means turns on any one of the plurality of transistors. In one embodiment of the semiconductor memory device of the present invention, the semiconductor memory device is a flash memory.

[ Effect of the invention ]

According to the present invention, the deep power saving mode can be released in response to the input of the standard command without a dedicated command for releasing the deep power saving mode, and the input standard command can be rapidly executed.

Drawings

Fig. 1A is a diagram showing an example of an operation waveform when jumping to the DPD mode in a conventional flash memory;

FIG. 1B is a diagram showing an example of an operation waveform when a conventional flash memory releases a DPD mode;

fig. 2 is a diagram showing an internal configuration of a conventional flash memory;

FIG. 3 is a diagram showing the internal configuration of a flash memory according to an embodiment of the present invention;

fig. 4 is a flowchart showing a release order of the DPD mode according to an embodiment of the present invention;

FIG. 5 is a table showing the relationship between the normal command and the restored voltage supply node and the restoration time according to another embodiment of the present invention.

[ description of symbols ]

10. 100, and (2) a step of: flash memory

20. 120: DPD controller

30. 130, 130: memory cell array

40: row decoder

50: page buffer/read-out circuit

60. 160, 170: peripheral circuit

70: high voltage circuit

110: standard command I/F circuit

140: row decoder (peripheral circuit)

150: page buffer/readout circuit (peripheral circuit)

180: high voltage circuit (peripheral circuit)

ABh: DPD Release Command

B9 h: DPD command

DEC: decoding result

DI: data input terminal

DPDEN, DPDEN1, DPDEN 2: DPD enable signal

INTVDD, INTVDD1, INTVDD 2: voltage supply node

P: PMOS transistor

P1, P2: transistor with a metal gate electrode

S100 to S130: step (ii) of

T_DPD、T_ST: time of day

tDP: for a certain period of time

tRES: period of time

VCC: voltage of external power supply

CS: chip select signal

Detailed Description

The semiconductor memory device of the present invention is Not particularly limited, and is implemented in, for example, a NAND-type OR NOR (Not OR, NOR) flash memory.

[ examples ]

Next, embodiments of the present invention will be described in detail with reference to the drawings. Fig. 3 is a diagram showing a schematic internal configuration of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 includes: a standard command interface (I/F) circuit 110 that receives a standard command, a DPD controller 120 that controls jumping to a DPD mode and releasing the DPD mode, and other internal circuits such as a memory cell array 130, a row decoder 140, a page buffer/readout circuit 150, a peripheral circuit 160, a peripheral circuit 170, and a high voltage circuit 180.

The flash memory 100 of the present embodiment can operate in a plurality of power consumption modes. The active mode performs operations such as standard commands (e.g., read, program, erase) without limiting power consumption and full specification. The standby mode is a mode in which, when not the active mode, the internal circuit is operated in accordance with a predetermined power consumption request, and the operation is performed so as to respond to an input of a standard command or the like. In the standby mode, for example, a charge pump (charge pump) of the high voltage circuit is stopped, or the internal supply voltage is lowered. In the DPD mode, power supply to a specific circuit is blocked in the standby mode in order to further reduce power consumption in the standby mode.

The standard command I/F circuit 110 and DPD controller 120 operate directly using an external power supply voltage VCC (e.g., 3.3V), i.e., are operable in a standby mode and a DPD mode. The standard command I/F circuit 110 is an interface circuit for receiving a standard command prepared in advance for standard operation of the flash memory from the outside. The standard commands are for example commands for reading, programming, erasing etc. The standard command I/F circuit 110 includes a Complementary Metal Oxide Semiconductor (CMOS) logic device for decoding an input standard command, and a decoding result DEC is provided to the DPD controller 120 and the peripheral circuit 160 (including a controller or a state machine (state machine) for controlling the operation of the standard command, etc.).

The DPD controller 120 controls jumping from the standby mode to the DPD mode and releasing of the DPD mode. A PMOS transistor P1 is connected between the external power supply voltage VCC and the voltage supply node INTVDD1, and a PMOS transistor P2 is connected between the external power supply voltage VCC and the voltage supply node INTVDD 2. The row decoder 140, the page buffer/readout circuit 150, the peripheral circuit 160, and the high voltage circuit 180 are connected to a voltage supply node INTVDD1, and the peripheral circuit 170 is connected to a voltage supply node INTVDD 2.

The DPD controller 120 generates the DPD enable signals DPDEN1 and DPD enable signals DPDEN2 at the L level in the active mode and the standby mode, turns on the transistors P1 and P2, and supplies the external power supply voltage VCC to the voltage supply node INTVDD1 and the voltage supply node INTVDD 2. In the DPD mode, the DPD controller 120 makes the DPD enable signals DPDEN1 and DPD enable signal DPDEN2 transition to the H level, turns off the transistors P1 and P2, and blocks the supply of power to the external power supply voltage VCC at the voltage supply nodes INTVDD1 and INTVDD 2. The DPD enable signal DPDEN1 and DPD enable signal DPDEN2 may transition to the H level at different timings according to an elapsed time from the time of jumping to the standby mode, for example.

The method of jumping from the standby mode to the DPD mode is not particularly limited, and in some form, the DPD controller 120 does not input a command for jumping to the DPD mode from a user, and automatically jumps to the DPD mode in response to a signal from a peripheral circuit 160 (including a controller that controls the operation of the flash memory). For example, when a signal indicating a transition to the standby mode is supplied from the peripheral circuit 160 to the DPD controller 120, the DPD controller 120 measures time from a time point indicating a transition to the standby mode, transitions to the DPD mode when the duration of the standby mode exceeds a certain time, transitions the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 to the H level, and blocks the supply of power from the external power supply voltage VCC. In addition, in another aspect, the DPD controller 120 may also jump to the DPD mode in response to an input of a command for jumping to the DPD mode from a user.

In the conventional method for releasing the DPD mode, a dedicated command for releasing the DPD mode needs to be inputted from the outside, but in the present embodiment, a function for automatically releasing the DPD mode without inputting such a dedicated command is provided. The release function will be described in detail later, but if the standard command I/F circuit 110 receives a standard command in the DPD mode, the DPD controller 120 releases the DPD mode in response to the standard command, and seamlessly executes the standard command after the time required for the restoration of the DPD mode has elapsed.

The DPD controller 120 of the present embodiment may be constructed using hardware and/or software, and may include, for example, a microcomputer, a state machine, a logic device, and the like.

The memory cell array 130 includes a plurality of blocks, each block including a plurality of NAND strings (strings). The NAND string may be formed two-dimensionally on the substrate or three-dimensionally in a vertical direction from the main surface of the substrate. In addition, the memory unit may store binary data or multivalued data.

The peripheral circuit 160 and the peripheral circuit 170 include, for example, the following components: a controller or state machine that controls the operation of the flash memory 100 based on a standard command or the like received by the standard command I/F circuit 110; or an Error Checking and Correcting (ECC) circuit and a column selection circuit, and performs Error detection and Correction of data. The high voltage circuit 180 includes a charge pump circuit and the like for generating high voltages necessary for reading, programming, and erasing. The flash memory 100 may be equipped with an SPI (serial Peripheral interface) that recognizes an input command, address, and data in synchronization with a serial clock signal in place of a control signal (address latch permission, command latch permission, and the like).

Next, a method of canceling the DPD mode in the flash memory according to this embodiment will be described with reference to the flowchart of fig. 4. If a standard command is input to the standard command I/F circuit 110 (S100), the standard command I/F circuit 110 decodes the standard command and provides its decoding result DEC to the DPD controller 120 and the peripheral circuit 160. Upon receiving the decoding result DEC, the DPD controller 120 determines whether or not the DPD mode is used (S110). If it is determined to be the DPD mode, the DPD controller 120 releases the DPD mode (S120). That is, the DPD controller 120 transits the DPD enable signals DPDEN1 and DPD enable signals DPDEN2 from the H level to the L level, turns on the transistors P1 and P2, and supplies power from the external power supply voltage VCC to the voltage supply nodes INTVDD1 and INTVDD 2. Thus, the internal voltage VDD1 is supplied from the voltage supply node INTVDD1 to the row decoder 140, the page buffer/readout circuit 150, and the peripheral circuit 160, and the internal voltage VDD2 is supplied from the voltage supply node INTVDD2 to the peripheral circuit 170. The peripheral circuits 140 to 180 are arranged so that tRES period has elapsed as shown in FIG. 1BTime T_STReverting to an operational state.

When the recovery of the peripheral circuits 140 to 180 is completed, the peripheral circuit 160 executes the execution of the standard command based on the decoding result DEC from the standard command I/F circuit 110 (S130). In the period (tRES) in which the DPD mode is released and the peripheral circuit is restored, a busy period in which access to the flash memory is prohibited is used.

On the other hand, if the DPD controller 120 determines that the standard command is not the DPD mode when the standard command is input (S110), the operation of the standard command is immediately performed by the peripheral circuit 160 without releasing the DPD (i.e., the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 are already at the L level) (S130).

As a specific operation example, when a read, program, or erase command is input to the standard command I/F circuit 110 in the DPD mode, the DPD controller 120 transits the DPD enable signals DPDEN1 and DPD enable signals DPDEN2 to L level to turn on the transistors P1 and P2 in order to release the DPD mode. Then, the internal circuit is restored in the tRES period shown in fig. 1B, and then immediately read, program, or erase is performed.

As described above, according to the present embodiment, the DPD mode is automatically released in response to the input of the standard command, and therefore, it is not necessary to input a dedicated command for releasing the DPD mode, and the DPD mode can be released even in a flash memory which does not support the command for releasing the DPD mode. Furthermore, if the flash memory is used to automatically control the jump from the standby mode to the DPD mode (i.e., no dedicated command for jumping to the DPD mode is required), the jump to the DPD mode and the release thereof can be automatically performed without performing user input of all commands related to the DPD mode.

Next, another embodiment of the present invention will be explained. In the above embodiment, the DPD controller 120 uniformly restores the internal circuits from the DPD mode in response to the input of the standard command, but in the present embodiment, the restored internal circuits are selected according to the type of the standard command. The table shown in fig. 5 shows the relationship between the normal command, the restored voltage supply node, and the restoration (recovery) time in the present embodiment. In addition to reading, programming, and erasing, the standard command includes Status Read (Status Read) or Identifier (ID) Read. Status read is whether the read flash memory is in ready (ready) status, whether it is in write protect mode, whether it is a command in program/erase operation, ID read is a command to read manufacturer or product identification.

When the normal command corresponds to the status read or the ID read, the DPD controller 120 transits only the DPD enable signal DPDEN1 to the L level, turns on the transistor P1, and restores only the voltage supply node INTVDD 1. At this time, only the voltage supply node INTVDD1 is restored, so that the restoration time can be shortened. On the other hand, when the normal command corresponds to programming, reading, and erasing, the DPD controller 120 transits both the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 to L level, turns on the transistors P1 and P2, and restores both the voltage supply node INTVDD1 and the voltage supply node INTVDD 2. Here, the recovery time is a standard time.

Thus, according to the present embodiment, the DPD mode can be released at an appropriate recovery time according to the operation content of the standard command, and the standard command can be executed.

In the above embodiment, the external power supply voltage VCC is supplied to the voltage supply nodes INTVDD1 and INTVDD2, but this is an example, and other internal voltages may be supplied to the voltage supply nodes INTVDD1 and INTVDD2 without being directly supplied from the external power supply voltage VCC.

While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the invention described in the claims.