阅读说明：本技术 一种用于核电厂svdu的多图层显示协处理器 (Multi-layer display coprocessor for SVDU (singular value decomposition) of nuclear power plant ) 是由 赵洋 刘明星 张文帅 魏荣超 谌志强 陈起 水璇璇 汪亨 徐孝芬 于 2021-09-23 设计创作，主要内容包括：本发明公开了一种用于核电厂SVDU的多图层显示协处理器,包括图层调度模块和图层处理模块；所述图层调度模块,内置多个基础指令,用于根据接收的控制指令选择相应的基础指令发送给所述图层处理模块；其中,所述控制指令由与所述多图层显示协处理器外接的主处理器生成；所述图层处理模块,用于根据所述基础指令生成相应的图像数据,并将所述图像数据传输至外接的显示设备进行显示。本发明的目的在于提供一种用于核电厂SVDU的多图层显示协处理器,减轻SVDU主处理器的时间任务开销,提升核电厂SVDU响应时间。(The invention discloses a multi-layer display coprocessor for a nuclear power plant SVDU (singular value decomposition), which comprises a layer scheduling module and a layer processing module, wherein the layer scheduling module comprises a layer scheduling module and a layer processing module; the layer scheduling module is internally provided with a plurality of basic instructions and is used for selecting corresponding basic instructions according to the received control instructions and sending the basic instructions to the layer processing module; the control instruction is generated by a main processor externally connected with the multi-layer display coprocessor; and the layer processing module is used for generating corresponding image data according to the basic instruction and transmitting the image data to an external display device for displaying. The invention aims to provide a multi-layer display coprocessor for a nuclear power plant SVDU (singular value decomposition), which reduces the time task overhead of a SVDU main processor and improves the nuclear power plant SVDU response time.)

1. A multi-layer display coprocessor for a nuclear power plant SVDU is characterized by comprising a layer scheduling module and a layer processing module;

the layer scheduling module is internally provided with a plurality of basic instructions and is used for selecting corresponding basic instructions according to the received control instructions and sending the basic instructions to the layer processing module; the control instruction is generated by a main processor externally connected with the multi-layer display coprocessor;

and the layer processing module is used for generating corresponding image data according to the basic instruction and transmitting the image data to an external display device for displaying.

2. The multi-layer display coprocessor for the nuclear power plant SVDU of claim 1, wherein said layer scheduling module comprises an instruction queue unit, a parameter queue unit and a control unit;

the instruction queue unit is used for storing instruction data in the control instruction;

the parameter queue unit is used for storing parameter data in the control instruction;

and the control unit is used for selecting a corresponding basic instruction according to the instruction data and transmitting the basic instruction and the corresponding parameter data to the layer processing module.

3. The multilayer display coprocessor for the nuclear power plant SVDU of claim 2, wherein said control unit comprises a reading subunit and a judging subunit;

the reading subunit is configured to read the instruction data and the parameter data from the instruction queue unit and the parameter queue unit, respectively;

the judging subunit is configured to judge whether instruction data a capable of performing superscalar processing exists in the instruction data;

selecting the basic instruction related to the instruction data A for the instruction data A capable of carrying out superscalar processing and simultaneously sending the basic instruction to the layer processing module;

and sequentially selecting the corresponding basic instructions according to the processing time sequence of the instruction data to send the corresponding basic instructions to the layer processing module for the instruction data which can not be subjected to superscalar processing.

4. The multi-layer display coprocessor for the nuclear power plant SVDU of claim 1, wherein said basic instructions comprise a dot matrix drawing instruction, a trend curve serialization drawing instruction, a two-dimensional rectangular graphics DMA instruction, a layer fusion instruction and a Buffer data access instruction.

5. The multi-layer display coprocessor for the nuclear power plant SVDU of claim 1, wherein said layer processing module comprises a first layer controller unit, a second layer controller unit, a third layer controller unit and a Buffer data access hardware function unit;

the first layer controller unit is used for realizing continuous display of the discretely sampled data points on the display equipment;

the second layer controller unit is used for realizing drawing of graphs, and the graphs comprise line graphs, ACII code graphs, rectangular graphs and rhombic graphs;

the third layer controller unit is used for copying the preset icon elements;

the Buffer data access accesses a hardware function Fun unit for generating an image to be displayed.

6. The multilayer display coprocessor for the nuclear power plant SVDU of claim 5, wherein said first layer controller unit comprises a computation subunit, a first judgment subunit, a rendering subunit, an update subunit and a second judgment subunit;

the calculating subunit is used for calculating the drawing range of the current column after a column of pixel points is drawn; the drawing range is the upper limit of the pixel point coordinate of the current column and the lower limit of the pixel point coordinate of the current column;

the first judgment subunit is used for judging the relationship between the pixel coordinate of the new sampling point and the upper limit and the lower limit of the pixel coordinate;

the drawing subunit is used for continuously drawing the pixel point coordinates of the new sampling point from the lower limit of the pixel point coordinates when the pixel point coordinates of the new sampling point are smaller than the lower limit of the pixel point coordinates; when the pixel point coordinate of the new sampling point is larger than the upper limit of the pixel point coordinate, continuously drawing the pixel point coordinate of the new sampling point from the upper limit of the pixel point coordinate; when the pixel point coordinate of the new sampling point is located at the lower limit of the pixel point coordinate and the upper limit of the pixel point coordinate, only drawing the pixel point coordinate of the new sampling point;

the updating subunit is used for calculating and updating the drawing range drawn by the drawing subunit;

and the second judging subunit is used for judging whether the data point of discrete sampling is drawn or not, and transmitting the updated drawing range to the first judging subunit when the drawing is not finished.

7. The multi-layer display co-processor for the nuclear power plant SVDU of claim 5, wherein said third layer controller unit comprises a two-dimensional rectangular graphics DMA hardware function Fun subunit and a cache subunit; and the two-dimensional rectangular graphic DMA hardware function Fun subunit is used for copying preset icon elements in the memory of the picture resource library to the cache subunit according to the mapping relation.

8. The multi-layer display co-processor for the nuclear power plant SVDU of claim 7, wherein said two-dimensional rectangular graphics DMA hardware function Fun subunit comprises a control subunit, a decompression pipeline processing subunit, and a rate adjuster subunit;

the control subunit is externally connected with a picture resource library memory and is used for acquiring the preset icon elements from the picture resource library memory;

the decompression pipeline processing subunit is configured to perform decompression operation on the preset icon elements that need to be decompressed;

the speed regulator subunit is configured to regulate a speed matching relationship between the cache subunit and the decompressed preset icon elements, and store the preset icon elements to the cache subunit according to the mapping relationship.

9. The multilayer display coprocessor for the nuclear power plant SVDU of claim 7 wherein said mapping relationship is: row-column pixel coordinate mapping.

10. The multilayer display coprocessor for the nuclear power plant SVDU of claim 8 wherein said decompression pipeline processing subunit performs decompression operations on said preset icon elements using reverse RLE decompression operations.

Technical Field

The invention relates to the technical field of digital instrument control, in particular to a multi-layer display coprocessor for SVDUs (singular value decomposition) of a nuclear power plant.

Background

The nuclear power plant SVDU is a man-machine interaction device which is applied to nuclear power industry and matched with a safety-level DCS. Currently, with the great progress of the liquid crystal display technology, users increasingly require that the nuclear power plant SVDU has high resolution and rich display forms.

In the existing nuclear power plant SVDU, the processing operation of the image is completed based on the main processor in the SVDU, and because the data amount required to be displayed and processed is large in the nuclear industry field, the phenomena of low efficiency, time delay and the like exist when one processor completes a large amount of data processing.

Disclosure of Invention

The invention aims to provide a multi-layer display coprocessor for a nuclear power plant SVDU (singular value decomposition), which reduces the time task overhead of a SVDU main processor and improves the nuclear power plant SVDU response time.

The invention is realized by the following technical scheme:

a multi-layer display coprocessor for a nuclear power plant SVDU comprises a layer scheduling module and a layer processing module;

the layer scheduling module is internally provided with a plurality of basic instructions and is used for selecting corresponding basic instructions according to the received control instructions and sending the basic instructions to the layer processing module; the control instruction is generated by a main processor externally connected with the multi-layer display coprocessor;

and the layer processing module is used for generating corresponding image data according to the basic instruction and transmitting the image data to an external display device for displaying.

Preferably, the layer scheduling module includes an instruction queue unit, a parameter queue unit and a control unit;

the instruction queue unit is used for storing instruction data in the control instruction;

the parameter queue unit is used for storing parameter data in the control instruction;

and the control unit is used for selecting a corresponding basic instruction according to the instruction data and transmitting the basic instruction and the corresponding parameter data to the layer processing module.

Preferably, the control unit comprises a reading subunit and a judging subunit;

the reading subunit is configured to read the instruction data and the parameter data from the instruction queue unit;

the judging subunit is configured to judge whether instruction data a capable of performing superscalar processing exists in the instruction data;

selecting the basic instruction related to the instruction data A for the instruction data A capable of carrying out superscalar processing and simultaneously sending the basic instruction to the layer processing module;

and sequentially selecting the corresponding basic instructions according to the processing time sequence of the instruction data to send the corresponding basic instructions to the layer processing module for the instruction data which can not be subjected to superscalar processing.

Preferably, the basic instruction comprises a dot matrix drawing instruction, a trend curve continuous drawing instruction, a two-dimensional rectangular graph DMA instruction, a layer fusion instruction and a Buffer data access instruction.

Preferably, the layer processing module includes a first layer controller unit, a second layer controller unit, a third layer controller unit, and a Buffer data access hardware function unit;

the first layer controller unit is used for realizing continuous display of the discretely sampled data points on the display equipment;

the second layer controller unit is used for realizing drawing of graphs, and the graphs comprise line graphs, ACII code graphs, rectangular graphs and rhombic graphs;

the third layer controller unit is used for copying the preset icon elements;

the Buffer data access accesses a hardware function Fun unit for generating an image to be displayed.

Preferably, the first graph layer controller unit comprises a calculating subunit, a first judging subunit, a drawing subunit, an updating subunit and a second judging subunit;

the calculating subunit is used for calculating the drawing range of the current column after a column of pixel points is drawn; the drawing range is the upper limit of the pixel point coordinate of the current column and the lower limit of the pixel point coordinate of the current column;

the first judgment subunit is used for judging the relationship between the pixel coordinate of the new sampling point and the upper limit and the lower limit of the pixel coordinate;

the drawing subunit is used for continuously drawing the pixel point coordinates of the new sampling point from the lower limit of the pixel point coordinates when the pixel point coordinates of the new sampling point are smaller than the lower limit of the pixel point coordinates; when the pixel point coordinate of the new sampling point is larger than the upper limit of the pixel point coordinate, continuously drawing the pixel point coordinate of the new sampling point from the upper limit of the pixel point coordinate; when the pixel point coordinate of the new sampling point is located at the lower limit of the pixel point coordinate and the upper limit of the pixel point coordinate, only drawing the pixel point coordinate of the new sampling point;

the updating subunit is used for calculating and updating the drawing range drawn by the drawing subunit;

and the second judging subunit is used for judging whether the data point of discrete sampling is drawn or not, and transmitting the updated drawing range to the first judging subunit when the drawing is not finished.

Preferably, the third layer controller unit includes a two-dimensional rectangular graphics DMA hardware function Fun subunit and a cache subunit; and the two-dimensional rectangular graphic DMA hardware function Fun subunit is used for copying preset icon elements in the memory of the picture resource library to the cache subunit according to the mapping relation.

Preferably, the two-dimensional rectangular graphics DMA hardware function Fun subunit includes a control subunit, a decompression pipeline processing subunit, and a rate adjuster subunit

The control subunit is externally connected with a picture resource library memory and is used for acquiring the preset icon elements from the picture resource library memory;

the decompression pipeline processing subunit is configured to perform decompression operation on the preset icon elements that need to be decompressed;

the speed regulator subunit is configured to regulate a speed matching relationship between the cache subunit and the decompressed preset icon elements, and store the preset icon elements to the cache subunit according to the mapping relationship.

Preferably, the decompression pipeline processing subunit performs a decompression operation on the preset icon element by using an inverse RLE decompression operation.

Preferably, the mapping relationship is: row-column pixel coordinate mapping.

Compared with the prior art, the invention has the following advantages and beneficial effects:

partial image processing data of the main processor are transmitted to the multilayer display coprocessor to be processed, so that time task overhead of the SVDU main processor is reduced, and indexes such as response time, picture resolution, trend data continuity precision and the like of the SVDU of the nuclear power plant are effectively improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram of a multi-layer display coprocessor according to the present invention;

FIG. 2 is a schematic diagram illustrating a graphics coprocessor instruction response flow of the present invention;

FIG. 3 is a schematic flow chart of a trend curve serialization algorithm of the present invention;

FIG. 4 is a schematic diagram of the internal structure of the two-dimensional rectangular graphics DMA hardware function Fun according to the present invention;

FIG. 5 is a schematic diagram of a data processing flow of the two-dimensional rectangular graphics DMA hardware function Fun according to the present invention;

FIG. 6 is a schematic diagram of a two-dimensional rectangular graphic data mapping relationship according to the present invention;

FIG. 7 is a two-dimensional rectangular graphics data DMA flow diagram according to the present invention;

FIG. 8 is a diagram illustrating the operation of reverse RLE decompression in accordance with the present invention;

fig. 9 is a schematic diagram of the pipeline processing adopted for inverse RLE decompression according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Examples

A multi-layer display coprocessor for a nuclear power plant SVDU (singular value decomposition) comprises a layer scheduling module and a layer processing module, as shown in FIG. 1;

the layer scheduling module is internally provided with a plurality of basic instructions and comprises: the device comprises a dot matrix drawing module, a trend curve continuous drawing module, a two-dimensional rectangular graph DMA (direct memory access), a graph layer fusion module and a Buffer data access module, wherein the two-dimensional rectangular graph DMA, the graph layer fusion module and the Buffer data access module are used for selecting a corresponding basic instruction according to a received control instruction and sending the basic instruction to a graph layer processing module; the control instruction is generated by a main processor externally connected with the multi-layer display coprocessor;

and the layer processing module is used for generating corresponding image data according to the basic instruction and transmitting the image data to an external display device for displaying.

In the existing SVDU of nuclear power plant, the processing operation of the image is completed based on the main processor in the SVDU, because in the field of nuclear industry, the data amount needing to be displayed and processed is large, and the phenomena of low efficiency, time delay and the like exist when one processor completes a large amount of data processing.

Further, the layer scheduling module in this embodiment includes an instruction queue unit, a parameter queue unit, and a control unit;

the instruction queue unit is used for storing instruction data in the control instruction, and in the embodiment, no more than 64 graphics coprocessing instructions are allowed to be stored in the instruction queue unit; the parameter queue unit is used for storing parameter data in the control instruction, and in the embodiment, no more than 64 graphics co-processing parameters are allowed to be stored in the parameter queue unit; and the control unit is used for selecting a corresponding basic instruction according to the instruction data, transmitting the basic instruction and the corresponding parameter data to the layer processing module and finishing the scheduling of the layer processing module. Specifically, as shown in fig. 2, it is assumed that a control instruction received by the layer scheduling module is an image co-acceleration processing trigger signal instruction, where the control instruction includes 10 instruction data and 10 parameter data, and one instruction data corresponds to one parameter data, and when the layer scheduling module receives the control instruction, 10 instruction data are transmitted to an instruction queue unit, and 10 parameter data instruction transmit parameter queue units; when the control unit starts to process the control instruction, firstly, 10 instruction data and 10 parameter data are read, and then whether instruction data A capable of carrying out superscalar processing exists in the 10 instruction data is judged; if the instruction data A capable of carrying out superscalar processing exists, carrying out superscalar processing on the instruction data A capable of carrying out superscalar processing, namely: selecting a basic instruction related to the instruction data A and sending the basic instruction to the layer processing module; and for the instruction data which can not be subjected to superscalar processing, sequentially selecting corresponding basic instructions according to the processing time sequence of the instruction data and sending the basic instructions to the layer processing module until all 10 instruction data are completely executed.

Further, the layer processing module in this embodiment is composed of 3 basic layer controllers (a first layer controller unit, a second layer controller unit, and a third layer controller unit) and 1 Buffer data access hardware function Fun. Wherein:

the first layer controller unit is composed of a trend curve continuous drawing hardware function Fun and a first layer cache, and is used for executing a trend curve continuous drawing instruction and realizing continuous display of discretely sampled data points on an LCD. The flow of the trend curve serialization algorithm is shown in fig. 3, and includes:

(1) when the drawing is started and a column of pixel points is drawn, calculating the drawing range of the current column; the drawing range in this embodiment is the upper limit of the pixel coordinates of the current column and the lower limit of the pixel coordinates of the current column;

(2) judging the relation between the pixel coordinate of the new sampling point and the upper limit and the lower limit of the pixel coordinate; when the pixel point coordinate of the new sampling point is smaller than the lower limit of the pixel point coordinate, continuously drawing the pixel point coordinate of the new sampling point from the lower limit of the pixel point coordinate; when the pixel point coordinate of the new sampling point is larger than the upper limit of the pixel point coordinate, continuously drawing the pixel point coordinate of the new sampling point from the upper limit of the pixel point coordinate; when the pixel point coordinate of the new sampling point is positioned at the lower limit of the pixel point coordinate and the upper limit of the pixel point coordinate, only drawing the pixel point coordinate of the new sampling point;

(3) calculating and updating the drawing range after drawing;

(4) and (4) judging whether the drawing of the data points of the discrete sampling is finished or not, and repeating the steps (2) to (3) when the drawing is not finished.

Therefore, the first graph layer controller unit in this embodiment includes a calculating subunit, a first judging subunit, a drawing subunit, an updating subunit, and a second judging subunit;

the calculation subunit is used for calculating the drawing range of the current column after a column of pixel points is drawn;

the first judgment subunit is used for judging the relationship between the pixel coordinate of the new sampling point and the upper limit and the lower limit of the pixel coordinate;

the drawing subunit is used for continuously drawing the pixel point coordinates of the new sampling points from the lower limit of the pixel point coordinates when the pixel point coordinates of the new sampling points are smaller than the lower limit of the pixel point coordinates; when the pixel point coordinate of the new sampling point is larger than the upper limit of the pixel point coordinate, continuously drawing the pixel point coordinate of the new sampling point from the upper limit of the pixel point coordinate; when the pixel point coordinate of the new sampling point is positioned at the lower limit of the pixel point coordinate and the upper limit of the pixel point coordinate, only drawing the pixel point coordinate of the new sampling point;

the updating subunit is used for calculating and updating the drawing range drawn by the drawing subunit;

and the second judgment subunit is used for judging whether the drawing of the data point of the discrete sampling is finished or not, and transmitting the updated drawing range to the first judgment subunit when the drawing is not finished.

The second layer controller unit is composed of a dot matrix drawing hardware function Fun and a second layer cache, and is used for executing dot matrix drawing instructions including drawing of lines, ACII codes, rectangles, diamonds and other graphics, and the dot matrix drawing hardware function Fun generates dot matrix form data as required and writes the dot matrix form data into the second layer cache.

The third layer controller unit consists of a two-dimensional rectangular graphic DMA hardware function Fun subunit and a third layer cache subunit, and is used for executing a two-dimensional rectangular graphic DMA instruction, as shown in FIG. 5, reading, decompressing and carrying preset icon elements to a target storage space; the internal structure of the two-dimensional rectangular graphics DMA hardware function Fun subunit is shown in FIG. 4, and includes a control subunit, a decompression pipeline processing subunit, and a rate regulator subunit; the control subunit is externally connected with a picture resource library memory and is used for acquiring preset icon elements from the picture resource library memory; the decompression pipeline processing subunit is used for carrying out decompression operation on the preset icon elements needing to be decompressed; and the speed regulator subunit is used for regulating the speed matching relationship between the cache subunit and the decompressed preset icon elements, and storing the preset icon elements into the cache subunit according to the mapping relationship for LCD display.

The mapping relation in this implementation is: row-column pixel coordinate mapping. In the memory of the picture resource library, the picture data is stored linearly, that is, the picture data is stored in a section of continuous address space in a row arrangement manner, when the preset icon elements are copied, as shown in fig. 6, mapping is required according to row-column pixel coordinates, and the mapped storage space is not completely continuous. The conversion flow is shown in fig. 7.

The decompression pipeline processing subunit in this embodiment performs a decompression operation on the preset icon element by using an inverse RLE decompression operation. Specifically, as shown in fig. 8:

in the data before decompression, when the identification code is '0', the data after the identification code is a pixel value, and can be directly sent to the third layer cache subunit for caching without decompression processing. When the identification code is "1" in the data before decompression, it indicates that the data after the data is compressed by the RLE algorithm, and the data may be further subdivided into the number of times of pixel value repetition and the pixel value. The number of pixel value repetitions is used in combination with the subsequent pixel values. A typical decompression flow is as follows:

typical compressed data packets: "1" - "3A" - "5B" - "2C".

The first step is as follows: when the identification code is determined to be "1", decompression needs to be started.

The second step is that: "3A" is decompressed to "AAA"; "5B" is decompressed to "BBBBB"; the "2C" is decompressed to "CC".

The final data generated is "AAABBBBBCC".

The inverse RLE decompression in this embodiment takes a pipeline technique to speed up the processing, as shown in fig. 9.

The Buffer data access hardware function Fun subunit is externally connected with a physical Buffer1, a physical Buffer2Buffer and an LCD; the data access hardware function Fun subunit is matched with the physical Buffer1 and the physical Buffer2 to realize the functions of Buffer data access and layer fusion instructions and realize the periodic refreshing of LCD data. Physical Buffer1 and physical Buffer2 are two identical physical memories. The physical Buffer1 and the physical Buffer2 can be used for a drawing board or a video memory and can be switched to use in a time-sharing manner. The drawing board is used for generating an image to be displayed; the display memory is used for storing data required by the LCD display.

The layer fusion function provided by the Buffer data access hardware function Fun is realized by the following steps: and copying the data of the first layer cache, the second layer cache and the third layer cache to the specified positions in the physical Buffer1 or the physical Buffer2 through a layer data bus to form image data which can be finally sent to an LCD for display.

The Buffer data access hardware function Fun provides timing driving of the physical Buffer1 and physical Buffer2 data access accesses.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.