阅读说明：本技术 存储装置、存储控制器以及存储控制器的操作方法 (Memory device, memory controller, and method of operating memory controller ) 是由 李翰滨 辛范柱 于 2021-02-19 设计创作，主要内容包括：本申请公开了存储装置、存储控制器以及存储控制器的操作方法。提供了一种电子装置,更具体地,一种用于减轻由于电流交叠而出现峰值电流的时段的存储装置。该存储装置包括：存储器装置,其包括多个管芯；以及存储控制器,其控制存储器装置。存储器装置在所有多个管芯均处于繁忙状态的繁忙时段期间生成关于多个管芯中的每一个所消耗的电流量的状态信息,并且其中,存储控制器基于状态信息来确定是否在跨越繁忙时段的多个子时段中的公共子时段中消耗所述多个管芯中的复数个管芯的峰值电流,并且当确定在公共子时段中消耗复数个管芯的峰值电流时,存储控制器控制存储器装置暂停对多个管芯当中的管芯的操作。(The application discloses a storage device, a storage controller and an operation method of the storage controller. An electronic device, and more particularly, a memory device for mitigating a period during which a peak current occurs due to current overlap is provided. The storage device includes: a memory device comprising a plurality of dies; and a memory controller that controls the memory device. The memory device generates status information regarding an amount of current consumed by each of the plurality of dies during a busy period in which all of the plurality of dies are in a busy state, and wherein the memory controller determines whether peak currents of a plurality of dies of the plurality of dies are consumed in a common sub-period of a plurality of sub-periods spanning the busy period based on the status information, and controls the memory device to suspend operation of a die of the plurality of dies when it is determined that the peak currents of the plurality of dies are consumed in the common sub-period.)

1. A memory controller for controlling a memory device including a plurality of dies, the memory controller comprising:

a state information determination component configured to determine, based on state information received from the memory device during a busy period in which all of the plurality of dies are in a busy state, whether peak currents of a plurality of the plurality of dies occur in a common sub-period of a plurality of sub-periods spanning the busy period, and to generate pause information based on determining that peak currents of the plurality of dies occur in the common sub-period; and

a peak current controller configured to output a pause command to pause operation of at least one die of the plurality of dies during the common sub-period based on the pause information.

2. The memory controller of claim 1, wherein the status information determining component outputs a status read command to obtain information about an amount of current consumed by the plurality of dies when a ready/busy signal is received from the memory device indicating that all of the plurality of dies are in the busy state.

3. The memory controller of claim 2, wherein the status information determining component receives the status information output from the memory device in response to the status read command.

4. The memory controller of claim 1, wherein the busy period is divided into a predetermined plurality of the sub-periods, and the status information comprises information regarding an amount of current consumption by each of the plurality of dies corresponding to the plurality of sub-periods.

5. The memory controller of claim 4, wherein the busy period is divided into the plurality of sub-periods based on a time interval at which sub-operations are performed on each of the plurality of dies.

6. The memory controller of claim 4, wherein the status information determination component sums the amount of current consumed by the plurality of dies for each of the plurality of sub-periods based on the status information and determines whether the peak current of the plurality of dies is present in the common sub-period based on the summed amounts of current.

7. The memory controller of claim 6, wherein the status information determination component determines that the peak currents of the plurality of dies occur in the common subinterval based on an added current amount having a maximum value.

8. The memory controller of claim 6, wherein the state information determination component generates the suspension information when the peak current of the plurality of dies occurs in the common subinterval, and

wherein the suspension information includes information about the at least one die for which operation is suspended and a time interval for which the operation is suspended.

9. The memory controller of claim 8, wherein the time interval during which the operation is suspended corresponds to the common sub-period during which the peak current of the plurality of dies occurs.

10. The memory controller of claim 8, wherein the peak current controller outputs the pause command indicating that the at least one die determined based on the pause information pauses particular operations for the time interval for the at least one die pause operation.

11. The memory controller of claim 8, wherein the peak current controller outputs a resume command to resume the suspended operation of the at least one die after the operation of the at least one die is suspended for the time interval.

12. A method of operating a memory controller for controlling a memory device comprising a plurality of dies, the method comprising the steps of:

receiving status information from the memory device during a busy period in which all of the plurality of dies are in a busy state;

determining, based on the status information, whether peak currents of a plurality of the plurality of dies occur in a common sub-period of a plurality of sub-periods spanning the busy period;

generating pause information for pausing operation of at least one die of the plurality of dies based on determining that peak current of the plurality of dies occurs in the common subinterval; and

outputting a pause command to pause operation of the at least one die during the common subinterval based on the pause information.

13. The method of claim 12, wherein the step of receiving the status information comprises the steps of:

receiving a ready/busy signal from the memory device indicating that all of the plurality of dies are in the busy state; and

outputting a status read command for obtaining information about an amount of current consumed by the plurality of dies,

wherein the status information is output from the memory device in response to the status read command.

14. The method of claim 12, wherein the busy period is divided into a predetermined plurality of the sub-periods, and the status information comprises information regarding an amount of current consumption by each of the plurality of dies corresponding to the plurality of sub-periods.

15. The method of claim 14, wherein the busy period is divided into the plurality of sub-periods based on a time interval at which sub-operations are performed on each of the plurality of dies.

16. The method of claim 14, wherein the step of determining whether the peak currents of the plurality of dies are present in the common subinterval comprises the steps of:

summing the amount of current consumed by the plurality of dies for each of the plurality of subintervals based on the status information; and

it is determined in which sub-period the added peak current occurs based on the amount of added current.

17. The method of claim 16, wherein the step of determining in which sub-period the summed peak current occurs comprises the steps of: it is determined at which subinterval the added current amount has the maximum value.

18. The method of claim 16, further comprising the steps of: generating the pause information when the peak current of the plurality of dies occurs in the common sub-period,

wherein the suspension information includes information about the at least one die for which operation is suspended and a time interval for which the operation is suspended.

19. The method of claim 18, wherein in generating the suspension information, the suspension information including information on the time interval during which the operation is suspended is generated, and the time interval during which the operation is suspended corresponds to a length of a common sub-period.

20. A memory device, the memory device comprising:

a memory device comprising a plurality of dies; and

a memory controller for controlling the memory device,

wherein the memory device generates status information about an amount of current consumed by each of the plurality of dies during a busy period in which all of the plurality of dies are in a busy state, and

wherein the memory controller determines whether peak currents of a plurality of dies are consumed in a common sub-period of a plurality of sub-periods spanning the busy period based on the state information, and controls the memory device to suspend operation of a die among the plurality of dies when it is determined that peak currents of the plurality of dies are consumed in the common sub-period.

Technical Field

Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to a storage device and an operating method of the storage device.

Background

The storage device may store data under the control of a host device such as a computer, smart phone, or smart tablet. Examples of the storage device include a device for storing data on a magnetic disk such as a Hard Disk Drive (HDD) and a device for storing data in a semiconductor memory, particularly a nonvolatile memory such as a Solid State Drive (SSD) or a memory card.

The memory device may include a memory device for storing data and a memory controller for controlling the memory device to store data. Memory devices may be classified as either volatile memory devices or nonvolatile memory devices. Examples of non-volatile memory devices include read-only memory (ROM) devices, Programmable ROM (PROM) devices, Electrically Programmable ROM (EPROM) devices, Electrically Erasable Programmable ROM (EEPROM) devices, flash memory devices, phase change RAM (PRAM) devices, Magnetic RAM (MRAM) devices, Resistive RAM (RRAM) devices, and Ferroelectric RAM (FRAM) devices.

Disclosure of Invention

Various embodiments relate to a memory device for mitigating a period in which a peak current occurs due to overlapping currents and a method of operating the memory device.

According to an embodiment, a memory controller for controlling a memory device comprising a plurality of dies may comprise a state information determination component configured to determine whether peak currents of a plurality of the plurality of dies occur in a common sub-period of a plurality of sub-periods spanning a busy period based on state information received from the memory device during the busy period in which all of the plurality of dies are in a busy state, and configured to generate pause information based on determining that peak currents of the plurality of dies occur in the common sub-period. The memory controller also includes a peak current controller configured to output a pause command to pause operation of at least one die of the plurality of dies during a common subinterval based on the pause information.

According to an embodiment, a method of operating a memory controller for controlling a memory device comprising a plurality of dies comprises the steps of: status information is received from a memory device during a busy period in which all of the plurality of dies are in a busy state. The method further comprises the following steps: determining, based on the status information, whether peak currents of a plurality of the plurality of dies occur in a common sub-period of a plurality of sub-periods spanning a busy period. The method further comprises the following steps: generating suspension information for suspending operation of at least one die of the plurality of dies based on the determination. The method further comprises the following steps: outputting a pause command to pause operation of the at least one die during the common subinterval based on the pause information.

According to an embodiment, a storage device includes: a memory device comprising a plurality of dies; and a memory controller that controls the memory device. The memory device generates status information regarding an amount of current consumed by each of the plurality of dies during a busy period in which all of the plurality of dies are in a busy state. The memory controller determines whether peak currents of a plurality of dies are consumed in a common sub-period of a plurality of sub-periods spanning a busy period based on the state information, and controls the memory device to suspend operation of a die among the plurality of dies when it is determined that the peak currents of the plurality of dies are consumed in the common sub-period.

Drawings

Fig. 1 is a block diagram showing a storage device.

Fig. 2 is a diagram illustrating a structure of the memory device shown in fig. 1.

Fig. 3 is a diagram illustrating an embodiment of the memory cell array shown in fig. 2.

Fig. 4 is a diagram illustrating a plurality of dies included in the memory device shown in fig. 1.

Fig. 5 is a diagram showing the amount of current consumed by each of the two dies and the total amount of current obtained by adding the amounts of current consumed by the two dies.

Fig. 6 is a diagram illustrating the operation of two dies during a period when peak current overlap occurs.

Fig. 7 is a diagram illustrating operation of two dies during a period when peak current overlap occurs, according to an embodiment.

Fig. 8 is a graph showing a comparison between the total amount of current shown in fig. 5 and the total amount of current shown in fig. 7.

Fig. 9 is a diagram showing the configuration of the memory controller shown in fig. 1 and a process of outputting a suspend command.

Fig. 10 is a diagram illustrating a method of subdividing overlapping busy periods.

Fig. 11A and 11B are tables showing state information output from the memory device.

Fig. 12 is a table showing a method of determining whether periods in which peak currents occur overlap based on state information.

Fig. 13 is a diagram illustrating an operation of a storage controller according to an embodiment.

Fig. 14 is a diagram illustrating an operation of a storage controller according to an embodiment.

Fig. 15 is a diagram illustrating another embodiment of the memory controller shown in fig. 1.

Fig. 16 is a block diagram showing a memory card system to which a storage device is applied according to an embodiment.

Fig. 17 is a block diagram illustrating an example of a Solid State Drive (SSD) system to which a storage device is applied according to an embodiment.

Fig. 18 is a block diagram showing a user system to which a storage device is applied according to an embodiment.

Detailed Description

Hereinafter, only a specific structural or functional description of an example of the embodiment according to the concept disclosed in the present specification is shown to describe the example of the embodiment according to the concept, and the example of the embodiment according to the concept may be implemented in various forms, but the description is not limited to the example of the embodiment described in the present specification.

Hereinafter, embodiments of the present disclosure are described with reference to the accompanying drawings so that those skilled in the art can implement the technical spirit of the present disclosure.

Fig. 1 is a block diagram showing a storage device 50.

Referring to fig. 1, the memory device 50 may include a memory device 100 and a memory controller 200.

The storage device 50 may store data in response to control of the host 300. Examples of hosts include cellular phones, smart phones, MP3 players, laptop computers, desktop computers, gaming consoles, TVs, tablet PCs, or in-vehicle infotainment systems.

The storage device 50 may be configured as one of various types of storage devices according to a host interface corresponding to a communication method with the host 300. For example, the storage device 50 may be configured as one of various types of storage devices, such as a Solid State Drive (SSD); a multimedia card (MMC) in the form of eMMC, RS-MMC or micro-MMC; a Secure Digital (SD) card; a mini-SD card; micro-SD card; a Universal Serial Bus (USB) storage device; a universal flash memory (UFS) device; personal Computer Memory Card International Association (PCMCIA) card type memory devices; a Peripheral Component Interconnect (PCI) card type storage device; PCI express (PCI-E) card type storage devices; a Compact Flash (CF) card; a smart media card; or a memory stick.

The memory device 50 may be manufactured in one of various types of packages. For example, the storage device 50 may be manufactured as a Package On Package (POP), a System In Package (SIP), a System On Chip (SOC), a multi-chip package (MCP), a Chip On Board (COB), a wafer-level manufacturing package (WFP), or a wafer-level package on package (WSP).

The memory device 100 may store data. The memory device 100 may operate in response to control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, and the plurality of memory cells may form a plurality of pages. According to an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. The memory block may be a unit for erasing data.

According to embodiments, memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM) device, a low power double data rate 4(LPDDR4) SDRAM device, a Graphics Double Data Rate (GDDR) SDRAM device, a low power DDR (LPDDR) device, a Rambus Dynamic Random Access Memory (RDRAM) device, a NAND flash memory device, a vertical NAND flash memory device, a NOR flash memory device, a Resistive Random Access Memory (RRAM) device, a phase change memory (PRAM) device, a Magnetoresistive Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, or a spin transfer torque random access memory (STT-RAM) device. For ease of illustration, it is assumed in the context of the following description that memory device 100 is a NAND flash memory device.

The memory device 100 may have a two-dimensional or three-dimensional array structure. Hereinafter, a three-dimensional array structure is described as an embodiment. However, the embodiments are not limited to the three-dimensional array structure. Embodiments of the present disclosure are applicable not only to flash memory devices in which the charge storage layer includes a conductive Floating Gate (FG), but also to Charge Trap Flash (CTF) memory devices in which the charge storage layer includes an insulating layer.

According to an embodiment, the memory device 100 may operate by a Single Level Cell (SLC) method in which one memory cell stores one bit of data. Alternatively, the memory device 100 may operate by a method in which one memory cell stores at least two bits of data. For example, the memory device 100 may operate by a Multi Level Cell (MLC) method in which one memory cell stores two bits of data, a Triple Level Cell (TLC) method in which one memory cell stores three bits of data, or a Quad Level Cell (QLC) method in which one memory cell stores four bits of data.

The memory device 100 may receive a command and an address from the memory controller 200 and access a region in the memory cell array selected by the address. That is, the memory device 100 may perform an operation corresponding to a command on an area selected by an address. For example, the memory device 100 may perform a write operation (or program operation), a read operation, or an erase operation according to the received command. For example, when a program command is received, the memory device 100 may program data into a region selected by an address. When a read command is received, the memory device 100 may read data from the area selected by the address. When receiving the erase command, the memory device 100 may erase data stored in the area selected by the address.

According to an embodiment, the storage controller 200 may include a state information determination component 210. The state information determining component 210 may determine the state of the plurality of dies included in the memory device 100 and also determine whether to suspend an operation performed on one of the plurality of dies.

For example, status information determining component 210 may receive ready/busy signals R/B from multiple dies. The ready signal may indicate that the die is in a ready state in which the die is standing by without performing an operation. The busy signal may indicate that the die is in a busy state where the die is performing an operation.

According to an embodiment, the status information determining component 210 may output a status read command to each of the plurality of dies when all signals received from the plurality of dies are busy signals. The memory device 100 may output status information in response to a status read command received from the status information determining component 210. The state information may include information indicative of the current consumed by each of the plurality of dies.

For example, the memory device 100 may subdivide a period in which each of the plurality of dies is in a busy state into sub-periods of a predetermined length, and may set and output a bit indicating an amount of current consumption corresponding to the sub-periods as the state information.

According to an embodiment, state information determining component 210 may determine the sub-period of peak current overlap based on state information received from memory device 100. The state information determining component 210 may select one of the plurality of dies during the sub-period when the peak current overlap occurs, and may generate pause information including information about the selected die and a time at which operation of the selected die is paused. The time interval for suspension of operation of the selected die may be the same as the sub-period during which peak current overlap occurs. In addition, the pause information may be communicated to the peak current controller 220.

According to an embodiment, the memory controller 200 may include a peak current controller 220. Peak current controller 220 may determine an output pause command based on pause information received from state information determining component 210.

For example, when the pause information includes information indicating that the operation on the predetermined die should be paused, the peak current controller 220 may output a pause command to the predetermined die whose operation is to be paused.

The memory controller 200 may control the general operation of the memory device 50.

The memory controller 200 may execute the firmware when a power supply voltage is applied to the memory device 50. When the memory device 100 is a flash memory device, the memory controller 200 may execute firmware such as a Flash Translation Layer (FTL) for controlling communication between the host 300 and the memory device 100.

According to an embodiment, the storage controller 200 may receive data and Logical Block Addresses (LBAs) from the host 300, and include firmware (not shown) that converts the LBAs into Physical Block Addresses (PBAs) indicating addresses of memory units in which the data included in the memory device 100 is to be stored. In addition, the storage controller 200 may store a logical-to-physical address mapping table configuring the mapping relationship between the LBA and the PBA in the buffer memory.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. in response to a request from the host 300. For example, when the memory controller 200 receives a program request from the host 300, the memory controller 200 may convert the program request into a program command and may provide the program command, PBA, and data to the memory device 100. When the storage controller 200 receives a read request and an LBA from the host 300, the storage controller 200 may convert the read request into a read command, select a PBA corresponding to the LBA, and then may provide the read command and the PBA to the memory device 100. When the storage controller 200 receives an erase request and an LBA from the host 300, the storage controller 200 may convert the erase request into an erase command, select a PBA corresponding to the LBA, and then may provide the erase command and the PBA to the memory device 100.

According to an embodiment, the memory controller 200 may generate and transmit a program command, an address, and data to the memory device 100 without a request from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as program operations for wear leveling and program operations for garbage collection.

According to an embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 300 and a buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data for controlling the memory device 100 to a buffer memory. For example, the memory controller 200 may temporarily store data input from the host 300, and thereafter transfer the data temporarily stored in the buffer memory to the memory device 100.

According to various embodiments, the buffer memory may be used as an operating memory or cache memory for the memory controller 200. The buffer memory may store code or commands executed by the memory controller 200. Alternatively, the buffer memory may store data processed by the memory controller 200.

According to embodiments, buffer memory 300 may include Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM) such as double data rate synchronous random access memory (DDR SDRAM), low power double data rate 4(LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, low power DDR (LPDDR) or Rambus Dynamic Random Access Memory (RDRAM).

According to various embodiments, the buffer memory may be coupled to the storage device 50 external to the storage device 50. A volatile memory device coupled to the storage device 50 outside the storage device 50 may be used as a buffer memory.

According to an embodiment, the memory controller 200 may control a plurality of memory devices. The memory controller 200 may control the memory device according to an interleaving scheme to improve operation performance.

The host 300 may communicate with the storage device 50 using AT least one of various communication methods such as Universal Serial Bus (USB), serial AT attachment (SATA), serial attached SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory AT high speed (NVMe), universal flash memory (UFS), Secure Digital (SD), Multi Media Card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered memory (rdimm), and/or load reduced DIMM (lrdimm).

Fig. 2 is a diagram illustrating the structure of the memory device 100 shown in fig. 1.

Referring to fig. 2, the memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

Memory cell array 110 may include a plurality of memory blocks BLK1 through BLKz. A plurality of memory blocks BLK1 through BLKz may be coupled to row decoder 121 by row lines RL. The plurality of memory blocks BLK1 through BLKz may be coupled to the page buffer group 123 through bit lines BL1 through BLn. Each of the plurality of memory blocks BLK1 through BLKz may include a plurality of memory cells. According to an embodiment, the plurality of memory cells may be non-volatile memory cells. Memory cells coupled to the same word line may be defined as one page. Thus, each memory block may include a plurality of pages.

The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

Each memory cell included in the memory cell array 110 may include a Single Level Cell (SLC) storing one bit of data, a Multi Level Cell (MLC) storing two bits of data, a Triple Level Cell (TLC) storing three bits of data, or a Quadruple Level Cell (QLC) storing four bits of data.

The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 in response to control of the control logic 130. The peripheral circuits 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row line RL and the bit lines BL1 through BLn or discharge the applied voltages in response to control by the control logic 130.

Peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a set of page buffers 123, a column decoder 124, input/output circuitry 125, and sensing circuitry 126.

Row decoder 121 may be coupled to memory cell array 110 by row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. According to an embodiment, the word lines may include a normal word line and a dummy word line. According to an embodiment, the row line RL may also include a tube select line.

The row decoder 121 may decode a row address RADD received from the control logic 130. The row decoder 121 may select at least one memory block among the memory blocks BLK1 through BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and apply a program pass voltage having a voltage level lower than the program voltage to unselected word lines. During a program verify operation, the row decoder 121 may apply a verify voltage to a selected word line and a verify pass voltage having a voltage level higher than the verify voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage having a voltage level higher than the read voltage to unselected word lines.

According to an embodiment, the erase operation of the memory device 100 may be performed in units of memory blocks. During an erase operation, the row decoder 121 may select one of the memory blocks according to the decoded address. During an erase operation, the row decoder 121 may apply a ground voltage to word lines coupled to a selected memory block.

The voltage generator 122 may operate in response to control by the control logic 130. The voltage generator 122 may generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. More specifically, the voltage generator 122 may generate various operation voltages Vop applied to perform a program operation, a read operation, and an erase operation in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verify voltage, a pass voltage, a read voltage, and an erase voltage in response to control of the control logic 130.

According to an embodiment, the voltage generator 122 may generate the internal supply voltage by adjusting the external supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operation voltage of the memory device 100.

According to an embodiment, the voltage generator 122 may generate the plurality of voltages using an external power supply voltage or an internal power supply voltage.

For example, the voltage generator 122 may include a plurality of pumping capacitors that receive the internal supply voltage and generate the plurality of voltages by selectively enabling the plurality of pumping capacitors in response to control by the control logic 130.

The generated plurality of voltages may be supplied to the memory cell array 110 through the row decoder 121.

The page buffer group 123 may include first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn may be coupled to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn are operable in response to control of the control logic 130. More specifically, the first to nth page buffers PB1 to PBn may operate in response to page buffer control signals PBSIGNALS. For example, the first to nth page buffers PB1 to PBn may temporarily store data received through the first to nth bit lines BL1 to BLn, or may sense voltages or currents of the bit lines BL1 to BLn during a read operation or a verify operation.

More specifically, during a program operation, when a program voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn may transfer DATA received through the input/output circuit 125 to a selected memory cell through the first to nth bit lines BL1 to BLn. The memory cells of the page selected according to the transferred DATA can be programmed. During a program verify operation, the first to nth page buffers PB1 to PBn may read page data from selected memory cells by sensing voltages or currents received through the first to nth bit lines BL1 to BLn, respectively.

During a read operation, in response to control of the column decoder 124, the first to nth page buffers PB1 to PBn may read DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read DATA to the input/output circuit 125.

During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn or may apply an erase voltage.

The column decoder 124 may transfer data between the input/output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data line DL, or may exchange data with the input/output circuit 125 through the column line CL.

The input/output circuit 125 may transfer commands CMD and addresses ADDR received from the memory controller 200 shown and described with reference to fig. 1 to the control logic 130 or may exchange DATA with the column decoder 124.

During a read operation or a verify operation, the sensing circuit 126 may generate a reference current in response to the permission bit VRYBIT signal and compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a PASS signal PASS or a FAIL signal FAIL.

The control logic 130 may control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT in response to the command CMD and the address ADDR. For example, control logic 130 may control a read operation of a selected memory block in response to a sub-block read command and address. In addition, the control logic 130 may control an erase operation of a selected sub-block included in the selected memory block in response to the sub-block erase command and the address. In addition, control logic 130 may determine whether the verify operation passed or failed in response to PASS signal PASS or FAIL signal FAIL. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be control logic circuitry that operates according to an algorithm and/or a processor that executes control logic code.

Fig. 3 is a diagram illustrating an embodiment of the memory cell array 110 shown in fig. 2.

Referring to fig. 2 and 3, fig. 3 is a circuit diagram illustrating one memory block BLKa among a plurality of memory blocks BLK1 through BLKz included in the memory cell array 110 illustrated in fig. 2.

The first selection line, the word line, and the second selection line arranged in parallel with each other may be coupled to the memory block BLKa. For example, word lines may be arranged parallel to each other between a first select line and a second select line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL.

More specifically, the memory block BLKa may include a plurality of strings coupled between the bit lines BL1 to BLn and the source lines SL. Bit lines BL 1-BLn may be respectively coupled to the strings, and source lines SL may be commonly coupled to the strings. Since these strings may have the same configuration, the string ST coupled to the first bit line BL1 is described as an example.

The string ST may include a source select transistor SST, a plurality of memory cells F1 to F16, and a drain select transistor DST coupled in series between a source line SL and a first bit line BL 1. Each string ST may include at least one source select transistor SST, at least one drain select transistor DST, and more memory cells than the memory cells F1 through F16 shown in fig. 3.

A source of the source select transistor SST may be coupled to a source line SL, and a drain of the drain select transistor DST may be coupled to a first bit line BL 1. The memory cells F1 through F16 may be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be coupled to a source select line SSL, the gates of the drain select transistors DST may be coupled to a drain select line DSL, and the gates of the memory cells F1 to F16 may be coupled to a plurality of word lines WL1 to WL16, respectively. A group of memory cells coupled to the same word line among memory cells included in different strings ST may be referred to as a physical page PPG. Accordingly, the memory block BLKa may include as many physical pages PPG as the number of word lines WL1 to WL 16.

A single memory cell may store one bit of data. Typically, such a memory cell is referred to as a Single Level Cell (SLC). One Physical Page (PPG) including the SLC may store data of one Logical Page (LPG). The data of one LPG may include as many data bits as the number of memory cells included in one PPG. Alternatively, a single memory cell may store two or more bits of data. Typically, such a memory cell is referred to as a multi-level cell (MLC). One PPG including an MLC may store data of two or more logical LPGs.

A single memory cell storing two or more bits of data may be referred to as a multi-level cell (MLC). Recently, however, as the number of data bits stored in a single memory cell increases, a multi-level cell (MLC) may refer to a memory cell storing two bits of data, a memory cell storing three or more bits of data is referred to as a Triple Level Cell (TLC), and a memory cell storing four or more bits of data is referred to as a Quad Level Cell (QLC). In addition to the above-described memory cells, various types of memory cells storing multi-bit data have been developed, and this embodiment is applicable to the memory device 100 storing two or more bits of data.

According to another embodiment, the memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked over a substrate. The plurality of memory cells may be arranged in the + X direction, + Y direction, and + Z direction.

Fig. 4 is a diagram illustrating a plurality of dies included in the memory device 100 shown in fig. 1.

Referring to fig. 4, memory device 100 may include a first DIE1 and a second DIE 2. First DIE1 and second DIE2 may be coupled to memory controller 200 through first channel CH1 and second channel CH2, respectively. Each of first DIE1 and second DIE2 may include multiple planes. Each of the plurality of planes may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of pages. Each of the plurality of pages may include a plurality of memory cells.

According to the embodiment shown in fig. 4, memory device 100 includes two DIEs, i.e., a first DIE1 and a second DIE 2. However, according to another embodiment, the memory device 100 may include more than two dies.

According to an embodiment, multiple dies may perform operations independently of each other. In other words, multiple dies may perform operations simultaneously or at different times.

Memory controller 200 may control operations performed on first DIE1 and second DIE2 independently of each other through channels CH1 and CH2, respectively. For example, memory controller 200 may control operations performed on a first DIE DIE1 via a first channel CH1 and operations performed on a second DIE DIE2 via a second channel CH 2.

Thus, memory controller 200 may output commands CMD, addresses, and data through the respective channels to perform operations on first DIE1 and second DIE 2. Operations may be performed on the first DIE1 and the second DIE2 based on commands CMD, addresses, and data received through the first channel CH1 and the second channel CH 2. The operation performed on first DIE1 and second DIE2 may be a program (or write) operation, a read operation, or an erase operation. Data for first DIE DIE1 and second DIE DIE2 may be transferred to memory controller 200 via first channel CH1 and second channel CH2, respectively.

When operations are performed on the plurality of dies in response to control of the memory controller 200, the plurality of dies may consume current (power). The current consumed by each of the plurality of dies may vary depending on the operation. For example, the current consumed during a program operation, a read operation, or an erase operation may vary. In addition, the current consumed during a precharge operation, a discharge operation, or a pulse application operation included in a program operation, a read operation, or an erase operation may vary.

According to an embodiment, when an operation in which all of a plurality of dies consume a peak current is performed, reliability of a memory device may be deteriorated. In other words, since the amount of current consumed by the storage device becomes maximum, it may be difficult to ensure the reliability of data stored in the storage device.

When it is predicted that an operation in which all of the plurality of dies consume the peak current is performed, the operation on the dies other than one die is suspended until the operation on the one die is completed. However, this approach may delay the completion of the operation and may be inefficient.

Thus, according to embodiments of the present disclosure, a method of operating a die may be provided. More specifically, according to the method of operating the dies, when all signals received from the plurality of dies are busy signals, the busy time period is subdivided into sub-periods, and the operation of the dies is suspended only during the sub-periods in which the peak current occurs.

Fig. 5 is a diagram showing the amount of current consumed by each of two dies and the total amount of current obtained by adding up the amounts of current consumed by the dies.

Fig. 5 illustrates variations of the amount of current consumed by the respective DIEs, the ready/busy signal R/B output from the respective DIEs, and the total amount of current obtained by adding up the amounts of current consumed by the first DIE1 and the second DIE 2.

According to an embodiment, first DIE1 and second DIE2 may only perform operations during time period t11 through t 17. In other words, each of first CURRENT1, which is indicative of the amount of CURRENT consumed by first DIE1, and second CURRENT2, which is indicative of the amount of CURRENT consumed by second DIE2, may have a non-zero value only during time period t11 to t17, and may be "0" outside of time period t11 to t 17.

In addition, the ready/busy signal R/B output from the first DIE1 and the second DIE2 may be in a high state at a time before t11 and at a time after t17, and may be in a low state during periods t11 to t 17. In other words, first DIE1 and second DIE2 may be in a ready state before time t11 and after time t17, and may be in a busy state only during time period t11 through t 17.

As a result, during the time before t11 and the time after t17, since first DIE1 and second DIE2 are in a standby state in which no operation is performed, first total current CUR _ SUM1 obtained by adding up the amounts of current consumed by first DIE1 and second DIE2 may be 0. However, the first total current CUR _ SUM1 during the period t11 to t17 may take a value obtained by adding up the amounts of current consumed during the respective sub-periods within the period t11 to t 17.

In fig. 5, assume that each of first DIE1 and second DIE2 performs a programming operation. Accordingly, a precharge operation, a discharge operation, a program voltage application operation, a verify voltage application operation, a pass voltage application operation, and the like may be performed during the period t11 to t 17.

For example, the period t11 to t17 in which the program operation is performed may be subdivided into sub periods t11 to t12, t12 to t13, t13 to t14, t14 to t15, t15 to t16, and t16 to t17 in which sub-operations of the program operation are performed. The amount of current consumed during each subinterval may vary depending on the sub-operation being performed in that subinterval. In other words, the first CURRENT1 and the second CURRENT2 may have various values that change from sub-period to sub-period according to the sub-operation performed by the respective die.

According to an embodiment, both first DIE1 and second DIE2 may consume peak current during subintervals t12 through t13 among the busy subintervals in intervals t11 through t 17. In other words, during the sub-periods t12 to t13, an operation consuming a peak current among sub-operations included in the program operation may be simultaneously performed on the first DIE1 and the second DIE2, and a first total current CUR _ SUM1 obtained by adding up current amounts consumed by the first DIE1 and the second DIE2 may have a maximum value.

When multiple dies consume peak current during the same busy period, operation on one of the dies may be suspended until the end of the entire busy period. However, when suspending operations on one of the dies until the end of the busy period, completion of the operations may be delayed and inefficient.

Fig. 6 is a diagram illustrating operation of two dies during a period when the peak currents of the dies overlap.

Fig. 6 shows ready/busy signal R/B output from first DIE1 and second DIE 2.

It is initially predictable that first DIE1 and second DIE2 are in a busy state during time period t21 through t 22. In other words, during time period t 21-t 22, ready/busy signal R/B output from first DIE1 and second DIE2 may be in a low state, and at times other than time period t 21-t 22, ready/busy signal R/B output from first DIE1 and second DIE2 may be in a high state.

However, in time periods t 21-t 22, peak currents may occur for both dies. In other words, the period during which the amount of current consumed by first DIE1 peaks may be the same period during which the amount of current consumed by second DIE2 peaks.

When peak currents of multiple dies occur at the same time period, operations on dies other than one die may be delayed by DELAY until the busy state of the one die ends. Thus, the peak current now occurs in a different period.

In other words, referring to fig. 6, when peak currents of the respective DIEs occur at the same time period t21 to t22, the memory device 100 shown in fig. 4 may suspend an operation on the second DIE2 for the entire time period t21 to t22 during which the first DIE1 is in a busy state, may DELAY an operation to be performed on the second DIE2 by DELAY, and may perform the delayed operation on the second DIE2 during a later time period t22 to t 23. Accordingly, as shown in fig. 6, the ready/busy signal R/B output from the second DIE2 may be in a high state outside the time period t22 to t23 and in a low state during the time period t22 to t 23.

As a result, memory device 100 shown in fig. 4 may suspend operation of one DIE (i.e., second DIE2 according to the embodiment shown in fig. 6) until a later period when peak currents of first DIE1 and second DIE2 overlap each other in the same period. Operation of second DIE2 may be suspended until the end of the busy state of first DIE 1.

When the operation of second DIE2 is suspended until the end of the busy state of first DIE1, the delay time of the operation performed on second DIE2 may increase and the operation may be inefficient.

Accordingly, the present disclosure teaches a method of delaying operation only during the sub-period when peak current occurs.

Fig. 7 is a diagram illustrating prevention of peak currents of different dies from occurring during the same sub-period according to an embodiment.

Referring to fig. 5 and 7, fig. 7 illustrates an implementation of the sub-period delay when the peak currents of different dies initially occur during the same sub-period as illustrated in fig. 5. In other words, the second CURRENT2 consumed by the second DIE2 shown in fig. 7 and the ready/busy signal R/B output from the second DIE2 correspond to the amount of CURRENT and signals when the operation performed on the second DIE2 shown in fig. 5 is delayed.

According to an embodiment, in fig. 5 and 7, the first CURRENT1 consumed by the first DIE1 is the same as the ready/busy signal R/B output from the first DIE 1. However, since sub-periods in which peak CURRENTs occur in first DIE1 and second DIE2 overlap each other as shown in fig. 5, the second CURRENT2 consumed by second DIE2 and the ready/busy signal R/B output from second DIE2 shown in fig. 5 may be different from the second CURRENT2 consumed by second DIE2 and the ready/busy signal R/B output from second DIE2 shown in fig. 7.

According to an embodiment, the sub-period during which peak current occurs in first DIE1 may overlap with the sub-period during which peak current occurs in second DIE 2. Since the periods during which the peak currents occur overlap each other, the operation of the second DIE2 between the first DIE1 and the second DIE2 may be delayed. Alternatively, according to another embodiment, the operation of first DIE1 between first DIE1 and second DIE2 may be delayed.

Referring to fig. 5, according to an embodiment, the occurrence of peak currents in both first DIE1 and second DIE2 during sub-periods t12 through t13 may suspend operations performed on second DIE2 during sub-periods t12 through t 13. In other words, operations performed on second DIE2 may be delayed and performed later.

For example, operations performed on the second DIE2 may be suspended during the sub-period t12 through t13, and the ready/busy signal R/B output from the second DIE2 may be in a high state. In other words, ready/busy signal R/B may be output indicating that second DIE2 is in a standby state. The second CURRENT2 consumed by second DIE2 may be "0" due to suspension of operations performed on second DIE 2. The suspended operation may be delayed as long as the sub-period in which the peak current overlap occurs.

Referring to fig. 7, the sub-period during which peak current occurs in first DIE1 and second DIE2 is t12 through t13, and operations performed on second DIE2 may be suspended during sub-period t12 through t13 (at time t13 minus t12, tsus).

According to an embodiment, the operation delayed at the sub-period t12 to t13 may be performed during the period t13 to t 14. In other words, operations performed on second DIE2 may be suspended for as long as the sub-period during which peak current overlap occurs, and the suspended operations may be resumed later.

Due to the introduced sub-period delay described above, the sub-period during which peak current occurs in first DIE1 is no longer the same sub-period during which peak current occurs in second DIE 2. In other words, the sub-period during which peak current occurs in first DIE1 is still t 12-t 13, while the sub-period during which peak current occurs in second DIE2 has shifted to t 13-t 14.

Accordingly, since the operation performed on the second DIE2 is delayed, the ready/busy signal R/B output from the second DIE2 may be in a low state during the sub-period t13 to t 28. In other words, the operation may be performed on second DIE2 for a delay time tsus, and a ready/busy signal R/B in a low state may be output during sub-period t17 to t 28.

Thereafter, when the sub-periods in which peak currents occur in first DIE1 and second DIE2 again overlap each other, operation of one of first DIE1 and second DIE2 may be again suspended.

As a result, when the sub-periods in which the peak currents occur in the plurality of dies overlap with each other, the operation of at least one die among the plurality of dies may be delayed as long as the sub-periods overlap with each other and then may be performed, so that the overlap of the sub-periods in which the peak currents occur may be mitigated. When the overlap of the sub-periods of the peak current occurs is mitigated, the reliability of the data stored in the storage device may be improved.

Fig. 8 is a graph showing a comparison between the total amount of current shown in fig. 5 and the total amount of current shown in fig. 7.

Referring to fig. 5, 7 and 8, fig. 8 illustrates the first total CURRENT CUR _ SUM1 shown in fig. 5 and the second total CURRENT CUR _ SUM2 obtained by adding the first CURRENT1 and the second CURRENT2 shown in fig. 7. In other words, fig. 8 shows first total current CUR _ SUM1 as the total amount of current consumed by first DIE1 and second DIE2 when operations performed on second DIE2 are not delayed as shown in fig. 5 and second total current CUR _ SUM2 as the total amount of current consumed by first DIE1 and second DIE2 when operations performed on second DIE2 are delayed as shown in fig. 7.

Referring to fig. 5, first total current CUR _ SUM1 may refer to a total amount of current consumed by first DIE1 and second DIE2 when operation of one DIE among first DIE1 and second DIE2 is not delayed even when there is a period in which sub-periods in which peak currents occur in first DIE diee 1 and second DIE2 overlap.

According to an embodiment, during time period t 12-t 13, first total current CUR _ SUM1 may have a maximum value since an operation of one of first DIE1 and second DIE2 is not delayed. In addition, the deviation of the value of the first total current CUR _ SUM1 may be large according to the sub-period.

However, referring to fig. 7, the second total current CUR _ SUM2 may refer to a total amount of current consumed by the first DIE1 and the second DIE2 when an operation on the second DIE2 is delayed due to an overlap of a sub-period in which a peak current occurs in the first DIE1 and a period in which a peak current occurs in the second DIE 2.

According to an embodiment, during sub-period t 13-t 14 instead of sub-period t 12-t 13, second total current CUR _ SUM2 may have a maximum value since operations performed on second DIE2 are delayed. In addition, the deviation of the value of the second total current CUR _ SUM2 may be small according to the period.

Fig. 9 is a diagram showing the configuration of the memory controller 200 shown in fig. 1 and the process of outputting a suspend command.

The memory controller 200 shown in fig. 9 may include a state information determination component 210 and a peak current controller 220.

According to an embodiment, status information determining component 210 may receive a ready/busy signal R/B from each of a plurality of dies included in memory device 100. The ready/busy signal R/B may indicate whether the die is in a busy state where the die is performing operations or a ready state where the die is not performing operations.

According to an embodiment, the status information determining component 210 may output a status read command SR _ CMD to the memory device 100 when all ready/busy signals R/B received from the plurality of dies, respectively, indicate a busy state (i.e., a low state). According to an embodiment, a status read command SR _ CMD may be output to determine whether the amount of current consumed by the respective dies and the period during which the peak current occurs overlap. In other words, the status read command SR _ CMD may indicate that information regarding the amount of current consumed by the die should be output.

The memory device 100 may output the STATUS information STATUS _ INF in response to the STATUS read command SR _ CMD. The STATUS information STATUS _ INF may include information about the amount of current consumed by the individual die when all of the plurality of dies are in a busy state.

For example, a period for maintaining a busy state may be divided into a plurality of sub-periods, and information on the amount of current consumed per sub-period of each die may be included in the state information STATUS _ INF. In other words, the memory device 100 may divide a busy period (i.e., a period in which a busy state is maintained) into a plurality of sub-periods, and may output information on an amount of current consumption corresponding to each of the plurality of sub-periods per die.

According to an embodiment, the period may be divided into a plurality of sub-periods according to a predetermined length or a predetermined operation. In other words, the period in which the busy state is maintained may be divided into sub-periods each having a predetermined length, or may be divided according to a busy sub-operation (e.g., a precharge operation, a discharge operation, or a voltage application operation).

According to an embodiment, the STATUS information determining component 210 may receive STATUS information STATUS _ INF. The STATUS information determining component 210 may determine whether to suspend operation of at least one die among the plurality of dies included in the memory device 100 and a time when the operation is suspended based on the STATUS information STATUS _ INF.

For example, the state information determining component 210 may determine to suspend operation of at least one die among the plurality of dies when it is determined that sub-periods in which peak currents occur in the plurality of dies overlap with each other based on the state information STATUS _ INF. Further, state information determining component 210 may determine to suspend operation during the sub-period when peak current overlap occurs.

When the state information determining component 210 determines to SUSPEND operation of at least one die among a plurality of dies included in the memory device 100, the state information determining component 210 may generate SUSPEND information SUSPEND _ INF. The SUSPEND information SUSPEND _ INF may include information on a die that SUSPENDs an operation and information on a sub-period during which an operation on a corresponding die is suspended. The state information determining component 210 may output the generated pause information SUSPEND _ INF to the peak current controller 220.

The peak current controller 220 may output a SUSPEND command SUSPEND _ CMD to the memory device 100 based on the SUSPEND information SUSPEND _ INF. In other words, the peak current controller 220 may control the corresponding die to SUSPEND an operation to be performed on the corresponding die during a suspension sub-period included in the suspension information SUSPEND _ INF (i.e., a sub-period during which the operation on the corresponding die is suspended).

According to an embodiment, the memory device 100 may receive a SUSPEND command SUSPEND _ CMD from the peak current controller 220 and SUSPEND an operation of a corresponding die based on the SUSPEND command SUSPEND _ CMD.

After suspending operation on the corresponding die in response to the SUSPEND command SUSPEND — CMD, the peak current controller 220 may output a resume command to resume the suspended operation when the SUSPEND sub-period ends.

Fig. 10 is a diagram illustrating a method of subdividing overlapping busy periods.

Fig. 10 illustrates a plurality of sub-periods included in the STATUS information STATUS _ INF when all ready/busy signals R/B output from a plurality of dies included in the memory device 100 illustrated in fig. 9 indicate a busy state.

In fig. 10, it is assumed that the number of dies included in the memory device 100 shown in fig. 9 is two. In other words, in fig. 10, assume that memory device 100 shown in fig. 9 includes first DIE1 and second DIE 2. According to another embodiment, the memory device 100 shown in FIG. 9 may include more than two dies.

According to an embodiment, all ready/busy signals R/B output from first DIE1 and second DIE2 may indicate a busy state. In other words, first DIE DIE1 and second DIE DIE2 may be in a busy state at the same time.

Referring to fig. 10, during time periods t 21-t 26, both first DIE1 and second DIE2 may be in a busy state where first DIE1 and second DIE2 perform operations.

The state information determination component 210 shown in fig. 9 may output the state read command SR _ CMD to the memory device 100 shown in fig. 9, and the memory device 100 shown in fig. 9 may output the state information STATUS _ INF corresponding to the state read command SR _ CMD to mitigate overlap of peak currents of the first DIE1 and the second DIE 2. The state information STATUS _ INF may divide the busy period into a plurality of sub periods and may include information on the amount of current consumed during the plurality of sub periods.

In fig. 10, the busy period for each of first DIE1 and second DIE2 may be divided into sub-periods a1 through a 9. The busy period may be divided into the sub-periods a1 to a9 according to the length of a predetermined sub-period or the length of a predetermined operation (e.g., a precharge operation, a discharge operation, or a voltage application operation).

According to an embodiment, sub-period A1 may correspond to time periods t 21-t 22, sub-period A3 may correspond to sub-period t 22-t 23, sub-period A5 may correspond to sub-period t 23-t 24, sub-period A7 may correspond to time periods t 24-t 25, and sub-period A9 may correspond to time periods t 25-t 26. Accordingly, the memory device 100 shown in fig. 9 may generate information on the amount of current consumed during each sub-period in response to the STATUS read command SR _ CMD and may output the generated information as the STATUS information STATUS _ INF.

A method of the memory device 100 shown in fig. 9 outputting the STATUS information STATUS _ INF is described with reference to fig. 11A and 11B.

Fig. 11A and 11B are diagrams illustrating the STATUS information STATUS _ INF output from the memory device 100.

Referring to fig. 11A and 11B, fig. 11A illustrates a BINARY NUMBER corresponding to the CURRENT consumption CURRENT, and fig. 11B illustrates a method of outputting the STATUS information STATUS _ INF.

According to an embodiment, the CURRENT consumption amount CURRENT may have a value from 0 to 100, and may be a value belonging to one range among four ranges shown in fig. 11A. The unit of the CURRENT consumption CURRENT may be milliampere (mA), microampere (μ a), or nanoamp (nA).

In fig. 11A, the CURRENT consumption amount CURRENT may belong to one range among predetermined ranges. According to an embodiment, the range may be subdivided into more ranges as the CURRENT consumption CURRENT increases. In other words, in order to minimize the overlap of the periods in which the peak CURRENTs occur, the range may be subdivided into more ranges as the CURRENT consumption amount CURRENT increases.

Referring to the example shown in fig. 11A, when the CURRENT consumption amount CURRENT falls within a range of 0 to 50 units, a BINARY NUMBER corresponding to the CURRENT consumption amount CURRENT may be "00". When the CURRENT consumption amount CURRENT falls within a range of 51 to 75 units, a BINARY NUMBER corresponding to the CURRENT consumption amount CURRENT may be "01". When the CURRENT consumption amount CURRENT falls within the range of 76 to 90 units, a BINARY NUMBER corresponding to the CURRENT consumption amount CURRENT may be "10". When the CURRENT consumption amount CURRENT falls within the range of 91 to 100 units, a BINARY NUMBER corresponding to the CURRENT consumption amount CURRENT may be "11".

According to another embodiment, when the range to which the CURRENT consumption amount CURRENT belongs is divided into five or more ranges, the BINARY NUMBER indicating the corresponding CURRENT consumption amount CURRENT may be one of "000", "001", "010", "011", "100", "101", "110", and "111". In other words, when the range to which the CURRENT consumption amount CURRENT belongs is subdivided into more ranges, the number of bits indicating the corresponding CURRENT consumption amount CURRENT may be increased.

Referring to fig. 11B, the state information STATUS _ INF is represented in eight bits and may be output to the memory controller 200 shown in fig. 9 by coupling the memory device 100 shown in fig. 9 to input/output pins DQ1 through DQ8 of the memory controller 200 shown in fig. 9. In other words, eight bits indicating the state information STATUS _ INF may be output through the input/output pins DQ1 through DQ 8.

In addition, during a busy period of a plurality of dies included in the memory device 100 shown in fig. 9, the busy period may be divided into sub-periods to output STATUS information STATUS _ INF every sub-period. In other words, when a bit indicating the CURRENT consumption amount CURRENT corresponding to one sub-period among the plurality of sub-periods is output through the input/output pins DQ1 to DQ8, the bit indicating the CURRENT consumption amount CURRENT corresponding to the sub-period after the one sub-period may be output.

According to an embodiment, when the amount of CURRENT consumed by the die falls within a range of 0 to 50, a BINARY NUMBER corresponding to the amount of CURRENT consumption CURRENT may be "00". Accordingly, the memory device 100 shown in fig. 9 may output "0" through the input/output pin DQ1 and "0" through the input/output pin DQ 2.

According to an embodiment, when the amount of CURRENT consumed by the die falls within a range of 51 to 75, a BINARY NUMBER corresponding to the amount of CURRENT consumption CURRENT may be "01", a "0" may be output through the input/output pin DQ1, and a "1" may be output through the input/output pin DQ 2. When the amount of CURRENT consumed by the die falls within the range of 76 to 90, a BINARY NUMBER corresponding to the amount of CURRENT consumed CURRENT may be "10", a "1" may be output through the input/output pin DQ1, and a "0" may be output through the input/output pin DQ 2. When the amount of CURRENT consumed by the die falls within the range of 91 to 100, a BINARY NUMBER corresponding to the amount of CURRENT consumed CURRENT may be "11", a "1" may be output through the input/output pin DQ1, and a "1" may be output through the input/output pin DQ 2.

According to an embodiment, the information indicating the ready/busy STATUS of the die and/or the information indicating whether the operation performed on the die passes or fails may be represented by the remaining bits other than two bits indicating the amount of current consumed by the die among the eight bits indicating the STATUS information STATUS _ INF.

According to another embodiment, when the range to which the CURRENT consumption amount CURRENT belongs is divided into five or more ranges, the CURRENT consumption amount CURRENT may be represented by three or more bits among eight bits indicating the STATUS information STATUS _ INF.

Fig. 12 is a diagram illustrating a method of determining whether sub-periods in which peak currents occur overlap based on the state information STATUS _ INF. For example, whether the peak current of each of DIE1 and DIE2 occurs in the same sub-period.

Referring to fig. 10, 11A, 11B, and 12, a first column of the table shown in fig. 12 may indicate the sub-periods a1 through a9 shown in fig. 10, a second column may indicate binary numbers corresponding to the amount of current consumed by the first DIE1 during the sub-periods a1 through a9 shown in fig. 10, respectively, and a third column may indicate binary numbers corresponding to the amount of current consumed by the second DIE2 during the sub-periods a1 through a9 shown in fig. 10, respectively.

According to an embodiment, during sub-periods a 1-a 9, first DIE1 and second DIE2 may be in a busy state. The busy state of first DIE1 and second DIE2 may be divided into sub-periods a1 through a9, and the amount of current consumed by first DIE1 and second DIE2 during each of sub-periods a1 through a9 may be output as state information STATUS _ INF to memory controller 200 shown in fig. 9.

The memory controller 200 shown in fig. 9 may determine whether sub-periods in which peak currents occur overlap each other based on the STATUS information STATUS _ INF received from the memory device 100 shown in fig. 9.

For example, during sub-period a1, the sub-periods in which peak currents occur in first DIE1 and second DIE2 may overlap, since the binary number corresponding to the amount of current consumed by first DIE1 during sub-period a1 is "11" and the binary number corresponding to the amount of current consumed by second DIE2 during sub-period a1 is "11". In other words, since both of the amounts of current consumed by the respective DIEs are binary numbers corresponding to the range indicating the maximum amount of current consumption shown in fig. 11A, the peak current in the first DIE1 and the peak current in the second DIE2 may occur simultaneously during the sub-period a 1.

Accordingly, memory controller 200 shown in fig. 9 may output a pause command to memory device 100 shown in fig. 9 indicating that memory device 100 shown in fig. 9 will pause operation of one of first DIE1 and second DIE2 for a time corresponding to sub-period a 1.

When a suspend command is output to memory device 100 shown in fig. 9, memory device 100 shown in fig. 9 may suspend operation of one of first DIE1 and second DIE2 for a time corresponding to sub-period a1 in response to the suspend command.

Fig. 13 is a diagram illustrating an operation of a storage controller according to an embodiment.

Referring to fig. 13, in step S1301, when the memory controller receives busy signals from all of the plurality of dies, the memory controller may output a status read command to the respective dies. A status read command may be output to determine whether the amount of current consumed by the various dies and the sub-periods during which peak current occurs overlap. In other words, the status read command may instruct the die to output information about the amount of current consumed by the die.

In step S1303, the memory controller may receive status information corresponding to the status read command from the memory device. The status information may include information about the amount of current consumed by the individual die when all of the plurality of dies are in a busy state. Further, the state information may divide a period in which a busy state is maintained into a plurality of sub-periods, and may include information on an amount of current consumed per sub-period by the respective dies.

In step S1305, the storage controller may generate pause information based on the state information. For example, the memory controller may generate the pause information when an amount of current consumption corresponding to a predetermined sub-period among the plurality of sub-periods has a maximum value in both the first die and the second die. In other words, the memory controller may generate the pause information when the sub-periods of peak current in the first die and the second die overlap. The suspension information may include information about the die between the first die and the second die for which operation was suspended and information about the time for which operation was suspended. The time at which operation is suspended may correspond to a sub-period during which peak currents of the first die and the second die overlap.

However, when the amount of current consumption corresponding to a predetermined sub-period among the plurality of sub-periods is not the peak current in any one of the first die and the second die, the memory controller may not generate the pause information.

In step S1307, the storage controller may output a pause command based on the pause information. In other words, since the pause information includes information on a die, from among the plurality of dies, for which the operation is paused and information on a time at which the operation is paused, the memory controller may output a pause command to the memory device, which instructs the corresponding die to pause the operation for a predetermined time based on the pause information.

Fig. 14 is a diagram illustrating an operation of a storage controller according to an embodiment.

Referring to fig. 14, the memory controller may add the amounts of current consumed per sub-period of the plurality of dies based on the state information received from the memory device at step S1401. The status information may include information about the amount of current consumed by the individual die when all of the plurality of dies are in a busy state. Further, the state information may divide a period in which a busy state is maintained into a plurality of sub-periods, and may include information on an amount of current consumed per sub-period by the respective dies.

In step S1403, the memory controller may determine whether there is a sub-period in which peak currents of different dies overlap among the plurality of sub-periods. In other words, the memory controller may sum the amounts of current consumed per sub-period of the plurality of dies, and may determine whether sub-periods in which peak currents occur in the respective dies overlap based on a result obtained by adding the amounts of current consumption.

When there is no period in which sub-periods of peak current overlap among the plurality of dies (S1403: no), the process flow may proceed to step S1401 again, and the memory controller may add up the amount of current consumed per sub-period by receiving the state information when all dies included in the memory device become busy.

However, when there is a period in which sub-periods of peak currents occurring in a plurality of dies overlap (S1403: YES), the process flow may proceed to step S1405.

In step S1405, the memory controller may output a suspend command to at least one die among the plurality of dies. In other words, a pause command indicating that operation of at least one die should be paused may be output to mitigate overlap of periods of peak current occurrence in multiple dies in the same sub-period. The time at which operation is suspended may correspond to a sub-period during which peak currents overlap.

In step S1407, the memory controller may output a resume command to resume the suspended operation on the die. In other words, since the suspended operation should be resumed for the die that suspended the operation by the suspend command when the time for the suspended operation has elapsed, the memory controller may output a resume command to the memory device.

Fig. 15 is a diagram illustrating another embodiment of the memory controller shown in fig. 1.

The memory controller 1000 may be coupled to a host and a memory device. In response to a request from a host, the memory controller 1000 may access the memory device. For example, the memory controller 1000 may control read operations, program operations, erase operations, and background operations of the memory device. The memory controller 1000 may provide an interface between the memory device and the host. The memory controller 1000 may run firmware for controlling the memory device.

Referring to fig. 15, the memory controller 1000 may include a processor 1010, a memory buffer 1020, an Error Correction Code (ECC) block 1030, a host interface 1040, a buffer controller 1050, a memory interface 1060, and a bus 1070.

Bus 1070 may provide a path between the components of memory controller 1000.

The processor 1010 may control the overall operation of the memory controller 1000 and may perform logical operations. The processor 1010 may communicate with an external host through a host interface 1040 and with a memory device through a memory interface 1060. Further, processor 1010 may communicate with memory buffer 1020 through buffer controller 1050. The processor 1010 may control the operation of the storage device using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

Processor 1010 may perform the functions of a Flash Translation Layer (FTL). Processor 1010 may convert Logical Block Addresses (LBAs) provided by a host to Physical Block Addresses (PBAs) through the FTL. The FTL can receive LBAs and convert the received LBAs to PBAs using a mapping table. There may be various address mapping methods for the FTL according to the mapping unit. Typical address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

Processor 1010 may randomize data received from the host. For example, processor 1010 may randomize data received from a host using a randomization seed. The randomized data can be provided to the memory device as data to be stored and can be programmed in the memory cell array.

According to an embodiment, the processor 1010 may run software or firmware to perform the randomization and the derandomization operations.

According to an embodiment, processor 1010 may determine the amount of current consumed by each of the plurality of dies included in memory device 100 shown in FIG. 9 based on the status information received from memory device 100 shown in FIG. 9. For example, the status information may be output from the memory device 100 shown in fig. 9 in response to a status response command output when all the dies included in the memory device 100 shown in fig. 9 are in a busy state. The status information may divide the busy period of the respective dies into a plurality of sub-periods having the same length, and may include information on the amount of current consumed by the respective dies corresponding to each of the plurality of sub-periods.

Processor 1010 may determine whether sub-periods of peak current occurring in the multiple dies overlap based on the state information. In other words, the processor 1010 may determine whether the maximum current is consumed in all the dies included in the memory device 100 shown in fig. 9 and whether sub-periods in which the dies consume the maximum current overlap.

According to an embodiment, processor 1010 may output a pause command when a sub-period overlap of peak currents occurs in multiple dies. The pause command may indicate that when periods of time during which peak currents occur in the plurality of dies overlap, operation of at least one die among the plurality of dies should be delayed by a sub-period of time during which periods of time during which peak currents occur in the plurality of dies overlap.

The memory device 100 shown in fig. 9 may delay operation of a corresponding die in response to a suspend command by a sub-period where sub-periods of peak currents occur overlap among a plurality of dies.

Memory buffer 1020 may be used as an operating memory, cache memory, or buffer memory for processor 1010. Memory buffer 1020 may store codes and commands that are executed by processor 1010. Memory buffer 1020 may store data processed by processor 1010. Memory buffer 1020 may include static ram (sram) or dynamic ram (dram).

The ECC block 1030 may perform error correction. The ECC block 1030 may perform ECC encoding based on data to be written to the memory device through the memory interface 1060. The ECC encoded data may be transferred to the memory device through the memory interface 1060. ECC block 1030 may perform ECC decoding based on data received from the memory device through memory interface 1060. For example, the ECC block 1030 may be included and disposed in the memory interface 1060 as a component of the memory interface 1060.

The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may perform communication using AT least one of various communication methods such as Universal Serial Bus (USB), serial AT attachment (SATA), serial attached SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), multimedia card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered DIMM (rdimm), and/or load reduced DIMM (lrdimm).

The buffer controller 1050 may control the memory buffer 1020 under the control of the processor 1010.

The memory interface 1060 may communicate with memory devices under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory devices through the channels.

Memory controller 1000 need not include memory buffer 1020 and buffer controller 1050 in all embodiments. Either or both of these components may be provided separately, or either or both of their functions may be performed by one or more other components in the storage controller 1000.

For example, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a non-volatile memory device (e.g., Read Only Memory (ROM)) disposed in the memory controller 1000. In another example, the processor 1010 may load code from a memory device through the memory interface 1060.

For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may transfer data in the memory controller 1000, and the control bus may transfer control information such as commands and addresses in the memory controller 1000. The data bus and the control bus may be isolated from each other so as not to interfere with, or affect, each other. The data bus may be coupled to a host interface 1040, a buffer controller 1050, an ECC block 1030, and a memory interface 1060. The control bus may be coupled to a host interface 1040, processor 1010, buffer controller 1050, memory buffers 1020, and memory interface 1060.

Fig. 16 is a block diagram showing a memory card system 2000 to which a storage device is applied according to an embodiment.

Referring to fig. 16, the memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 may be coupled to a memory device 2200. The memory device 2200 is accessible to the memory controller 2100. For example, the memory controller 2100 may control read operations, write operations, erase operations, and background operations of the memory device 2200. The storage controller 2100 may provide an interface between the memory device 2200 and a host. The memory controller 2100 may execute firmware for controlling the memory device 2200. The memory device 2200 may be configured in the same manner as the memory device 100 shown in fig. 1 described above with reference to fig. 1.

For example, memory controller 2100 may include components such as a Random Access Memory (RAM), a processing unit, a host interface, a memory interface, and ECC blocks.

The memory controller 2100 may communicate with an external device through the connector 2300. The storage controller 2100 may communicate with an external device (e.g., a host) according to a predetermined communication protocol. For example, the storage controller 2100 may communicate with external devices via at least one of various communication protocols such as Universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (pcie), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and/or non-volatile memory at high speed (NVMe) protocols. For example, the connector 2300 may be defined by at least one of the various communication protocols described above.

For example, memory device 2200 may be embodied as one of various non-volatile memory devices such as electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), and spin torque transfer magnetic RAM (STT-MRAM).

The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device and form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card ((MMC, RS-MMC, MMCmicro, or eMMC), a Secure Digital (SD) card (SD, miniSD, microSD, or SDHC), and a Universal Flash (UFS).

According to an embodiment, the memory controller 2100 may determine an amount of current consumed by each of a plurality of dies included in the memory device 2200 based on the state information received from the memory device 2200. For example, the status information may be output from the memory device 2200 in response to a status response command output when all dies included in the memory device 2200 are in a busy state. The status information may divide the busy period of the respective dies into a plurality of sub-periods having the same length, and may include information on the amount of current consumed by the respective dies corresponding to each of the plurality of sub-periods.

The memory controller 2100 may determine whether sub-periods in which peak currents occur in multiple dies overlap based on the state information. In other words, the memory controller 2100 may determine whether the maximum current is consumed in all the dies included in the memory device 2200 and whether sub-periods in which the dies consume the maximum current overlap.

According to an embodiment, memory controller 2100 may output a suspend command when a sub-period overlap of peak currents occurs in multiple dies. The pause command may indicate that operation of at least one die among the plurality of dies should be delayed by a sub-period of peak current overlap.

The memory device 2200 may delay operation of the corresponding die for a sub-period of the die's peak current overlap in response to the suspend command.

Fig. 17 is a block diagram illustrating an example of a Solid State Drive (SSD) system 3000 to which a storage device is applied according to an embodiment.

Referring to fig. 17, SSD system 3000 may include host 3100 and SSD 3200. The SSD 3200 may exchange signals SIG with the host 3100 through the signal connector 3001, and may receive power PWR through the power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

According to an embodiment, the SSD controller 3210 may perform the functions of the storage controller 200 of fig. 1 described above with reference to fig. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, signal SIG may be a signal based on the interface of host 3100 and SSD 3200. For example, the signal SIG may be defined by at least one of various interfaces such as Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (pcie), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and non-volatile memory at high speed (NVMe) interfaces.

According to an embodiment, the SSD controller 3210 may determine an amount of current consumed by each of the plurality of dies included in the plurality of flash memories 3221 to 322n based on status information received from each of the plurality of flash memories 3221 to 322 n. For example, the state information may be output from the plurality of flash memories 3221 to 322n in response to a state response command output when all dies included in the plurality of flash memories 3221 to 322n are in a busy state. The status information may divide the busy period of the respective dies into a plurality of sub-periods having the same length, and may include information on the amount of current consumed by the respective dies corresponding to each of the plurality of sub-periods.

The SSD controller 3210 may determine whether sub-periods of peak current of the die overlap based on the status information. In other words, the SSD controller 3210 may determine whether the maximum current is consumed in all the dies included in the plurality of flash memories 3221 to 322n and whether sub-periods in which the dies consume the maximum current overlap.

According to an embodiment, the SSD controller 3210 may output a pause command when sub-periods of peak current overlap among multiple dies. The pause command may indicate that operation of at least one die among the plurality of dies should be delayed by a sub-period where peak currents of the plurality of dies overlap.

The plurality of flash memories 3221 through 322n may delay operations of the corresponding dies for a sub-period where peak currents overlap in response to a pause command.

The auxiliary power supply 3230 may be coupled to the host 3100 via a power connector 3002. The auxiliary power supply 3230 may be charged using power PWR supplied from the host 3100. When the power PWR is not smoothly supplied from the host 3100, the auxiliary power supply 3230 may supply the power of the SSD 3200. For example, the auxiliary power supply 3230 may be provided inside or outside the SSD 3200. For example, the auxiliary power supply 3230 may be provided on a motherboard and may supply auxiliary power to the SSD 3200.

The buffer memory 3240 can be used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the plurality of flash memories 3221 to 322 n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Fig. 18 is a block diagram illustrating a user system 4000 to which a storage device is applied according to an embodiment.

Referring to fig. 18, the user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may run components included in the user system 4000, an Operating System (OS), or user programs. For example, the application processor 4100 may include a controller, interface, graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may be used as a main memory, an operation memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a Package On Package (POP) to be provided as a single semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communication such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), Wimax, WLAN, UWB, bluetooth, or Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

The memory module 4400 may store data. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transfer data stored in the memory module 4400 to the application processor 4100. For example, the memory module 4400 may be embodied as a non-volatile semiconductor memory device such as a phase change ram (pram) device, a magnetic ram (mram) device, a resistance ram (rram) device, a NAND flash memory device, a NOR flash memory device, or a NAND flash memory device having a three-dimensional (3D) structure. For example, the storage module 4400 may be provided as a removable storage medium (i.e., a removable drive), such as a memory card or an external drive of the user system 4000.

For example, the memory module 4400 may include a plurality of non-volatile memory devices, each of which may operate in the same manner as the memory devices described above with reference to fig. 2 and 3. The memory module 4400 may operate in the same manner as the memory device 50 described above with reference to fig. 1.

According to an embodiment, the application processor 4100 may determine the amount of current consumed by each of the plurality of dies included in the memory module 4400 based on the status information received from the memory module 4400. For example, the status information may be output from the memory module 4400 in response to a status response command output when all of the dies included in the memory module 4400 are in a busy state. The status information may divide the busy period of the respective dies into a plurality of sub-periods having the same length and may include information on the amount of current consumed by the respective dies corresponding to each of the plurality of sub-periods.

The application processor 4100 may determine whether the sub-periods in which the peak currents occur overlap based on the state information. In other words, the application processor 4100 may determine whether the maximum current is consumed in all the dies included in the memory module 4400 and whether sub-periods in which the dies consume the maximum current overlap.

According to an embodiment, the application processor 4100 may output a pause command when sub-periods of peak current overlap in multiple dies. The pause command may indicate that operation of at least one die among the plurality of dies should be overlapped by a sub-period delayed by the occurrence of peak current in the plurality of dies.

The memory module 4400 may delay operation of the corresponding die for a sub-period of time overlapping periods of time during which peak currents occur in the multiple dies in response to the suspend command.

The user interface 4500 may include an interface that inputs data or commands to the application processor 4100 or outputs data to an external device. For example, the user interface 4500 can include user input interfaces such as keyboards, keypads, buttons, touch panels, touch screens, touch pads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric devices. The user interface 4500 may also include user output interfaces such as Liquid Crystal Displays (LCDs), Organic Light Emitting Diode (OLED) display devices, active matrix OLED (amoled) display devices, LEDs, speakers, and monitors.

According to embodiments of the present disclosure, when busy periods of a plurality of dies overlap, the overlapping portion of the busy periods may be subdivided into sub-periods to determine the sub-periods in which peak currents of the plurality of dies overlap. Operation of one of the plurality of dies may be suspended during the sub-period so that performance of the memory device may be improved.

Cross Reference to Related Applications

The present application claims priority from korean patent application No. 10-2020-0063685, filed on the korean intellectual property office on 27/5/2020, the entire disclosure of which is incorporated herein by reference.