阅读说明：本技术 单片集成霍尔电路 (Monolithic integrated Hall circuit ) 是由 朱忻 于 2021-08-06 设计创作，主要内容包括：本发明的实施例公开了一种单片集成霍尔电路,所述单片集成霍尔电路包括含有IC电路的基板；粘结层,所述粘结层位于基板的表面上；磁感应部,所述磁感应部通过粘结层键合到基板上；和电极部,所述电极部位于磁感应部的周边,所述电极部的一端与磁感应部形成欧姆接触,所述电极部的另一端与IC电路的引线端电连接。本发明属于半导体技术领域,通过把化合物半导体霍尔元件集成到含有IC电路的基板上,减少了对原有支撑化合物半导体霍尔元件的衬底的使用需求,减小了整个装置的尺寸。通过引线端设置在粘结层中,增加了引线的固定牢固度。(The embodiment of the invention discloses a monolithic integrated Hall circuit, which comprises a substrate containing an IC circuit; an adhesive layer on a surface of a substrate; a magnetic induction part bonded to the substrate through an adhesive layer; and the electrode part is positioned at the periphery of the magnetic induction part, one end of the electrode part forms ohmic contact with the magnetic induction part, and the other end of the electrode part is electrically connected with a lead terminal of the IC circuit. The invention belongs to the technical field of semiconductors, and reduces the use requirement on the original substrate for supporting the compound semiconductor Hall element and the size of the whole device by integrating the compound semiconductor Hall element on a substrate containing an IC circuit. The lead terminals are arranged in the bonding layer, so that the fixing firmness of the lead is improved.)

1. A monolithically integrated hall circuit comprising:

a substrate including an IC circuit;

an adhesive layer on a surface of a substrate;

a magnetic induction part bonded to the substrate through an adhesive layer; and

and the electrode part is positioned at the periphery of the magnetic induction part, one end of the electrode part forms ohmic contact with the magnetic induction part, and the other end of the electrode part is electrically connected with a lead terminal of the IC circuit.

2. The monolithically integrated Hall circuit of claim 1, wherein,

the substrate is a flexible circuit board or a rigid circuit board containing an IC circuit.

3. The monolithically integrated Hall circuit of claim 2, wherein,

the rigid circuit board is a silicon-based wafer including an IC circuit, and lead terminals of the substrate are electrically connected with electrode portions to form a hybrid IC circuit.

4. The monolithically integrated Hall circuit of claim 2, wherein,

the flexible circuit board comprises a flexible printed circuit board which is made of polyimide or polyester film as a base material.

5. The monolithically integrated Hall circuit of claim 1, wherein,

the lead terminals are provided in the adhesive layer, and interconnection lines for interconnecting the lead terminals and the electrode portions are formed simultaneously with the formation of the electrode portions, or the lead terminals and the electrode portions are connected by leads.

6. The monolithically integrated Hall circuit of claim 1, wherein,

the magnetic induction part is prepared by the following steps:

epitaxially growing a compound semiconductor material film on a semiconductor single crystal substrate as a magnetic induction functional layer of a compound semiconductor Hall;

coating an adhesive layer on at least one of the compound semiconductor material film and the substrate, and bonding the compound semiconductor material film and the substrate face to face through the adhesive layer;

selectively removing a part of the semiconductor single crystal substrate and the compound semiconductor material film, and forming the magnetic induction part by a patterning process;

wherein the magnetic induction part comprises InSb, GaAs, InAs, InGaAs or InGaP.

7. The monolithically integrated Hall circuit of claim 6, wherein,

the mobility of the magnetic induction part with only the semiconductor single crystal substrate removed is greater than 40000cm²and/Vs, the thickness of the magnetic induction part is 500nm-10 μm.

8. The monolithically integrated Hall circuit of claim 6, wherein,

the mobility of the magnetic induction part in which the semiconductor single crystal substrate and a part of the compound semiconductor material film are simultaneously removed is more than 50000cm²Vs and less than 78000cm²and/Vs, the thickness of the magnetic induction part is 10nm-9 μm.

9. The monolithically integrated Hall circuit of any of claims 1-8, wherein,

the bonding layer comprises polyimide or epoxy resin;

the monolithic integrated hall circuit further includes a protective layer that covers at least all of the magnetic induction portion and the electrode portion.

10. The monolithically integrated Hall circuit of claim 9, wherein,

the protective layer includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silica gel, a silicon dioxide, and a polyimide film.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a monolithic integrated hall circuit including a hall element.

Background

The hall element is a magnetic sensor based on the hall effect. The hall effect is a physical phenomenon in which when a magnetic field acts on carriers in a metal conductor or a semiconductor, the carriers are deflected, an additional electric field is generated in a direction perpendicular to a current and the magnetic field, and a lateral potential difference is generated between both ends of the semiconductor. The Hall device made according to the Hall effect can convert the motion parameters of an object into voltage to be output by taking a magnetic field as a working medium, so that the Hall device has the functions of sensing and switching.

The hall element is often a hall chip, and the signal processing circuit adapted to the hall element is integrated on another substrate (referred to as a signal processing circuit board). This results in a complicated and weak wire bonding connection between the hall chip and the signal processing circuit board, and occupies a large volume.

Compound semiconductor materials, GaAs, InSb, InAs, and the like, used for manufacturing the magnetic induction portion of the hall element are expected to have high carrier mobility and thus high hall magnetic induction sensitivity. Semiconductor materials such as InSb are generally prepared by vapor deposition or heteroepitaxy. However, because of the obvious lattice mismatch between the InSb semiconductor material and the foreign substrate, the mobility of the InSb semiconductor material film prepared by heteroepitaxy is not ideal under the condition of thin thickness, and the optimal mobility does not exceed 50000cm²/Vs。

On the one hand, if the heteroepitaxially grown semiconductor material film is thin, the quality of the semiconductor material film is poor and the mobility is too low to meet the expected requirements; on the other hand, if the thickness of the semiconductor material film is increased, the mobility becomes good, but at this time the sheet resistance of the semiconductor material film is lowered, which is disadvantageous in terms of controlling the power consumption of the hall element.

Disclosure of Invention

In view of the above, there is an urgent need for a monolithically integrated hall circuit integrated with a hall element which is expected to include a compound semiconductor material film having high mobility and, at the same time, higher sheet resistance.

In order to solve at least one of the above-mentioned problems occurring in the prior art, an embodiment of the present invention provides a monolithically integrated hall circuit integrated with a hall element, the monolithically integrated hall circuit including a hall element and a signal processing circuit board integrated together, desirably the hall element including a compound semiconductor material film, which has not only high electron mobility but also high sheet resistance at the same time.

According to an aspect of the present invention, there is provided a monolithically integrated hall circuit comprising:

a substrate including an IC circuit;

an adhesive layer on a surface of a substrate;

a magnetic induction part bonded to the substrate through an adhesive layer; and

and the electrode part is positioned at the periphery of the magnetic induction part, one end of the electrode part forms ohmic contact with the magnetic induction part, and the other end of the electrode part is electrically connected with a lead terminal of the IC circuit.

In one example, the substrate is a flexible circuit board or a rigid circuit board containing IC circuitry.

In one example, the rigid circuit board is a silicon-based wafer including an IC circuit, and the lead terminals of the substrate are electrically connected with the electrode portions to form a hybrid IC circuit.

In one example, the flexible circuit board includes a flexible printed circuit board made of a polyimide or polyester film as a base material.

In one example, the lead terminal is provided in the adhesive layer, and an interconnection line interconnecting the lead terminal and the electrode portion is formed at the same time as the electrode portion is formed, or the lead terminal and the electrode portion are connected by a lead.

In one example, the magnetic induction part is prepared by the following steps:

epitaxially growing a compound semiconductor material film on a semiconductor single crystal substrate as a magnetic induction functional layer of a compound semiconductor Hall;

coating an adhesive layer on at least one of the compound semiconductor material film and the substrate, and bonding the compound semiconductor material film and the substrate face to face through the adhesive layer;

selectively removing a part of the semiconductor single crystal substrate and the compound semiconductor material film, and forming the magnetic induction part by a patterning process;

wherein the magnetic induction part comprises InSb, GaAs, InAs, InGaAs or InGaP.

In one example, the mobility of the magnetic induction portion from which only the semiconductor single crystal substrate is removed is larger than 40000cm²and/Vs, the thickness of the magnetic induction part is 500nm-10 μm.

In one example, the mobility of the magnetic induction part where the semiconductor single crystal substrate and a part of the film of the compound semiconductor material are simultaneously removed is more than 50000cm²Vs and less than 78000cm²and/Vs, the thickness of the magnetic induction part is 10nm-9 μm.

In one example, the bonding layer comprises polyimide or epoxy;

the monolithic integrated hall circuit further includes a protective layer that covers at least all of the magnetic induction portion and the electrode portion.

In one example, the protective layer includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silicon gel, silicon dioxide, and a polyimide film.

Other objects and advantages of the present disclosure will become apparent from the following description of the embodiments of the present disclosure, which is made with reference to the accompanying drawings, and can assist in a comprehensive understanding of the present disclosure.

Drawings

These and/or other aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1A is a schematic diagram of a cross-sectional structure of a monolithically integrated Hall circuit according to one embodiment of the invention;

FIG. 1B is another cross-sectional schematic of a monolithically integrated Hall circuit according to one embodiment of the invention;

FIG. 2A shows a schematic cross-sectional structure of heteroepitaxial growth of a compound semiconductor material film having a Hall magnetic induction function on a semiconductor single-crystal substrate;

FIG. 2B is a schematic cross-sectional view of the structure of FIG. 2A after an adhesive layer and a bonding substrate are coated thereon;

FIG. 2C shows a schematic view of the cross-sectional structure after selective removal of the semiconductor single-crystal substrate originally used for hetero-epitaxial growth of the compound semiconductor material film on the basis of the structure of FIG. 2B;

fig. 2D shows a schematic cross-sectional structure after removing a first portion of the film of compound semiconductor material on the basis of the structure of fig. 2C;

FIG. 2E is a schematic cross-sectional structure and a top view of the patterned magnetic induction part prepared based on the structure of FIG. 2D;

FIG. 2F is a schematic cross-sectional view and a top view showing the structure of FIG. 2E after a patterned electrode layer is formed and electrically connected to the lead terminals of the circuit board containing the IC via interconnection lines and a protective layer is formed;

fig. 2G shows a schematic cross-sectional structure and a top view of the structure of fig. 2E after a patterned electrode layer is prepared and the electrode layer is electrically connected to a lead terminal of a circuit board including an IC through a lead, and a protective layer is prepared.

Detailed Description

The technical scheme of the invention is further specifically described by the following embodiments and the accompanying drawings. In the specification, the same or similar reference numerals denote the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the general inventive concept of the present invention and should not be construed as limiting the invention.

As discussed in the background section, GaAs, InSb, InAs and the like, which are materials that can be used to fabricate the compound semiconductor material film, have high electron mobility at room temperature, wherein the electron mobility of the InSb material at room temperature is the highest and can reach 78000cm²and/Vs, therefore, is considered to be the most suitable material for manufacturing the magnetic induction part of the hall element.

The inventors of the present invention have found, based on a long-term study, that a monolithically integrated hall circuit in which a magnetic induction portion has not only high mobility but also high sheet resistance (i.e., low power consumption) can integrate a hall element and a signal processing circuit board together is proposed.

In one embodiment of the present invention, there are two methods for preparing the compound semiconductor material film such as InSb, one is to obtain a polycrystalline InSb film by evaporating an InSb material onto a mica sheet or a silicon oxide substrate by evaporation. Although the InSb film prepared by the method has low manufacturing cost, the quality is poor, and the mobility is generally only 15000cm²Vs to 30000cm²The expected requirement of the Hall element for higher mobility is not met. The other preparation method is to prepare the InSb monocrystal substrate by adopting a homoepitaxial growth method, so that a high-quality InSb monocrystal film can be obtained, and the mobility of the prepared InSb monocrystal film is very high. However, since the semi-insulating InSb single crystal substrate is expensive, there is no method for mass production.

Therefore, in the manufacture of the hall element, other semiconductor single crystal substrates, such as GaAs substrates or Si substrates, are often selected. Although these alternative semiconductor single crystal substrates are relatively inexpensive, they have a large lattice mismatch with InSb, and therefore lead to a decrease in the quality of InSb single crystal films grown on such alternative semiconductor single crystal substrates, and a much lower mobility, typically 30000cm, than that of InSb single crystal films obtained on InSb single crystal substrates²Vs to 50000cm²Vs.

Because of the large lattice mismatch between the InSb film and the semiconductor single crystal substrate, the InSb film grown from the beginning is poor in quality and very low in mobility. As the thickness of the InSb film material increases, the lattice quality becomes better and the mobility increases.

To reach higher than 50000cm²The mobility of/Vs generally requires that the InSb film be grown to a thickness exceeding 1-2 μm, but this case causes a decrease in the sheet resistance of the InSb film due to the thick InSb film thickness, which is disadvantageous for the finally manufactured hall element. The square resistance is reduced, which will result in the power consumption of the whole Hall elementAnd (4) increasing.

See document Oh et al, "Journal of Applied Physics", volume 66, 10 months 1989, 3618-.

It is described that if an InSb film is formed on a GaAs, InP substrate, there is a large lattice mismatch between the substrate and the InSb film, and therefore a large number of misfit dislocations are present in the formed InSb film, and these dislocations and defects generate residual electrons, significantly lowering the electron mobility.

In general, crystal defects of the thin film caused by mismatch with the substrate are conspicuous near the interface of the substrate. Although the density of crystal defects is gradually reduced along with the growth of the thin film, the concentration of crystal defects is high and the electron mobility is lowered. If a thin film of several micrometers is formed, the influence of defects in the vicinity of the interface becomes very small, but such a solution is not only impractical in manufacturing a device, but also causes problems such as reduction in resistance due to the film thickness, increase in power consumption, and the like.

In order to solve this problem, the following methods are proposed: a buffer layer for alleviating lattice mismatch is grown on a GaAs substrate, and high-resistance Al is used_xIn_1-xSb (x.gtoreq.0.07) to produce the above buffer layer, but this results in a defect that the overall film thickness is increased and the mobility of the InSb film is still not sufficiently high (see Liu et al, "Journal of vacuum Science&Technology B "volume 14, 1996 month 5, page 2339-.

The following embodiments of the present invention provide a monolithically integrated hall circuit and a method of manufacturing the monolithically integrated hall circuit, in which a compound semiconductor hall element, the magnetic induction portion of which has high mobility and at the same time has a large sheet resistance as compared with a magnetic induction portion prepared in the related art, is integrated with a signal processing circuit board, and the thickness of the magnetic induction portion and the entire monolithically integrated hall circuit are formed to be relatively small.

As shown in fig. 1A and 2F, a monolithically integrated hall circuit 200 according to an embodiment of the present invention includes a compound semiconductor hall element 100, a substrate 210 including an IC, and an adhesive layer 20. The compound semiconductor hall element 100 includes a magnetic induction portion 30 and an electrode portion 40. Optionally, the compound semiconductor hall element 100 may further include a protective layer 50.

The substrate 210 includes a silicon-based wafer of IC circuits that may be suitable for various uses of the hall element, so that a hybrid IC may be formed after the hall element is formed on the substrate 210 and electrically connected thereto. In one embodiment, substrate 210 is a silicon-based wafer containing ICs (integrated circuits). The form of the integrated circuit included in the substrate 210 is not limited in the present invention. The substrate 210 may be a flexible circuit board so that an irregular shaped object can be detected. Alternatively, the substrate 210 may also be a rigid circuit board, so that detection of regularly shaped objects may be performed.

The adhesive layer 20 is disposed on one surface of the substrate 210 and may comprise any suitable adhesive material such as polyimide or epoxy, or any suitable photoresist.

The magnetic induction portion 30 is bonded to the substrate 210 through the adhesive layer 20, and includes any suitable semiconductor thin film material such as InSb, GaAs, InAs, InGaAs, or InGaP. Alternatively, the magnetic induction portion 30 is generally in an electrically insulated state with the substrate 210. The magnetic induction part 30 may also be stepped in cross section, or rectangular or cross in plan view.

In one example of the present invention, a compound semiconductor hall element manufactured by obtaining the magnetic induction portion 30 in the following manner has advantages of high mobility, large sheet resistance, and appropriate thickness.

As shown in fig. 2A in conjunction, a film 70 of a compound semiconductor material is epitaxially grown on a semiconductor single-crystal substrate 60, wherein the film 70 of the compound semiconductor material includes a first portion 71 of inferior quality grown first and a second portion 72 of superior quality grown subsequently. Here, the first portion 71 and the second portion 72 to be explained do not have a clear interface as shown in the drawing, and they are artificially divided into two portions only for the convenience of the following description.

Referring to fig. 2B, an adhesive layer 20 is coated on the second portion 72 of the compound semiconductor material film 70 and bonded together with the substrate 210 through the adhesive layer 20.

With reference to fig. 2C, 2D, and 2E, the semiconductor single-crystal substrate 60 and the first portion 71 of the compound semiconductor material film 70 are removed, and a patterning process is employed to form the magnetic induction parts 30. The specific process steps can be seen in the flow charts shown in fig. 2A-2G described below, and will not be described again here.

Therefore, the mobility of the magnetic induction part 30 prepared by the above process with only the semiconductor single crystal substrate 60 removed is more than 40000cm²Vs and a thickness of 500nm to 10 μm. Preferably, the mobility of the magnetic induction part 30 where the semiconductor single-crystal substrate 60 and a part of the compound semiconductor material film 71 are simultaneously removed is more than 50000cm²Vs and less than 78000cm²Vs and the sheet resistance can be selectively increased to a target value by etching the thickness of the magnetic induction portion to 10nm-9 μm.

As described previously, in the present invention, the first portion 71 of the compound semiconductor material film 70 of poor quality grown on the semiconductor single-crystal substrate 60 is etched away, and therefore the mobility of the compound semiconductor material film 70 can be made at least larger than 50000cm²/Vs, preferably greater than 60000cm²Vs. In summary, the method of the present invention can select the compound semiconductor material film 70 having an appropriate mobility and thickness while taking into account the thickness and sheet resistance of the compound semiconductor material film 70, and thus not only is the process simple and inexpensive, but also provides a solution to the relative contradiction between mobility and sheet resistance.

Electrode portions 40 are provided on both ends of the magnetic induction portion 30, and as shown in fig. 1A, interconnection lines 212 interconnecting the lead terminals 211 and the electrode portions 40 are formed at the same time as the electrode portions 40 are formed. In the configuration shown in fig. 1B, the left side of the adhesive layer 20 exposes the lead terminals 211 of the IC circuit in the substrate 210 by photolithography or other suitable means, and the lead terminals 211 are electrically connected to the electrode portion 40 by wire bonding 12, thereby forming a hybrid IC circuit. Specifically, fig. 1A shows a method for realizing interconnection through a photolithography patterning process, and fig. 1B shows a scheme for realizing electrical connection through wire bonding.

In an alternative embodiment, the protective layer 50 covers all of the magnetic induction parts 30 and the adhesive layer 20, but the electrode part 40 is electrically connected to the lead terminals 211. The protective layer 50 includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silica gel, a silicon dioxide, and a polyimide film.

In the present invention, the magnetic induction portion 30 and the substrate 210 containing an IC circuit are integrated by employing the provision of the adhesive layer 20, and the interconnection line is formed by the photolithography process etching and patterning process and the metallization process to be electrically connected to the lead terminal 211. Thus, not only are the mobility, thickness, and other properties of the magnetic induction portions 30 improved, but also the use requirement for the substrate supporting the magnetic induction portions 30 is eliminated, thereby saving the occupied space and making the monolithically integrated hall circuit compact in size. Finally, the IC circuit and the magnetic induction portion 30 are electrically connected by the interconnection line 212 or the lead, and the fixing firmness of the electrical connection is increased.

In addition, not only can the reliability of connection and the firmness of fixation be improved by forming the interconnection line 212, but also the manufacturing process can be simplified, so that the interconnection line 212 is formed at the same time as the electrode part 40 is formed.

Of course, it is also possible to electrically connect the IC circuit and the magnetic induction portion 30 by wire bonding, which can function similarly to the interconnection line 212.

Referring to fig. 2A-2G, a flow chart of a fabrication of a monolithically integrated hall circuit according to an embodiment of the present invention is shown.

Specifically, as shown in fig. 2A, a compound semiconductor material film 70 is grown on a semiconductor single-crystal substrate 60 by epitaxial means (e.g., MOCVD or MBE), the compound semiconductor material film 70 including a first portion 71 of poor quality and a second portion 72 of better quality. In one example, the semiconductor single crystal substrate may be any suitable single crystal substrate of GaAs, InP, GaN, Si, or the like. The film of compound semiconductor material may comprise a binary, ternary, quaternary material composed of In, Sb, As, Ga, P, etc., such As GaAs, InAs, InSb, InGaAs, InGaP, InGaAsP, etc., preferably an InSb film.

The following will exemplify InSb. In one example, the thickness of the compound semiconductor material film 70 is between 10nm-10 microns, preferably between 500nm-3 microns, more preferably 800nm-2 microns. Taking InSb film as an example, the mobility is more than 40000cm²Vs, preferably greater than 50000cm²Vs, more preferably greater than 60000cm²/Vs。

As shown in fig. 2B, an adhesive is applied on the compound semiconductor material film 70 and/or the substrate to form an adhesive layer 20. In one example, a binder such as polyimide or epoxy is applied to the compound semiconductor material film 70 by coating or doctor blading. Subsequently, the film 70 of compound semiconductor material is bonded face-to-face with the substrate 210 by means of the adhesive layer 20, said substrate 210 comprising any kind of integrated circuit suitable for the specific application of the hall element, which may be, for example, a silicon-based wafer containing suitable integrated circuits. Of course, it is also possible to apply an adhesive to the substrate 210 or to apply an adhesive to both the compound semiconductor material film 70 and the substrate 210, and a person skilled in the art can select the material of the substrate 210 as needed without being limited to the examples described herein.

As shown in fig. 2C, the semiconductor single-crystal substrate 60 is selectively removed to expose the back surface of the compound semiconductor material film 70, i.e., to expose the first portion 71 of the compound semiconductor material film 70. In one example, mechanical grinding or chemical etching may be used. The mechanical grinding can be traditional semiconductor grinding equipment, and the chemical corrosion solution can be a mixed solution of phosphoric acid and hydrogen peroxide or a hydrochloric acid solution. It will be appreciated by those skilled in the art that the mechanical grinding or chemical etching herein may take other alternative forms known in the art.

As shown in fig. 2D, the exposed first portions 71 of the compound semiconductor material film 70 are removed to leave high-quality second portions 72 of the compound semiconductor material film 70. In one example, the exposed first portion 71 of the compound semiconductor material film 70 may be removed by dry or wet etching, i.e., the first portion 71 that was previously grown on the semiconductor single-crystal substrate 60 is removed, and the first portion 71 is of poor quality due to lattice mismatch, so that the second portion 72 of the compound semiconductor material film 70 of high quality (e.g., high mobility) may be retained. The dry etching described herein may be ion beam etching or the like, and the wet etching may be etching using any suitable solution.

It will be understood by those skilled in the art that the mobility and thickness of the compound semiconductor material film 70 can be selected in accordance with the design requirements of the device in the manner described in the present invention, thereby providing great flexibility in selection of the mobility and thickness of the compound semiconductor material film 70, so that a compound semiconductor material film 70 having a higher mobility and a thinner thickness (higher sheet resistance) can be obtained at the same time.

As shown in fig. 2E, the second portion 72 of the etched compound semiconductor material film 70 is patterned, thereby forming the magnetic induction parts 30. In one example, the mesa pattern of the magnetic induction part 30 of the compound semiconductor hall element can be prepared by photolithography, and specifically, the mesa pattern of the compound semiconductor hall element can be formed by removing the regions not protected by the photoresist by dry etching or wet etching. The mesa pattern of the compound semiconductor hall element described herein may be a step shape, or a rectangular or cross shape in a plan view thereof.

In one example, the magnetic induction is formed in a photolithographic process. A photoresist pattern covering the second portion 72 of the compound semiconductor material film 70 is first formed by applying a photoresist material and exposing and developing using a photolithography process. Then, with this pattern as a mask, the area of the second portion 72 of the compound semiconductor material film 70 not masked by the photoresist pattern is removed by a wet or dry process. Finally, the photoresist pattern is removed. Thereby, for example, the magnetic induction unit 30 is formed in a cross shape.

As shown in fig. 2F, the electrode portions 40 and the interconnection lines 212 are prepared at four corners of the magnetic induction portion 30. In one example, a metal electrode layer is formed by deposition such as electron beam evaporation or magnetron sputtering, and the material of the metal electrode layer may include Au, Ge, Ni, Ti, Cr, Cu, or their alloys; then, the electrode portion 40 and the interconnection line 212 are formed by the metal electrode layer by means of peeling or etching; the electrode part 40 is optionally subjected to an annealing process to form a better ohmic contact between the electrode part 40 and the magnetic induction part 30.

The electrode portion 40 and the interconnection line 212, which form an ohmic contact, may be formed around the magnetic induction portion 30 by a metal lift off method or an etching method. Prepared by thermal evaporation, electron beam evaporation, sputter plating or electroless plating, etc., to form four electrode portions 40 and corresponding interconnection lines 212.

In some examples, a photoresist pattern exposing the end portions of the magnetic induction portions is first formed using a photolithography process through coating of a photoresist material and an exposure and development process. Then, using the pattern as a mask, a metal electrode material layer is deposited, and the photoresist pattern and the metal electrode material layer thereon are stripped by a metal stripping process, resulting in an electrode portion 40 and an interconnection line 212 covering the end portion of the magnetic induction portion 30.

In other examples, the metal electrode layer is first deposited, then a photoresist pattern covering the end portions of the magnetic induction portions 30 is formed by applying a photoresist material and exposing and developing processes using a photolithography process, and then the photoresist material is stripped using an etching process with the pattern as a mask, and the portions of the metal electrode layer exposed through the resist pattern are removed, resulting in the electrode portions 40 and the interconnection lines 212 covering the end portions of the magnetic induction portions 30.

Of course, those skilled in the art may set the shape and height of the electrode portion as desired, not limited to the illustrated case, and for example, the shape of the electrode portion may be set to be square, circular, elliptical, stepped, trapezoidal, or the like.

Alternatively, as shown in fig. 2G, the lead or interconnection line 212 electrically connecting the lead terminals 211 is formed by a photolithography process etching away and patterning, metallization process.

Further, a protective layer 50 is formed on at least a part (for example, the entire surface) of the magnetic induction portion 30 and the electrode portion 40 of the compound semiconductor hall element in the monolithically integrated hall circuit.

The protective layer 50 can prevent the magnetic induction portion 30 of the compound semiconductor hall element 100 from being damaged in the subsequent process, and prevent moisture, impurity particles, and the like from entering the magnetic induction portion 30 of the compound semiconductor hall element 100. The protective layer 50 includes any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, an epoxy resin, a silica gel, a silicon dioxide, and a polyimide film. The compound semiconductor hall element 100 shown in fig. 1A and 1B can be obtained by forming a photoresist pattern as a mask on at least a portion of the magnetic induction portions 30 and the electrode portions 40 by PECVD, sputtering, or other conventional film forming means, with high sensitivity and low power consumption.

With the embodiment of FIGS. 2A to 2G of the present invention for fabricating the monolithic Hall circuit 200, if the compound semiconductor material film of the magnetic induction part 30 is made of InSb material, the mobility of the compound semiconductor material film may exceed 60000cm²Vs, while the sheet resistance of the compound semiconductor material film can be designed to a desired value, so that the InSb compound semiconductor hall element 100 with high sensitivity and low power consumption can be finally obtained.

Referring to table 1, a comparison of the performance of InSb hall elements in a monolithically integrated hall circuit 200 prepared by the process shown in the examples of the invention (e.g., fig. 2A-2G) is shown compared to comparative and commercial InSb hall elements. The comparative example differs from the example of the present invention only in that the first portion 71 of the compound semiconductor material film 70 is not removed, but when the thicknesses of the compound semiconductor material films 70, both of which are finally used to form magnetic induction portions, are uniform (for example, the thickness is about 600 nm), the mobility of the compound semiconductor hall element of the example of the present invention reaches 65000cm²the/Vs is more than 2 times of that of a commercial InSb Hall element under the condition of the same square resistance, and shows remarkably excellent magnetic induction sensitivity performance.

TABLE 1 comparison of the Performance of InSb compound semiconductor Hall elements prepared in inventive and comparative examples with commercial InSb Hall elements

	Mobility (cm)2/Vs)	Square resistance (omega/SQ)
			Examples of the invention	65000	200
Comparative example	47300	87
			Commercial InSb hall element	30000	200

In summary, the compound semiconductor hall element in the monolithically integrated hall circuit and the method for manufacturing the compound semiconductor hall element according to the embodiments of the present invention solve the technical problems proposed in the background art, and specifically, the obtained compound semiconductor material film for manufacturing the magnetic induction portion has better lattice quality, higher mobility, and reduced overall film thickness compared to the material manufactured by the prior art, so that the monolithically integrated hall circuit 200 has high sensitivity and low power consumption.

Further, the magnetic induction portion 30 and the substrate containing the IC circuit are integrated by employing the provision of the adhesive layer 20, and the lead or the interconnection line 212 is formed by etching and patterning the adhesive layer 20 by a photolithography process and a metallization process. In this way, not only are the mobility, thickness, etc. of the magnetic induction portions 30 improved, but also the use of a substrate supporting the magnetic induction portions 30 is eliminated, thereby saving the occupied space and making the monolithically integrated hall circuit 200 compact in size. Finally, the IC circuit and the magnetic induction part are electrically connected through the interconnection line or the lead, and the fixing firmness of the electrical connection is increased.

Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.