阅读说明：本技术 包括外延源极线和位线的存储阵列 (Memory array including epitaxial source lines and bit lines ) 是由 杨柏峰 杨世海 张志宇 徐志安 林佑明 于 2021-03-26 设计创作，主要内容包括：本公开涉及包括外延源极线和位线的存储阵列。公开了一种3D存储阵列及其形成方法,其中,水平合并并且垂直不合并的外延源极/漏极区域被用作源极线和位线。在实施例中,一种存储阵列包括：第一沟道区域,在半导体衬底之上；第一外延区域,电耦合到第一沟道区域；第二外延区域,在与半导体衬底的主表面垂直的方向上位于第一外延区域正上方；电介质材料,在第一外延区域和第二外延区域之间,第二外延区域通过电介质材料与第一外延区域隔离；栅极电介质,围绕第一沟道区域；以及栅极电极,围绕栅极电介质。(The present disclosure relates to a memory array including an epitaxial source line and a bit line. A3D memory array and method of forming the same are disclosed in which horizontally merged and vertically non-merged epitaxial source/drain regions are used as source and bit lines. In an embodiment, a memory array includes: a first channel region over the semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to the main surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.)

1. A memory array, comprising:

a first channel region over the semiconductor substrate;

a first epitaxial region electrically coupled to the first channel region;

a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to the main surface of the semiconductor substrate;

a dielectric material between the first epitaxial region and the second epitaxial region, wherein the second epitaxial region is isolated from the first epitaxial region by the dielectric material;

a gate dielectric surrounding the first channel region; and

a gate electrode surrounding the gate dielectric.

2. The memory array of claim 1, further comprising a second channel region directly above the first channel region in a direction perpendicular to the major surface of the semiconductor substrate, the second channel region electrically coupled to the second epitaxial region, wherein the gate dielectric also surrounds the second channel region.

3. The memory array of claim 2, wherein a ratio of a distance between the first channel region and the second channel region in a direction perpendicular to a main surface of the semiconductor substrate to a height of the first channel region and the second channel region is 2 to 10.

4. The storage array of claim 2, further comprising:

a second channel region directly above the first channel region in a direction perpendicular to a main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region; and

a third channel region adjacent to the first channel region in a direction parallel to a major surface of the semiconductor substrate, the third channel region electrically coupled to the first epitaxial region.

5. The memory array of claim 4, wherein a distance between the first channel region and the second channel region in a direction perpendicular to a major surface of the semiconductor substrate is greater than a distance between the first channel region and the third channel region in a direction parallel to the major surface of the semiconductor substrate.

6. The memory array of claim 1, wherein a distance between the second epitaxial region and the semiconductor substrate is greater than a distance between the first epitaxial region and the semiconductor substrate, and wherein a length of the second epitaxial region is less than a length of the first epitaxial region.

7. The memory array of claim 1, wherein the gate dielectric comprises a ferroelectric material.

8. A semiconductor device, comprising:

a first channel region over the semiconductor substrate;

a second channel region located directly above the first channel region in a vertical direction;

a first gate structure surrounding the first channel region and the second channel region;

a third channel region adjacent to the first channel region in a horizontal direction;

a first source/drain region electrically coupled to the first channel region and the third channel region; and

a second source/drain region electrically coupled to the second channel region and isolated from the first source/drain region, wherein a first dielectric material extends between the first source/drain region and the second source/drain region.

9. The semiconductor device of claim 8, wherein a second gate structure surrounds the third channel region, the second gate structure being separated from the first gate structure by a second dielectric material.

10. A method for forming a semiconductor device, comprising:

forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material;

patterning the multilayer stack to form a first plurality of nanostructures comprising the first semiconductor material and a second plurality of nanostructures comprising the second semiconductor material, the second plurality of nanostructures comprising first nanostructures, second nanostructures, and third nanostructures, the second nanostructures being adjacent to the first nanostructures in a direction parallel to a major surface of the semiconductor substrate, the third nanostructures being directly above the first nanostructures in a direction perpendicular to the major surface of the semiconductor substrate;

forming a gate structure over the multi-layer stack;

etching the multi-layer stack to form a first recess adjacent to the gate structure; and

epitaxially growing a source/drain region from the second plurality of nanostructures, wherein after epitaxially growing the source/drain region, a first source/drain region epitaxially grown from the first nanostructure and a second source/drain region epitaxially grown from the second nanostructure merge with one another, and wherein a third source/drain region epitaxially grown from the third nanostructure is isolated from the first source/drain region.

Technical Field

The present disclosure relates generally to semiconductor devices, and in particular, to memory arrays including epitaxial source lines and bit lines.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: insulating or dielectric layers of materials, conductive layers, and semiconductor layers are sequentially deposited over a semiconductor substrate, and the various material layers are patterned using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided a memory array including: a first channel region over the semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to the main surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, wherein the second epitaxial region is isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

According to another embodiment of the present disclosure, there is provided a semiconductor device including: a first channel region over the semiconductor substrate; a second channel region located right above the first channel region in a vertical direction; a first gate structure surrounding the first channel region and the second channel region; a third channel region adjacent to the first channel region in a horizontal direction; a first source/drain region electrically coupled to the first channel region and the third channel region; and a second source/drain region electrically coupled to the second channel region and isolated from the first source/drain region, wherein the first dielectric material extends between the first source/drain region and the second source/drain region.

According to yet another embodiment of the present disclosure, there is provided a method including: forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; patterning the multilayer stack to form a first plurality of nanostructures comprising a first semiconductor material and a second plurality of nanostructures comprising a second semiconductor material, the second plurality of nanostructures comprising a first nanostructure, a second nanostructure, and a third nanostructure, the second nanostructure being adjacent to the first nanostructure in a direction parallel to the major surface of the semiconductor substrate, the third nanostructure being directly above the first nanostructure in a direction perpendicular to the major surface of the semiconductor substrate; forming a gate structure over the multi-layer stack; etching the multi-layer stack to form a first recess adjacent to the gate structure; and epitaxially growing a source/drain region from the second plurality of nanostructures, wherein, after epitaxially growing the source/drain region, a first source/drain region epitaxially grown from the first nanostructure and a second source/drain region epitaxially grown from the second nanostructure merge with one another, and wherein a third source/drain region epitaxially grown from the third nanostructure is isolated from the first source/drain region.

Drawings

Aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A and 1B illustrate perspective and circuit diagrams of a memory array according to some embodiments.

FIG. 2, FIG. 3, FIG. 4A, FIG. 4B, FIG. 4C, FIG. 5A, FIG. 5B, FIG. 5C, FIG. 6A, FIG. 6B, FIG. 6C, FIG. 7A, FIG. 7B, FIG. 7C, FIG. 8, FIG. 9A, FIG. 9B, FIG. 10A, FIG. 10B, FIG. 10C, FIG. 10D, FIG. 11A, FIG. 11B, FIG. 11C, FIG. 11D, FIG. 12A, FIG. 12B, FIG. 12C, FIG. 12D, FIG. 13A, FIG. 13B, FIG. 13C, FIG. 13D, FIG. 14A, FIG. 14B, FIG. 14C, FIG. 14D, FIG. 15A, FIG. 15B, FIG. 15C, FIG. 15D, FIG. 15E, FIG. 15F, FIG. 16A, FIG. 16B, FIG. 16C, FIG. 16D, FIG. 17A, FIG. 17C, FIG. 17D, FIG. 18A, FIG. 18B, FIG. 18C, FIG. 19A, FIG. 19B, FIG. 19A, FIG. 20C, FIG. 20D, FIG. 20A, FIG. 20C, Fig. 21B, 21C, 21D, 22A, 22B, 22C, 22D, and 23 illustrate different views of fabricating a semiconductor device including a memory array according to some embodiments.

Fig. 24A, 24B, 24C, 25A, 25B, 25C, 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, 28C, 29A, 29B, 29C, 29D, 30A, 30B, 30C, 30D, 31A, 31B, 31C, 31D, and 32 illustrate different views of fabricating a semiconductor device including a memory array according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide a 3D memory array in which epitaxially grown source/drain regions are merged in a horizontal direction and isolated in a vertical direction, and a method of forming the same. The method may include forming a channel region, which may be a nanostructure or the like. Portions of the channel region may be etched and source/drain regions may be epitaxially grown from the remainder of the channel region. The channel region may be formed such that the source/drain regions adjacent in the horizontal direction are merged with each other while the source/drain regions adjacent in the vertical direction remain unmerged. The source/drain regions may then be etched to form a stepped (ladder) structure so that separate connections may be made to each set of merged source/drain regions. The source/drain regions may be used as source lines and bit lines in a 3D memory array. The method for forming a 3D memory array is compatible with existing nanostructured field effect transistor (nanoFET) processes and allows the formation of 3D memory arrays in reduced areas, thereby increasing device density and reducing cost.

Embodiments are described below in a particular context (i.e., a die including a nanoFET). However, various embodiments may be applied to dies that include other types of transistors (e.g., fin field effect transistors (finfets), planar transistors, etc.) instead of or in combination with nanofets.

Fig. 1A and 1B illustrate examples of a memory array 200 according to some embodiments. FIG. 1A illustrates an example of a portion of a memory array 200 of a three-dimensional view and FIG. 1B illustrates a circuit diagram of the memory array 200, according to some embodiments. The memory array 200 includes a plurality of memory cells 202, and the memory cells 202 may be arranged in a grid of rows and columns. Memory cells 202 may further be vertically stacked to provide a three-dimensional memory array, thereby increasing device density. In some embodiments, the memory array 200 may be disposed in a back end of line (BEOL) of semiconductor die. For example, the memory array 200 may be disposed in an interconnect layer of a semiconductor die, e.g., over one or more active devices (e.g., transistors) formed on a semiconductor substrate.

In some embodiments, the memory array 200 is a flash memory array, e.g., a NOR flash memory array, or the like. Each memory cell 202 may include a transistor 204 having a gate dielectric layer 100. Gate dielectric layer 100 may serve as a gate dielectric. In some embodiments, the gate electrode 102 of each transistor 204 may correspond to or be electrically coupled to a respective word line. The first epitaxial source/drain region 92 of each transistor 204 may correspond to or be electrically coupled to a respective bit line, and the second epitaxial source/drain region 92 of each transistor 204 may correspond to or be electrically coupled to a respective source line. Memory cells 202 in the same horizontal row of memory array 200 may share a common epitaxial source/drain region 92 corresponding to a common source line and a common epitaxial source/drain region 92 corresponding to a common bit line, while memory cells 202 in the same vertical column of memory array 200 may share a common gate electrode 102 corresponding to a common word line.

The memory array 200 includes a plurality of vertically stacked epitaxial source/drain regions 92, with a first ILD 96 disposed between vertically adjacent epitaxial source/drain regions 92. The epitaxial source/drain regions 92 extend in a direction parallel to the major surface of the underlying substrate 50. The epitaxial source/drain regions 92 may have a stepped configuration such that the lower epitaxial source/drain regions 92 are longer than the upper epitaxial source/drain regions 92 and extend laterally beyond the ends of the upper epitaxial source/drain regions 92. For example, in fig. 1A, a plurality of stacked layers of epitaxial source/drain regions 92 are shown, with the topmost epitaxial source/drain region 92 being the shortest and the bottommost epitaxial source/drain region 92 being the longest. The respective lengths of the epitaxial source/drain regions 92 may increase in a direction toward the underlying substrate. In this manner, a portion of each epitaxial source/drain region 92 may be accessed from above the memory array 200 and conductive contact may be made to the exposed portion of each epitaxial source/drain region 92.

The memory array 200 also includes a plurality of gate electrodes 102. The gate electrodes 102 may each extend in a direction perpendicular to the epitaxial source/drain regions 92. A dielectric material 106 is disposed between adjacent gate electrodes 102 and isolates adjacent gate electrodes 102. Pairs of epitaxial source/drain regions 92 and intersecting gate electrodes 102 define boundaries of each memory cell 202, and a dielectric material 106 is disposed between and isolates adjacent pairs of epitaxial source/drain regions 92. In some embodiments, the alternating stack of epitaxial source/drain regions 92 may be electrically connected to ground and a voltage source.

The memory array 200 may also include nanostructures 54. The nanostructures 54 may provide a channel region of the transistor 204 of the memory cell 202. For example, when an appropriate voltage (e.g., above the corresponding threshold voltage (V) of the corresponding transistor 204) is applied through the gate electrode 102_th) The nanostructures 54 intersecting the gate electrode 102 may allow current to flow from a first epitaxial source/drain region 92 on a first side of the nanostructures 54 to a second epitaxial source/drain region 92 on a second side of the nanostructures 54 opposite the first side of the nanostructures 54.

Gate dielectric layer 100 is disposed between gate electrode 102 and nanostructures 54, and gate dielectric layer 100 provides the gate dielectric of transistor 204. In some embodiments, gate dielectric layer 100 comprises a Ferroelectric (FE) material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, and the like. Thus, the memory array 200 may be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the gate dielectric layer 100 may be a multi-layer structure, a different ferroelectric material, a different type of memory layer (e.g., capable of storing bits), and the like. The use of ferroelectric material for the gate dielectric layer 100 may shift the threshold voltage (Vt) and provide memory reliability and improved performance.

In embodiments where gate dielectric layer 100 includes an FE material, gate dielectric layer 100 may be polarized in one of two different directions. The polarization direction may be changed by applying an appropriate voltage difference across gate dielectric layer 100 and generating an appropriate electric field. Depending on the polarization direction of a particular gate dielectric layer 100, the threshold voltage of the corresponding transistor 204 changes and a digital value (e.g., 0 or 1) may be stored. For example, when gate dielectric layer 100 has a first electrical polarization direction, the corresponding transistor 204 may have a relatively low threshold voltage, and when gate dielectric layer 100 has a second electrical polarization direction, the corresponding transistor 204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 202.

To perform a write operation on the memory cell 202, a write voltage is applied to the gate dielectric layer 100 corresponding to the memory cell 202. The write voltage may be applied, for example, by applying appropriate voltages to the gate electrodes 102 (e.g., by respective word lines) and the respective epitaxial source/drain regions 92 (e.g., by respective bit lines and source lines). By applying a write voltage across gate dielectric layer 100, the polarization direction of gate dielectric layer 100 may be changed. As a result, the respective threshold voltage of the respective transistor 204 may be switched from a low threshold voltage to a high threshold voltage and vice versa, and a digital value may be stored in the memory cell 202. Since gate electrode 102 intersects epitaxial source/drain regions 92, individual memory cells 202 may be selected for a write operation.

To perform a read operation on memory cell 202, a read voltage (e.g., a voltage between a low threshold voltage and a high threshold voltage) is applied to the corresponding gate electrode 102 (e.g., by the corresponding word line). Depending on the polarization direction of the corresponding gate dielectric layer 100, the transistor 204 of the memory cell 202 may or may not be conductive. As a result, a respective epitaxial source/drain region 92 (e.g., a respective epitaxial source/drain region electrically coupled to a source line) may discharge through (or may not pass through) the respective epitaxial source/drain region 92 (e.g., a respective source/drain region electrically coupled to ground), and a digital value stored in memory cell 202 may be determined. Since gate electrode 102 intersects epitaxial source/drain regions 92, individual memory cells 202 may be selected for a read operation.

Fig. 1A also shows a reference cross section of a memory array 200 used in later figures. Cross section a-a' is along the longitudinal axis of the nanostructure 54 and in a direction parallel to the direction of current flow through the nanostructure 54 of the transistor 204. Cross section B-B 'is perpendicular to cross section a-a' and extends through gate electrode 102 in a direction parallel to the longitudinal axis of epitaxial source/drain regions 92. Section C-C 'is parallel to section B-B' and extends through epitaxial source/drain region 92. For clarity, the subsequent figures refer to these reference sections.

Some embodiments discussed herein are discussed in the context of a nanoFET formed using a gate-last process. In other embodiments, a gate first process may be used. Further, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs) or fin field effect transistors (finfets).

Fig. 2-32 are cross-sectional and top views of an intermediate stage in the fabrication of a memory array 200 according to some embodiments. Fig. 2, fig. 3, fig. 4A, fig. 5A, fig. 6A, fig. 7A, fig. 8, fig. 9A, fig. 9B, fig. 10A, fig. 11A, fig. 12A, fig. 13A, fig. 14A, fig. 15A, fig. 16A, fig. 17A, fig. 18A, fig. 19A, fig. 20A, fig. 21A, fig. 22A, fig. 24A, fig. 25A, fig. 26A, fig. 27A, fig. 28A, fig. 29A, fig. 30A, and fig. 31A show a reference section a-a' shown in fig. 1A. Fig. 4B, fig. 5B, fig. 6B, fig. 7B, fig. 10B, fig. 11B, fig. 12B, fig. 13B, fig. 14B, fig. 15E, fig. 15F, fig. 16B, fig. 17B, fig. 18B, fig. 19B, fig. 20B, fig. 21B, fig. 22B, fig. 24B, fig. 25B, fig. 26B, fig. 27B, fig. 28B, fig. 29B, fig. 30B, and fig. 31B show a reference section B-B' shown in fig. 1A. Fig. 10C, fig. 11C, fig. 12C, fig. 13C, fig. 14C, fig. 15C, fig. 16C, fig. 17C, fig. 18C, fig. 19C, fig. 20C, fig. 21C, fig. 22C, fig. 29C, fig. 30C, and fig. 31C show a reference section C-C' shown in fig. 1A. Fig. 4C, 5C, 6C, 7C, 10D, 11D, 12D, 13D, 14D, 15D, 16D, 17D, 18D, 19D, 20D, 21D, 22D, 23, 24C, 25C, 26C, 27C, 28C, 29D, 30D, 31D, and 32 show plan views.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be an integrated circuit die, e.g., a logic die, a memory die, an ASIC die, etc. The substrate 50 may be a Complementary Metal Oxide Semiconductor (CMOS) die and may be referred to as a CMOS lower array (CUA). Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination of the foregoing.

Fig. 2 further illustrates circuitry that may be formed over substrate 50. The circuit includes transistors located on the top surface of the substrate 50. The transistor may include a gate dielectric layer 302 over the top surface of the substrate 50, and a gate electrode 304 over the gate dielectric layer 302. Source/drain regions 306 are disposed in the substrate 50 on opposite sides of the gate dielectric layer 302 and the gate electrode 304. Gate spacers 308 are formed along the sidewalls of the gate dielectric layer 302 and separate the source/drain regions 306 from the gate electrode 304 by an appropriate lateral distance. The transistor may include a fin field effect transistor (FinFET), a nanostructure (e.g., nanosheet, nanowire, gate all around, etc.) FET (nanofet), planar FET, etc., or a combination thereof, and may be formed by a gate-first process or a gate-last process.

A first ILD 310 surrounds and isolates the source/drain regions 306, the gate dielectric layer 302, and the gate electrode 304, and a second ILD 312 is over the first ILD 310. A source/drain contact 314 extends through the second ILD 312 and the first ILD 310 and is electrically connected to the source/drain region 306, and a gate contact 316 extends through the second ILD 312 and is electrically connected to the gate electrode 304. Over the second ILD 312, the source/drain contacts 314, and the gate contact 316 is an interconnect structure 320 comprising one or more stacked dielectric layers 324 and conductive features 322 formed in the one or more dielectric layers 324. The interconnect structure 320 may be electrically connected to the gate contact 316 and the source/drain contact 314 to form a functional circuit. In some embodiments, the functional circuitry formed by interconnect structure 320 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input/output circuitry, image sensor circuitry, the like, or combinations of the preceding. Although fig. 2 discusses transistors formed over substrate 50, other active devices (e.g., diodes, etc.) and/or passive devices (e.g., capacitors, resistors, etc.) may also be formed as part of the functional circuitry. For simplicity and clarity, the transistors, ILD, and interconnect structure 320 formed over the substrate 50 may be omitted in subsequent figures. The substrate 50, as well as the transistors (e.g., source/drain regions 306, gate dielectric layer 302, and gate electrode 304), gate spacers 308, first ILD 310, second ILD 312, and interconnect structure 320 may be a CMOS Under Array (CUA), a logic die, and the like.

In some embodiments, substrate 50 may include an n-type region and a p-type region (not separately shown). The n-type regions may be used to form n-type devices such as NMOS transistors, e.g., n-type nanofets, and the p-type regions may be used to form p-type devices such as PMOS transistors, e.g., p-type nanofets. The n-type region may be physically separated from the p-type region, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region and the p-type region. Any number of n-type and p-type regions may be provided.

In fig. 3, a multi-layer stack 64 is formed over the structure of fig. 2. For simplicity and clarity, the transistors, ILD, and interconnect structure 320 may be omitted in subsequent figures. Although the multi-layer stack 64 is shown contacting the substrate 50, any number of intermediate layers may be disposed between the substrate 50 and the multi-layer stack 64. For example, one or more interconnect layers may be disposed between the substrate 50 and the multi-layer stack 64, the interconnect layers including conductive features in an insulating layer (e.g., a low-k dielectric layer). In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines for active devices on the substrate 50 and/or the memory array 200 (see fig. 1A and 1B). In some embodiments, the multi-layer stack 64 may be formed directly over the substrate 50.

The multi-layer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form channel regions of the nanoFET in both the p-type and n-type regions, as discussed in more detail below. In some embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in one or both of the n-type region and the p-type region. In embodiments where the channel region is formed by the first semiconductor layer 51 or the second semiconductor layer 53 in both the n-type region and the p-type region, the channel regions in both the n-type region and the p-type region may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously.

For purposes of example, the multi-layer stack 64 is shown as including three layers each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first and second semiconductor layers 51, 53. Each layer in the multi-layer stack 64 may be epitaxially grown using a process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), and the like. In some embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material such as silicon germanium or the like, and the second semiconductor layer 53 may be formed of a second semiconductor material such as silicon, silicon carbon, silicon germanium, germanium or the like. In embodiments where the first and second semiconductor materials are formed of silicon germanium, the first and second semiconductor materials may have different silicon and germanium concentrations from one another such that the first and second semiconductor materials may be selectively etched with respect to one another. For purposes of example, the multi-layer stack 64 is shown with one of the first semiconductor layers 51 as the bottommost semiconductor layer. In some embodiments, the multi-layer stack 64 may be formed such that the bottommost layer is one of the second semiconductor layers 53.

The first semiconductor material and the second semiconductor material may be materials having high etch selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in embodiments where the second semiconductor layer 53 of the second semiconductor material is removed, the second semiconductor layer 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

The first semiconductor layer 51 may be formed to have a thickness T in the range of about 100nm to about 500nm_lAnd the second semiconductor layer 53 may be formed to have a thickness T in the range of about 10nm to about 50nm₂. In some embodiments, the thickness T of the first semiconductor layer 51₁And the thickness T of the second semiconductor layer 53₂The ratio may be in the range of about 2 to about 10. Forming first and second semiconductor layers 51, 53 with a prescribed thickness may help allow horizontally adjacent subsequently formed epitaxial source/drain regions (e.g., epitaxial source/drain regions 92 discussed below with respect to fig. 10A-10D) to merge while vertically adjacent subsequently formed epitaxial source/drain regions do not includeAnd (3) and (2). This allows the horizontally merged epitaxial source/drain regions to be used as source lines and bit lines and prevents shorting between vertically adjacent epitaxial source/drain regions. The use of merged epitaxial source/drain regions as source and bit lines reduces device size, increases device density, and reduces cost.

In fig. 4A-4C, nanostructures 55 are formed in a multilayer stack 64. In some embodiments, the nanostructures 55 may be formed in the multi-layer stack 64 by etching trenches in the multi-layer stack 64. The etch may be any acceptable etch process, such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations thereof. The etch may be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 may define first nanostructures 52A-C (collectively first nanostructures 52) from first semiconductor layer 51, and may define second nanostructures 54A-C (collectively second nanostructures 54) from second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 may be collectively referred to as nanostructures 55.

The nanostructures 55 may be patterned by any suitable method. For example, the nanostructures 55 may be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Typically, a double or multiple patterning process combines a lithographic process and a self-aligned process, allowing for the creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the nanostructures 55.

In some embodiments, the nanostructures 55 in the n-type region and the p-type region have substantially equal widths; however, the width of the nanostructures 55 may be greater in one of the n-type region or the p-type region. Further, although each nanostructure 55 is shown as having a consistent width throughout, in some embodiments, the nanostructures 55 may have tapered sidewalls such that the width of each nanostructure 55 continuously increases in a direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

The nanostructures 55 may have a width W in the range of about 10nm to about 50nm₁. The nanostructures 55 may be separated by a distance D in the range of about 50nm to about 100nm₁. Forming first nanostructures 55 having a specified width and spacing may help allow horizontally adjacent subsequently formed epitaxial source/drain regions (e.g., epitaxial source/drain regions 92 discussed below with respect to fig. 10A-10D) to merge while vertically adjacent subsequently formed epitaxial source/drain regions do not merge. This allows the horizontally merged epitaxial source/drain regions to be used as source lines and bit lines and prevents shorting between vertically adjacent epitaxial source/drain regions. The use of merged epitaxial source/drain regions as source and bit lines reduces device size, increases device density, and reduces cost.

The process described above with respect to fig. 3-4C is only one example of how nanostructures 55 may be formed. In some embodiments, nanostructures 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure may be epitaxially grown in the trench and the dielectric layer may be recessed such that the epitaxial structure protrudes from the dielectric layer to form the nanostructures 55. The epitaxial structure may include alternating semiconductor materials (e.g., a first semiconductor material and a second semiconductor material) as discussed above. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and/or subsequent implantation, although in situ and implantation doping may be used together.

Further, for example purposes only, the first semiconductor layer 51 (and resulting first nanostructures 52) and the second semiconductor layer 53 (and resulting second nanostructures 54) are shown and discussed herein as including the same material in the p-type region and the n-type region. As such, in some embodiments, one or both of the first and second semiconductor layers 51, 53 may be different materials in the p-type and n-type regions, or may be formed in a different order.

Further in fig. 4A to 4C, appropriate wells (not separately shown) may be formed in the nanostructures 55. In embodiments with different well types, different implantation steps for the n-type and p-type regions may be achieved using a photoresist or other mask (not separately shown). For example, a photoresist may be formed over the nanostructures 55 and the substrate 50 in the n-type and p-type regions. The photoresist is patterned to expose the p-type region. The photoresist may be formed using spin-coating techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region. The n-type impurity may be phosphorus, arsenic, antimony, or the like, implanted into the region at a concentration of about 10 deg.f¹³Atom/cm³To about 10¹⁴Atom/cm³Within the range of (1). After implantation, the photoresist is removed, for example, by an acceptable ashing process. The process may then be repeated to perform a p-type impurity implantation in the n-type region, wherein a photoresist is formed and patterned to substantially prevent p-type impurities from being implanted into the p-type region. The p-type impurity may be boron, boron fluoride, indium, etc. implanted into the region at a concentration of about 10 deg.f¹³Atom/cm³To about 10¹⁴Atom/cm³Within the range of (1). After implantation of the n-type and p-type regions, an anneal may be performed to repair implantation damage and activate the implanted p-type and/or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be doped in-situ during growth, which may eliminate implantation, but in-situ doping and implant doping may be used together.

In fig. 5A to 5C, a dummy dielectric layer 70 is formed on the nanostructure 55. Dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70 and a mask layer 74 is formed over the dummy gate layer 72. Dummy gate layer 72 may be deposited over dummy dielectric layer 70 and then planarized, for example by CMP. A mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material and may be selected from the group consisting of: amorphous silicon, polysilicon (polysilicon), poly-silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials having a high etch selectivity with respect to the etching of the isolation regions. The mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type and p-type regions. Note that dummy dielectric layer 70 is shown covering only nanostructures 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the substrate 50 such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the substrate 50.

In fig. 6A-6C, mask layer 74 (see fig. 5A-5C) may be patterned using acceptable photolithography and etching techniques to form mask 78. The pattern of mask 78 may then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. Dummy gate 76 covers the corresponding channel region of nanostructure 55. The pattern of mask 78 may be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gates 76 may also have a length direction that is substantially perpendicular to the length direction of the corresponding nanostructures 55.

Further in fig. 6A-6C, first spacers 80 are formed over the nanostructures 55 and adjacent to the dummy gate dielectric 71, the dummy gate 76, and the mask 78. The first spacers 80 may serve as spacers for forming self-aligned source/drain regions. May be formed by coating the top surface of substrate 50; the top surface and sidewalls of nanostructures 55 and mask 78; and depositing a first spacer layer (not separately shown) on sidewalls of dummy gate 76 and dummy gate dielectric layer 71 to form first spacers 80. The first spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using a technique such as thermal oxidation, or may be deposited by CVD, ALD, or the like.

After forming the first spacer layer, implantation for lightly doped source/drain (LDD) regions (not separately shown) may be performed. In embodiments with different device types, similar to the implantation discussed above in fig. 4A-4C, a mask (e.g., photoresist) may be formed over the n-type region while exposing the p-type region, and an impurity of the appropriate type (e.g., p-type) may be implanted into the exposed nanostructures 55 in the p-type region. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the p-type region while exposing the n-type region, and an appropriate type (e.g., n-type) of impurity may be implanted into the exposed nanostructures 55 in the n-type region. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities and the p-type impurity may be any of the previously discussed p-type impurities. The lightly doped source/drain region may have a thickness of about 1 × 10¹⁵Atom/cm³To about 1X 10¹⁹Atom/cm³An impurity concentration within the range of (1). Annealing may be used to repair implant damage and activate implanted impurities.

The first spacer layer may then be etched to form first spacers 81. As will be discussed in more detail below, the first spacers 80 are used to self-align subsequently formed source drain regions, as well as protect the sidewalls of the nanostructures 55 during subsequent processing. The first spacer layer may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), and so forth. As shown in fig. 6A, first spacers 80 may be disposed on sidewalls of mask 78, dummy gate 76, and dummy gate dielectric 71. As shown in fig. 6C, the first spacers 80 may be further disposed on sidewalls of the nanostructures 55.

Note that the above disclosure generally describes the process of forming the spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be employed, a different order of steps may be employed, additional spacers may be formed and removed, and so forth. Further, different structures and steps may be used to form the n-type device and the p-type device.

In fig. 7A to 7C, a first groove 86 is formed in the nanostructure 55. In some embodiments, the first groove 86 may also extend at least partially into the substrate 50. Epitaxial source/drain regions will subsequently be formed in the first recess 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54. As shown in fig. 7A, the first recess 86 may extend to the top surface of the substrate 50. The first recess 86 may be formed by etching the nanostructure 55 using an anisotropic etching process (e.g., RIE, NBE, etc.). The first spacers 80 and the mask 78 mask portions of the nanostructures 55 during an etching process for forming the first recesses 86. Each layer of nanostructures 55 may be etched using a single etch process or multiple etch processes. A timed etch process may be used to stop etching first recess 86 after first recess 86 reaches a desired depth.

In fig. 8, portions of the sidewalls of the layers of the multi-layer stack 64 formed of the first semiconductor material (e.g., the first nanostructures 52) exposed by the first recess 86 are etched to form sidewall recesses 88. Although the sidewalls of the first nanostructures 52 adjacent to the sidewall recesses 88 are shown as straight in fig. 8, these sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etch process (e.g., wet etch, etc.). In embodiments where the first nanostructures 52 comprise, for example, silicon germanium and the second nanostructures 54 comprise, for example, silicon or silicon carbide, a wet or dry etch process utilizing hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch the sidewalls of the first nanostructures 52.

In fig. 9A and 9B, a first internal spacer 90 is formed in the sidewall groove 88. The first internal spacers 90 may be formed by depositing an internal spacer layer (not separately shown) over the structure shown in fig. 8. The first interior spacers 90 serve as isolation features between subsequently formed source/drain regions and the gate structure. As will be discussed in more detail below, source/drain regions will be formed in the first recess 86, and the first nanostructure 52 will be replaced with a corresponding gate structure.

The interior spacer layer can be deposited by a conformal deposition process such as CVD, ALD, etc. The interior spacer layer may comprise a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, for example, a low dielectric constant (low-k) material having a k value of less than about 3.5. The interior spacer layer may then be anisotropically etched to form the first interior spacer 90. Although the outer sidewalls of the first interior spacers 90 are shown as being flush with the sidewalls of the second nanostructures 54, the outer sidewalls of the first interior spacers 90 may extend beyond the sidewalls of the second nanostructures 54, or be recessed relative to the sidewalls of the second nanostructures 54.

Further, although the outer sidewall of the first interior spacer 90 is shown as straight in fig. 9A, the outer sidewall of the first interior spacer 90 may be concave or convex. As an example, fig. 9B shows an embodiment in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first interior spacers 90 are concave, and the first interior spacers 90 are recessed relative to the sidewalls of the second nanostructures 54. The inner spacer layer may be etched by an anisotropic etching process such as RIE, NBE, or the like. The first interior spacers 90 may serve to prevent damage to source/drain regions (e.g., epitaxial source/drain regions 92 discussed below with respect to fig. 10A-10D) subsequently formed by a subsequent etch process (e.g., an etch process for forming a gate structure).

In fig. 10A-10D, epitaxial source/drain regions 92A-C are formed in the first recess 86. The epitaxial source/drain regions 92A-C may be collectively referred to as epitaxial source/drain regions 92. In some embodiments, the epitaxial source/drain regions 92 may exert stress on the second nanostructures 54, thereby improving performance. As shown in fig. 10A, epitaxial source/drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a respective adjacent pair of epitaxial source/drain regions 92. In some embodiments, the first spacers 80 are used to separate the epitaxial source/drain regions 92 from the dummy gate 76 by an appropriate lateral distance, and the first internal spacers 90 are used to separate the epitaxial source/drain regions 92 from the first nanostructures 52 by an appropriate lateral distance, such that the epitaxial source/drain regions 92 do not short the gates of the subsequently formed resulting nanofets.

As shown in fig. 10A, 10C, and 10D, epitaxial source/drain regions 92A-C (collectively referred to as epitaxial source/drain regions 92) may be epitaxially grown from the second nanostructures 54A-C, respectively. The epitaxial source/drain regions 92 may be grown such that horizontally adjacent epitaxial source/drain regions 92 (e.g., epitaxial source/drain regions 92 adjacent to each other in a direction parallel to the major surface of the substrate 50) merge with each other, these epitaxial source/drain regions 92 being exemplified by epitaxial source/drain regions 92A.i and 92a.ii, epitaxial source/drain regions 92B.i and 92b.ii, epitaxial source/drain regions 92C.i and 92c.ii, and corresponding dashed lines. On the other hand, vertically adjacent epitaxial source/drain regions 92 (e.g., epitaxial source/drain regions 92 directly above/below each other in a direction perpendicular to the major surface of substrate 50) remain separated from each other, e.g., epitaxial source/drain regions 92A-C. The epitaxial source/drain regions 92 may extend from sidewalls of the second nanostructures 54 and may extend along sidewalls of the first inner spacers 90 and the first spacers 80.

The epitaxial source/drain regions 92 may be epitaxially grown to have a thickness T in the range of about 30nm to about 200nm₃. The epitaxial source/drain regions 92 may have a height H in the range of about 50nm to about 400nm₁And may be separated from each other by a gap 93, the gap 93 having a height H in the range of about 50nm to about 200nm₂. The spacing and size of the first nanostructures 52 and the second nanostructures 54 may be related to the thickness T₃Together, to allow horizontally adjacent epitaxial source/drain regions 92 to merge with one another while vertically adjacent epitaxial source/drain regions 92 remain unmerged. In some embodiments, this may be accomplished by forming the film to have a thickness T₁The thickness T of the first semiconductor layer 51₁Greater than adjacentDistance D between nanostructures 55₁Such that horizontally adjacent second nanostructures 54 are more closely spaced than vertically adjacent second nanostructures 54. Horizontally adjacent second nanostructures 54 may be separated from each other by a distance D₁The distance D₁In the range of about 50nm to about 200nm, while vertically adjacent second nanostructures 54 may be separated from each other by a distance D₂The distance D₂Greater than the distance D₁And in the range of about 100nm to about 500 nm. This allows the horizontally merged epitaxial source/drain regions 92 to be used as source and bit lines and prevents shorting between vertically adjacent epitaxial source/drain regions 92. The use of merged epitaxial source/drain regions 92 as source and bit lines reduces device size, increases device density, and reduces cost.

Although the epitaxial source/drain regions 92 are shown as having a rectangular shape in the cross-sectional view shown in fig. 10A and a circular shape in the cross-sectional view shown in fig. 10C, the epitaxial source/drain regions 92 may have any suitable cross-sectional shape, such as hexagonal, octagonal, or other shape. In some embodiments, the epitaxial source/drain regions 92 may have facets. In some embodiments, the epitaxial source/drain regions 92 in both the n-type and p-type regions may comprise materials such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, silicon germanium, boron-doped silicon germanium, germanium tin, and the like.

Epitaxial source/drain regions 92 in n-type regions (e.g., NMOS regions) may be formed by masking p-type regions (e.g., PMOS regions). Epitaxial source/drain regions 92 are then epitaxially grown in the first recess 86 in the n-type region. Epitaxial source/drain regions 92 may comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructures 54 are silicon, the epitaxial source/drain regions 92 may comprise a material that exerts a tensile strain on the second nanostructures 54, e.g., silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, and the like.

Epitaxial source/drain regions 92 in p-type regions (e.g., PMOS regions) may be formed by masking n-type regions (e.g., NMOS regions). Epitaxial source/drain regions 92 are then epitaxially grown in the first recess 86 in the p-type region. Epitaxial source/drain regions 92 may comprise any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source/drain regions 92 may comprise a material that exerts a compressive strain on the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium tin, or the like.

The epitaxial source/drain regions 92, the second nanostructures 54, and/or the substrate 50 may be implanted with dopants to form source/drain regions (similar to the process previously discussed for forming lightly doped source/drain regions), and then annealed. The impurity concentration of the source/drain region may be about 1 × 10¹⁹Atom/cm³And about 1X 10²¹Atom/cm³In the meantime. The n-type and/or p-type impurities for the source/drain regions may be any of the previously discussed impurities. In some embodiments, the epitaxial source/drain regions 92 may be doped in-situ during growth.

In fig. 11A-11D, a first interlayer dielectric (ILD)96 is deposited over the structure shown in fig. 10A-10D, respectively. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (pecvd), ALD, and the like. The dielectric material may include silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon carbide, silicon oxynitride, and the like. Other insulating materials formed by any acceptable process may be used. As shown in fig. 11A and 11C, a first ILD 96 may be formed to surround the epitaxial source/drain regions 92 and fill the gap 93. The first ILD 96 may be formed along: the top, side and bottom surfaces of the epitaxial source/drain regions 92; a side surface of the first inner spacer 90; side and top surfaces of the first spacer 80; and the top surface of mask 78.

In fig. 12A-12D, a planarization process, such as CMP, may be performed to level the top surface of the first ILD 96 with the top surface of the dummy gate 76 or mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, as well as portions of the first spacers 80 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, first spacer 80, and first ILD 96 are flush within process variations. Thus, the top surface of dummy gate 76 is exposed by first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacers 80.

In fig. 13A-13D, dummy gate 76 and mask 78 (if present) are removed in one or more etching steps to form second recess 98. Portions of the dummy gate dielectric 71 in the second recess 98 may also be removed. In some embodiments, dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using reactive gas (es) that selectively etch the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 80. Each second recess 98 exposes and/or overlies portions of the nanostructures 55 that serve as channel regions in a subsequently completed nanoFET. The portion of the nanostructure 55 that serves as the channel region is disposed between adjacent pairs of the epitaxial source/drain regions 92. During removal, dummy gate dielectric 71 may serve as an etch stop layer when dummy gate 76 is etched. Dummy gate dielectric 71 may then be removed after dummy gate 76 is removed.

In fig. 14A to 14D, the first nanostructure 52 is removed, thereby expanding the second groove 98. The first nanostructures 52 may be removed by performing an isotropic etching process (e.g., wet etching, etc.) using an etchant selective to the material of the first nanostructures 52, while the second nanostructures 54, the substrate 50, the STI regions 58 remain relatively unetched compared to the first nanostructures 52. In embodiments where the first nanostructures 52 comprise, for example, silicon germanium and the second nanostructures 54A-54C comprise, for example, silicon or silicon carbide, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the first nanostructures 52. After the first nanostructures 52 are removed, the second nanostructures 5 adjacent in a vertical direction (e.g., a direction perpendicular to the major surface of the substrate 50)4 may be spaced apart from each other by a thickness of the first nanostructure (e.g., thickness T)₁) An equal distance.

In fig. 15A to 15D, a gate dielectric layer 100 and a gate electrode 102 are formed for a replacement gate. A gate dielectric layer 100 is conformally deposited in the second recess 98. A gate dielectric layer 100 may be formed on the top surface of the substrate 50, and on the top, side, and bottom surfaces of the second nanostructure 54. A gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, the top surface and side surfaces of the first spacer 80, and the side surfaces of the first inner spacer 90. The gate dielectric layer 100 may be deposited by CVD, PVD, ALD, Molecular Beam Deposition (MBD), PECVD, or the like.

In some embodiments, gate dielectric layer 100 may comprise a material that is capable of being switched between two different polarization directions by applying an appropriate voltage difference across gate dielectric layer 100. Gate dielectric layer 100 may be a high-k dielectric material, such as a hafnium (Hf) based dielectric material, or the like. In some embodiments, gate dielectric layer 100 comprises a Ferroelectric (FE) material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, and the like. In some embodiments, gate dielectric layer 100 may comprise a different ferroelectric material or a different type of dielectric material. In some embodiments, gate dielectric layer 100 may be in two SiO' s_xComprising SiN between layers_xA multi-layer dielectric structure of layers (e.g., an ONO structure). The structure of gate dielectric layer 100 may be the same or different in the n-type region and the p-type region. Gate dielectric layer 100 may have a thickness in the range of about 5nm to about 20 nm. Forming gate dielectric layer 100 to a thickness of less than 5nm may compromise performance, while forming gate dielectric layer 100 to a thickness of greater than 20nm may take up too much space.

A gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although a single layer of gate electrode 102 is shown in fig. 15A-15D, gate electrode 102 may include any number of liner layers, any number of work function adjusting layers, and a fill material. Any combination of layers making up the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructures 54A and the substrate 50.

The formation of gate dielectric layer 100 in the n-type region and the p-type region may occur simultaneously such that gate dielectric layer 100 in each region is formed of the same material, and the formation of gate electrode 102 may occur simultaneously such that gate electrode 102 in each region is formed of the same material. In some embodiments, gate dielectric layer 100 in each region may be formed by a different process such that gate dielectric layer 100 may be a different material and/or have a different number of layers, and/or gate electrode 102 in each region may be formed by a different process such that gate electrode 102 may be a different material and/or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate areas.

After filling the second recesses 98, a planarization process such as CMP may be performed to remove excess portions of the material of the gate dielectric layer 100 and the gate electrode 102 that are over the top surfaces of the first ILD 96 and the first spacers 80. The material of gate electrode 102 and the remaining portion of gate dielectric layer 100 thus form the replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure".

Although the second nanostructures 54 are shown as having a rectangular cross-sectional shape in fig. 14B and 15B, the second nanostructures 54 may have a circular, square, or other cross-sectional shape after removal of the dummy gate dielectric 71, the dummy gate 76, and the first nanostructures 52. As an example, fig. 15E shows an embodiment in which the second nanostructure 54 has a circular shape in a cross-sectional view, and fig. 15F shows an embodiment in which the second nanostructure 54 has a square shape in a cross-sectional view. The shape of the second nanostructures 54 may be controlled by controlling the thickness of the second semiconductor layer 53, the width of the second nanostructures 54, and the parameters of the etching process used to pattern the second nanostructures 54, remove the dummy gate dielectric 71, the dummy gate 76, and the first nanostructures 52. Gate dielectric layer 100 is conformally formed and thus has a cross-sectional shape similar to the cross-sectional shape of second nanostructure 54. For example, in the embodiment shown in fig. 15E, the gate dielectric layer 100 has a circular shape in a cross-sectional view, and in the embodiment shown in fig. 15E, the gate dielectric layer 100 has a square shape in a cross-sectional view.

In fig. 16A-16D, a trench 104 is patterned through the gate electrode 102, the gate dielectric layer 100, and the first spacer 80. The trench 104 may also be patterned through the second nanostructure 54. The trench 104 may be patterned by a combination of lithography and etching. The etch may be any acceptable etch process, for example, wet or dry etch, RIE, NBE, etc., or combinations thereof. The etch may be anisotropic. Trenches 104 may be disposed between opposing sidewalls of the first ILD 96 and the epitaxial source/drain regions 92, and the trenches 104 may physically separate adjacent stacks of memory cells 202 in the memory array 200 (see fig. 1A). The trench 104 may also be patterned through the gate electrode 102, the gate dielectric layer 100, the first spacer 80, and the second nanostructure 54 in portions of the structure that will subsequently form a stair step structure (e.g., stair step structure 110 discussed below with respect to fig. 21A-21D).

In fig. 17A-17D, a dielectric material 106 is deposited in the trench 104 and fills the trench 104. The dielectric material 106 may comprise, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, silicon carbide, silicon oxynitride, and the like, which may be deposited by CVD, PVD, ALD, PECVD, and the like. A dielectric material 106 may fill the trenches 104 and may be deposited to extend along the top surfaces of the first ILD 96, first spacer 80, gate dielectric layer 100, gate electrode 102, and substrate 50, and along the sidewalls of the gate dielectric layer 100, gate electrode 102, first ILD 96, and epitaxial source/drain regions 92. After deposition, a planarization process (e.g., CMP, etchback, etc.) may be performed to remove excess portions of the dielectric material 106. In the resulting structure, the top surfaces of the first ILD 96, first spacer 80, gate dielectric layer 100, gate electrode 102, and dielectric material 106 may be substantially flush with one another (e.g., within process variations).

Fig. 18A-21D illustrate patterning the first ILD 96 and the epitaxial source/drain regions 92 to form a stepped structure 110 (shown in fig. 21A-21D). In fig. 18A-18D, a photoresist 108 is formed over the first ILD 96, dielectric material 106, first spacer 80, gate dielectric layer 100, and gate electrode 102. The photoresist 108 may be formed using spin-coating techniques and may be patterned using acceptable photolithographic techniques. The patterned photoresist 108 may expose portions of the first ILD 96 and dielectric material 106 in the region 111 while masking the remaining portions of the first ILD 96, dielectric material 106, first spacer 80, gate dielectric layer 100, and gate electrode 102.

Further in fig. 18A-18D, the exposed portions of the first ILD 96 in the region 111 are etched using the photoresist 108 as a mask, and the portions of the epitaxial source/drain regions 92C under the exposed portions of the first ILD 96 in the region 111 are etched using the first ILD 96 as a mask. The etch may be any acceptable etch process, for example, wet or dry etch, RIE, NBE, etc., or combinations thereof. The etch may be anisotropic. The etch may remove portions of the first ILD 96 and the epitaxial source/drain regions 92C in the region 111 and define the opening 109. Since the first ILD 96 and the epitaxial source/drain regions 92C have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the epitaxial source/drain regions 92C serve as an etch stop layer when the first ILD 96 is etched, and the first ILD 96 serves as an etch stop layer when the epitaxial source/drain regions 92C are etched. As a result, portions of the first ILD 96 and epitaxial source/drain regions 92C may be selectively removed without removing the remaining portions of the first ILD 96 and epitaxial source/drain regions 92, and the openings 109 may extend to a desired depth. Alternatively, a timed etch process may be used to stop etching of opening 109 after opening 109 reaches a desired depth. In the resulting structure, a portion of the first ILD 96 over the epitaxial source/drain regions 92B is exposed in the region 111.

In fig. 19A-19D, the photoresist 108 is trimmed to expose additional portions of the first ILD 96 and the dielectric material 106. Acceptable photolithography techniques may be used to trim the photoresist 108. As a result of trimming, the width of the photoresist 108 is reduced and portions of the first ILD 96 and dielectric material 106 in the regions 111 and 113 are exposed. For example, the top surfaces of the first ILD 96 and dielectric material 106 in regions 113 and 111 may be exposed.

The exposed portions of the first ILD 96 and epitaxial source/drain regions 92 may then be etched using the photoresist 108 and portions of the first ILD 96 and epitaxial source/drain regions 92C as a mask. The etch may be any suitable etch process, for example, wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etch may extend the opening 109 further into the first ILD 96 and the epitaxial source/drain regions 92. Since the first ILD 96 and the epitaxial source/drain regions 92 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the epitaxial source/drain regions 92B-C serve as etch stops when etching portions of the first ILD 96, and portions of the first ILD 96 serve as etch stops when etching the epitaxial source/drain regions 92B-C. As a result, the first ILD 96 and epitaxial source/drain regions 92B-C may be selectively etched without etching the remaining portions of the first ILD 96 and epitaxial source/drain regions 92, and the opening 109 may extend to a desired depth. Alternatively, a timed etch process may be used to stop etching of opening 109 after opening 109 reaches a desired depth. Furthermore, during the etching process, the unetched portions of the first ILD 96 and epitaxial source/drain regions 92 serve as a mask for the underlying layers, and thus the previous pattern of the first ILD 96 and epitaxial source/drain regions 92C (see fig. 18A-18D) may be transferred to the underlying first ILD 96 and the underlying epitaxial source/drain regions 92B. In the resulting structure, the portions of first ILD 96 over epitaxial source/drain regions 92A are exposed in regions 111 and the portions of first ILD 96 over epitaxial source/drain regions 92B are exposed in regions 113.

In fig. 20A-20D, the photoresist 108 is trimmed to expose additional portions of the first ILD 96 and the dielectric material 106. Acceptable photolithography techniques may be used to trim the photoresist 108. As a result of trimming, the width of the photoresist 108 is reduced and portions of the first ILD 96 and dielectric material 106 in the regions 111, 113, and 115 are exposed. For example, the top surfaces of first ILD 96 and dielectric material 106 in regions 115, 113 and 111 may be exposed.

Exposed portions of the first ILD 96 and the epitaxial source/drain regions 92 may then be etched using the photoresist 108, the first ILD 96, the portions of the epitaxial source/drain regions 92C and the epitaxial source/drain regions 92B as a mask. The etch may be any suitable etch process, for example, wet or dry etch, RIE, NBE, or the like, or combinations thereof. The etching process may be anisotropic. The etch may extend the opening 109 further into the first ILD 96 and the epitaxial source/drain regions 92. Since the first ILD 96 and the epitaxial source/drain regions 92 have different material compositions, the etchant used to remove the exposed portions of these layers may be different. In some embodiments, the epitaxial source/drain regions 92A-C serve as etch stops when etching portions of the first ILD 96, and portions of the first ILD 96 serve as etch stops when etching the epitaxial source/drain regions 92A-C. As a result, the first ILD 96 and epitaxial source/drain regions 92A-C may be selectively etched without etching the remainder of the first ILD 96, and the opening 109 may extend to a desired depth. Alternatively, a timed etch process may be used to stop etching of opening 109 after opening 109 reaches a desired depth. Furthermore, during the etching process, the unetched portions of the first ILD 96 and epitaxial source/drain regions 92 serve as a mask for the underlying layers, and thus the previous pattern of the first ILD 96 and epitaxial source/drain regions 92B-C (see fig. 19A-19D) may be transferred to the underlying first ILD 96 and the underlying epitaxial source/drain regions 92A-B. In the resulting structure, the portion of the first ILD 96 over the substrate 50 is exposed in region 111, the portion of the first ILD 96 over the epitaxial source/drain regions 92A is exposed in region 113, and the portion of the first ILD 96 over the epitaxial source/drain regions 92B is exposed in region 115.

In fig. 21A through 21D, the photoresist 108 is removed by an acceptable ashing or wet strip process. Thus, the stepped structure 110 is formed. The stair-step structure 110 includes a stack of alternating layers of first ILD 96 and epitaxial source/drain regions 92. As shown in fig. 21C, the length of the epitaxial source/drain region 92 increases in a direction toward the substrate 50 such that the epitaxial source/drain region 92A is longer and extends laterally beyond the epitaxial source/drain region 92B, and the epitaxial source/drain region 92B is longer and extends laterally beyond the epitaxial source/drain region 92C. As a result, conductive contact may be made to each epitaxial source/drain region 92 from above the stepped structure 110 in subsequent process steps.

In fig. 22A-22D, an inter-metal dielectric (IMD)112 is deposited over the structure of fig. 21A-21D. An IMD 112 may be formed along top surfaces of the first ILD 96, first spacers 80, gate dielectric layer 100, gate electrode 102, dielectric material 106, and epitaxial source/drain regions 92A-C, and along side surfaces of the first ILD 96 and epitaxial source/drain regions 92A-C. IMD 112 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (fcvd), and the like. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. In some embodiments, IMD 112 may include an oxide (e.g., silicon oxide, etc.), a nitride (e.g., silicon nitride, etc.), combinations thereof, and the like. Other dielectric materials formed by any acceptable process may be used.

Further in fig. 22A-22D, contacts 114 and 116 are formed to extend and electrically couple to the epitaxial source/drain regions 92 and the gate electrode 102, respectively. The stepped shape of the epitaxial source/drain regions 92 provides a surface for landing (land on) of the contact 114 on each epitaxial source/drain region 92. For example, forming contacts 114 and 116 may include patterning openings in IMD 112 using a combination of photolithography and etching to expose portions of epitaxial source/drain regions 92 and gate electrode 102. In some embodiments, the openings in the IMD 112 may be formed by a process having a high etch selectivity to the material of the IMD 112. In this manner, openings in IMD 112 may be formed without significantly removing the material of epitaxial source/drain regions 92 and gate electrode 102.

In some embodiments, openings exposing each of the epitaxial source/drain regions 92A-C may be formed simultaneously. Due to variations in the thickness of IMD 112 over each epitaxial source/drain region 92A-C, epitaxial source/drain region 92C may be exposed to an etch for a longer duration than epitaxial source/drain region 92B, while epitaxial source/drain region 92B is exposed to an etch for a longer duration than epitaxial source/drain region 92A. Exposure to the etch may cause some material loss, pitting, or other damage in the epitaxial source/drain regions 92, such that the epitaxial source/drain regions 92C are damaged to a maximum extent, the epitaxial source/drain regions 92B are damaged to a reduced extent, and the epitaxial source/drain regions 92A are damaged to a minimum extent. The opening exposing the gate electrode 102 may be formed at the same time as the opening exposing the epitaxial source/drain region 92, or by a separate etching process similar or identical to the etching process used to form the opening exposing the epitaxial source/drain region 92.

A liner (not separately shown) such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, or the like. The contacts 114 and 116 may be formed simultaneously or separately. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 112. The remaining liner and conductive material form contacts 114 and 116 in the openings. As shown in fig. 22C, the contacts 114 may extend to each of the epitaxial source/drain regions 92A-C. As shown in fig. 22B, the contact 116 extends to each gate electrode 102.

In fig. 23, conductive lines 118 and 120 are formed over contacts 114 and 116, respectively, and are electrically coupled to contacts 114 and 116, respectively. Conductive lines 118 and conductive lines 120 may be formed over IMD 112. In some embodiments, conductive lines 118 and 120 may be formed in additional IMD layers formed over IMD 112 by processes and materials the same as or similar to those used for IMD 112. In some embodiments, conductive lines 118 and conductive lines 120 may be formed using a damascene process, in which additional IMD layers above IMD 112 are patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of conductive lines 118 and conductive lines 120. An optional diffusion barrier layer and/or an optional adhesion layer may be deposited in the trench, and then the trench may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, or other alternatives. Suitable materials for the conductive material include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, combinations thereof, and the like. In an embodiment, conductive lines 118 and 120 may be formed as follows: a seed layer of copper or copper alloy is deposited and electroplating is used to fill the trenches. A Chemical Mechanical Planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the additional IMD layer and planarize the conductive lines 118 and 120 and the surface of the additional IMD layer for subsequent processes.

As shown in fig. 23, gate electrodes 102 that are adjacent in a direction perpendicular to the length direction of epitaxial source/drain regions 92 may be electrically coupled to different conductive lines 120. Each contact 114 may be electrically coupled to one of the conductive wires 118. In some embodiments, gate electrode 102 may be a word line, which is connected to a word signal through contact 116 and conductive line 120. The epitaxial source/drain region 92 on the first side of the stair-step structure 110 may be a source line that is electrically coupled to a voltage source through contact 114 and conductive line 118, and the epitaxial source/drain region 92 on the second side of the stair-step structure 110 may be a bit line that is electrically coupled to ground through contact 114 and conductive line 118.

Forming epitaxial source/drain regions 92 that are horizontally merged with one another and vertically isolated allows for separate connections to be made to each epitaxial source/drain region 92A-C in the stepped structure 110. This increases the number of devices that can be provided in a given area (e.g., increases device density) and reduces cost.

Fig. 24A to 32 illustrate an embodiment in which the second nanostructures 54 of adjacent gate structures are staggered (staggered) with respect to each other. Fig. 24A-24C show the nanostructures 55 after steps similar or identical to those shown in fig. 3-4C and discussed above have been performed. The nanostructures 55 may be formed to have different widths and pitches than discussed above with respect to the embodiments of fig. 3-4C. For example, the nanostructures 55 may have a width W in the range of about 10nm to about 50nm₂. The nanostructures 55 may be separated by a distance D in the range of about 20nm to about 300nm₃. Forming first nanostructures 55 having a defined width and spacing may help allow horizontally adjacent subsequently formed epitaxial source/drain regions (e.g., epitaxial source/drain regions 92 discussed below with respect to fig. 29A-29D) to merge while vertically adjacent subsequently formed epitaxial source/drain regions do not merge. This allows the horizontally merged epitaxial source/drain regions to be used as source lines and bit lines and prevents shorting between vertically adjacent epitaxial source/drain regions. The use of merged epitaxial source/drain regions as source and bit lines reduces device size, increases device density, and reduces cost.

The nanostructures 55 may include first nanostructures 52A-C (collectively referred to as first nanostructures 52) and second nanostructures 54A-C (collectively referred to as second nanostructures 54) similar or identical to those described above. The first nanostructures 52 may be formed to have a height H in a range of about 100nm to about 500nm₃While the second nanostructures 54 may be formed to have a height H in the range of about 10nm to about 50nm₄. In some embodiments, the height H of the first nanostructure 52₃Height H from the second nanostructure 54₄The ratio may be in the range of about 2 to about 10. Forming first nanostructures 52 and second nanostructures 54 with a specified thickness may help allow for horizontally adjacent subsequently formed epitaxial source/drainsRegions (e.g., epitaxial source/drain regions 92 discussed below with respect to fig. 29A-29D) merge, while vertically adjacent subsequently formed epitaxial source/drain regions do not merge. This allows the horizontally merged epitaxial source/drain regions to be used as source lines and bit lines and prevents shorting between vertically adjacent epitaxial source/drain regions. The use of merged epitaxial source/drain regions as source and bit lines reduces device size, increases device density, and reduces cost.

In fig. 25A to 25C, the nanostructures 55 are patterned to form a gap 130 in each of the nanostructures 55. The gap 130 may extend through the second nanostructures 54A-C and the first nanostructures 52A-C and may expose a surface of the substrate 50. The nanostructures 55 may be patterned using the same or similar processes as discussed above with respect to fig. 4A-4C. In some embodiments, the nanostructures 55 may be formed and patterned in a single process step to form the gaps 130. As shown in fig. 25C, the gaps 130 formed in adjacent nanostructures 55 may be staggered, and the remaining portions of adjacent nanostructures 55 may also be staggered. Portions of the remaining portions of adjacent nanostructures 55 may overlap each other. Forming the nanostructures 55 in a staggered configuration may simplify connection to the second nanostructures 54 in subsequent steps, reducing cost and device defects. Following patterning of nanostructures 55, portions of nanostructures 55 that subsequently form the channel region of transistor 204 may be separated from each other by a distance D in the range of about 50nm to about 200nm in a direction perpendicular to the longitudinal axis of nanostructures 55₄。

In fig. 26A to 26C, a dummy dielectric layer 70 is formed on the nanostructure 55. Dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70 and a mask layer 74 is formed over the dummy gate layer 72. Dummy gate layer 72 may be deposited over dummy dielectric layer 70 and then planarized, for example by CMP. A mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material and may be selected from the group consisting of: amorphous silicon, polysilicon (polysilicon), poly-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials having a high etch selectivity with respect to the etching of the isolation regions. The mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed over the n-type region and the p-type region. Note that dummy dielectric layer 70 is shown to cover only nanostructures 55 for exemplary purposes only. In some embodiments, dummy dielectric layer 70 may be deposited such that dummy dielectric layer 70 covers substrate 50 such that dummy dielectric layer 70 extends between dummy gate layer 72 and substrate 50.

In fig. 27A-27C, mask layer 74 (see fig. 26A-26C) may be patterned using acceptable photolithography and etching techniques to form mask 78. The pattern of mask 78 may then be transferred to dummy gate layer 72 and dummy dielectric layer 70, respectively, to form dummy gate 76 and dummy gate dielectric 71. Dummy gate 76 covers the corresponding channel region of nanostructure 55. The pattern of the mask 78 may be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gates 76 may also have a length direction that is substantially perpendicular to the length direction of the corresponding nanostructures 55.

Further in fig. 27A-27C, first spacers 80 are formed over the nanostructures 55, adjacent dummy gate dielectric 71, dummy gate 76, and mask 78. The first spacers 80 may serve as spacers for forming self-aligned source/drain regions. May be formed by at the top surface of substrate 50; the top surface and sidewalls of nanostructures 55 and mask 78; and depositing a first spacer layer (not separately shown) on sidewalls of dummy gate 76 and dummy gate dielectric 71 to form first spacers 80. The first spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation, or may be deposited by CVD, ALD, or the like.

The first spacer layer may then be etched to form first spacers 81. As will be discussed in more detail below, the first spacers 80 are used to self-align subsequently formed source drain regions, as well as protect the sidewalls of the nanostructures 55 during subsequent processing. The first spacer layer may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), and so forth. As shown in fig. 27A, first spacers 80 may be disposed on sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. As shown in fig. 27C, the first spacers 80 may be further disposed on sidewalls of the nanostructures 55.

As shown in fig. 27A, the first spacers 80 may be formed to extend along the end surfaces of the first and second nanostructures 52, 54. In some embodiments, the dummy gate 76 may be formed to extend along end surfaces of the first and second nanostructures 52, 54, and the first spacer 80 may be formed over the second nanostructure 54C.

Although nanostructures 55 are described as being patterned to form gaps 130 prior to forming and patterning dummy gate 76, dummy gate dielectric 71, and mask 78, in some embodiments, nanostructures 55 may be patterned to form gaps 130 after forming and patterning dummy gate 76, dummy gate dielectric 71, and mask 78. Further, the nanostructures 55 may be patterned to form the gaps 130 before or after forming the first spacers 80.

In fig. 28A to 28C, a first groove 86 is formed in the nanostructure 55. In some embodiments, the first groove 86 may also extend at least partially into the substrate 50. Epitaxial source/drain regions will subsequently be formed in the first recess 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54. As shown in fig. 28A, the first recess 86 may extend to the top surface of the substrate 50. The first recess 86 may be formed by etching the nanostructure 55 using an anisotropic etching process (e.g., RIE, NBE, etc.). The first spacers 80 and mask 78 mask portions of the nanostructures 55 during an etching process for forming the first recesses 86. Each layer of nanostructures 55 may be etched using a single etch process or multiple etch processes. A timed etch process may be used to stop etching first recess 86 after first recess 86 reaches a desired depth.

Further in fig. 28A-28C, the portions of the sidewalls of the first nanostructures 52 exposed by the first grooves 86 are replaced by first interior spacers 90. The first nanostructures 52 may be etched using the same or similar process as discussed above with respect to fig. 8. The first interior spacer 90 may then be formed using the same or similar processes and materials as discussed above with respect to fig. 9A or 9B.

In fig. 29A-29D, epitaxial source/drain regions 92A-C are formed in the first recess 86. The epitaxial source/drain regions 92A-C may be collectively referred to as epitaxial source/drain regions 92. In some embodiments, the epitaxial source/drain regions 92 may exert stress on the second nanostructures 54, thereby improving performance. As shown in fig. 29A, epitaxial source/drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a respective adjacent pair of epitaxial source/drain regions 92. In some embodiments, the first spacers 80 are used to separate the epitaxial source/drain regions 92 from the dummy gate 76 by an appropriate lateral distance, and the first internal spacers 90 are used to separate the epitaxial source/drain regions 92 from the first nanostructures 52 by an appropriate lateral distance, such that the epitaxial source/drain regions 92 do not short the gates of the subsequently formed resulting nanofets.

As shown in fig. 29A, 29C, and 29D, epitaxial source/drain regions 92A-C may be epitaxially grown from the second nanostructures 54A-C, respectively. The epitaxial source/drain regions 92 may be grown such that horizontally adjacent epitaxial source/drain regions 92 (e.g., epitaxial source/drain regions 92 adjacent to each other in a direction parallel to the major surface of the substrate 50) merge with each other, e.g., epitaxial source/drain regions 92A.i and 92a.ii, epitaxial source/drain regions 92B.i and 92b.ii, epitaxial source/drain regions 92C.i and 92c.ii, and corresponding dashed lines. On the other hand, vertically adjacent epitaxial source/drain regions 92 (e.g., epitaxial source/drain regions 92 directly above/below each other in a direction perpendicular to the major surface of substrate 50) remain separated from each other, e.g., epitaxial source/drain regions 92A-C. The epitaxial source/drain regions 92 may extend from sidewalls of the second nanostructures 54 and may extend along sidewalls of the first inner spacers 90 and the first spacers 80.

The epitaxial source/drain regions 92 may be epitaxially grown to have a thickness T in the range of about 30nm to about 200nm₄. The epitaxial source/drain regions 92 may have a height H in the range of about 50nm to about 400nm₅And may be separated from each other by a gap 93, the gap 93 having a height H in the range of about 50nm to about 200nm₆. The spacing and size of the first nanostructures 52 and the second nanostructures 54 may be related to the thickness T₄Together, to allow horizontally adjacent epitaxial source/drain regions 92 to merge with one another while vertically adjacent epitaxial source/drain regions 92 remain unmerged. In some embodiments, this may be accomplished as follows: is formed to have a height H₃The height H of the first nanostructure 52₃Greater than the distance D between adjacent nanostructures 55₄Such that horizontally adjacent second nanostructures 54 are more closely spaced than vertically adjacent second nanostructures 54. Horizontally adjacent second nanostructures 54 may be separated from each other by a distance D₄The distance D₄In the range of about 50nm to about 200nm, while vertically adjacent second nanostructures 54 may be separated from each other by a distance D₅The distance D₅Greater than the distance D₄And in the range of about 100nm to about 500 nm. This allows the horizontally merged epitaxial source/drain regions 92 to be used as source and bit lines and prevents shorting between vertically adjacent epitaxial source/drain regions 92. The use of merged epitaxial source/drain regions 92 as source and bit lines reduces device size, increases device density, and reduces cost.

Although the epitaxial source/drain regions 92 are shown as having a rectangular shape in the cross-sectional view shown in fig. 29A and a circular shape in the cross-sectional view shown in fig. 29C, the epitaxial source/drain regions 92 may have any suitable cross-sectional shape, such as hexagonal, octagonal, or other shape. In some embodiments, the epitaxial source/drain regions 92 may have facets. In some embodiments, the epitaxial source/drain regions 92 in both the n-type and p-type regions may comprise materials such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, silicon germanium, boron-doped silicon germanium, germanium tin, and the like.

Epitaxial source/drain regions 92 in n-type regions (e.g., NMOS regions) may be formed by masking p-type regions (e.g., PMOS regions). Epitaxial source/drain regions 92 are then epitaxially grown in the first recess 86 in the n-type region. Epitaxial source/drain regions 92 may comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructures 54 are silicon, the epitaxial source/drain regions 92 may comprise a material that exerts a tensile strain on the second nanostructures 54, e.g., silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, and the like.

Epitaxial source/drain regions 92 in p-type regions (e.g., PMOS regions) may be formed by masking n-type regions (e.g., NMOS regions). Epitaxial source/drain regions 92 are then epitaxially grown in the first recess 86 in the p-type region. Epitaxial source/drain regions 92 may comprise any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source/drain regions 92 may comprise a material that exerts a compressive strain on the second nanostructure 54, such as silicon germanium, boron-doped silicon germanium, germanium tin, or the like.

The epitaxial source/drain regions 92, the second nanostructures 54, and/or the substrate 50 may be implanted with dopants to form source/drain regions, similar to the processes previously discussed for forming lightly doped source/drain regions, and then annealed. The impurity concentration of the source/drain region may be about 1 × 10¹⁹Atom/cm³And about 1X 10²¹Atom/cm³In the meantime. The n-type and/or p-type impurities for the source/drain regions may be any of the previously discussed impurities. In some embodiments, the epitaxial source/drain regions 92 may be doped in-situ during growth.

Fig. 30A to 30D show the structure after the steps shown in fig. 11A to 21D have been performed as described above. Specifically, a first ILD 96 is formed around the epitaxial source/drain regions 92, the dummy gate structure is replaced with a gate structure including a gate electrode 102 and a gate dielectric layer 100, portions of the gate structure are replaced with a dielectric material 106, and a stair step structure 110 is formed in the epitaxial source/drain regions 92 and the first ILD 96.

In fig. 31A to 31D, an inter-metal dielectric (IMD)112 is deposited over the structure of fig. 30A to 30D. An IMD 112 may be formed along top surfaces of the first ILD 96, first spacers 80, gate dielectric layer 100, gate electrode 102, dielectric material 106, and epitaxial source/drain regions 92A-C, and along side surfaces of the first ILD 96 and epitaxial source/drain regions 92A-C. IMD 112 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (fcvd), and the like. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. In some embodiments, IMD 112 may include an oxide (e.g., silicon oxide, etc.), a nitride (e.g., silicon nitride, etc.), combinations thereof, and the like. Other dielectric materials formed by any acceptable process may be used.

Further in fig. 31A-31D, contacts 114 and 116 are formed to extend and electrically couple to the epitaxial source/drain regions 92 and the gate electrode 102, respectively. The stepped shape of the epitaxial source/drain regions 92 provides a surface for landing of the contacts 114 on each epitaxial source/drain region 92. For example, forming contacts 114 and 116 may include patterning openings in IMD 112 using a combination of photolithography and etching to expose portions of epitaxial source/drain regions 92 and gate electrode 102. In some embodiments, the openings in the IMD 112 may be formed by a process having a high etch selectivity to the material of the IMD 112. In this manner, openings in IMD 112 may be formed without significantly removing the material of epitaxial source/drain regions 92 and gate electrode 102.

In some embodiments, openings exposing each of the epitaxial source/drain regions 92A-C may be formed simultaneously. Due to variations in the thickness of IMD 112 over each epitaxial source/drain region 92A-C, epitaxial source/drain region 92C may be exposed to an etch for a longer duration than epitaxial source/drain region 92B, while epitaxial source/drain region 92B is exposed to an etch for a longer duration than epitaxial source/drain region 92A. Exposure to the etch may cause some material loss, pitting, or other damage in the epitaxial source/drain regions 92, such that the epitaxial source/drain regions 92C are damaged to a maximum extent, the epitaxial source/drain regions 92B are damaged to a reduced extent, and the epitaxial source/drain regions 92A are damaged to a minimum extent. The opening exposing the gate electrode 102 may be formed at the same time as the opening exposing the epitaxial source/drain region 92, or by a separate etching process similar or identical to the etching process used to form the opening exposing the epitaxial source/drain region 92.

A liner (not separately shown) such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, or the like. The contacts 114 and 116 may be formed simultaneously or separately. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 112. The remaining liner and conductive material form contacts 114 and 116 in the openings. As shown in fig. 31C, the contacts 114 may extend to each of the epitaxial source/drain regions 92A-C. As shown in fig. 31B, the contact 116 extends to each gate electrode 102.

In fig. 32, conductive lines 118 and 120 are formed over contacts 114 and 116, respectively, and are electrically coupled to contacts 114 and 116, respectively. Conductive lines 118 and conductive lines 120 may be formed over IMD 112. In some embodiments, conductive lines 118 and 120 may be formed in additional IMD layers formed over IMD 112 by processes and materials the same as or similar to those used for IMD 112. In some embodiments, conductive lines 118 and conductive lines 120 may be formed using a damascene process, in which additional IMD layers above IMD 112 are patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of conductive lines 118 and conductive lines 120. An optional diffusion barrier layer and/or an optional adhesion layer may be deposited in the trench, and then the trench may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, or other alternatives. Suitable materials for the conductive material include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, titanium nitride, tantalum nitride, combinations thereof, and the like. In an embodiment, conductive lines 118 and 120 may be formed as follows: a seed layer of copper or copper alloy is deposited and electroplating is used to fill the trenches. A Chemical Mechanical Planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the additional IMD layer and planarize the conductive lines 118 and 120 and the surface of the additional IMD layer for subsequent processes.

As shown in fig. 32, the gate electrode 102 formed by each stack of first nanostructures 52 (shown in fig. 24A-24C) may be electrically coupled to the same conductive line 120. The gate electrodes 102 formed by adjacent first nanostructures 52 are connected to adjacent conductive lines 120. Each contact 114 may be electrically coupled to one of the conductive wires 118. In some embodiments, gate electrode 102 may be a word line, which is connected to a word signal through contact 116 and conductive line 120. The epitaxial source/drain region 92 on the first side of the stair-step structure 110 may be a source line that is electrically coupled to a voltage source through contact 114 and conductive line 118, and the epitaxial source/drain region 92 on the second side of the stair-step structure 110 may be a bit line that is electrically coupled to ground through contact 114 and conductive line 118. Forming nanostructures 55 in the staggered configuration of fig. 25A-25C allows for electrically coupling a single conductive line 120 to gate electrode 102 formed by each stack of first nanostructures 52, which simplifies the connection layout, reduces cost, and reduces device defects.

Embodiments may achieve various advantages. For example, forming epitaxial source/drain regions 92 that are horizontally merged with one another and vertically isolated allows for separate connections to be made to each epitaxial source/drain region 92A-C in the stepped structure 110. This increases the number of devices that can be provided in a given area (e.g., increases device density) and reduces cost.

According to one embodiment, a memory array comprises: a first channel region over the semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to the main surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric. In one embodiment, the memory array further comprises: a second channel region directly above the first channel region in a direction perpendicular to the main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region, the gate dielectric also surrounding the second channel region. In an embodiment, a ratio of a distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate to a height of the first channel region and the second channel region is 2 to 10. In one embodiment, the memory array further comprises: a second channel region located directly above the first channel region in a direction perpendicular to the main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region; and a third channel region adjacent to the first channel region in a direction parallel to the main surface of the semiconductor substrate, the third channel region being electrically coupled to the first epitaxial region. In an embodiment, a distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate is larger than a distance between the first channel region and the third channel region in a direction parallel to the main surface of the semiconductor substrate. In an embodiment, a distance between the second epitaxial region and the semiconductor substrate is greater than a distance between the first epitaxial region and the semiconductor substrate, and a length of the second epitaxial region is less than a length of the first epitaxial region. In an embodiment, the gate dielectric comprises a ferroelectric material.

According to another embodiment, a semiconductor device includes: a first channel region over the semiconductor substrate; a second channel region located right above the first channel region in a vertical direction; a first gate structure surrounding the first channel region and the second channel region; a third channel region adjacent to the first channel region in a horizontal direction; a first source/drain region electrically coupled to the first channel region and the third channel region; and a second source/drain region electrically coupled to the second channel region and isolated from the first source/drain region, the first dielectric material extending between the first source/drain region and the second source/drain region. In an embodiment, a second gate structure surrounds the third channel region, the second gate structure being separated from the first gate structure by a second dielectric material. In one embodiment, the length of the second source/drain region is less than the length of the first source/drain region. In an embodiment, the first and second source/drain regions are bit lines or source lines and the first gate structure is a word line. In one embodiment, the memory array further comprises: a third source/drain region electrically coupled to the first channel region and the third channel region, the third source/drain region being disposed on an opposite side of the first channel region and the third channel region from the first source/drain region, the first source/drain region being a source line, and the third source/drain region being a bit line. In one embodiment, the memory array further comprises: a fourth channel region electrically coupled to the first source/drain region, a longitudinal axis of the fourth channel region being aligned with a longitudinal axis of the first channel region; a second gate structure surrounding the fourth channel region; a first conductive line electrically coupled to the first gate structure, the first conductive line disposed at a first side of the first channel region and the fourth channel region in a horizontal direction; and a second conductive line electrically coupled to the second gate structure, the second conductive line being disposed on a second side of the first and fourth channel regions opposite to the first side in a horizontal direction. In one embodiment, the memory array further comprises: a fourth channel region electrically coupled to the first source/drain region opposite the first channel region, a longitudinal axis of the fourth channel region being aligned with the first gate structure; and a second gate structure surrounding the fourth channel region, a longitudinal axis of the first channel region being aligned with the second gate structure.

According to yet another embodiment, a method comprises: forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; patterning the multilayer stack to form a first plurality of nanostructures comprising a first semiconductor material and a second plurality of nanostructures comprising a second semiconductor material, the second plurality of nanostructures comprising the first nanostructures, second nanostructures adjacent to the first nanostructures in a direction parallel to the major surface of the semiconductor substrate, and third nanostructures directly above the first nanostructures in a direction perpendicular to the major surface of the semiconductor substrate; forming a gate structure over the multi-layer stack; etching the multi-layer stack to form a first recess adjacent to the gate structure; and epitaxially growing source/drain regions from the second plurality of nanostructures, after epitaxially growing the source/drain regions, a first source/drain region epitaxially grown from the first nanostructure and a second source/drain region epitaxially grown from the second nanostructure merging with one another, and a third source/drain region epitaxially grown from the third nanostructure being isolated from the first source/drain region. In an embodiment, the longitudinal axes of the first and second plurality of nanostructures extend parallel to a first direction, and after patterning the multilayer stack, the first and second plurality of nanostructures form a first stack and a second stack, the second stack being separated from the first stack in the first direction. In an embodiment, after patterning the multi-layer stack, the first plurality of nanostructures and the second plurality of nanostructures further form a third stack separated from the first stack and the second stack in a second direction perpendicular to the first direction, a first end surface of the third stack being located between opposing end surfaces of the first stack in the first direction, and a second end surface of the third stack opposite the first end surface being located between opposing end surfaces of the second stack in the first direction. In an embodiment, the method further comprises: removing the first plurality of nanostructures and the gate structure to form a second recess; and forming a replacement gate structure in the second recess. In an embodiment, the method further comprises: patterning the replacement gate structure to form a third recess, the third recess separating the first replacement gate structure from the second replacement gate structure; and forming a dielectric material in the third recess. In an embodiment, the method further comprises: a dielectric material is formed between the first source/drain region and the third source/drain region, the dielectric material isolating the first source/drain region from the third source/drain region.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1. a memory array, comprising:

a first channel region over the semiconductor substrate;

a first epitaxial region electrically coupled to the first channel region;

a second epitaxial region located directly above the first epitaxial region in a direction perpendicular to the main surface of the semiconductor substrate;

a dielectric material between the first epitaxial region and the second epitaxial region, wherein the second epitaxial region is isolated from the first epitaxial region by the dielectric material;

a gate dielectric surrounding the first channel region; and

a gate electrode surrounding the gate dielectric.

Example 2. the memory array of example 1, further comprising a second channel region directly above the first channel region in a direction perpendicular to the major surface of the semiconductor substrate, the second channel region electrically coupled to the second epitaxial region, wherein the gate dielectric also surrounds the second channel region.

Example 3. the memory array of example 2, wherein a ratio of a distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate to a height of the first channel region and the second channel region is 2 to 10.

Example 4. the memory array of example 2, further comprising:

a second channel region directly above the first channel region in a direction perpendicular to a main surface of the semiconductor substrate, the second channel region being electrically coupled to the second epitaxial region; and

a third channel region adjacent to the first channel region in a direction parallel to a major surface of the semiconductor substrate, the third channel region electrically coupled to the first epitaxial region.

Example 5 the memory array of example 4, wherein a distance between the first channel region and the second channel region in a direction perpendicular to the main surface of the semiconductor substrate is greater than a distance between the first channel region and the third channel region in a direction parallel to the main surface of the semiconductor substrate.

Example 6. the memory array of example 1, wherein a distance between the second epitaxial region and the semiconductor substrate is greater than a distance between the first epitaxial region and the semiconductor substrate, and wherein a length of the second epitaxial region is less than a length of the first epitaxial region.

Example 7. the memory array of example 1, wherein the gate dielectric comprises a ferroelectric material.

Example 8. a semiconductor device, comprising:

a first channel region over the semiconductor substrate;

a second channel region located directly above the first channel region in a vertical direction;

a first gate structure surrounding the first channel region and the second channel region;

a third channel region adjacent to the first channel region in a horizontal direction;

a first source/drain region electrically coupled to the first channel region and the third channel region; and

a second source/drain region electrically coupled to the second channel region and isolated from the first source/drain region, wherein a first dielectric material extends between the first source/drain region and the second source/drain region.

Example 9. the semiconductor device of example 8, wherein a second gate structure surrounds the third channel region, the second gate structure being separated from the first gate structure by a second dielectric material.

Example 10 the semiconductor device of example 8, wherein a length of the second source/drain region is less than a length of the first source/drain region.

Example 11 the semiconductor device of example 8, wherein the first and second source/drain regions are bit lines or source lines, and wherein the first gate structure is a word line.

Example 12 the semiconductor device of example 8, further comprising: a third source/drain region electrically coupled to the first and third channel regions, the third source/drain region disposed on an opposite side of the first and third channel regions from the first source/drain region, wherein the first source/drain region is a source line, and wherein the third source/drain region is a bit line.

Example 13 the semiconductor device of example 8, further comprising:

a fourth channel region electrically coupled to the first source/drain region, wherein a longitudinal axis of the fourth channel region is aligned with a longitudinal axis of the first channel region;

a second gate structure surrounding the fourth channel region;

a first conductive line electrically coupled to the first gate structure, the first conductive line disposed on a first side of the first and fourth channel regions in the horizontal direction; and

a second conductive line electrically coupled to the second gate structure, the second conductive line disposed on a second side of the first and fourth channel regions opposite the first side in the horizontal direction.

Example 14 the semiconductor device of example 8, further comprising:

a fourth channel region electrically coupled to the first source/drain region opposite the first channel region, wherein a longitudinal axis of the fourth channel region is aligned with the first gate structure; and

a second gate structure surrounding the fourth channel region, wherein a longitudinal axis of the first channel region is aligned with the second gate structure.

Example 15. a method, comprising:

forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material;

patterning the multilayer stack to form a first plurality of nanostructures comprising the first semiconductor material and a second plurality of nanostructures comprising the second semiconductor material, the second plurality of nanostructures comprising first nanostructures, second nanostructures, and third nanostructures, the second nanostructures being adjacent to the first nanostructures in a direction parallel to a major surface of the semiconductor substrate, the third nanostructures being directly above the first nanostructures in a direction perpendicular to the major surface of the semiconductor substrate;

forming a gate structure over the multi-layer stack;

etching the multi-layer stack to form a first recess adjacent to the gate structure; and

epitaxially growing a source/drain region from the second plurality of nanostructures, wherein after epitaxially growing the source/drain region, a first source/drain region epitaxially grown from the first nanostructure and a second source/drain region epitaxially grown from the second nanostructure merge with one another, and wherein a third source/drain region epitaxially grown from the third nanostructure is isolated from the first source/drain region.

Example 16. the method of example 15, wherein longitudinal axes of the first and second pluralities of nanostructures extend parallel to a first direction, and wherein, after patterning the multilayer stack, the first and second pluralities of nanostructures form a first stack and a second stack, the second stack being separated from the first stack in the first direction.

The method of example 16, wherein, after patterning the multilayer stack, the first and second pluralities of nanostructures further form a third stack separated from the first and second stacks in a second direction perpendicular to the first direction, wherein a first end surface of the third stack is located between opposing end surfaces of the first stack in the first direction, and wherein a second end surface of the third stack opposite the first end surface is located between opposing end surfaces of the second stack in the first direction.

Example 18. the method of example 15, further comprising:

removing the first plurality of nanostructures and the gate structure to form a second recess; and

and forming a replacement gate structure in the second groove.

Example 19. the method of example 18, further comprising:

patterning the replacement gate structure to form a third recess separating the first replacement gate structure from the second replacement gate structure; and

forming a dielectric material in the third recess.

Example 20. the method of example 15, further comprising: forming a dielectric material between the first source/drain region and the third source/drain region, the dielectric material isolating the first source/drain region from the third source/drain region.