阅读说明：本技术 阵列基板及其制备方法、显示面板 (Array substrate, preparation method thereof and display panel ) 是由 王旭 徐洪远 江志雄 胡道兵 于 2021-07-16 设计创作，主要内容包括：本发明提供一种阵列基板及其制备方法、显示面板,该阵列基板包括衬底和设置于衬底上的低温多晶硅薄膜晶体管。其中,低温多晶硅薄膜晶体管包括第一有源层,第一有源层包括层叠设置的多晶硅层和非晶硅层。本发明通过将低温多晶硅薄膜晶体管的有源层设置为多晶硅层和非晶硅层的双层结构,因此无需传统的低温多晶硅薄膜晶体管制程中对有源层进行离子掺杂,可以减少光罩使用数量,从而精简制程,降低成本。(The invention provides an array substrate, a preparation method thereof and a display panel. The low-temperature polycrystalline silicon thin film transistor comprises a first active layer, and the first active layer comprises a polycrystalline silicon layer and an amorphous silicon layer which are arranged in a stacked mode. The active layer of the low-temperature polycrystalline silicon thin film transistor is set to be a double-layer structure of the polycrystalline silicon layer and the amorphous silicon layer, so that the active layer does not need to be subjected to ion doping in the traditional low-temperature polycrystalline silicon thin film transistor manufacturing process, the number of used photomasks can be reduced, the manufacturing process is simplified, and the cost is reduced.)

1. An array substrate, comprising:

a substrate;

the low-temperature polycrystalline silicon thin film transistor is arranged on the substrate;

the low-temperature polycrystalline silicon thin film transistor comprises a first active layer, wherein the first active layer comprises a polycrystalline silicon layer and an amorphous silicon layer which are arranged in a stacked mode.

2. The array substrate of claim 1, wherein the amorphous silicon layer is located on a side of the polysilicon layer away from the substrate.

3. The array substrate of claim 1, further comprising an oxide thin film transistor disposed on the substrate and spaced apart from the low temperature polysilicon thin film transistor, wherein the oxide thin film transistor and the low temperature polysilicon thin film transistor are both bottom gate structures.

4. The array substrate of claim 3,

the low temperature polysilicon thin film transistor further comprises:

the first grid is positioned on one side, close to the substrate, of the first active layer;

the first source electrode and the first drain electrode are positioned on one side of the first active layer, which is far away from the substrate, and are respectively contacted with the non-channel region of the first active layer;

the oxide thin film transistor includes:

the second grid electrode is arranged on the same layer as the first grid electrode;

the second active layer is positioned on one side of the second grid electrode, which is far away from the substrate, and is arranged on the same layer as the first active layer;

and the second source electrode and the second drain electrode are positioned on one side of the second active layer, which is far away from the substrate, are arranged at the same layer as the first source electrode and the first drain electrode, and are respectively contacted with a non-channel region of the second active layer.

5. The array substrate of claim 4, wherein the LTPS TFT further comprises an ionic layer correspondingly located on a non-channel region of the first active layer on a side away from the substrate, the first source electrode and the first drain electrode are located on the ionic layer, and the first source electrode and the first drain electrode are respectively in contact with the non-channel region of the first active layer through the ionic layer;

the oxide thin film transistor further comprises an etching barrier layer, the etching barrier layer is located on one side, far away from the substrate, of the second active layer, the second source electrode and the second drain electrode are located on the etching barrier layer, the etching barrier layer comprises a through hole penetrating through the etching barrier layer, the through hole exposes a non-channel region of the second active layer, and the second source electrode and the second drain electrode are respectively in contact with the non-channel region of the second active layer through the through hole.

6. The preparation method of the array substrate is characterized by comprising a preparation method of a first active layer of a low-temperature polycrystalline silicon thin film transistor, and the preparation method of the first active layer comprises the following steps:

forming a first amorphous silicon layer on a substrate, wherein the first amorphous silicon layer includes a plurality of regions to be crystallized;

performing a laser annealing process on the multiple regions to be crystallized to enable the first amorphous silicon layer to form polycrystalline silicon corresponding to the parts of the multiple regions to be crystallized;

forming a second amorphous silicon layer on the first amorphous silicon layer;

and patterning the first amorphous silicon layer and the second amorphous silicon layer to remove the first amorphous silicon layer and the second amorphous silicon layer except the polycrystalline silicon layer, and forming the first active layer comprising the polycrystalline silicon layer and the amorphous silicon layer which are arranged in a stacked manner.

7. The method for manufacturing an array substrate according to claim 6, wherein the method for manufacturing an array substrate comprises:

step S21, forming a plurality of first gates and a plurality of second gates on the substrate;

step S22, forming a dielectric layer on the first gate, the second gate and the substrate;

step S23 of forming the first active layer facing the first gate electrode and an ionic film pattern on the dielectric layer, the ionic film pattern being formed on the first active layer;

step S24, forming a second active layer on the dielectric layer opposite to the second gate electrode;

step S25, forming an etching barrier layer on the second active layer, and simultaneously forming a via hole exposing the non-channel region of the second active layer on the etching barrier layer;

step S26, forming a first source electrode and a first drain electrode on the ion layer, simultaneously forming a second source electrode and a second drain electrode on the etching barrier layer, and simultaneously forming an ion layer;

wherein the first source electrode and the first drain electrode are in contact with a non-channel region of the first active layer through the ionic layer, respectively, and the second source electrode and the second drain electrode are in contact with a non-channel region of the second active layer through the via hole, respectively.

8. The method for manufacturing the array substrate according to claim 7, wherein the first gate and the second gate are made of the same material, and the first gate and the second gate are formed simultaneously by using the same mask; the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are made of the same material, and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are formed at the same time by adopting the same photomask.

9. The method of manufacturing the array substrate of claim 7, wherein the method of forming the first active layer and the ionic film pattern on the dielectric layer facing the first gate electrode comprises:

and sequentially forming a second amorphous silicon layer and an ion film which are stacked on the first amorphous silicon layer, and patterning the first amorphous silicon layer, the second amorphous silicon layer and the ion film to remove the first amorphous silicon layer, the second amorphous silicon layer and the ion film except the polycrystalline silicon layer, thereby forming a polysilicon layer, an amorphous silicon layer and an ion film pattern which are stacked.

10. The method for preparing the array substrate according to claim 6, wherein the step of performing a laser annealing process on the plurality of regions to be crystallized of the first amorphous silicon layer comprises: and carrying out local annealing crystallization on the first amorphous silicon layer by adopting a single or a plurality of blue laser sources, so that the part of the first amorphous silicon layer corresponding to the plurality of regions to be crystallized is crystallized into polycrystalline silicon.

11. A display panel comprising an opposite substrate, a liquid crystal layer and the array substrate of any one of claims 1 to 5, wherein the opposite substrate is spaced opposite to the array substrate, and the liquid crystal layer is sandwiched between the array substrate and the opposite substrate.

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel.

Background

In a display device, a Thin Film Transistor (TFT) is generally used as a switching element for controlling an operation of a pixel or as a driving element for driving a pixel. Display panels based on Low Temperature Polysilicon (LTPS) thin film transistors have been widely used in high-end mobile phones and tablet computers, but the manufacturing process of the array substrate in the LTPS display panel is very complicated, and in the prior art, a photomask is required to be used to perform heavy ion doping and light ion doping on a Low Temperature polysilicon semiconductor layer (active layer), so that the number of photomasks used is increased, and the manufacturing process is complicated and the cost is high.

Therefore, the prior art has defects which need to be solved urgently.

Disclosure of Invention

The invention provides an array substrate, a preparation method thereof and a display panel, which can solve the problems that ion doping needs to be carried out on an active layer by using a photomask in the traditional low-temperature polycrystalline silicon thin film transistor manufacturing process, so that the number of the photomasks used is increased, the manufacturing process is complex, and the cost is high.

In order to solve the above problems, the technical scheme provided by the invention is as follows:

an embodiment of the present invention provides an array substrate, including:

a substrate;

the low-temperature polycrystalline silicon thin film transistor is arranged on the substrate;

the low-temperature polycrystalline silicon thin film transistor comprises a first active layer, wherein the first active layer comprises a polycrystalline silicon layer and an amorphous silicon layer which are arranged in a stacked mode.

Optionally, in some embodiments of the present invention, the amorphous silicon layer is located on a side of the polycrystalline silicon layer away from the substrate.

Optionally, in some embodiments of the present invention, the array substrate further includes an oxide thin film transistor disposed on the substrate and spaced apart from the low temperature polysilicon thin film transistor, wherein the oxide thin film transistor and the low temperature polysilicon thin film transistor are both bottom gate structures.

Optionally, in some embodiments of the present invention, the low temperature polysilicon thin film transistor further includes:

the first grid is positioned on one side, close to the substrate, of the first active layer;

the first source electrode and the first drain electrode are positioned on one side of the first active layer, which is far away from the substrate, and are respectively contacted with the non-channel region of the first active layer;

the oxide thin film transistor includes:

the second grid electrode is arranged on the same layer as the first grid electrode;

the second active layer is positioned on one side of the second grid electrode, which is far away from the substrate, and is arranged on the same layer as the first active layer;

and the second source electrode and the second drain electrode are positioned on one side of the second active layer, which is far away from the substrate, are arranged at the same layer as the first source electrode and the first drain electrode, and are respectively contacted with a non-channel region of the second active layer.

Optionally, in some embodiments of the present invention, the ltps tft further includes an ionic layer, the ionic layer is correspondingly located on a non-channel region of the first active layer on a side away from the substrate, the first source electrode and the first drain electrode are located on the ionic layer, and the first source electrode and the first drain electrode are respectively in contact with the non-channel region of the first active layer through the ionic layer;

the oxide thin film transistor further comprises an etching barrier layer, the etching barrier layer is located on one side, far away from the substrate, of the second active layer, the second source electrode and the second drain electrode are located on the etching barrier layer, the etching barrier layer comprises a through hole penetrating through the etching barrier layer, the through hole exposes a non-channel region of the second active layer, and the second source electrode and the second drain electrode are respectively in contact with the non-channel region of the second active layer through the through hole.

The invention also provides a preparation method of the array substrate, the preparation method of the array substrate comprises a preparation method of a first active layer of the low-temperature polycrystalline silicon thin film transistor, and the preparation method of the first active layer comprises the following steps:

forming a first amorphous silicon layer on a substrate, wherein the first amorphous silicon layer includes a plurality of regions to be crystallized;

performing a laser annealing process on the multiple regions to be crystallized to enable the first amorphous silicon layer to form polycrystalline silicon corresponding to the parts of the multiple regions to be crystallized;

forming a second amorphous silicon layer on the first amorphous silicon layer;

and patterning the first amorphous silicon layer and the second amorphous silicon layer to remove the first amorphous silicon layer and the second amorphous silicon layer except the polycrystalline silicon layer, and forming the first active layer comprising the polycrystalline silicon layer and the amorphous silicon layer which are arranged in a stacked manner.

Optionally, in some embodiments of the present invention, a method for manufacturing an array substrate includes:

step S21, forming a plurality of first gates and a plurality of second gates on the substrate;

step S22, forming a dielectric layer on the first gate, the second gate and the substrate;

step S23 of forming the first active layer facing the first gate electrode and an ionic film pattern on the dielectric layer, the ionic film pattern being formed on the first active layer;

step S24, forming a second active layer on the dielectric layer opposite to the second gate electrode;

step S25, forming an etching barrier layer on the second active layer, and simultaneously forming a via hole exposing the non-channel region of the second active layer on the etching barrier layer;

step S26, forming a first source electrode and a first drain electrode on the ion layer, simultaneously forming a second source electrode and a second drain electrode on the etching barrier layer, and simultaneously forming an ion layer;

wherein the first source electrode and the first drain electrode are in contact with a non-channel region of the first active layer through the ionic layer, respectively, and the second source electrode and the second drain electrode are in contact with a non-channel region of the second active layer through the via hole, respectively.

Optionally, in some embodiments of the present invention, the first gate and the second gate are made of the same material, and the first gate and the second gate are formed simultaneously by using the same mask; the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are made of the same material, and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are formed at the same time by adopting the same photomask.

Alternatively, in some embodiments of the present invention, a method of forming a first active layer and an ionic film pattern on the dielectric layer facing the first gate electrode includes:

and sequentially forming a second amorphous silicon layer and an ion film which are stacked on the first amorphous silicon layer, and patterning the first amorphous silicon layer, the second amorphous silicon layer and the ion film to remove the first amorphous silicon layer, the second amorphous silicon layer and the ion film except the polycrystalline silicon layer, thereby forming a polysilicon layer, an amorphous silicon layer and an ion film pattern which are stacked.

Optionally, in some embodiments of the present invention, a method for performing a laser annealing process on a plurality of regions to be crystallized of the first amorphous silicon layer includes: and carrying out local annealing crystallization on the first amorphous silicon layer by adopting a single or a plurality of blue laser sources, so that the part of the first amorphous silicon layer corresponding to the plurality of regions to be crystallized is crystallized into polycrystalline silicon.

The invention also provides a display panel which comprises an opposite substrate, a liquid crystal layer and the array substrate, wherein the opposite substrate and the array substrate are oppositely arranged at intervals, and the liquid crystal layer is clamped between the array substrate and the opposite substrate.

The invention has the beneficial effects that: the active layer of the low-temperature polycrystalline silicon thin film transistor is set to be a double-layer structure of the polycrystalline silicon layer and the amorphous silicon layer, so that the active layer does not need to be subjected to ion doping in the traditional low-temperature polycrystalline silicon thin film transistor manufacturing process, the number of used photomasks can be reduced, the manufacturing process is simplified, and the cost is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

fig. 2A to fig. 2D are schematic views illustrating a manufacturing process of an array substrate according to an embodiment of the invention;

fig. 3 is a schematic structural diagram of an array substrate according to a second embodiment of the present invention;

fig. 4A to fig. 4G are schematic views illustrating a manufacturing process of an array substrate according to a second embodiment of the invention;

fig. 5 is a schematic diagram of an annealing process of an amorphous silicon layer according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Furthermore, it should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, and are not intended to limit the present invention. In the present invention, unless otherwise specified, the use of directional terms such as "upper" and "lower" generally means upper and lower in the actual use or operation of the device, particularly in the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.

The invention provides an array substrate and a preparation method thereof, and aims to solve the problems that ion doping needs to be performed on an active layer by using a photomask in the traditional low-temperature polycrystalline silicon thin film transistor process, so that the number of photomasks used is increased, the process is complex, and the cost is high, and the array substrate comprises a substrate 10 and a low-temperature polycrystalline silicon thin film transistor 100, wherein the low-temperature polycrystalline silicon thin film transistor 100 is arranged on the substrate 10, as shown in fig. 1-5. The low temperature polysilicon thin film transistor 100 includes a first active layer 12, and the first active layer 12 includes a polysilicon layer 121 and an amorphous silicon layer 122 stacked together.

The array substrate of the invention can be used in an LCD display panel, an OLED display panel, an LED display panel, and a quantum dot display panel, but is not limited thereto.

The invention also provides a preparation method of the array substrate, wherein the preparation method of the array substrate comprises the following steps:

forming a first amorphous silicon layer on a substrate, wherein the first amorphous silicon layer comprises a plurality of regions to be crystallized, and performing a laser annealing process on the plurality of regions to be crystallized of the first amorphous silicon layer to form polycrystalline silicon on the part of the first amorphous silicon layer corresponding to the regions to be crystallized;

forming a second amorphous silicon layer on the polycrystalline silicon of the first amorphous silicon layer and the amorphous silicon except the polycrystalline silicon, patterning the first amorphous silicon layer and the second amorphous silicon layer, removing the first amorphous silicon layer and the second amorphous silicon layer except the polycrystalline silicon correspondingly, and forming a polycrystalline silicon layer and an amorphous silicon layer which are arranged in a stacked mode; the polycrystalline silicon layer and the amorphous silicon layer which are stacked form a first active layer of the low-temperature polycrystalline silicon thin film transistor.

In the invention, the first active layer 12 of the low-temperature polycrystalline silicon thin film transistor 100 is set to be a double-layer structure of the polycrystalline silicon layer 121 and the amorphous silicon layer 122, so that ion heavy doping and ion light doping on the active layer (polycrystalline silicon layer) by 2 photomasks in the traditional low-temperature polycrystalline silicon thin film transistor process are not needed, the number of photomasks used can be reduced, the process is simplified, and the cost is reduced.

With specific reference to the following examples, it should be noted that the order of description of the following examples is not intended to limit the preferred order of the examples.

Example one

Referring to fig. 1, the array substrate provided in this embodiment includes a substrate 10, a dielectric layer 20, and a low temperature polysilicon thin film transistor 100. The low temperature polysilicon thin film transistor 100 includes a first gate electrode 11, a first active layer 12, an ion layer 13, a first source electrode 14, and a first drain electrode 15.

The first gate 11 is disposed on the substrate 10, the dielectric layer 20 is disposed on the first gate 11 and the substrate 10, and the first active layer 12 is disposed on one side of the dielectric layer 20 away from the substrate 10, wherein the first active layer 12 includes a channel region and non-channel regions disposed on two sides of the channel region, and the first gate 11 is disposed opposite to the channel region.

The ion layer 13 is disposed on a side of the first active layer 12 away from the substrate 10, and the ion layer 13 is correspondingly located in a non-channel region of the first active layer 12. The first source electrode 14 and the first drain electrode 15 are located on the ionic layer 13. Wherein a portion of the first source electrode 14 is in contact with the non-channel region of the first active layer 12 through the ionic layer 13, and another portion of the first source electrode 14 extends onto the dielectric layer 20 along the side of the first active layer 12. A portion of the first drain electrode 15 is in contact with a non-channel region of the first active layer 12 through the ionic layer 13, and another portion of the first drain electrode 15 extends onto the dielectric layer 20 along a side surface of the first active layer 12.

The first active layer 12 includes a polysilicon layer 121 and an amorphous silicon layer 122 stacked on each other, and the amorphous silicon layer 122 is located on a side of the polysilicon layer 121 away from the substrate 10.

In the present embodiment, the low temperature polysilicon thin film transistor 100 is taken as a bottom gate structure for illustration, but of course, in other embodiments, the low temperature polysilicon thin film transistor 100 may also be a top gate structure.

In addition, the array substrate of the embodiment may further include other conventional film layers, such as a passivation layer, and the like, which is not limited herein.

In this embodiment, since the active layer 12 of the low temperature polysilicon thin film transistor 100 is a double-layer structure of the polysilicon layer 121 and the amorphous silicon layer 122, the first active layer 12 does not need to be ion-doped, but the ion layer 13 is separately disposed on the non-channel region of the first active layer 12, and the ion layer 13 can be simultaneously formed by using the existing photomask process of the array substrate, and a new photomask does not need to be added, so that 2 photomasks for performing ion heavy doping and ion light doping on the active layer can be reduced, thereby simplifying the process and reducing the cost.

The invention also provides a preparation method of the array substrate, which comprises the following steps:

in step S11, please refer to fig. 2A, a plurality of first gates 11 are formed on the substrate 10.

Specifically, a first metal layer is prepared on the substrate 10, and a plurality of first gates 11 are formed after a first mask patterning. It is to be understood that "patterning" in the present invention refers to an exposure-development-etching process.

The substrate 10 may be a flexible substrate made of polyimide or the like, or may be a rigid substrate made of glass or the like.

In step S12, please refer to fig. 2A, a dielectric layer 20 is formed on the first gate 11 and the substrate 10.

Wherein the dielectric layer 20 includes a single-layer or multi-layer structure formed by at least one of silicon nitride and silicon oxide. Illustratively, the dielectric layer 20 includes a silicon nitride layer and a silicon oxide layer stacked from bottom to top.

Step S13, please refer to fig. 2B, a first amorphous silicon layer 121 'is prepared on the dielectric layer 20, the first amorphous silicon layer 121' includes a plurality of regions a to be crystallized, and a laser annealing process is performed on the plurality of regions a to be crystallized of the first amorphous silicon layer 121 ', so that polysilicon is formed on a portion of the first amorphous silicon layer 121' corresponding to the regions a to be crystallized.

The region a to be crystallized actually corresponds to a region where the active layer is located, and the first amorphous silicon layer 121' outside the region a to be crystallized is not crystallized, so that the amorphous silicon material is maintained.

Specifically, the method for performing a laser annealing process on a plurality of regions to be crystallized of the first amorphous silicon layer includes: the first amorphous silicon layer 121 'is locally annealed and crystallized by using one or more Blue Laser Diodes (BLD) 300, and light emitted from the Blue Laser source 300 passes through a lens 301 and irradiates the region a to be crystallized, so that a portion of the first amorphous silicon layer 121' corresponding to the region a to be crystallized is crystallized into polysilicon.

Step S14, please refer to fig. 2C, in which a second amorphous silicon layer and an ion film are sequentially formed on the first amorphous silicon layer 121 ', the first amorphous silicon layer, the second amorphous silicon layer and the ion film are patterned by using a second mask, the first amorphous silicon layer, the second amorphous silicon layer and the ion film outside the region a to be crystallized are removed, and a stacked polysilicon layer 121, an amorphous silicon layer 122 and an ion film pattern 13' are formed.

Wherein the polycrystalline silicon layer 121 and the amorphous silicon layer 122 constitute a first active layer 12 of the low temperature polycrystalline silicon thin film transistor.

Step S15, please refer to fig. 2D, in which a second metal layer is prepared on the ionic film pattern 13 ', and the second metal layer and the ionic film pattern 13' are patterned by using a third mask to form a first source electrode 14 and a first drain electrode 15, and an ionic layer 13 is also formed at the same time, and the first source electrode 14 and the first drain electrode 15 are respectively in contact with the non-channel region of the first active layer 12 through the ionic layer 13.

Wherein, when the second metal layer is etched, a portion of the ionic film pattern 13' corresponding to the channel region of the first active layer 12 is also etched away at the same time.

In this embodiment, since the ion layer 13 is formed in the second photo-masking process and the third photo-masking process, no new photo-masking is required to be added, so that 2 photo-masks for performing ion heavy doping and ion light doping on the active layer can be reduced, thereby simplifying the process and reducing the cost.

In the prior art, Low Temperature Poly-Oxide (LTPO) thin film transistor (tft) technology is gradually emerging to reduce power consumption and improve display quality of display devices. Current LTPO thin film transistor technology requires that the pixel circuit include both LTPO thin film transistors and LTPS thin film transistors. The technology mainly utilizes the characteristics of low leakage current of the LTPO thin film transistor and high mobility of the LTPS thin film transistor to improve the usable refresh rate range (1 Hz-120 Hz) of the pixel circuit, so that the screen can adjust the refresh rate according to the display content and reduce the power consumption.

In an array substrate using the LTPO thin film transistor technology, due to the difference between the structures and the processes of the LTPS thin film transistor and the LTPO thin film transistor, the LTPS thin film transistor and the LTPO thin film transistor are usually fabricated on different films, and both the LTPS thin film transistor and the LTPO thin film transistor are generally of a top gate structure, or one of the LTPS thin film transistor and the LTPO thin film transistor is of a bottom gate structure, and the other is of a top gate structure. Therefore, the number of the required photomasks is large in the process of preparing the array substrate, which results in complex process and high product cost.

In order to solve the above problems in the prior art, embodiments of the present invention further provide an array substrate and a method for manufacturing the same, which refer to the following second embodiment.

Example two

Referring to fig. 3, the array substrate provided in this embodiment includes a substrate 10, a low temperature polysilicon thin film transistor 100, and an oxide thin film transistor 200. Wherein, the low temperature polysilicon thin film transistor 100 is arranged on the substrate 10; the oxide thin film transistor 200 is disposed on the substrate 10 and spaced apart from the low temperature polysilicon thin film transistor 100 in a horizontal direction. The oxide thin film transistor 200 and the low temperature polysilicon thin film transistor 100 are both bottom gate structures.

The oxide thin film transistor 200 may be a low temperature polycrystalline oxide thin film transistor.

Specifically, the array substrate of the present embodiment includes:

the substrate 10 may be a flexible substrate made of polyimide or the like, or may be a rigid substrate made of glass or the like, for example.

A plurality of first gates 11 and a plurality of second gates 21 disposed on the substrate 10, and the first gates 11 or the second gates 21 may include a single layer or a multi-layer structure formed of at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). Further, the materials of the first gate electrode 11 and the second gate electrode 21 may be the same.

In this embodiment, the plurality of first gates 11 and the plurality of second gates 21 are disposed at the same layer and spaced apart from each other.

A dielectric layer 20 disposed on the first gate 11, the second gate 21 and the substrate 10, wherein the dielectric layer 20 includes a single-layer or multi-layer structure formed by at least one of silicon nitride and silicon oxide. Illustratively, the dielectric layer 20 includes a silicon nitride layer and a silicon oxide layer stacked from bottom to top.

The first active layer 12 and the second active layer 22 are arranged on one side, far away from the substrate 10, of the dielectric layer 20, the first active layer 12 is arranged right opposite to the first grid electrode 11, the second active layer 22 is arranged right opposite to the second grid electrode 21, the first active layer 12 comprises a channel region and non-channel regions located on two sides of the channel region, and the second active layer 22 comprises a channel region and non-channel regions located on two sides of the channel region.

In the present embodiment, the first active layer 12 includes a polysilicon layer 121 and an amorphous silicon layer 122, the amorphous silicon layer 122 is located on a side of the polysilicon layer 121 away from the substrate 10, the second active layer 22 includes an oxide layer, and the material of the second active layer 22 includes, but is not limited to, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In)₂O₃) At least one of Indium Gallium Oxide (IGO) and zinc aluminum oxide (AZO).

The ion layer 13 is disposed on a side of the first active layer 12 away from the substrate 10 and corresponds to the non-channel region. The ionic layer 13 is a conductive ionic layer, and the kind of the conductive ions may be nitrogen ions, boron ions, or phosphorus ions. Of course, the present invention is not limited to the above-mentioned ions.

An Etch Stop Layer (ESL) 23 disposed on a side of the second active layer 22 away from the substrate 10, wherein the etch stop layer 23 includes a via hole penetrating through the etch stop layer 23, and the etch stop layer 23 exposes a non-channel region of the second active layer 22 through the via hole. The material of the etching barrier layer 23 may be silicon oxide; or a composite layer formed by laminating silicon oxide and silicon nitride; or a composite layer formed by laminating silicon nitride, silicon oxide and silicon oxynitride; or a composite layer formed by laminating silicon nitride, silicon oxide and aluminum oxide. The material of the etching barrier layer 23 may also be aluminum nitride, hafnium oxide, or the like. In this embodiment, the etching stop layer 23 not only can perform an insulating function, but also can protect the second active layer 22 from moisture and etching in subsequent processes.

A first source electrode 14 and a first drain electrode 15 disposed on the ionic layer 13, and a second source electrode 24 and a second drain electrode 25 disposed on the etch stopper 23. Wherein the first source electrode 14 and the first drain electrode 15 are respectively overlapped with the non-channel region of the first active layer 12 through the ionic layer 13, and the second source electrode 24 and the second drain electrode 25 are in contact with the non-channel region of the second active layer 22 through a via hole on the etch stopper layer 23.

In the present embodiment, a portion of the first source electrode 14 contacts the non-channel region of the first active layer 12 through the ionic layer 13, and another portion of the first source electrode 14 extends onto the dielectric layer 20 along the side surface of the first active layer 12. A portion of the first drain electrode 15 is in contact with a non-channel region of the first active layer 12 through the ionic layer 13, and another portion of the first drain electrode 15 extends onto the dielectric layer 20 along a side surface of the first active layer 12. The etch stop layer 23 also extends to the side of the second active layer 22, thereby better protecting the second active layer 22.

Wherein the first source electrode 14, the first drain electrode 15, the second source electrode 24, or the second drain electrode 25 may include a single-layer or multi-layer structure formed of at least one metal selected from aluminum, platinum, palladium, silver, magnesium, gold, nickel, neodymium, iridium, chromium, lithium, calcium, molybdenum, titanium, tungsten, and copper. Further, the materials of the first source electrode 14, the first drain electrode 15, the second source electrode 24 and the second drain electrode 25 of the present embodiment are the same.

In this embodiment, the first source 14, the first drain 15, the second source 24 and the second drain 25 are disposed in the same layer.

Wherein the first gate electrode 11, the first active layer 12, the ion layer 13, the first source electrode 14 and the first drain electrode 15 form a low temperature polysilicon thin film transistor 100. The second gate electrode 21, the second active layer 22, the etch stopper layer 23, the second source electrode 24, and the second drain electrode 25 form an oxide thin film transistor 200.

The array substrate of the embodiment may further include other conventional film layers, such as a passivation layer, besides the above structure, which is not limited herein.

It is understood that the above-mentioned "same layer" refers to the same layer on the surface of the same film or formed by etching the same film.

In this embodiment, since the first active layer 12 of the low temperature polysilicon thin film transistor 100 adopts the above-mentioned double-layer structure design, the first active layer 12 does not need to be ion-doped, but the ion layer 13 is separately disposed on the non-channel region of the first active layer 12, and the ion layer 13 can be formed simultaneously by using the existing photomask process of the array substrate without adding a new photomask, so that 2 photomasks for performing ion heavy doping and ion light doping on the active layer can be reduced, thereby simplifying the process and reducing the cost. In addition, since the low temperature polysilicon thin film transistor 100 and the oxide thin film transistor 200 are both bottom gate structures, a portion of the film (e.g., dielectric layer) can be shared between the two structures, and a portion of the film (e.g., gate, source and drain) can be simultaneously fabricated, thereby further reducing the number of photomasks, simplifying the fabrication process, and reducing the cost.

On the basis of simplifying the manufacturing process, reducing the cost and ensuring the high mobility, the array substrate of the embodiment can utilize the characteristics of low leakage current of the oxide thin film transistor and high mobility of the low-temperature polycrystalline silicon thin film transistor to improve the usable refresh rate range of the pixel circuit, so that the screen can adjust the refresh rate according to the display content and reduce the power consumption.

The embodiment of the invention also provides a preparation method of the array substrate, which comprises the following steps:

in step S21, as shown in fig. 4A, a plurality of first gates 11 and a plurality of second gates 21 are formed on the substrate 10.

Specifically, a first metal layer is prepared on the substrate 10, and is patterned by using a first mask, so as to form a plurality of first gates 11 and a plurality of second gates 21.

In step S22, as shown in fig. 4B, a dielectric layer 20 is formed on the first gate 11, the second gate 21 and the substrate 10.

Specifically, the dielectric layer 20 includes a single-layer or multi-layer structure formed of at least one material of silicon nitride and silicon oxide.

In step S23, as shown in fig. 4C and 4D, a first active layer 12 and an ionic film pattern 13' facing the first gate electrode 11 are formed on the dielectric layer 20.

Specifically, as shown in fig. 4C, a first amorphous silicon layer 121 'is first formed on the dielectric layer 20, where the first amorphous silicon layer 121' includes a plurality of regions a to be crystallized corresponding to the plurality of first gates 11, and a laser annealing process is performed on the plurality of regions a to be crystallized of the first amorphous silicon layer 121 'to form polysilicon on a portion of the first amorphous silicon layer 121' corresponding to the regions a to be crystallized.

The region a to be crystallized actually corresponds to a region where the active layer is located, and the first amorphous silicon layer 121' outside the region a to be crystallized is not crystallized, so that the amorphous silicon material is maintained.

Specifically, the method for performing a laser annealing process on a plurality of regions to be crystallized of the first amorphous silicon layer includes: the first amorphous silicon layer 121 'is locally annealed and crystallized by using one or more Blue Laser Diodes (BLD) 300, and light emitted from the Blue Laser source 300 passes through a lens 301 and irradiates the region a to be crystallized, so that a portion of the first amorphous silicon layer 121' corresponding to the region a to be crystallized is crystallized into polysilicon.

Referring to fig. 4D, a second amorphous silicon layer and an ion film are sequentially formed on the polysilicon of the first amorphous silicon layer 121 'and the amorphous silicon except for the polysilicon, and the first amorphous silicon layer, the second amorphous silicon layer and the ion film are patterned by using a second mask to remove the first amorphous silicon layer, the second amorphous silicon layer and the ion film outside the region a to be crystallized, so as to form a stacked polysilicon layer 121, an amorphous silicon layer 122 and an ion film pattern 13'.

Wherein the polycrystalline silicon layer 121 and the amorphous silicon layer 122 constitute a first active layer 12 of the low temperature polycrystalline silicon thin film transistor.

In step S24, as shown in fig. 4E, a second active layer 22 opposite to the second gate electrode 21 is formed on the dielectric layer 20.

Wherein, the second active layer 22 is formed by using the 3 rd photo mask, and the material of the second active layer 22 includes but is not limited to at least one of indium tin oxide, indium zinc oxide, indium gallium oxide and zinc aluminum oxide.

In step S25, as shown in fig. 4F, an etching stopper layer 23 is formed on the second active layer 22, and a via hole 231 exposing the non-channel region of the second active layer 22 is formed on the etching stopper layer 23.

Specifically, an etching blocking layer is formed on the entire surface of the second active layer 22, a fourth photomask is used to pattern the etching blocking layer, the etching blocking layer on the upper surface and the side surface of the second active layer 22 is retained, and an opening 231 is formed in a position of the etching blocking layer corresponding to the non-channel region of the second active layer 22 to expose the non-channel region.

Step S26, as shown in fig. 4G, forms a first source electrode 14 and a first drain electrode 15 on the ionic layer 13, simultaneously forms a second source electrode 24 and a second drain electrode 25 on the etch stopper 23, and simultaneously forms the ionic layer 13.

Specifically, a second metal layer is formed on the ionic membrane pattern 13 'and the etching stop layer 23, and the second metal layer and the ionic membrane pattern 13' are patterned by using a fifth photomask, so as to form a first source electrode 14, a first drain electrode 15, an ionic layer 13, a second source electrode 24, and a second drain electrode 25.

Wherein, when the second metal layer is etched, a portion of the ionic film pattern 13' corresponding to the channel region of the first active layer 12 is also etched away at the same time.

Wherein the first source electrode 14 and the first drain electrode 15 are respectively overlapped with the non-channel region of the first active layer 12 through the ionic layer 13, and the second source electrode 24 and the second drain electrode 25 are in contact with the non-channel region of the second active layer 22 through a via hole on the etch stopper layer 23.

The preparation method of the array substrate may further include: and preparing a passivation layer on the first source electrode, the first drain electrode, the second source electrode and the second drain electrode.

In this embodiment, on one hand, since the first active layer 12 of the low temperature polysilicon thin film transistor 100 adopts the above-mentioned double-layer structure design, the first active layer 12 does not need to be ion-doped, and the ion layer 13 is formed in the second photo-masking process and the fifth photo-masking process, and no new photo-mask needs to be added, so that 2 photo-masks for performing ion heavy doping and ion light doping on the active layer can be reduced; on the other hand, the low temperature polysilicon thin film transistor 100 and the oxide thin film transistor 200 have a structure in which a portion of the film (e.g., the dielectric layer) can be shared and a portion of the film (e.g., the gate, the source and the drain) can be simultaneously formed, so that the number of photomasks can be further reduced, and the invention can achieve the purposes of simplifying the manufacturing process and reducing the cost.

In addition, an Excimer Laser Annealing (ELA) process is often used in the prior art to crystallize the deposited amorphous silicon layer to form a polycrystalline silicon layer. The excimer laser annealing process generally performs crystallization treatment on the amorphous silicon layer in the following two ways: firstly, crystallizing an amorphous silicon layer in a whole-surface scanning mode by utilizing a linear light source; and secondly, shielding by using the mask plate, and carrying out laser annealing crystallization on the amorphous silicon layer in the hollow area of the mask plate. With the increase of the size of the substrate, the length of the laser beam required to adopt the first mode is increased, but at present, the method can only realize the product preparation of a G6 generation line, and cannot be applied to the production of larger generation lines. The second mode has excessive light loss, about 90% of light is shielded by the mask plate, and the energy consumption is high.

The preparation method provided by the invention utilizes single or a plurality of blue laser sources to carry out local annealing crystallization on the amorphous silicon layer, the process does not need channel doping and source and drain doping in the prior art, the process can be simplified, the using number of photomasks is reduced, and meanwhile, the number of blue laser sources can be increased to adapt to the requirement of a large generation line, such as the production of G8.5 and above large generation lines. As shown in fig. 5, in the production process of the large generation line, the amorphous silicon layer 121 'may be locally annealed and crystallized by using a plurality of blue laser sources 300, light emitted by the blue laser sources 300 passes through a lens 301 and is emitted to a region a to be crystallized of the amorphous silicon layer 121', so that a portion of the amorphous silicon layer 121 'corresponding to the region a to be crystallized is crystallized to form polysilicon, and the first amorphous silicon layer 121' outside the region a to be crystallized is not crystallized and still maintains an amorphous silicon material.

The invention also provides a display panel which comprises an opposite substrate, a liquid crystal layer and the array substrate, wherein the opposite substrate and the array substrate are oppositely arranged at intervals, and the liquid crystal layer is clamped between the array substrate and the opposite substrate.

The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.