阅读说明：本技术 阵列基板及其制作方法 (Array substrate and manufacturing method thereof ) 是由 贺晖 于 2021-07-28 设计创作，主要内容包括：本发明公开了一种阵列基板及阵列基板的制作方法,所述阵列基板的制作方法包括步骤S1,在所述钝化层上形成平坦化层；步骤S2,对所述平坦化层对应所述源极的区域进行碳化,形成第一黑色吸光层；以及步骤S3,在所述平坦化层上形成像素电极层以及覆盖所述平坦化层及所述像素电极层的像素定义层,其中所述像素电极层穿过所述第一黑色吸光层与所述源极电性连接。(The invention discloses an array substrate and a manufacturing method thereof, wherein the manufacturing method of the array substrate comprises the step S1 of forming a planarization layer on a passivation layer; step S2, carbonizing the area of the planarization layer corresponding to the source electrode to form a first black light absorption layer; and step S3, forming a pixel electrode layer and a pixel defining layer covering the planarization layer and the pixel electrode layer on the planarization layer, wherein the pixel electrode layer is electrically connected to the source electrode through the first black light absorbing layer.)

1. The manufacturing method of the array substrate comprises the steps of providing a substrate, forming a transistor and a passivation layer covering the transistor on the substrate, wherein the transistor comprises a source electrode and a drain electrode; and is characterized by comprising the following steps:

step S1, forming a planarization layer on the passivation layer;

step S2, carbonizing the area of the planarization layer corresponding to the source electrode to form a first black light absorption layer; and

step S3, forming a pixel electrode layer and a pixel defining layer covering the planarization layer and the pixel electrode layer on the planarization layer, wherein the pixel electrode layer is electrically connected to the source electrode through the first black light absorbing layer.

2. The method for manufacturing an array substrate according to claim 1, wherein in step S2, the size of the first black light absorption layer is greater than or equal to the size of the corresponding source electrode, so that the projection of the source electrode on the substrate completely falls within the projection range of the first black light absorption layer on the substrate.

3. The method for manufacturing an array substrate according to claim 1, wherein the step S2 further includes carbonizing a region of the planarization layer corresponding to the drain electrode to form a second black light absorbing layer, so that a projection of the drain electrode on the substrate falls within a projection range of the second black light absorbing layer on the substrate.

4. The method of claim 3, wherein in step S2, the planarization layer is carbonized in the regions corresponding to the source electrode and the drain electrode by using a mask, wherein the mask is the same as the mask used for patterning to form the source electrode and the drain electrode.

5. The method of claim 1, wherein in step S2, the carbonization method includes laser irradiation.

6. The method for manufacturing an array substrate of claim 5, wherein in step S2, the laser irradiation wavelength ranges from 100nm to 500 nm.

7. An array substrate comprises a substrate, a transistor and a passivation layer, wherein the transistor is arranged on the substrate, the passivation layer covers the transistor, and the transistor comprises a source electrode and a drain electrode; characterized in that, the array substrate still includes:

a planarization layer disposed on the passivation layer;

a first black light absorbing layer disposed in a region of the planarization layer corresponding to the source electrode, wherein the first black light absorbing layer;

a pixel electrode layer disposed on the planarization layer, wherein the pixel electrode layer passes through the first black light absorbing layer and is electrically connected to the source electrode; and

and the pixel defining layer covers the planarization layer and the pixel electrode layer.

8. The array substrate of claim 7, wherein the first black light absorbing layer has a size greater than or equal to the size of the corresponding source electrode, such that a projection of the source electrode on the substrate completely falls within a projection range of the first black light absorbing layer on the substrate.

9. The array substrate of claim 1, further comprising a second black light absorbing layer disposed in the planarization layer at a region corresponding to the drain electrode.

10. A display panel, comprising:

the array substrate of any one of claims 7 to 9, wherein a color film is disposed in the planarization layer, an opening is formed in the pixel defining layer to expose the pixel electrode layer, a light emitting device is disposed in the opening, and projections of the color film and the light emitting device on the substrate overlap.

Technical Field

The invention relates to the technical field of display, in particular to an array substrate and a manufacturing method thereof.

Background

When a white light organic diode (WOLED) display with bottom emission emits light, the light needs to pass through a planarization layer and an R/G/B color filter, and since the planarization layer of the white light organic diode (WOLED) display with bottom emission is generally made of a highly transparent organic material, the light propagation multi-directionality often causes the phenomenon that a pixel which does not need to emit light emits light due to the light emission of an adjacent pixel, and light leakage occurs.

The light leakage phenomenon occurs because criss-cross metal wires, such as various data lines, gate lines, metal electrodes, etc., are disposed in the array substrate, and when light passes through the cathode and the metal wires, the cathode and the metal wires reflect the light, so that the light illuminates the edge of the opening of the pixel definition layer of the adjacent pixel, resulting in light leakage, and thus bright spots, i.e., "dark bright spots", appear when the liquid crystal display panel presents a dark picture.

Therefore, there is a need for an array substrate and a method for fabricating the same that can effectively avoid the light leakage problem caused by the light reflected by the cathode and the metal trace to illuminate the adjacent pixels.

Disclosure of Invention

The invention aims to solve the technical problem of light leakage caused by that light is reflected by a metal layer in an array substrate to illuminate adjacent pixels. In order to solve the above problems, an embodiment of the present invention provides a method for manufacturing an array substrate, the method including providing a substrate, forming a transistor on the substrate, and forming a passivation layer covering the transistor, wherein the transistor includes a source and a drain; and in that the method further comprises the steps of:

step S1, forming a planarization layer on the passivation layer;

step S2, carbonizing the area of the planarization layer corresponding to the source electrode to form a first black light absorption layer; and

step S3, forming a pixel electrode layer and a pixel defining layer covering the planarization layer and the pixel electrode layer on the planarization layer, wherein the pixel electrode layer is electrically connected to the source electrode through the first black light absorbing layer.

According to an embodiment of the invention, in step S2, the size of the first black light absorbing layer is greater than or equal to the size of the corresponding source electrode, so that the projection of the source electrode on the substrate completely falls within the projection range of the first black light absorbing layer on the substrate.

According to an embodiment of the present invention, step S2 further includes carbonizing a region of the planarization layer corresponding to the drain electrode to form a second black light absorbing layer, so that a projection of the drain electrode on the substrate falls completely within a projection range of the second black light absorbing layer on the substrate.

According to an embodiment of the invention, in step S2, regions of the planarization layer corresponding to the source and the drain are carbonized using a mask, wherein the mask is the same as the mask used for patterning to form the source and the drain.

According to an embodiment of the present invention, in step S2, the method of carbonizing includes laser irradiation.

According to an embodiment of the present invention, in step S2, the laser irradiation has a wavelength ranging from 100nm to 500 nm.

Another embodiment of the present invention further provides an array substrate, which includes a substrate, a transistor disposed on the substrate, and a passivation layer covering the transistor, wherein the transistor includes a source and a drain; characterized in that, the array substrate still includes:

a planarization layer disposed on the passivation layer;

the first black light absorption layer is arranged in the area, corresponding to the source electrode, of the planarization layer;

a pixel electrode layer disposed on the planarization layer, wherein the pixel electrode layer passes through the first black light absorbing layer and is electrically connected to the source electrode; and

and the pixel defining layer covers the planarization layer and the pixel electrode layer.

According to an embodiment of the invention, the size of the first black light absorbing layer is larger than or equal to the size of the corresponding source electrode, so that the projection of the source electrode on the substrate completely falls within the projection range of the first black light absorbing layer on the substrate.

According to an embodiment of the invention, the array substrate further includes a second black light absorbing layer disposed in a region of the planarization layer corresponding to the drain electrode.

A further embodiment of the present invention further provides a display panel, which includes the array substrate, wherein a color film is disposed in the planarization layer, an opening is formed in the pixel defining layer to expose the pixel electrode layer, a light emitting element is disposed in the opening, and projections of the color film and the light emitting element on the substrate are overlapped.

The array substrate and the manufacturing method thereof provided by the invention relate to a bottom-emitting White Organic Light Emitting Diode (WOLED) display and a manufacturing method thereof.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required in the description of the embodiments or the prior art:

FIG. 1 is a flow chart of a method for fabricating an array substrate according to an embodiment of the invention;

fig. 2 to 6 are schematic structural diagrams of a manufacturing method of an array substrate in each step according to an embodiment of the invention.

Detailed Description

The following detailed description of the embodiments of the present invention will be provided with reference to the accompanying drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details or with a specific form of the description.

Referring to fig. 1 and fig. 2 to 6, fig. 1 is a flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the invention; fig. 2 to 6 are schematic structural diagrams of a manufacturing method of an array substrate in each step according to an embodiment of the invention. As shown in fig. 2 and fig. 3, a method for manufacturing an array substrate 100 according to an embodiment of the present invention includes providing a substrate 11, forming a transistor 12 on the substrate 11 and a passivation layer 13 covering the transistor 12, wherein the transistor 12 includes a source 121 and a drain 122; the manufacturing method of the array substrate 100 according to the embodiment of the invention further includes the following steps:

step S1, forming a planarization layer 14 on the passivation layer 13, as shown in fig. 4;

step S2, carbonizing the region of the planarization layer 14 corresponding to the source electrode 121 to form a first black light absorbing layer 151, as shown in fig. 4; and

step S3 is to form a pixel electrode layer 17 and a pixel defining layer 18 covering the planarization layer 14 and the pixel electrode layer 17 on the planarization layer 14, wherein the pixel electrode layer 17 is electrically connected to the source electrode 121 through the conductive plug 16, as shown in fig. 5 and 6.

Specifically, according to an embodiment of the present invention, the method for manufacturing the array substrate 100 according to an embodiment of the present invention further includes, before the step S1: providing a substrate 11, forming a light-shielding layer 111 on the substrate 11, forming a buffer layer 112 on the light-shielding layer 111 and the substrate 11, forming an oxide semiconductor layer 113 on the buffer layer 112, forming a gate insulating layer 114 on the oxide semiconductor layer 113, forming a gate electrode 115 on the gate insulating layer 114, forming an interlayer dielectric layer 116 covering the oxide semiconductor layer 113, the gate insulating layer 114, the gate electrode 115, and the buffer layer 112, forming the source electrode 121 and the drain electrode 122 disposed on the interlayer dielectric layer 116 and electrically connected to the oxide semiconductor layer 113 through the interlayer dielectric layer 116, forming the passivation layer 13 covering the source electrode 121, the drain electrode 122, and the interlayer dielectric layer 116, and forming a color film 117 on the passivation layer 13, as shown in fig. 2 and 3.

According to an embodiment of the present invention, step S1 specifically includes: forming a planarization layer 14 on the passivation layer 13 in a region not covered by the color film 117, exposing and developing the planarization layer 14 to form the through hole 141 penetrating through the planarization layer 14, and filling the through hole 141 with a conductive plug 16 penetrating through the through hole 141, as shown in fig. 1 and 4.

According to an embodiment of the present invention, the through hole 141 may be located in a carbonized region of the planarization layer 14, that is, the first black light absorbing layer 151 has the through hole 141 therein, and the through hole 141 is configured with a conductive plug 16 penetrating through the through hole 141 therein, as shown in fig. 1 and 4.

According to an embodiment of the present invention, the planarization layer 14 is an organic material to facilitate carbonization to form the black light absorbing layer 15. In a specific embodiment of the present invention, the material of the planarization layer 14 includes: acrylic resin (acrylic resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), poly amine resin (polyamide resin), polyimide resin (polyimide resin), or combinations thereof.

Referring to fig. 1 and 4, in step S2, the first black light absorbing layer 151 has a size greater than or equal to the size of the corresponding source electrode 121, so that the projection of the source electrode 121 on the substrate 11 completely falls within the projection range of the first black light absorbing layer 151 on the substrate 11. In one embodiment, the first black light absorbing layer 151 may have a size greater than 10% to 30% of the source electrode 121 corresponding thereto. Basically, the larger the width of the black light absorbing layer 15 formed by carbonizing the planarization layer 14, the more the reflected light of each metal trace and metal film layer can be sufficiently blocked (the arrow in fig. 6 represents the path of light), however, the required width of the black light absorbing layer 15 can be selectively designed according to the product positioning requirement in consideration of the cost and the display aperture ratio.

With continued reference to fig. 4, according to an embodiment of the present invention, step S2 further includes carbonizing a region of the planarization layer 14 corresponding to the drain electrode 122 to form a second black light absorbing layer 152, where the size of the second black light absorbing layer 152 is greater than or equal to the size of the corresponding drain electrode 122, so that the projection of the drain electrode 122 on the substrate 11 completely falls within the projection range of the second black light absorbing layer 152 on the substrate 11. In one embodiment, the second black light absorbing layer 152 may have a size greater than 10% to 30% of the corresponding drain electrode 122. In the embodiment of the invention, the principle of using the second black light absorbing layer 152 formed by carbonizing the planarization layer 14 to block the reflected light of the drain 122, other metal traces and metal film is the same as the above, and is not repeated herein.

According to an embodiment of the present invention, in step S2, the mask used for carbonizing the region of the planarization layer 14 corresponding to the source electrode 121 and the drain electrode 122 may be the same as the mask used for patterning to form the source electrode 121 and the drain electrode 122, so that the black light absorbing layer 15 formed by carbonizing the planarization layer 14 has the same pattern as the source electrode 121 and the drain electrode 122 and corresponds to each other, as shown in fig. 4.

According to other embodiments of the present invention, the mask used for carbonizing the area of the planarization layer 14 corresponding to the source 121 and the drain 122 may be different from the mask used for patterning to form the source 121 and the drain 122 (not shown), so that the pattern of the black light absorbing layer 15 formed by carbonizing the planarization layer 14 may not completely correspond to the source 121 and the drain 122, for example, the black light absorbing layer 15 may completely cover the entire transistor 12, including the source 121, the gate 115 and the drain 122, even extend to the metal traces adjacent to the transistor 12, so that the coverage of the black light absorbing layer 15 may further cover the reflected light of other metal traces and metal film layers besides the reflected light of the source 121 and the drain 122. The pattern of the black light absorbing layer 15 of the present invention is not limited to the example shown in fig. 4.

According to an embodiment of the present invention, in step S2, the carbonization method may use laser irradiation or other carbonization methods known in the art; the carbonization of the planarizing layer 14 is preferably performed using laser irradiation with a wavelength ranging from 100nm to 500 nm. If the wavelength exceeds the above range, there may be a problem that the laser energy is insufficient, resulting in poor carbonization effect. If the wavelength is below the above range, the laser energy may be too strong, resulting in the destruction of other layers by the laser. In one embodiment, the carbonization of the planarization layer 14 is performed using laser irradiation in a wavelength range of 200nm to 300 nm.

It should be noted that the carbonization step is preferably performed before the pixel electrode layer 17 and the pixel defining layer 18 are formed, so as to avoid the laser used from adversely affecting the pixel electrode layer 17 and the pixel defining layer 18.

In an embodiment of the present invention, the materials of the buffer layer 112, the gate insulating layer 114, the interlayer insulating layer, and the passivation layer 13 may each independently include: silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof; the materials of the gate 115, the source 121, and the drain 122 may each independently include: one or more combinations of molybdenum (Mo), titanium (Ti), aluminum (A1), and copper (Cu); the material of the light-shielding layer 111 may include: silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), neodymium (Nd), or an alloy thereof.

In the embodiment of the present invention, the pixel defining layer 18 may be made of an organic material or an inorganic material. Specifically, the material of the pixel defining layer 18 includes an organic material selected from, for example, a photoresist, a polypropylene-based resin, a polyimide-based resin, and an acryl-based resin, or an inorganic material selected from, for example, a silicon compound. In a preferred embodiment of the present invention, the pixel defining layer 18 is made of an organic material.

Referring to fig. 6, another embodiment of the present invention further provides an array substrate 100, where the array substrate 100 includes a substrate 11, a transistor 12 disposed on the substrate 11, and a passivation layer 13 covering the transistor 12, where the transistor 12 includes a source 121 and a drain 122; the array substrate 100 further includes: a planarization layer 14 disposed on the passivation layer 13; a first black light absorbing layer 151 disposed in a region of the planarization layer 14 corresponding to the source electrode 121, wherein the first black light absorbing layer 151 has a via 141 therein, and the via 141 has a conductive plug 16 disposed therein and penetrating through the via 141; a pixel electrode layer 17 disposed on the planarization layer 14, wherein the pixel electrode layer 17 is electrically connected to the source electrode 121 through the conductive plug 16; and a pixel defining layer 18 covering the planarization layer 14 and the pixel electrode layer 17.

Referring to fig. 4 to 6, in particular, according to an embodiment of the present invention, the array substrate 100 provided in an embodiment of the present invention further includes: a light-shielding layer 111 disposed on the substrate 11; a buffer layer 112 disposed on the light-shielding layer 111 and the substrate 11; an oxide semiconductor layer 113 disposed on the buffer layer 112; a gate insulating layer 114 disposed on the oxide semiconductor layer 113; a gate electrode 115 disposed on the gate insulating layer 114; an interlayer dielectric layer 116 covering the oxide semiconductor layer 113, the gate insulating layer 114, the gate electrode 115, and the buffer layer 112; the source electrode 121 and the drain electrode 122 disposed on the interlayer dielectric layer 116 and electrically connected to the oxide semiconductor layer 113 through the interlayer dielectric layer 116; a passivation layer 13 covering the source electrode 121 and the drain electrode 122 and the interlayer dielectric layer 116; and a color film 117 disposed on the passivation layer 13, wherein the planarization layer 14 is disposed in an area of the passivation layer 13 not covered by the color film 117, as shown in fig. 4.

Referring to fig. 4, according to an embodiment of the present invention, the size of the first black light absorbing layer 151 is greater than or equal to the size of the corresponding source electrode 121, so that the projection of the source electrode 121 on the substrate 11 completely falls within the projection range of the first black light absorbing layer 151 on the substrate 11. In one embodiment, the first black light absorbing layer 151 may have a size greater than 10% to 30% of the source electrode 121 corresponding thereto. Basically, the larger the width of the black light absorbing layer 15 formed by carbonizing the planarization layer 14, the more the reflected light of each metal trace and metal film layer can be sufficiently blocked (the arrow in fig. 6 represents the path of light), however, the required width of the black light absorbing layer 15 can be selectively designed according to the product positioning requirement in consideration of the cost and the display aperture ratio.

With continued reference to fig. 4, according to an embodiment of the present invention, the array substrate 100 provided in the embodiment of the present invention further includes: the substrate further includes a second black light absorbing layer 152, the second black light absorbing layer 152 is disposed in a region corresponding to the drain electrode 122 in the planarization layer 14, and the size of the second black light absorbing layer 152 is greater than or equal to the size of the corresponding drain electrode 122, so that the projection of the drain electrode 122 on the substrate 11 completely falls within the projection range of the second black light absorbing layer 152 on the substrate 11. In one embodiment, the second black light absorbing layer 152 may have a size greater than 10% to 30% of the corresponding drain electrode 122. In the embodiment of the invention, the principle of using the second black light absorbing layer 152 formed by carbonizing the planarization layer 14 to block the reflected light of the drain 122, other metal traces and metal film is the same as the above, and is not repeated herein.

According to an embodiment of the present invention, the black light absorbing layer 15 has the same pattern as the source electrode 121 and the drain electrode 122 and corresponds to each other, as shown in fig. 4.

According to other embodiments of the present invention, the pattern of the black light absorbing layer 15 may not completely correspond to the source electrode 121 and the drain electrode 122, and the coverage of the black light absorbing layer 15 may further shield the reflected light of other metal traces and metal films besides shielding the reflected light of the source electrode 121 and the drain electrode 122. The pattern of the black light absorbing layer 15 of the present invention is not limited to the example shown in fig. 4.

In the array substrate 100 provided in the embodiments of the present invention, the materials of the film layers can refer to the foregoing embodiments, and are not described herein again.

In addition, referring to fig. 6, an embodiment of the present invention further provides a display panel, where the display panel includes the array substrate 100 provided in any one of the foregoing embodiments, a color film 117 is disposed in the planarization layer 14, an opening 18a is formed in the pixel definition layer 18 to expose the pixel electrode layer 17, a light emitting element 19 is disposed in the opening 18a, and projections of the color film 117 and the light emitting element 19 on the substrate 11 are overlapped, and similar structural portions may refer to the foregoing embodiments and are not described herein again. In one embodiment, the light emitting device 19 is a White Organic Light Emitting Diode (WOLED), but the invention is not limited thereto.

As can be seen from the above description, the array substrate 100 and the manufacturing method thereof according to the present invention relate to a bottom emission White Organic Light Emitting Diode (WOLED) display and a manufacturing method thereof, after the planarization layer 14 is manufactured, a black light absorbing layer is formed by performing a carbonization process on an area of the planarization layer 14 corresponding to a metal trace position, so as to effectively avoid a light leakage problem caused by the light of the light emitting element 19 being reflected by the cathode and the metal trace to illuminate an adjacent pixel.

Furthermore, the features of the various embodiments may thus be combined in any desired manner to form new embodiments, all such combinations being within the scope of the invention. The described features or characteristics may be combined in any other suitable manner in one or more embodiments. In the above description, certain specific details are provided, such as thicknesses, amounts, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth.

While the above examples are illustrative of the principles of the present invention in one or more applications, it will be apparent to those of ordinary skill in the art that various changes in form, usage and details of implementation can be made without departing from the principles and concepts of the invention. Accordingly, the invention is defined by the appended claims.