阅读说明：本技术 阵列基板的制作方法及阵列基板 (Manufacturing method of array substrate and array substrate ) 是由 刘凯军 周佑联 许哲豪 袁海江 于 2021-07-29 设计创作，主要内容包括：本申请适用于显示技术领域,提供了一种阵列基板的制作方法及阵列基板。阵列基板的制作方法包括：提供基板,基板包括衬底、设于衬底上的栅极、覆盖于衬底和栅极上的第一绝缘层、覆盖于第一绝缘层上的半导体层以及覆盖于半导体层的金属层；在金属层上形成第二绝缘层,以覆盖金属层；在第二绝缘层上设置光刻胶,采用光罩对光刻胶进行曝光和显影处理,得到阻挡层,以露出需要蚀刻的第二绝缘层；以阻挡层为遮挡,对第二绝缘层进行第一次蚀刻,去除露出的第二绝缘层,以露出需要蚀刻的金属层；对金属层进行第二次蚀刻,去除露出的金属层,得到金属线,第二绝缘层可以防止金属层被氧化或者杂质掉落至金属层的表面,有效避免金属线咬伤或断线的情况发生。(The application is applicable to the technical field of display, and provides a manufacturing method of an array substrate and the array substrate. The manufacturing method of the array substrate comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a grid arranged on the substrate, a first insulating layer covering the substrate and the grid, a semiconductor layer covering the first insulating layer and a metal layer covering the semiconductor layer; forming a second insulating layer on the metal layer to cover the metal layer; arranging photoresist on the second insulating layer, and carrying out exposure and development treatment on the photoresist by adopting a photomask to obtain a barrier layer so as to expose the second insulating layer to be etched; taking the barrier layer as a shield, carrying out first etching on the second insulating layer, and removing the exposed second insulating layer to expose the metal layer to be etched; and etching the metal layer for the second time to remove the exposed metal layer to obtain the metal wire, wherein the second insulating layer can prevent the metal layer from being oxidized or impurities from falling to the surface of the metal layer, and the metal wire is effectively prevented from being bitten or broken.)

1. A manufacturing method of an array substrate is characterized by comprising the following steps:

providing a substrate, wherein the substrate comprises a substrate, a grid electrode arranged on the substrate, a first insulating layer covering the substrate and the grid electrode, a semiconductor layer covering the first insulating layer, a metal layer covering the semiconductor layer and an ohmic contact layer arranged between the metal layer and the semiconductor layer, the substrate is provided with a TFT (thin film transistor) area, the TFT area is provided with a channel area, and the grid electrode is arranged corresponding to the TFT area;

forming a second insulating layer on the metal layer to cover the metal layer;

arranging photoresist on the second insulating layer, and carrying out exposure and development treatment on the photoresist by adopting a photomask to obtain a barrier layer so as to expose the second insulating layer to be etched;

taking the barrier layer as a shield, carrying out first etching on the second insulating layer, reserving the second insulating layer arranged corresponding to the TFT area, and removing the exposed second insulating layer to expose the metal layer to be etched;

performing second etching on the metal layer, and removing the exposed metal layer to obtain a metal wire;

etching the barrier layer, the second insulating layer, the semiconductor layer and the ohmic contact layer for the third time, and removing the barrier layer and the second insulating layer of the channel region to expose the metal layer of the channel region; removing the exposed ohmic contact layer and the exposed semiconductor layer, and reserving the ohmic contact layer and the semiconductor layer of the TFT region;

etching the metal layer for the fourth time, removing the metal layer in the channel region, and forming source electrodes and drain electrodes which are arranged at intervals;

and etching the ohmic contact layer for the fifth time, removing the ohmic contact layer in the channel region, and forming a first ohmic contact layer arranged corresponding to the source electrode and a second ohmic contact layer arranged corresponding to the drain electrode, wherein the first ohmic contact layer and the second ohmic contact layer are arranged at intervals.

2. The method of manufacturing an array substrate of claim 1, wherein the second insulating layer is etched for the first time by a dry etching process.

3. The method of claim 1, wherein the metal layer is etched for a second time by a wet etching process.

4. The method of manufacturing the array substrate of claim 1, wherein the barrier layer, the second insulating layer, the semiconductor layer and the ohmic contact layer are etched for a third time by using a dry etching process.

5. The method for manufacturing the array substrate according to claim 1, wherein the metal layer is etched for a fourth time by a wet etching process.

6. The method for manufacturing the array substrate according to claim 1, wherein the ohmic contact layer is etched fifth time by using a dry etching process.

7. The method for manufacturing an array substrate according to any one of claims 1 to 6, further comprising: and after the ohmic contact layer is etched for the fifth time, a passivation layer is formed on the barrier layer and the first insulating layer, and a pixel electrode is formed on the passivation layer and is electrically connected with the drain electrode.

8. The method of any one of claims 1 to 6, wherein the mask is a halftone mask.

9. The method for manufacturing the array substrate according to any one of claims 1 to 6, wherein the substrate further comprises a scan line disposed on the same layer as the gate electrode, and the scan line is disposed perpendicular to the metal line.

10. An array substrate manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 9, the array substrate comprising:

a substrate;

the grid is arranged on the substrate;

the first insulating layer covers the substrate and the grid electrode;

the semiconductor layer is arranged on the first insulating layer and is arranged corresponding to the grid electrode;

the first ohmic contact layer and the second ohmic contact layer are arranged on the semiconductor layer at intervals;

and the metal layer comprises a source electrode arranged on the first ohmic contact layer, a drain electrode arranged on the second ohmic contact layer and a metal wire electrically connected with the drain electrode.

Technical Field

The application belongs to the technical field of display, and particularly relates to a manufacturing method of an array substrate and the array substrate.

Background

Liquid crystal displays have been widely used in various fields of work and life as a main medium for transmitting information. With the progress of science and technology and the development of society, the development of displays towards high refresh rate, high resolution and large size has become a necessary trend, and copper wires are considered to be the best metal material for producing high refresh rate and large size panels due to the advantages of low resistivity, good film thickness uniformity and the like. However, copper has the characteristics of easy corrosion, oxidation and the like, so that the copper has the difficulties of wide influence range, more attention-paying processes, complex development process and the like in production.

In the manufacturing process of the array substrate, after a metal material (such as copper) is deposited on the substrate to form a metal layer (copper layer), the substrate with the metal layer formed thereon is transferred to other workshops to etch the metal layer, and in the transfer process, the metal layer is easily oxidized, and impurities are easily adsorbed on the surface of the metal layer, so that the subsequent photoresist is not well adhered to cause the produced metal wire to be bitten or broken.

Disclosure of Invention

The present application aims to provide a manufacturing method of an array substrate and the array substrate, and aims to solve the technical problem that metal wires of the array substrate are easy to bite or break.

The present application is realized as such, and a method for manufacturing an array substrate includes:

providing a substrate, wherein the substrate comprises a substrate, a grid electrode arranged on the substrate, a first insulating layer covering the substrate and the grid electrode, a semiconductor layer covering the first insulating layer, a metal layer covering the semiconductor layer and an ohmic contact layer arranged between the metal layer and the semiconductor layer, the substrate is provided with a TFT (thin film transistor) area, the TFT area is provided with a channel area, and the grid electrode is arranged corresponding to the TFT area;

forming a second insulating layer on the metal layer to cover the metal layer;

arranging photoresist on the second insulating layer, and carrying out exposure and development treatment on the photoresist by adopting a photomask to obtain a barrier layer so as to expose the second insulating layer to be etched;

taking the barrier layer as a shield, carrying out first etching on the second insulating layer, reserving the second insulating layer arranged corresponding to the TFT area, and removing the exposed second insulating layer to expose the metal layer to be etched;

performing second etching on the metal layer, and removing the exposed metal layer to obtain a metal wire;

etching the barrier layer, the second insulating layer, the semiconductor layer and the ohmic contact layer for the third time, and removing the barrier layer and the second insulating layer of the channel region to expose the metal layer of the channel region; removing the exposed ohmic contact layer and the exposed semiconductor layer, and reserving the ohmic contact layer and the semiconductor layer of the TFT region;

etching the metal layer for the fourth time, removing the metal layer in the channel region, and forming source electrodes and drain electrodes which are arranged at intervals;

and etching the ohmic contact layer for the fifth time, removing the ohmic contact layer in the channel region, and forming a first ohmic contact layer arranged corresponding to the source electrode and a second ohmic contact layer arranged corresponding to the drain electrode, wherein the first ohmic contact layer and the second ohmic contact layer are arranged at intervals.

In one embodiment, the second insulating layer is first etched using a dry etching process.

In one embodiment, the metal layer is etched a second time using a wet etch process.

In one embodiment, the barrier layer, the second insulating layer, the semiconductor layer, and the ohmic contact layer are etched for a third time using a dry etching process.

In one embodiment, the metal layer is etched a fourth time using a wet etch process.

In one embodiment, the ohmic contact layer is fifth etched using a dry etching process.

In one embodiment, further comprising: and after the ohmic contact layer is etched for the fifth time, a passivation layer is formed on the barrier layer and the first insulating layer, and a pixel electrode is formed on the passivation layer and is electrically connected with the drain electrode.

In one embodiment, the mask is a halftone mask.

In one embodiment, the substrate further includes a scan line disposed on a same layer as the gate electrode, and the scan line is disposed perpendicular to the metal line.

Another object of the present invention is to provide an array substrate, which is manufactured by the method for manufacturing an array substrate, the array substrate including:

a substrate;

the grid is arranged on the substrate;

the first insulating layer covers the substrate and the grid electrode;

the semiconductor layer is arranged on the first insulating layer and is arranged corresponding to the grid electrode;

the first ohmic contact layer and the second ohmic contact layer are arranged on the semiconductor layer at intervals;

and the metal layer comprises a source electrode arranged on the first ohmic contact layer, a drain electrode arranged on the second ohmic contact layer and a metal wire electrically connected with the drain electrode.

The array substrate and the manufacturing method thereof provided by the embodiment of the application have the beneficial effects that: this application is through after forming the metal level on the base plate, forms the second insulating layer in order to cover on the metal level can prevent that the base plate from in the transfer process, and the metal level is by oxidation or impurity drops to the surface of metal level, and the photoetching glue of follow-up setting can be stably attached to on the second insulating layer, guarantees that the etching of metal level normally goes on, effectively avoids the condition emergence of metal wire sting or broken string.

Drawings

Fig. 1 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of steps S1-S3 provided by an embodiment of the present application;

fig. 3 is a schematic diagram of step S4 provided by the embodiment of the present application;

fig. 4 is a schematic diagram of step S5 provided by the embodiment of the present application;

fig. 5 is a schematic diagram of step S6 provided by the embodiment of the present application;

fig. 6 is a schematic diagram of step S7 provided by the embodiment of the present application;

fig. 7 is a schematic diagram of step S8 provided by the embodiment of the present application;

fig. 8 is a schematic view of step S9 and a schematic structure diagram of the array substrate according to the embodiment of the present disclosure.

Wherein, in the figures, the respective reference numerals:

100-a substrate; 110-a substrate; a 111-TFT region; 112-a channel region; 120-a gate; 130-a storage electrode; 140-a first insulating layer; 150-a semiconductor layer; 160-ohmic contact layer; 161-a first ohmic contact layer; 162-a second ohmic contact layer; 170-a metal layer; 171-source electrode; 172-drain electrode; 200-a second insulating layer; 300-a barrier layer; 400-a passivation layer; 500-pixel electrodes; 600-mask.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.

The description and claims of this invention and the word "comprise" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

In order to explain the technical solutions of the present application, the following detailed descriptions are made with reference to specific drawings and examples.

Referring to fig. 1, an embodiment of the present invention provides a method for manufacturing an array substrate 100, including:

step S1, as shown in fig. 2, providing a substrate 100, where the substrate 100 includes a substrate 110, a gate electrode 120 disposed on the substrate 110, a first insulating layer 140 covering the substrate 110 and the gate electrode 120, a semiconductor layer 150 covering the first insulating layer 140, a metal layer 170 covering the semiconductor layer 150, and an ohmic contact layer 160 disposed between the metal layer 170 and the semiconductor layer 150, the substrate 110 is provided with a TFT region 111, the TFT region 111 has a channel region 112, and the gate electrode 120 is disposed corresponding to the TFT region 111;

step S2, as shown in fig. 2, forming a second insulating layer 200 on the metal layer 170 to cover the metal layer 170;

step S3, as shown in fig. 2, a photoresist is disposed on the second insulating layer 200, and the photoresist is exposed and developed by using the mask 600 to obtain the barrier layer 300, so as to expose the second insulating layer 200 to be etched;

step S4, as shown in fig. 3, the barrier layer 300 is used as a mask to perform a first etching on the second insulating layer 200, the second insulating layer 200 disposed corresponding to the TFT region 111 is retained, and the exposed second insulating layer 200 is removed to expose the metal layer 170 to be etched;

step S5, as shown in fig. 4, performing a second etching on the metal layer 170 to remove the exposed metal layer 170, so as to obtain a metal line (not shown);

step S6, as shown in fig. 5, performing a third etching on the barrier layer 300, the second insulating layer 200, the semiconductor layer 150 and the ohmic contact layer 160 to remove the barrier layer 300 and the second insulating layer 200 in the channel region 112 to expose the metal layer 170 in the channel region 112; and removing the exposed ohmic contact layer 160 and the semiconductor layer 150, leaving the ohmic contact layer 160 and the semiconductor layer 150 of the TFT region 111;

step S7, as shown in fig. 6, performing a fourth etching on the metal layer 170, removing the metal layer 170 in the channel region 112, and forming the source 171 and the drain 172 that are spaced apart from each other;

step S8, as shown in fig. 7, is to perform a fifth etching on the ohmic contact layer 160, remove the ohmic contact layer 160 in the channel region 112, form a first ohmic contact layer 161 corresponding to the source electrode 171 and a second ohmic contact layer 162 corresponding to the drain electrode 172, and dispose the first ohmic contact layer 161 and the second ohmic contact layer 162 at intervals. It should be noted that the ohmic contact layer 160 is used to make the subsequently manufactured source electrode 171 and the subsequently manufactured drain electrode 172 respectively make ohmic contact with the semiconductor layer 150, so as to effectively reduce the resistance value, and facilitate the input and output of current.

According to the application, after the metal layer 170 is formed on the substrate 100, the second insulating layer 200 is formed on the metal layer 170 to cover the metal layer 170, the second insulating layer 200 can play a role in protection, the substrate 100 can be prevented from being transferred, the metal layer 170 is oxidized or impurities fall to the surface of the metal layer 170, subsequently arranged photoresist can be stably attached to the second insulating layer 200, etching of the metal layer 170 is guaranteed to be normally carried out, and the situation that metal wires are bitten or broken is effectively avoided.

As a specific embodiment of the present application, in the step S1, the material of the metal layer 170 is copper, and it is understood that the material of the metal layer 170 may be modified appropriately according to the choice of actual conditions and specific requirements, and is not limited herein.

As a specific embodiment of the present application, in the step S4, the first etching is performed by using a dry etching process, and specifically, but not limited to, the second insulating layer 200 may be bombarded by using plasma to achieve the etching effect.

As an embodiment of the present invention, in the step S5, the second etching is performed by a wet etching process, specifically, but not limited to, etching the exposed metal layer 170 by using an etchant to achieve the etching effect.

It should be noted that in the embodiment of the present application, the source electrode 171, the drain electrode 172 and the metal line are all obtained by patterning the metal layer 170, that is, the source electrode 171, the drain electrode 172 and the metal line are located in the same layer; the metal line is a data line, and the drain 172 is connected to the metal line, so that the drain 172 is electrically connected to the metal line. Under the structure, the source electrode 171, the drain electrode 172 and the metal wire are not required to be manufactured through corresponding metal structure layers, but the source electrode 171, the drain electrode 172 and the metal wire are manufactured only by adopting the same metal layer 170, so that the manufacturing cost is greatly saved.

As a specific embodiment of the present application, in the step S6, a third etching is performed by using a dry etching process, and specifically, but not limited to, the barrier layer 300, the second insulating layer 200, the ohmic contact layer 160 and the semiconductor layer 150 may be bombarded by using plasma to achieve the etching effect.

As an embodiment of the present invention, in the step S7, the fourth etching is performed by using a wet etching process, specifically, but not limited to, etching the exposed metal layer 170 by using an etchant to achieve the etching effect.

As a specific embodiment of the present application, in the step S8, the fifth etching is performed by using a dry etching process, and specifically, but not limited to, the ohmic contact layer 160 is bombarded by using plasma to achieve the etching effect.

As a specific embodiment of the present application, in the step S1, the material of the semiconductor layer 150 is amorphous silicon (a-Si), and the material of the ohmic contact layer 160 is amorphous silicon heavily doped with N-type dopant, it can be understood that the materials of the semiconductor layer 150 and the ohmic contact layer 160 can be appropriately modified according to the selection and specific requirement of the actual situation, and are not limited herein.

As an embodiment of the present application, the method for manufacturing the array substrate 100 further includes:

in step S9, as shown in fig. 8, after the ohmic contact layer 160 is etched for the fifth time, a passivation layer 400 is formed on the barrier layer 300 and the first insulating layer 140, and a pixel electrode 500 is formed on the passivation layer 400, wherein the pixel electrode 500 is electrically connected to the drain electrode 172.

In this embodiment, the pixel electrode 500 is electrically connected to the drain electrode 172 through the conductive material by providing a through via on the passivation layer 400, the barrier layer 300, and the second insulating layer 200 and exposing the drain electrode 172, and filling the through via with the conductive material.

As an embodiment of the present application, in the step S2, the material and the conductive material of the pixel electrode 500 are Indium Tin Oxide (ITO), and it is understood that the material and the conductive material of the pixel electrode 500 may be modified appropriately according to the choice of actual situations and specific requirements, and are not limited herein.

As one embodiment of the present application, as shown in fig. 2 to 8, in step S1, the substrate 100 further includes a storage electrode 130 disposed between the substrate 110 and the first insulating layer 140, the storage electrode 130 is disposed opposite to the pixel electrode 500 to be formed subsequently, and the storage electrode 130 and the pixel electrode 500 constitute a storage capacitor. In this embodiment, the storage electrode 130 and the gate electrode 120 are of the same layer structure.

As an embodiment of the present application, as shown in fig. 2, in the step S3, the mask 600 is a halftone mask to obtain the barrier layers 300 with different heights, and it is to be understood that the mask 600 may also be a mask 600 with regions with different light transmittances to obtain the barrier layers 300 with different heights, which is not limited herein.

As an embodiment of the present application, in step S1, the substrate 100 further includes a scan line (not shown) disposed on the same layer as the gate electrode 120, the scan line being disposed perpendicular to the metal line, and the plurality of metal lines and the plurality of scan lines intersecting each other to define a plurality of pixel regions on the substrate 100. In this embodiment, each scan line is connected to the corresponding gate electrode 120, so that each scan line is electrically connected to the corresponding gate electrode 120, and the scan lines and the gate electrodes 120 are in the same layer structure.

Referring to fig. 8, an array substrate 100 is further provided in the present embodiment, and is manufactured by the manufacturing method of the array substrate 100, where the array substrate 100 includes a substrate 110, a gate 120 disposed on the substrate 110, a first insulating layer 140 covering the substrate 110 and the gate 120, a semiconductor layer 150 disposed on the first insulating layer 140 and corresponding to the gate 120, a first ohmic contact layer 161 and a second ohmic contact layer 162 disposed on the semiconductor layer 150 at an interval, and a metal layer 170, and the metal layer 170 includes a source 171 disposed on the first ohmic contact layer 161, a drain 172 disposed on the second ohmic contact layer 162, and a metal line electrically connected to the drain 172. Since the array substrate 100 provided in this embodiment is manufactured by the above manufacturing method, all the advantages brought by the technical solutions of the above embodiments are also achieved, and are not described in detail herein.

As an embodiment of the present invention, the array substrate 100 further includes a passivation layer 400 covering the metal layer 170, and a pixel electrode 500 disposed on the passivation layer 400, wherein the pixel electrode 500 is electrically connected to the drain electrode 172.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.