阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 王晨晨 吕俊颉 徐志安 林佑明 杨世海 于 2021-04-23 设计创作，主要内容包括：本发明涉及半导体器件及其形成方法。一种器件,包括：在衬底之上的第一晶体管,布置在第一晶体管之上的第二晶体管,以及布置在第二晶体管之上的存储器元件。第二晶体管包括沟道层,围绕沟道层的侧壁的栅极电介质层,以及围绕栅极电介质层的侧壁的栅极电极。(The invention relates to a semiconductor device and a forming method thereof. A device, comprising: a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding sidewalls of the channel layer, and a gate electrode surrounding sidewalls of the gate dielectric layer.)

1. A semiconductor device, comprising:

a first transistor disposed over a substrate;

a second transistor disposed over the first transistor, wherein the second transistor includes:

a channel layer;

a gate dielectric layer surrounding sidewalls of the channel layer; and

a gate electrode surrounding sidewalls of the gate dielectric layer; and

a memory element disposed over the second transistor.

2. The semiconductor device according to claim 1, wherein the channel layer has a columnar shape.

3. The semiconductor device according to claim 1, wherein the channel layer has a ring shape in a plan view.

4. The semiconductor device according to claim 3, wherein the channel layer surrounds a sidewall of the insulating layer in a plan view.

5. The semiconductor device of claim 1, wherein the second transistor further comprises a first electrode and a second electrode separated by the channel layer.

6. The semiconductor device according to claim 5, wherein the first electrode is arranged below the channel layer and includes a wire extending in a first direction.

7. The semiconductor device of claim 5, wherein the first electrode is disposed below the channel layer and has sidewalls aligned with sidewalls of the channel layer.

8. The semiconductor device of claim 7, wherein each of the first and second electrodes comprises a metallic material or a doped semiconductor material.

9. A semiconductor device, comprising:

a substrate;

a first array of transistors over the substrate;

a first insulating layer covering the first transistor array;

a second transistor array disposed over the first insulating layer, wherein transistors of the second transistor array include:

a first channel layer;

a first gate dielectric layer surrounding sidewalls of the first channel layer; and

a first gate electrode surrounding sidewalls of the first gate dielectric layer; and

a first memory element disposed over and electrically connected to the second transistor array.

10. A method of manufacturing a semiconductor device, comprising:

forming a first conductive line;

forming a gate electrode layer over the first wire;

patterning an opening in the gate electrode layer;

forming a gate dielectric layer on sidewalls of the opening;

forming a channel layer on sidewalls of the gate dielectric layer in the opening;

forming a memory element disposed over the channel layer; and

patterning the gate electrode layer to define gate electrodes, wherein each of the gate electrodes surrounds a respective sidewall of the channel layer.

Technical Field

The present disclosure relates to semiconductor devices and methods of forming the same.

Background

Many modern electronic devices contain electronic memory. The electronic memory may be volatile memory or non-volatile memory. Non-volatile memory retains its stored data when power is removed, while volatile memory loses its stored data when power is removed. Emerging memories such as Resistive Random Access Memory (RRAM), Magnetoresistive Random Access Memory (MRAM), and Phase Change Random Access Memory (PCRAM) are promising candidates for next generation non-volatile memories due to their simple structure and their compatibility with Complementary Metal Oxide Semiconductor (CMOS) logic fabrication processes.

Disclosure of Invention

According to a first aspect of the present disclosure, there is provided a semiconductor device comprising: a first transistor disposed over a substrate; a second transistor disposed over the first transistor, wherein the second transistor includes: a channel layer; a gate dielectric layer surrounding sidewalls of the channel layer; and a gate electrode surrounding sidewalls of the gate dielectric layer; and a memory element disposed over the second transistor.

According to a second aspect of the present disclosure, there is provided a semiconductor device comprising: a substrate; a first array of transistors over the substrate; a first insulating layer covering the first transistor array; a second transistor array disposed over the first insulating layer, wherein transistors of the second transistor array include: a first channel layer; a first gate dielectric layer surrounding sidewalls of the first channel layer; and a first gate electrode surrounding sidewalls of the first gate dielectric layer; and a first memory element disposed over and electrically connected to the second transistor array.

According to a third aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: forming a first conductive line; forming a gate electrode layer over the first wire; patterning an opening in the gate electrode layer; forming a gate dielectric layer on sidewalls of the opening; forming a channel layer on sidewalls of the gate dielectric layer in the opening; forming a memory element disposed over the channel layer; and patterning the gate electrode layer to define gate electrodes, wherein each of the gate electrodes surrounds a respective sidewall of the channel layer.

Drawings

Various aspects of this disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1Q illustrate exemplary cross-sectional and plan views of a semiconductor device at intermediate stages according to embodiments of the disclosure.

FIG. 1R illustrates an equivalent circuit diagram of a memory cell according to an embodiment of the present disclosure.

Fig. 2A-2E illustrate exemplary cross-sectional views of a semiconductor device at intermediate stages according to embodiments of the disclosure.

Fig. 3A-3G illustrate exemplary cross-sectional views of a semiconductor device at intermediate stages according to embodiments of the disclosure.

Fig. 4A-4D illustrate exemplary cross-sectional views of a semiconductor device at intermediate stages according to embodiments of the disclosure.

Fig. 5A-5G illustrate exemplary cross-sectional views of a semiconductor device at intermediate stages according to embodiments of the disclosure.

Fig. 6A-6C illustrate exemplary cross-sectional views of a semiconductor device at intermediate stages according to embodiments of the present disclosure.

Fig. 7A-7B illustrate exemplary cross-sectional views of a semiconductor device at intermediate stages according to embodiments of the disclosure.

Fig. 8 illustrates an exemplary cross-sectional view of a semiconductor device at an intermediate stage according to an embodiment of the disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The embodiments discussed herein will provide examples to enable or use the subject matter of the present disclosure, and one of ordinary skill in the art will readily appreciate modifications that can be made while remaining within the intended scope of the different embodiments. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

The present disclosure relates to a semiconductor device having a logic circuit with a high-density embedded memory array. The semiconductor device of the present disclosure includes a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion disposed above the FEOL portion. A memory cell including a memory array and a transistor array is formed in a BEOL portion of a semiconductor device. Each memory cell includes a Resistive Random Access Memory (RRAM) cell, a Phase Change Random Access Memory (PCRAM) cell, a Magnetoresistive Random Access Memory (MRAM) cell, or any type of memory compatible with nanoscale logic circuitry. Each memory cell may store a single bit that may be read from or written to. Logic circuits, input/output (I/O) circuits, electrostatic discharge (ESD) circuits, and any other circuits may be formed in the FEOL portion of the semiconductor device.

Fig. 1A-1Q illustrate exemplary cross-sectional and plan views of a portion of a semiconductor device 100 at an intermediate stage according to embodiments of the present disclosure. For example, fig. 1Q shows a plan view of a portion of the semiconductor device 100. The cross-sectional views in fig. 1A to 1O correspond to the portions of the cross-section labeled a-a in fig. 1Q. The cross-sectional view in fig. 1P corresponds to the cross-section labeled B-B in fig. 1Q. It should be understood that for additional embodiments of the method, additional manufacturing steps may be provided before, during, and after the processes shown in the figures, and some manufacturing steps may be replaced or eliminated. The order of these operations/processes may be interchangeable.

Referring to fig. 1A, a FEOL portion 100F of a semiconductor device 100 is shown. The FEOL portion 100F includes a substrate 102. The substrate 102 may be a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may comprise other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

According to some embodiments, the transistor array is formed over the substrate 102 and covered by an insulating layer 106. The transistor array may be formed of transistors 104. In some embodiments, the transistor 104 is included in a logic circuit, an I/O circuit, an ESD circuit, any other circuit, or a combination thereof. The transistor 104 may include an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET). In some embodiments, the transistor 104 is a fin FET (finfet), a surrounding gate FET (gaa FET), a planar FET, or a combination thereof. At least one of the transistors 104 may have a source electrode and a drain electrode laterally inserted into the channel layer. For example, when the transistor 104 is a FinFET, the transistor 104 may include source and drain features disposed over respective sides of the fin.

According to some embodiments, the FEOL portion 100F may further include an insulating layer 106 formed over the substrate 102. In some embodiments, insulating layer 106 includes one or more sub-layers. Insulating layer 106 may comprise silicon oxide, silicon oxynitride, silicon nitride, spin-on dielectric materials, or low-k dielectrics, such as porous silicon oxide or other suitable dielectric materials having a dielectric constant of less than about 3.9. The insulating layer 106 may be formed by: flowable CVD (fcvd) (e.g., CVD-based materials that can flow to fill gaps and spaces with high aspect ratios and convert to oxide by curing during deposition), high density plasma chemical vapor deposition (HDP-CVD), sub-atmospheric CVD (sacvd), other suitable CVD techniques, Atomic Layer Deposition (ALD), spin-on coating, or combinations thereof. In some embodiments, the transistors 104 are electrically isolated from each other by an insulating layer 106.

After the FEOL portion 100F is formed, the steps of manufacturing the BEOL portion 100B (see fig. 1O) of the semiconductor device 100 are continued. For example, referring to fig. 1B, the conductive line 110 is formed over the insulating layer 106 and extends along a first direction (e.g., the X direction shown in fig. 1Q). The conductive line 110 may include a conductive layer over a barrier layer, a conductive layer over a glue layer (e.g., Ti/TiN/TaN), or a combination of all. In one embodiment, the conductive layer of the wire 110 may include a metal material such as Ru, Ta, Ti, Al, TiN, W, Cu, etc., an alloy thereof, or a combination thereof. In some embodiments, the barrier layer comprises Ta, Ti, Pt, other noble metals, other refractory metals, nitrides thereof, or combinations thereof. In one embodiment, the conductive lines 110 are formed in a dielectric layer (or referred to as an inter-layer dielectric (ILD) layer, not shown). The ILD layer may be made of materials including Si, O, C, and/or H, such as silicon oxide, SiCOH, SiOC, and SiOCN, low-k materials, organic materials, any other suitable dielectric material, or combinations thereof. In some embodiments, conductive line 110 provides a source line for a subsequently formed memory cell.

In some embodiments, the conductive lines 110 are formed by: an ILD layer is first deposited and patterned to form openings (e.g., using appropriate photolithography and etching processes), and the openings in the ILD layer are filled with barrier and conductive layers. In other embodiments, the conductive line 110 is formed by: firstly, depositing a barrier layer and a conductive layer; patterning the barrier and conductive layers into conductive lines 110; and the space between adjacent conductive lines 110 is filled with an ILD layer. In any of the above embodiments, after depositing the conductive layer and the ILD layer, a planarization process such as Chemical Mechanical Planarization (CMP) is performed to remove excess portions of the conductive layer over the dielectric layer or expose the conductive lines 110 from the ILD layer. The conductive or barrier layers may be deposited by Physical Vapor Deposition (PVD), CVD, ALD, e-beam evaporation, or other suitable process. The ILD layer may be formed by any CVD technique, spin coating, or combination thereof.

Referring to fig. 1C, a dielectric layer 114, a gate electrode layer 118, and a dielectric layer 120 are deposited over the conductive line 110. In one embodiment, the dielectric layers 114 and 120 comprise a material comprising Si, O, C, N, and/or H, such as silicon oxide, SiCOH, SiOC, SiOCN, SiON, SiN, low-k materials, organic materials, any other suitable dielectric material, or combinations thereof. In some embodiments, dielectric layer 114 and dielectric layer 120 may each have a thickness of about 0.2nm to about 5 nm. Dielectric layers 114 and 120 may be deposited by any CVD technique, PVD, spin coating, or combinations thereof.

In some embodiments, gate electrode layer 118 may be formed from a conductive material such as Ru, Ta, Ti, Al, TiN, W, alloys thereof, or the like, or combinations thereof. Gate electrode layer 118 may be deposited by PVD, any CVD technique, ALD, e-beam evaporation, other suitable process, or combinations thereof. In some embodiments, gate electrode layer 118 has a thickness T of about 0.1nm to about 10 nm.

Referring to FIG. 1D, an opening 124 is formed in dielectric layer 120, gate electrode layer 118, and dielectric layer 114, according to some embodiments. The opening 124 may be formed by one or more photolithography and etching processes. For example, in one embodiment, a photoresist layer is applied over the dielectric layer 120 and patterned by photolithography. The portions of the dielectric layer 120, the gate electrode layer 118, and the dielectric layer 114 not covered by the patterned photoresist layer are etched by one or more anisotropic etch processes, such as Reactive Ion Etching (RIE) or Ion Beam Etching (IBE). The anisotropic etching process may include etching the different layers using various suitable gases. In some embodiments, the opening 124 is at least partially aligned with the wire 110 and exposes the wire 110. The opening 124 may have an approximately circular shape or may have a rectangular shape, such as an oval shape, a rounded rectangle, or the like. In some embodiments, the openings 124 have a diameter or major axis of about 10nm to about 100 nm.

Referring to fig. 1E, a gate dielectric layer 128 is conformally formed in the opening 124 and over the dielectric layer 120, according to some embodiments. In some embodiments, gate dielectric layer 128 comprises a high-k dielectric layer, such as HfO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titania, hafnia-alumina (HfO)₂-Al₂O₃) Alloy, Ta₂O₃、La₂O₃、 HfO₂-La₂O₃、Y₂O₃Other suitable high-k dielectric materials, or combinations thereof. The gate dielectric layer 128 may be formed by ALD or any suitable CVD technique. In some embodiments, gate dielectric layer 128 has a thickness of about 0.5nm to about 20 nm.

Referring to fig. 1F, according to some embodiments, the bottom of gate dielectric layer 128 is removed by an etching process and conductive line 110 is exposed. In some embodiments, the etching process is anisotropic and includes Reactive Ion Etching (RIE) or Ion Beam Etching (IBE) and is configured to vertically etch the gate dielectric layer 128 with minimal lateral etching. The gate dielectric layer 128 above the dielectric layer 120 may be partially or completely removed in an etching process.

Referring to fig. 1G, according to some embodiments, the channel layer 132 is formed ofIs formed over gate dielectric layer 128 and fills opening 124. In some embodiments, the channel layer 132 includes an oxide semiconductor having a bandgap higher than that of silicon. For example, the channel layer 132 may have a bandgap of about 2eV to about 4 eV. In some embodiments, the channel layer 132 includes indium oxide (In)₂O₃) Indium Zinc Oxide (IZO), Zinc Tin Oxide (ZTO), Indium Gallium Oxide (IGO), indium tungsten oxide (IWO), Indium Gallium Zinc Oxide (IGZO), tin oxide (SnO)₂) Nickel oxide (NiO), copper oxide (Cu)₂O), zinc oxide (ZnO), and the like, or combinations thereof. The channel layer 132 may be formed by any suitable CVD technique, PVD, or combinations thereof.

Referring to fig. 1H, according to some embodiments, the gate dielectric layer 128 and the excess portion of the channel layer 132 are removed by a planarization process (e.g., by CMP). For example, portions of gate dielectric layer 128 and channel layer 132 above dielectric layer 120 may be removed. According to some embodiments, after the planarization process, the resulting gate dielectric layer 128 has a ring shape in each opening 124 in plan view, and the resulting channel layer 132 has a pillar shape in each opening 124.

In fig. 1I and 1J, memory stack layers are deposited over channel layer 132 and dielectric layer 120, according to some embodiments. In one embodiment, the memory stack layers include a bottom electrode layer 136, a memory layer 140, and a top electrode layer 144. Referring to FIG. 1I, a bottom electrode layer 136 of memory stack layers is deposited. In one embodiment, the bottom electrode layer 136 is deposited over the dielectric layer 120 and the channel layer 132 using one or more suitable techniques, such as CVD, ALD, PVD, sputtering, electroplating, or the like, or combinations thereof. In some embodiments, the bottom electrode layer 136 is formed from multiple layers of materials. The bottom electrode layer 136 may include Cu, Al, Ti, Ta, W, Pt, Ni, Cr, Ru, Co_xFe_yB_zW_wTiN, TaN, etc., combinations thereof, or multilayers thereof. For example, the bottom electrode layer 136 may include a tantalum nitride layer and a titanium nitride layer formed over the tantalum nitride layer.

Next, in fig. 1J, memory layer 140 of the memory stack layers is deposited over bottom electrode layer 136 using one or more suitable techniques, such as CVD, ALD, PVD, sputtering, electroplating, or the like, or combinations thereof. In some embodiments, memory layer 140 includes a resistive material. The resistive material may be made of a metal oxide, such as NiOx, WOx, HfOx, ZnOx, TiOx, TaOx, FeOx, GeOx, AlOx, NbOx, GdOx, CeOx, ZrOx, CuOx, CuSiOx, PrCaMnOx, or combinations thereof, where x may be an oxygen number corresponding to the highest oxidation state of the metal or a lower oxidation state of the metal. In other embodiments, the memory layer includes other resistive materials, such as TiON, Ag-GeSe, Cu-GeSe, or combinations thereof.

In some embodiments, memory layer 140 includes a binary phase change material, such as GeSb, InSb, InSe, SbTe, GeTe, and/or GaSb; ternary systems (ternary systems), such as GeSbTe, InSbTe, GaSeTe, SnSbTe, InSbGe and/or GaSbTe; or quaternary systems, such as GeSnSbTe, GeSbSeTe, TeGeSbS, GeSbTeO and/or GeSbTeN. In certain embodiments, the phase change material is a GeSbTe alloy (e.g., Ge) with or without nitrogen doping and/or silicon oxide₂Sb₂Te₅)。

In other embodiments, memory layer 140 is a multilayer structure, for example, including a magnetic tunnel junction (MJT) structure, which may include a stack of barrier layers sandwiched by a free layer and a reference layer. Whether the memory layer 140 is in the high resistance state or the low resistance state depends on the relative orientation of the spin polarizations of the free layer and the reference layer. The free layer may be formed of one or more ferromagnetic materials, such as one or more layers of CoFe, NiFe, CoFeB, CoFeBW, Ru, alloys thereof, or the like, or combinations thereof. In some embodiments, the barrier layer is formed of one or more materials such as MgO, AlO, AlN, or the like, or combinations thereof. The reference layer may be formed of a ferromagnetic material, such as one or more layers of CoFe, NiFe, CoFeB, CoFeBW, alloys thereof, or the like, or combinations thereof.

In some embodiments, the memory layer 140 also includes a Synthetic Antiferromagnet (SAF) layer coupled to the MJT structure through a spacer layer. The SAF layer may provide antiferromagnetic coupling to pin (pin) the spin polarization direction of the reference layer in a fixed direction, where the coupling strength may be determined by the thickness of the spacer layer. Pinning the spin polarization direction of the reference layer allows the memory layer 140 to be switched between a low resistance state and a high resistance state by changing the spin polarization direction of the free layer relative to the reference layer. In some embodiments, the spacer layer is formed from a material such as W, Mo or the like or a combination thereof. In some embodiments, the SAF layer may include multiple layers of different materials. For example, the SAF layer may include a stack of one or more ferromagnetic layers and one or more nonmagnetic layers. For example, the SAF layer may be formed by a nonmagnetic layer or a stack of alternating nonmagnetic and ferromagnetic layers sandwiched between two ferromagnetic layers. The ferromagnetic layer may be formed of a material such as Co, Fe, Ni, CoFe, NiFe, CoFeB, CoFeBW, alloys thereof, or the like, or combinations thereof. The nonmagnetic layer may be formed of a material such as Cu, Ru, Ir, Pt, W, Ta, Mg, or the like, or a combination thereof.

In some embodiments, the memory layer 140 further includes a spin-orbit-torque (SOT) layer formed over the free layer of the MJT stack. The SOT layer may be formed of a heavy metal or metal alloy, such as W, Ta, Pt, Au, Pt, W₃Ta、B_ixSe_yBiSeTe, multilayers thereof, alloys thereof, and the like, or combinations thereof. In some embodiments, the SOT layer acts as a generator of spin-polarized current. By passing current through the SOT layer, spin-polarized currents are generated in the lateral direction and these spin-polarized currents are used to control the magnetic moment of the free layer of the MJT structure.

After depositing memory layer 140, a top electrode layer 144 of the memory stack layers is deposited over memory layer 140 using one or more suitable techniques, such as CVD, ALD, PVD, sputtering, electroplating, the like, or combinations thereof. The top electrode layer 144 may include one or more layers of materials such as Cu, Al, Ti, Ta, W, Pt, Ni, Cr, Ru, Co, Zr, TiN, TaN, etc., combinations thereof, or multilayers thereof. For example, the top electrode layer 144 may include a Ru layer and a Ta layer formed over the Ru layer. In some cases, the top electrode layer 144 may be considered a "capping layer," or one or more layers within the top electrode layer 144 may be considered a "capping layer.

Referring to fig. 1K, a patterning process is performed to pattern the bottom electrode layer 136, the memory layer 140, and the top electrode layer 144 to form individual memory stacks 150 (e.g., including the bottom electrode 136a, the memory element 140a, and the top electrode 144a), according to some embodiments. The patterning process may include one or more suitable photolithography and etching processes. For example, a photoresist is applied over the top electrode layer 144 and then patterned by one or more photolithography processes. Portions of the layers of the memory stack not covered by the patterned photoresist may be etched by one or more anisotropic etch processes. The one or more anisotropic etch processes may include a RIE process or an IBE process that uses various suitable gases to etch different ones of the layers of the memory stack. The memory stacks 150 may each have an approximately circular shape or a rectangular shape, such as an oval, a rounded rectangle, or the like. In some embodiments, the memory stack 150 has a size that is larger than the size of the opening 124 or substantially the same size as the size of the opening 124. For example, in some embodiments, the memory stack 150 has a diameter or long axis of about 10nm to about 500 nm. The memory stack 150 may have about 100nm²To about 250000nm²The area of (a). In some embodiments, memory stack 150 forms a memory array of memory cells.

Referring to fig. 1L, a dielectric layer 154 is formed over memory stack 150 and dielectric layer 120, according to some embodiments. In one embodiment, the portion of dielectric layer 154 over memory stack 150 is removed by a planarization process, such as CMP, exposing memory stack 150. Dielectric layer 154 may comprise a material similar to that described above for insulating layer 106, and may be formed by a similar method.

Referring to FIG. 1M, according to some embodiments, an opening 158 is formed in dielectric layer 120, gate electrode layer 118, and dielectric layer 114, and forms a select transistor 190 for the memory cell. In some embodiments, an opening 158 is formed between two adjacent memory stacks 150. For example, referring to fig. 1Q, an opening is provided where fill material 162 (which will later fill opening 158) will be deposited later. In some embodiments, the openings 158 (i.e., the filler material 162) extend along a direction (e.g., the Y-direction in fig. 1Q) that is substantially perpendicular to the conductive lines 110. For example, openings 158 (i.e., fill material 162) extend through and separate the gate electrode layer into discrete portions to define gate electrode 118a (e.g., strips 118a shown in fig. 1Q). In plan view, gate electrode 118a may surround and encircle sidewalls of gate dielectric layer 128 and sidewalls of channel layer 132. In some embodiments, the opening 158 may extend through the dielectric layer 120 and the dielectric layer 114 to define the spacers 120a and 114 a. The spacers 120a and 114a may have substantially the same shape as the gate electrode 118a in a plan view. For example, spacers 120a and 114a are inserted vertically into gate electrode 118a and laterally surround gate dielectric material 128 and channel layer 132.

In some embodiments, each select transistor 190 includes a channel layer 132, the channel layer 132 being surrounded by a gate dielectric layer 128 and a gate electrode 118 a. The channel layer 132 may be interposed by the wire 110 and the bottom electrode 136a (e.g., serving as a source/drain electrode). Bottom electrode 136a may serve as both an electrode of memory stack 150 and a drain electrode of select transistor 190. In some embodiments, select transistor 190 is a junction-less transistor with a vertical channel that extends between a first source/drain electrode (e.g., a portion of conductive line 110) and a second source/drain electrode (e.g., a portion of bottom electrode 136 a). Opening 158 may be formed by etching dielectric layer 120, gate electrode layer 118, and dielectric layer 114 using an etching process. The etching process may be anisotropic and may include a RIE process or an IBE process, wherein various suitable gases are used to etch the different layers.

Referring to fig. 1N, according to some embodiments, a fill material 162 is deposited to fill the opening 158. For example, fill material 162 may comprise a material similar to that described above for dielectric layer 114, dielectric layer 120, or dielectric layer 154, and may be formed using a similar method. In some embodiments, the fill material 162 is made of the same material as the dielectric layer 154. In some embodiments, after deposition, an excess portion of the fill material 162, e.g., a portion of the fill material 162 over the dielectric layer 154, is removed by a planarization process, such as CMP, to expose a top surface of the memory stack 150.

Referring to fig. 1O, conductive lines 166 are formed over dielectric layer 154 and fill material 162 and in contact with memory stack 150, according to some embodiments. In one embodiment, conductive lines 166 are formed in dielectric layer 170 (e.g., see fig. 1Q). In some embodiments, conductive lines 166 are formed by a damascene process. Wire 166 may be formed from materials similar to those described above for wire 110, and may be formed by similar methods. In one embodiment, conductive line 166 extends in a direction substantially parallel to conductive line 110 or substantially perpendicular to gate electrode 118a (e.g., along the X-direction shown in fig. 1Q). In some embodiments, conductive lines 166 provide bit lines for memory cells.

Referring to fig. 1P (which shows a cross-sectional view along a portion of the cross-section labeled B-B in fig. 1R), according to some embodiments, vias 174 and conductive lines 178 are formed. Via 174 may be in contact with gate electrode 118a to make an electrical connection between wire 178 and gate electrode 118 a. In some embodiments, conductive lines 178 and conductive lines 166 (see fig. 1O) are formed in the same dielectric layer, such as dielectric layer 170 shown in fig. 1P. For example, in such embodiments, vias 174 are formed in spacers 120a and dielectric layer 154, and conductive lines 166 and 178 are formed in dielectric layer 170. However, in other embodiments, conductive lines 178 and conductive lines 166 are formed in different dielectric layers. For example, in such embodiments, conductive line 178 is formed in an upper dielectric layer above dielectric layer 170, and via 174 extends through spacer 120, dielectric layer 154, and dielectric layer 170 to make an electrical connection between conductive line 178 and gate electrode 118 a. The wires 178 may be formed from materials similar to those described above for the wires 110. The vias 174 and conductive lines 178 may be formed by PVD, CVD, ALD, or other suitable method. In one embodiment, conductive line 178 extends in a direction substantially perpendicular to conductive line 110 or substantially parallel to gate electrode 118a (e.g., along the Y-direction shown in fig. 1Q). Further, to form the via 174, an opening may be defined through the associated layers by, for example, suitable photolithography and etching processes, and the opening may then be filled with a conductive material to form the via 174. In some embodiments, conductive line 178 provides a word line for the memory cell.

In some embodiments, vias 174 and conductive lines 178 are formed by a single damascene process or a dual damascene process. For example, when via 174 and conductive line 178 are formed by a single damascene process, via 174 may be formed first and then conductive lines 166 and 178 may be formed in dielectric layer 170 in the same or a different deposition process. When the via 174 and the conductive line 178 are formed by a dual damascene process, the via 174 and the conductive line 178 may be formed together (e.g., in the same deposition process), and the conductive line 166 may be formed before or after the via 174 and the conductive line 178 are formed.

One or more additional sets of vias and conductive lines (not shown) may be formed over conductive lines 178. Additional vias and sets of leads may be formed in a similar manner as vias 174 and leads 178. In some embodiments, pads and bumps (not shown) are also formed over the additional sets of vias and wires to complete the BEOL portion 100B.

Embodiments of the present disclosure have some advantageous features. For example, the select transistor 190 is integrated with a memory array formed by the memory stack 150 to form a memory cell in the BEOL portion 100B. The memory array and select transistor 190 implement a 1T1R (one transistor and one resistor) type memory cell in the BEOL portion 100B. For example, referring to the equivalent circuit of a 1T1R memory cell as shown in FIG. 1R, each memory stack 150 is operatively connected to one side of a transistor 190. The 1T1R memory cell may be operated by applying various voltages to the source line 110, bit line 166, and word line 178. Therefore, the selection transistor 190 may be formed above the logic circuit, the I/O circuit, and the ESD circuit in the FEOL portion 100A, instead of being formed in the same horizontal plane. As a result, the footprint of the memory cell can be reduced. It should be understood that although only a 1T1R type memory cell structure is shown in the above embodiments, other types of memory cell structures, such as a 2T1R type memory cell structure or other variations, are also contemplated within the scope of the present disclosure.

Fig. 2A-2E illustrate exemplary cross-sectional views of a semiconductor device 200 at intermediate stages according to some embodiments of the present disclosure. In some embodiments, semiconductor device 200 is the same as semiconductor device 100 except for the details described below.

Referring to fig. 2A, in accordance with some embodiments, after gate dielectric layer 128 is formed over sidewalls of opening 124 (e.g., referring to fig. 1F), channel layer 232 is conformally deposited over conductive lines 110 and gate dielectric layer 128. The channel layer 232 may include materials similar to those described above for the channel layer 132. The channel layer 232 may be formed by ALD or other suitable CVD techniques. The thickness of the channel layer 232 may be about 3nm to about one-third of the thickness T of the gate electrode 118. When the thickness of the channel layer 232 is less than about 3nm, the carrier concentration in the channel layer 232 will be too low and may not generate sufficient drive current to meet the requirements of RRAM, MRAM, or PCRAM.

Referring to fig. 2B, according to some embodiments, the bottom of the channel layer 232 is removed by an anisotropic etching process and the wires 110 are exposed. In one embodiment, the anisotropic etching process includes a RIE process or an IBE process and is configured to etch the channel layer 232 with minimal lateral etching. Referring to fig. 2C, an insulating layer 234 is formed to fill the opening 124, according to some embodiments. The insulating layer 234 may comprise silicon oxide, silicon oxynitride, silicon oxycarbide, low-k dielectric layers, or combinations thereof. Insulating layer 234 may be formed by CVD, PVD, or other suitable methods.

Referring to fig. 2C, portions of gate dielectric layer 128, channel layer 232, and insulating layer 234 over dielectric layer 120 are removed by a planarization process, such as CMP, in accordance with some embodiments, leaving planar top surfaces of gate dielectric layer 128, channel layer 232, insulating layer 234, and dielectric layer 120. In some embodiments, in plan view, both the channel layer 232 and the gate dielectric layer 128 have a ring shape in each opening 124. In plan view, gate dielectric layer 128 and channelLayer 232 may be concentric within opening 124. Thereafter, steps similar to those shown in fig. 1I through 1P are performed, as shown in fig. 2E, to form a memory cell including a memory array formed by memory stack 150 and a transistor array formed by select transistor 290. The selection transistor 290 is similar to the selection transistor 190 except that the selection transistor 290 has a thin channel layer 232, and the channel layer 232 surrounds and surrounds the sidewall of the insulating layer 234 in plan view. Because the channel layer 232 is thin, the gate electrode 118 may provide I to the select transistor 290_offAnd (4) effective control of current.

Fig. 3A-3E illustrate exemplary cross-sectional views of a semiconductor device 300 at intermediate stages according to some embodiments of the present disclosure. In some embodiments, semiconductor device 300 is the same as semiconductor device 100 or 200 except for the details described below.

Referring to fig. 3A, after forming gate dielectric layer 128 over sidewalls of opening 124 (e.g., referring to fig. 1F), electrode material 330 is formed over conductive line 110 and gate dielectric layer 128, in accordance with some embodiments. In some embodiments, the electrode material 330 is deposited by a method that provides relatively poor sidewall coverage (e.g., PVD). For example, the bottom thickness of the electrode material 330 may be 3-20 times its sidewall thickness. Referring to fig. 3B, the sidewall portion of the electrode material 330 is removed by an anisotropic etching process such as an RIE process or an IBE process. The anisotropic etch process may be configured to minimize sidewall redeposition and maximize bottom redeposition, for example, by employing an appropriate tilt angle. In some embodiments, the thickness of the electrode material 330 after removing the sidewall portions is about 0.1nm to about 10 nm. The thickness of the electrode material 330 may be more than half the thickness of the dielectric layer 114. In some embodiments, the electrode material 330 comprises a metallic material. For example, the metallic material may include a titanium-rich material such as TiN.

Referring to fig. 3C, a channel layer 332 is formed over the electrode material 330 and fills the opening 124, according to some embodiments. In some embodiments, the channel material 332 comprises an oxide semiconductor, such as indium oxide (In)₂O₃) Indium Zinc Oxide (IZO), Zinc Tin Oxide (ZTO), Indium Gallium Oxide (IGO), indium tungsten oxide (IWO), Indium Gallium Zinc Oxide (IGZO), tin oxide (SnO)₂) Nickel oxide (NiO), copper oxide (Cu)₂O), zinc oxide (ZnO), and the like, or combinations thereof.

Referring to fig. 3D, portions of the channel layer 332 and the electrode material 330 are removed, according to some embodiments. In some embodiments, portions of the channel layer 332 and portions of the electrode material 330 above the dielectric layer 120 are removed by a planarization process, such as CMP. The channel layer 332 may then be etched by an etching process, and the opening 334 is formed. The opening 334 may be surrounded by the dielectric layer 120.

In some embodiments, the height of the opening 334 is substantially equal to the thickness of the electrode material 330.

Referring to fig. 3E, according to some embodiments, electrode material 338 is formed over channel layer 332 and fills opening 334. In one embodiment, the electrode material 338 overfills the openings 334, and as shown in fig. 3F, the portion of the electrode material 338 above the dielectric layer 120 can be removed by a planarization process, such as CMP. Thereafter, steps similar to those shown in fig. 1I-1P are performed, as shown in fig. 3G, forming a memory cell comprising a memory array formed by memory stack 150 and a transistor array formed by select transistor 390. Select transistor 390 is similar to select transistor 190 except that select transistor 390 includes source/drain electrodes 330 and 338 that are separate from conductive line 110 and bottom electrode 136 a. The channel layer 332 is vertically interposed by the source/drain electrodes 330 and 338 to provide a vertical channel. In some embodiments, the channel layer 332 takes up oxygen diffused from the source/drain electrodes 330 and 338 and absorbed by the source/drain electrodes 330 and 338 such that contact resistance between the channel material and the source/drain electrodes is minimal.

Fig. 4A-4B illustrate exemplary cross-sectional views of a semiconductor device 400 at an intermediate stage, according to some embodiments of the present disclosure. In some embodiments, semiconductor device 400 is the same as semiconductor device 300 except for the details described below.

Referring to fig. 4A, in accordance with some embodiments, after etching channel layer 332 to form opening 334 (e.g., refer to fig. 3D), electrode material 438 is formed over dielectric layer 120 and fills opening 334. Electrode material 438 may include materials similar to those described above for electrode material 338 and may be formed using similar methods. In some embodiments, a planarization process such as CMP is used to reduce the thickness of the electrode material 438 to a desired value and planarize the top surface of the electrode material 438.

Referring to fig. 4B, a memory layer 140 and a top electrode layer 144 are formed over electrode material 438, according to some embodiments. Referring to fig. 4C, the top electrode layer 144, the memory layer 140, and the electrode material 438 are patterned to form individual memory stacks 450, according to some embodiments. In some embodiments, the electrode material 438 has a T-shape in cross-section. For example, the electrode material 438 may have a first portion having substantially the same width as the channel layer 332 and a second portion having substantially the same width as the memory element 140 a. Thereafter, steps similar to those shown in fig. 1L through 1P are performed, as shown in fig. 4D, forming a memory cell comprising a memory array formed by memory stack 450 and a transistor array formed by select transistor 490. Memory stack 450 and select transistor 490 are similar to memory stack 150 and select transistor 390, respectively, except that electrode material 438 has a T-shape in cross-section. The electrode material 438 may serve as both the bottom electrode of the memory stack 450 and the drain electrode of the select transistor 490. The step of fabricating a single bottom electrode for the memory stack may be omitted.

Fig. 5A-5E illustrate exemplary cross-sectional views of semiconductor device 100 at intermediate stages, according to some embodiments of the present disclosure. In some embodiments, semiconductor device 500 is the same as semiconductor device 100, 200, or 300 except for the details described below.

Referring to fig. 5A, according to some embodiments, after gate dielectric layer 128 is formed over the sidewalls of opening 124 (e.g., as shown in fig. 1F), electrode material 530 is deposited over conductive line 110 and gate dielectric layer 128. In some embodiments, the electrode material is deposited by, for example, a method with poor sidewall coverage (e.g., PVD/CV). For example, the bottom thickness of the electrode material 530 may be 3-20 times its sidewall thickness. Referring to fig. 5B, the sidewall portion of the electrode material 530 is removed by an anisotropic etching process such as an RIE process or an IBE process. The anisotropic etch process may be configured to minimize sidewall redeposition and maximize bottom redeposition. In some embodiments, the thickness of the electrode material 530 is about 0.1nm to about 10nm after removing the sidewall portions. For example, the thickness of the electrode material 530 may be more than half the thickness of the dielectric layer 114. In some embodiments, electrode material 530 includes a doped material such as borosilicate glass (BSG) or phosphosilicate glass (PSG).

Referring to fig. 5C, a channel layer 532 is formed over the electrode material 530 and fills the opening 124, according to some embodiments. In some embodiments, the electrode material 532 comprises polysilicon, Ge, SiGe, or a combination thereof. The electrode material 532 may be doped with the opposite type of electrode material 530.

Referring to figure 5D, portions of the channel layer 532 and the electrode material 530 are removed, according to some embodiments. In some embodiments, the portion of channel layer 532 above dielectric layer 120 and the portion of electrode material 530 above dielectric layer 120 are removed by a planarization process, such as CMP. The channel layer 532 may then be etched by an etching process and an opening 534 is formed. The opening 534 may be surrounded by the dielectric layer 120. In some embodiments, the height of opening 534 is substantially equal to the thickness of electrode material 530.

Referring to fig. 5E, an electrode material 538 is formed over channel layer 532 and fills opening 534, in accordance with some embodiments. Electrode material 538 may include a material similar or identical to electrode material 530. In one embodiment, electrode material 538 overfills openings 534 and, as shown in fig. 5F, the portion of electrode material 538 above dielectric layer 120 may be removed by a planarization process, such as CMP. Thereafter, steps similar to those shown in fig. 1I to 1P are performed, and as shown in fig. 5G, a memory cell including a memory array formed by the memory stack 150 and a transistor array formed by the select transistor 590 is formed. Select transistor 590 is similar to select transistor 190 except that select transistor 590 includes source/drain electrodes 530 and 538 separated from conductive line 110 and bottom electrode 136. The channel layer 532 may be vertically interposed by the source/drain electrodes 530 and 538 to provide a vertical channel.

Fig. 6A-6B illustrate exemplary cross-sectional views of a semiconductor device 600 at an intermediate stage, according to some embodiments of the present disclosure. In some embodiments, semiconductor device 600 is the same as semiconductor device 500 except for the details described below.

Referring to fig. 6A, in accordance with some embodiments, after etching channel layer 532 to form opening 534 (e.g., refer to fig. 5D), electrode material 638 is formed over dielectric layer 120 and fills opening 534. Electrode material 638 may include materials similar to those described above for electrode material 538, and may be formed using similar methods. In some embodiments, a planarization process, such as CMP, is used to reduce the thickness of the electrode material 638 to a desired value and planarize the top surface of the electrode material 638.

Referring to fig. 6B, bottom electrode layer 136, memory layer 140, and top electrode layer 144 are formed over electrode material 638, according to some embodiments. Referring to fig. 6C, top electrode layer 144, memory layer 140, bottom electrode layer 136, and electrode material 638 are patterned together, according to some embodiments. In some embodiments, electrode material 638 has a T-shape in cross-section, and memory stack 150 is formed over electrode material 638. Thereafter, steps similar to those shown in fig. 1L to 1P are performed, and as shown in fig. 6C, a memory cell including a memory array formed of the memory stack 150 and a transistor array formed of the select transistor 690 is formed. The selection transistor 690 is similar to the selection transistor 590 except that the drain electrode 638 of the selection transistor 690 has a T-shape. Because the drain electrode 638 of the transistor 690 is patterned with the memory stack 150, the tolerance window for aligning the memory stack 150 to the selector transistor may be increased.

Fig. 7A-7B illustrate exemplary cross-sectional views of a semiconductor device 700 at an intermediate stage, according to some embodiments of the present disclosure. In some embodiments, semiconductor device 700 is the same as semiconductor device 100 except for the details described below. Referring to fig. 7A, after forming the conductive line 110 (e.g., referring to fig. 1B), a conductive via 710 is formed over the conductive line 110. In some embodiments, conductive vias 710 are formed in dielectric layer 712. Conductive via 710 may comprise a material similar to that described above for conductive line 110 and may be formed by a damascene process. Dielectric layer 712 may comprise a material similar to that described above for the ILD layer in which conductive lines 110 are formed, and it may be formed by any suitable CVD technique. The conductive via 710 may provide similar functionality as the conductive line 110 (e.g., source electrode), providing greater flexibility to match the intermetal dielectric height required for certain foundry BEOL processes. Thereafter, steps similar to those shown in fig. 1C to 1P are performed, and as shown in fig. 7B, a memory cell including a memory array formed by the memory stack 150 and a transistor array formed by the select transistor 190 is formed. Conductive via 710 may function as a source line along with conductive line 110. Although the semiconductor device 700 is shown using an integration scheme of the semiconductor device 100, it is understood that the conductive via 710 may be used in semiconductor devices in various embodiments of the present disclosure, including the semiconductor devices 200, 300, 400, 500, and 600 described above.

Fig. 8 illustrates an exemplary cross-sectional view of a semiconductor device 800 at an intermediate stage, according to some embodiments of the present disclosure. In fig. 8, a semiconductor device 800 includes a multi-layer memory cell. Each memory cell is interposed by a dielectric layer 180. Dielectric layer 180 may comprise a material similar to that described above for dielectric layer 154 and may be formed by a similar method. In some embodiments, semiconductor device 800 includes a single type of memory structure. The memory stacks 150, 150', 150 ″ in different layers of the memory array may be the same type of memory, such as RRAM, MRAM, or PCRAM (e.g., having memory elements formed of resistive material, phase change material, or MJT structures). In other embodiments, semiconductor device 800 includes a hybrid memory structure. For example, the memory stacks 150, 150', 150 ″ in different layers of the memory array may include different types of memory, e.g., selected from a combination of RRAM, MRAM, and PCRAM. Although the semiconductor device 800 is shown using an integrated scheme of the semiconductor device 100, it is understood that a single type or hybrid type memory structure of the semiconductor device 800 may be used in various embodiments of the present disclosure, including the semiconductor devices 200, 300, 400, 500, 600, and 700 described above.

In one embodiment, a semiconductor device includes: a substrate; a first conductive line over the substrate and extending along a first direction; a transistor disposed over the first conductive line; and a memory stack disposed over the transistor. The transistor includes: a channel layer; a gate dielectric layer surrounding sidewalls of the channel layer; and a gate electrode surrounding sidewalls of the gate dielectric layer and extending along the second direction.

In one embodiment, a semiconductor device includes: a substrate; a first transistor array over the substrate; a first insulating layer covering the first transistor array; a second transistor array disposed over the first insulating layer; and a first memory stack disposed over and connected to the second transistor array, wherein the transistors of the second transistor array comprise: a first channel layer; a first gate dielectric layer surrounding sidewalls of the first channel layer; and a first gate electrode surrounding sidewalls of the first gate dielectric layer.

In one embodiment, a method comprises: forming a first conductive line over a substrate; forming a gate electrode layer over the first wire; forming an opening in the gate electrode layer; forming a gate dielectric layer over sidewalls of the opening; forming a channel layer over sidewalls of the gate dielectric layer in the opening; forming a memory stack disposed over the channel layer; and separating the gate electrode layer from the gate electrode, wherein the gate electrode surrounds sidewalls of the channel layer.

The foregoing has outlined features of some embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1. a semiconductor device, comprising: a first transistor disposed over a substrate; a second transistor disposed over the first transistor, wherein the second transistor includes: a channel layer; a gate dielectric layer surrounding sidewalls of the channel layer; and a gate electrode surrounding sidewalls of the gate dielectric layer; and a memory element disposed over the second transistor.

Example 2 the semiconductor device according to example 1, wherein the channel layer has a columnar shape.

Example 3 the semiconductor device according to example 1, wherein the channel layer has a ring shape in a plan view.

Example 4 the semiconductor device of example 3, wherein the channel layer surrounds a sidewall of the insulating layer in a plan view.

Example 5 the semiconductor device of example 1, wherein the second transistor further includes a first electrode and a second electrode separated by the channel layer.

Example 6 the semiconductor device of example 5, wherein the first electrode is disposed below the channel layer and includes a wire extending along a first direction.

Example 7 the semiconductor device of example 5, wherein the first electrode is disposed below the channel layer and has sidewalls aligned with sidewalls of the channel layer.

Example 8 the semiconductor device of example 7, wherein each of the first and second electrodes comprises a metallic material or a doped semiconductor material.

Example 9 the semiconductor device of example 5, wherein the second electrode has a portion over the gate dielectric layer and has sidewalls aligned with sidewalls of the memory element.

Example 10 the semiconductor device of example 1, wherein the channel layer includes IGO, ZnO, IGZO, IWO, or a combination thereof.

Example 11 the semiconductor device of example 1, wherein the channel layer comprises polysilicon, Ge, SiGe, or a combination thereof.

Example 12 the semiconductor device according to example 1, wherein the second transistor further includes a spacer surrounding the gate electrode, and wherein the spacer has a ring shape in a plan view.

Example 13 the semiconductor device of example 1, wherein the memory element includes a resistive material, a phase change material, or a magnetic tunnel junction structure.

Example 14. a semiconductor device, comprising: a substrate; a first array of transistors over the substrate; a first insulating layer covering the first transistor array; a second transistor array disposed over the first insulating layer, wherein transistors of the second transistor array include: a first channel layer; a first gate dielectric layer surrounding sidewalls of the first channel layer; and a first gate electrode surrounding sidewalls of the first gate dielectric layer; and a first memory element disposed over and electrically connected to the second transistor array.

Example 15 the semiconductor device of example 14, wherein the first array of transistors includes finfets, surrounding gate FETs, or planar FETs.

Example 16 the semiconductor device of example 14, further comprising: a third transistor array and a second memory element arranged above the first memory element, wherein the second memory element is electrically connected to the third transistor array.

Example 17 the semiconductor device of example 16, wherein the first and second memory elements include different types of memory.

Example 18a method of fabricating a semiconductor device, comprising: forming a first conductive line; forming a gate electrode layer over the first wire; patterning an opening in the gate electrode layer; forming a gate dielectric layer on sidewalls of the opening; forming a channel layer on sidewalls of the gate dielectric layer in the opening; forming a memory element disposed over the channel layer; and patterning the gate electrode layer to define gate electrodes, wherein each of the gate electrodes surrounds a respective sidewall of the channel layer.

Example 19. the method of example 18, wherein the gate dielectric layer and the channel layer completely fill the opening.

Example 20. the method of example 18, further comprising: an insulating layer is formed to fill a remaining portion of the opening after the channel layer is formed.