阅读说明：本技术 磁隧道结结构及集成方案 (Magnetic tunnel junction structure and integration scheme ) 是由 张淑禧 陈福南 N·蒂亚加拉亚 孙永顺 于 2021-05-28 设计创作，主要内容包括：本发明涉及磁隧道结结构及集成方案。提供了一种存储器器件,该存储器器件包括位于电介质层中的接触柱。可以在接触柱上方设置磁隧道结。可以在磁隧道结的侧壁上设置在电介质层的水平表面上方延伸的阻挡层。可以在阻挡层上方设置间隔物。(The invention relates to a magnetic tunnel junction structure and an integration scheme. A memory device is provided that includes a contact pillar in a dielectric layer. A magnetic tunnel junction may be disposed over the contact stud. A barrier layer extending over the horizontal surface of the dielectric layer may be disposed on sidewalls of the magnetic tunnel junction. Spacers may be disposed over the barrier layer.)

1. A memory device, comprising:

a contact post in the dielectric layer;

a magnetic tunnel junction located over the contact pillar;

a barrier layer on sidewalls of the magnetic tunnel junction and extending above a horizontal surface of the dielectric layer; and

a spacer over the barrier layer.

2. The memory device of claim 1, wherein the barrier layer extends over sidewalls of an upper portion of the dielectric layer.

3. The memory device of claim 2, wherein the upper portion of the dielectric layer is located between the barrier layer and the contact pillar.

4. The memory device of claim 1, wherein the barrier layer extends over an upper portion of the contact pillar.

5. The memory device of claim 4, wherein a width of the magnetic tunnel junction is equal to a width of the contact pillar.

6. The memory device of claim 1, wherein the spacers are located on an upper surface and sidewalls of the barrier layer.

7. The memory device of claim 6, wherein the spacers completely cover the upper surface of the barrier layer.

8. The memory device of claim 1, wherein the spacers and the blocking layer completely cover the sidewalls of the magnetic tunnel junction.

9. The memory device of claim 1, further comprising:

a low dielectric constant material covering the spacers and the dielectric layer.

10. The memory device of claim 1, wherein the spacers are made of tetraethyl orthosilicate (TEOS) or silicon nitride.

11. The memory device of claim 9, wherein the low dielectric constant material comprises SiCOH or an ultra-low dielectric constant material.

12. The memory device of claim 1, wherein the dielectric layer comprises TEOS, SiCOH, or silicon nitride.

13. An array of memory devices, comprising:

a first contact pillar and a second contact pillar located in the dielectric layer;

a first magnetic tunnel junction located over the first contact pillar and a second magnetic tunnel junction located over the second contact pillar;

a barrier layer on sidewalls of the first and second magnetic tunnel junctions, wherein the barrier layer extends over a horizontal surface of the dielectric layer; and

a spacer over the barrier layer.

14. The array of memory devices of claim 13, wherein the spacer is located in a gap between the first and second magnetic tunnel junctions.

15. The array of memory devices of claim 14, wherein the spacer completely fills a gap between the first and second magnetic tunnel junctions.

16. The array of memory devices of claim 13, further comprising:

a low dielectric constant material covering the spacers and the dielectric layer.

17. A method of manufacturing a memory device, comprising:

providing a contact post in the dielectric layer;

arranging a magnetic tunnel junction above the contact pillar;

providing a barrier layer on sidewalls of the magnetic tunnel junction and above a horizontal surface of the dielectric layer; and

a spacer is disposed over the barrier layer.

18. The method of claim 17, further comprising:

patterning the dielectric layer using the magnetic tunnel junction as a masking layer to leave a portion of the dielectric layer under the magnetic tunnel junction.

19. The method of claim 18, wherein disposing the blocking layer on sidewalls of the magnetic tunnel junction and above horizontal surfaces of the dielectric layer further comprises:

disposing the blocking layer over the portion of the dielectric layer below the magnetic tunnel junction.

20. The method of claim 17, wherein disposing a spacer over the barrier layer further comprises:

forming a dielectric spacer material over the barrier layer;

patterning the dielectric spacer material to leave a portion of the dielectric spacer material over the sidewalls of the magnetic tunnel junction and the horizontal surface of the dielectric layer.

Technical Field

The disclosed embodiments relate generally to Magnetic Tunnel Junction (MTJ) devices and, more particularly, to MTJ devices with high density and integration schemes thereof.

Background

Magnetoresistive Random Access Memory (MRAM) devices include MTJs whose resistance can be adjusted to represent a logic state "0" or "1". An MTJ includes two ferromagnetic layers, each of which may have a magnetic moment, separated by an insulating layer. One of the two layers can be pinned by an antiferromagnetic layer (hereinafter referred to as "fixed layer") set to a specific polarity. The polarization of the other layer (hereinafter "free layer") can be changed by a specific current direction or by applying a sufficiently strong external magnetic field. If the two layers have the same polarization, the resistance of the MTJ will be lower, and if the two layers have opposite polarizations, the resistance will be higher.

As integrated circuits continue to shrink, it becomes increasingly difficult to isolate adjacent MTJ stacks in MRAM devices. The space between adjacent MTJ stacks may be filled with a dielectric material. However, since the gap-fill problem may affect the upper metallization level, it may not be effective to fill the smaller and smaller spaces between adjacent MTJ stacks. Accordingly, there is a significant need for an improved MRAM device that overcomes the above-mentioned challenges.

Disclosure of Invention

In an aspect of the present disclosure, a memory device is provided. The memory device includes a contact pillar in a dielectric layer. A magnetic tunnel junction may be disposed over the contact pillar. A barrier layer (barrier layer) extending over the horizontal surface of the dielectric layer may be disposed on sidewalls of the magnetic tunnel junction. Spacers may be disposed over the barrier layer.

In another aspect of the present disclosure, there is provided an array of memory devices, the array comprising: a first contact stud and a second contact stud located in the dielectric layer. A first magnetic tunnel junction may be disposed over the first contact pillar and a second magnetic tunnel junction may be disposed over the second contact pillar. A blocking layer may be disposed on sidewalls of the first and second magnetic tunnel junctions. The barrier layer may extend over a horizontal surface of the dielectric layer. Spacers may be disposed over the barrier layer.

In yet another aspect of the present disclosure, a method of fabricating a memory device is provided that includes providing a contact pillar in a dielectric layer. A magnetic tunnel junction may be disposed over the contact pillar. A barrier layer may be disposed on sidewalls of the magnetic tunnel junction and above a horizontal surface of the dielectric layer. Spacers may be disposed over the barrier layer.

Many advantages can be obtained from the embodiments described below. These memory devices eliminate the gap-fill problem between adjacent MTJ stacks in high density MRAM arrays, thereby improving the fabrication and reliability of the devices. Embodiments are compatible with back end of line (BEOL) manufacturing of logic devices and make logic devices faster due to reduced resistance-capacitance (RC) delay.

Drawings

The disclosed embodiments will be better understood from a reading of the following detailed description taken in conjunction with the drawings in which:

fig. 1A is a cross-sectional view of an array of memory devices according to an embodiment of the present disclosure.

Fig. 1B is an enlarged view of a portion of a memory device array circled by a dashed line in accordance with an embodiment of the present disclosure.

Fig. 1C is a cross-sectional view of a metallization structure in a corresponding logic device, in accordance with embodiments of the present disclosure.

Fig. 2A-7A illustrate a fabrication process flow of the memory device array shown in fig. 1A according to an embodiment of the disclosure.

Fig. 2B-7B illustrate a fabrication process flow of a metallization structure in the respective logic device shown in fig. 1C, in accordance with embodiments of the present disclosure.

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and specific descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the embodiments of the devices described. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the devices. The same reference numbers in different drawings identify the same elements, and similar reference numbers may, but do not necessarily, identify similar elements.

Detailed Description

The following detailed description is exemplary in nature and is not intended to limit the device or the application and uses of the device. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the devices or the following detailed description.

Fig. 1A is a cross-sectional view of an array 108 of memory devices according to an embodiment of the present disclosure. In an embodiment, the memory device array 108 may be an MRAM array. Referring to fig. 1A, the memory device array 108 may include a dielectric layer 128 having a first portion 128a and a second portion 128b immediately adjacent to the first portion 128 a. The first and second contact pillars 132 and 136 may be formed in the second portion 128b of the dielectric layer. The first magnetic tunnel junction 148 may be formed over the first contact pillar 132 and the second magnetic tunnel junction 158 may be formed over the second contact pillar 136. The blocking layer 142 may be formed on sidewalls of the first and second magnetic tunnel junctions 148 and 158. The barrier layer 142 may extend over a horizontal surface of the second portion 128b of the dielectric layer. The spacers 138 may cover the barrier layer 142. The spacer 138 covering the barrier layer 142 may be located in a gap between the first magnetic tunnel junction 148 and the second magnetic tunnel junction 158. In an embodiment, the spacer 138 covering the barrier layer 142 may completely fill the gap between the first magnetic tunnel junction 148 and the second magnetic tunnel junction 158. A low dielectric constant material 150 may be formed over the spacers 138 and barrier layer 142. The low dielectric constant material 150 may be made of a carbon doped oxide dielectric or an ultra low dielectric constant material including silicon, carbon, oxygen, and hydrogen or SiCOH. The term "low dielectric constant material" may refer to a dielectric material having a dielectric constant less than 3.9. The term "ultra-low dielectric constant material" may refer to a dielectric material having a dielectric constant less than 2.5 and a porosity greater than 5%.

The barrier layer 142 may extend over sidewalls of an upper portion of the second portion 128b of the dielectric layer. An upper portion of the second portion 128b of the dielectric layer may be located between the barrier layer 142 and the first contact stud 132 and between the barrier layer 142 and the second contact stud 136. Dielectric layer 128 may be made of tetraethyl orthosilicate (TEOS), SiCOH, or silicon nitride. In further embodiments, barrier layer 142 may extend over upper portions of first contact pillar 132 and second contact pillar 136. Spacers 138 may be located on the upper surface and sidewalls of barrier layer 142. The upper surface of the barrier layer 142 may extend above the horizontal surface of the second portion 128b of the dielectric layer. In an embodiment, the spacers 138 may completely cover the upper surface of the barrier layer 142. The spacers 138 and the blocking layer 142 may completely cover sidewalls of the first magnetic tunnel junction 148 and the second magnetic tunnel junction 158. The barrier layer 142 may be made of silicon nitride, an oxygen-free dielectric material, or any other suitable dielectric material. The spacers 138 may be made of TEOS or silicon nitride.

A first upper metallization layer 152 may be formed over the first magnetic tunnel junction 148 and a second upper metallization layer 156 may be formed over the second magnetic tunnel junction 158. The first upper metallization layer 152 and the second upper metallization layer 156 may be formed in the low dielectric constant material 150.

The NBloK layer 126 may surround a lower portion of the first contact pillar 132 and a lower portion of the second contact pillar 136. NBloK layer 126 may be formed between dielectric layer 128 and low dielectric constant material 112. The first and second lower metallization layers 116, 118 may be formed in the low dielectric constant material 112 and in contact with the bottom of the first and second contact pillars 132, 136, respectively.

Fig. 1B is an enlarged view of a portion of the memory device array 108 circled by a dashed line in accordance with an embodiment of the present disclosure. Referring to fig. 1B, the first magnetic tunnel junction 148 may include a bottom electrode layer 180 located over the first contact pillar 132. Although not shown, an antiferromagnetic layer may be formed over the bottom electrode layer 180. A ferromagnetic pinned layer 178 may be formed over the bottom electrode layer 180 or the antiferromagnetic layer. An insulating layer 176 may be formed over the ferromagnetic pinned layer 178. A ferromagnetic free layer 172 may be formed over the insulating layer 176. A capping layer 170 may be formed over the ferromagnetic free layer 172. A top electrode layer 168 may be formed over the cap layer 170.

Fig. 1C is a cross-sectional view of a metallization structure in a respective logic device 110, in accordance with an embodiment of the present disclosure. The same reference numbers used in fig. 1A and 1B may be used in fig. 1C to indicate the same features. Referring to fig. 1C, metallization structures in the respective logic devices 110 may be fabricated simultaneously with the memory device array 108. Referring to fig. 1C, the metallization structure in the respective logic device 110 may include a contact pillar 162, a lower portion of the contact pillar 162 being surrounded by the first portion 128a of the dielectric layer. The upper portion of the contact pillar 162 and the upper metallization layer 166 over the contact pillar 162 may be surrounded by the low dielectric constant material 150. The low dielectric constant material 150 may cover an upper surface of the first portion 128a of the dielectric layer.

The lower metallization layer 122 may be in contact with the bottom of the contact pillar 162. The lower metallization layer 122 may be formed in the low dielectric constant material 112. NBloK layer 126 may be formed over low dielectric constant material 112 and lower metallization layer 122 and under first portion 128a of the dielectric layer. NBloK layer 126 may serve as an etch stop layer during the via (via) etch for contact pillars 132, 136 and 162. The NBloK layer 126 may be replaced by a nitride layer or silicon carbon nitride (SiCN).

Fig. 2A-7A illustrate a fabrication process flow of the memory device array 108 shown in fig. 1A, according to an embodiment of the disclosure. Fig. 2B-7B illustrate a fabrication process flow of the metallization structure in the respective logic device 110 shown in fig. 1C, in accordance with an embodiment of the present disclosure.

Fig. 2A is a cross-sectional view of a partially completed array of memory devices 108 according to an embodiment of the present disclosure. Referring to fig. 2A, a first lower metallization layer 116 and a second lower metallization layer 118 may be formed in the low dielectric constant material 112. An NBLoK layer 126 may be formed over the low dielectric constant material 112, the first lower metallization layer 116, and the second lower metallization layer 118. A dielectric layer 128 may be formed over the NBLoK layer 126. First and second contact pillars 132, 136 may be formed in the dielectric layer 128 and the NBLoK layer 126. In an embodiment, the first and second contact pillars 132, 136 may have a height substantially equal to a height of the dielectric layer 128. The bottom of the first and second contact pillars 132, 136 may be located above the first and second lower metallization layers 116, 118, respectively.

Fig. 2B is a cross-sectional view of a partially completed metallization structure in a respective logic device 110, in accordance with an embodiment of the present disclosure. Referring to fig. 2B, a lower metallization layer 122 may be formed in the low dielectric constant material 112. An NBLoK layer 126 may be formed over the lower metallization layer 122 and the low dielectric constant material 112. A dielectric layer 128 may be formed over the NBLoK layer 126.

FIG. 3A is a cross-sectional view of a partially completed memory device array after forming a magnetic tunnel junction according to an embodiment of the present disclosure. Referring to fig. 3A, a first magnetic tunnel junction 148 may be formed over the first contact pillar 132, and a second magnetic tunnel junction 158 may be formed over the second contact pillar 136. The formation of the first magnetic tunnel junction 148 and the second magnetic tunnel junction 158 is well known in the art and will not be described in further detail herein. In an embodiment, the magnetic tunnel junctions 148 and 158 may have a width x that is greater than or equal to the width y of the contact pillars 132 and 136, respectively. The first magnetic tunnel junction 148 and the second magnetic tunnel junction 158 may be used as a masking layer to remove an upper portion of the dielectric layer 128. The removal process may be a dry etch or a wet etch process. The removal process may leave a portion of the upper portion of the dielectric layer 128 below the first and second magnetic tunnel junctions 148 and 158 and around the upper portions of the first and second contact pillars 132 and 136. In further embodiments, the removal process may completely remove an upper portion of the dielectric layer 128 to expose upper portions of the first and second contact pillars 132, 136. In an embodiment, the removal process may leave a lower portion of the dielectric layer 128 surrounding the lower portions of the first and second contact pillars 132, 136 and extending horizontally over the NBLoK layer 126.

Fig. 3B is a cross-sectional view of a partially completed metallization structure in a respective logic device 110 after removing an upper portion of the dielectric layer 128, in accordance with an embodiment of the present disclosure. Referring to fig. 3B, the removal process may leave a lower portion of the dielectric layer 128 extending horizontally over the NBLoK layer 126.

Fig. 4A is a cross-sectional view of a partially completed memory device array 108 after forming a barrier layer 142 and a dielectric spacer material 146, according to an embodiment of the disclosure. Referring to fig. 4A, a barrier layer 142 may be deposited over sidewalls and top surfaces of the first and second magnetic tunnel junctions 148 and 158, over sidewalls of an upper portion of the dielectric layer 128, and over a horizontal surface of a lower portion of the dielectric layer 128. In further embodiments, a barrier layer 142 may be deposited over upper portions of the first and second contact pillars 132, 136. A layer of dielectric spacer material 146 may be deposited over the barrier layer 142. The deposition process for the barrier layer 142 and the dielectric spacer material 146 may be Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or any other suitable deposition process.

Fig. 4B is a cross-sectional view of a partially completed metallization structure in a corresponding logic device 110 after forming a barrier layer 142, in accordance with an embodiment of the present disclosure. A barrier layer 142 may be deposited over horizontal surfaces of the dielectric layer 128. A layer of dielectric spacer material 146 may be deposited over the barrier layer 142.

Fig. 5A is a cross-sectional view of a partially completed array of memory devices 108 after forming spacers 138, in accordance with an embodiment of the present disclosure. Referring to fig. 5A, forming spacers 138 over barrier layer 142 may include: a first portion of the layer of dielectric spacer material 146 is removed from the top surface of the first magnetic tunnel junction 148 and the top surface of the second magnetic tunnel junction 158 and the horizontal surface of the first portion 128a of the dielectric layer. The removal process may be an anisotropic etch. The term "anisotropic etch" may refer to an etch process that removes material in a particular direction. The removal process may leave a second portion of the layer of dielectric spacer material 146 over sidewalls of the first and second magnetic tunnel junctions 148 and 158 and over horizontal surfaces of the second portion 128b of the dielectric layer, forming the spacers 138.

Fig. 5B is a cross-sectional view of a partially completed metallization structure in a respective logic device 110 after removal of a first portion of the layer of dielectric spacer material 146, in accordance with an embodiment of the present disclosure. Referring to fig. 5B, the removal process may leave the barrier layer 142 on the horizontal surface of the first portion 128a of the dielectric layer.

Fig. 6A is a cross-sectional view of a partially completed memory device array 108 after removing a first portion of the barrier layer 142 from horizontal surfaces of the first portion 128a of the dielectric layer and top surfaces of the first and second magnetic tunnel junctions 148 and 158 according to an embodiment of the present disclosure. The removal process may be a wet etch or a dry etch and may leave a second portion of the barrier layer 142 on sidewalls of the first and second magnetic tunnel junctions 148 and 158 and above horizontal surfaces and sidewalls of the second portion 128b of the dielectric layer. In further embodiments, the removal process may leave a second portion of barrier layer 142 over upper portions of first contact pillar 132 and second contact pillar 136.

Fig. 6B is a cross-sectional view of a partially completed metallization structure in a respective logic device 110 after removing a first portion of the barrier layer 142 from horizontal surfaces of the first portion 128a of the dielectric layer, in accordance with an embodiment of the present disclosure. The removal process may leave a first portion 128a of the dielectric layer over the NBLoK layer 126.

Fig. 7A is a cross-sectional view of the memory device array 108 after forming a layer of low dielectric constant material 150, in accordance with an embodiment of the present disclosure. Referring to fig. 7A, a layer of low dielectric constant material 150 may be deposited over the spacers 138, the first magnetic tunnel junction 148, the second magnetic tunnel junction 158, and the dielectric layer 128. The deposition process may be CVD, ALD, PVD or any other suitable deposition process. A first upper metallization layer 152 may be formed over the first magnetic tunnel junction 148 and a second upper metallization layer 156 may be formed over the second magnetic tunnel junction 158. A first upper metallization layer 152 and a second upper metallization layer 156 may be formed in the low dielectric constant material 150. The formation of the first upper metallization layer 152 and the second upper metallization layer 156 is well known in the art and will not be described in further detail herein.

Fig. 7B is a cross-sectional view of a metallization structure in a corresponding logic device 110 after forming a layer of low dielectric constant material 150, in accordance with an embodiment of the present disclosure. Referring to fig. 7B, a layer of low dielectric constant material 150 may be deposited over the first portion 128a of the dielectric layer. Contact pillars 162 may be formed in the layer of low dielectric constant material 150, the first portion 128a of the dielectric layer, and the NBLoK layer 126. The bottom of the contact pillar 162 may be located on the lower metallization layer 122. An upper metallization layer 166 may be formed over the top surface of the contact pillar 162. The formation of contact pillars 162 and upper metallization layer 166 is well known in the art and will not be described in further detail herein.

The terms first, second, third and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes only and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Similarly, if a method described herein includes a series of steps, the order in which those steps are presented herein is not necessarily the only order in which those steps may be performed, certain ones of the steps may be omitted, and/or certain other steps not described herein may be added to the method. Furthermore, the terms "comprises," "comprising," "includes," "including," "has," "having," and any variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

While several exemplary embodiments have been presented in the foregoing detailed description of the devices, it should be appreciated that a vast number of variations exist. It should be further understood that the embodiments are merely examples, and are not intended to limit the scope, applicability, size, or configuration of the device in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment and method of manufacturing the same without departing from the scope of the disclosure as set forth in the appended claims.