阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 郑有宏 张煜群 李静宜 李汝谅 于 2021-07-02 设计创作，主要内容包括：本文公开了用于高压绝缘体上半导体器件的深沟槽隔离结构。示例性深沟槽隔离结构围绕绝缘体上半导体衬底的有源区域。深沟槽隔离结构包括第一绝缘体侧壁间隔件、第二绝缘体侧壁间隔件以及设置在第一绝缘体侧壁间隔件和第二绝缘体侧壁间隔件之间的多层含硅隔离结构。多层含硅隔离结构包括设置在底部硅部分上方的顶部多晶硅部分。底部多晶硅部分由选择性沉积工艺形成,而顶部多晶硅部分由非选择性沉积工艺形成。在一些实施例中,底部硅部分掺杂有硼。本发明的实施例还涉及半导体器件及其形成方法。(Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multi-layer silicon-containing isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multi-layer silicon-containing isolation structure includes a top polysilicon portion disposed above a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process and the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron. Embodiments of the invention also relate to semiconductor devices and methods of forming the same.)

1. A semiconductor device, comprising:

a semiconductor-on-insulator substrate comprising a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, and an insulator layer disposed between the first semiconductor layer and the second semiconductor layer; and

an isolation structure surrounding an active region of the semiconductor-on-insulator substrate, wherein the isolation structure extends through the second semiconductor layer and the insulator layer of the semiconductor-on-insulator substrate to the first semiconductor layer of the semiconductor-on-insulator substrate, and wherein the isolation structure comprises:

a first insulator sidewall spacer having a first sidewall spacer,

a second insulator sidewall spacer, and

a multi-layer silicon-containing isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer, wherein the multi-layer silicon-containing isolation structure comprises a top polysilicon portion disposed above a bottom silicon portion.

2. The semiconductor device of claim 1, wherein the top polysilicon portion has a first thickness, the bottom silicon portion has a second thickness, a sum of the first thickness and the second thickness is equal to a depth of the isolation structure in the semiconductor-on-insulator substrate, and the second thickness is greater than the first thickness.

3. The semiconductor device of claim 1, wherein the bottom silicon portion comprises a dopant and the top polysilicon portion is free of a dopant.

4. The semiconductor device of claim 1, wherein the bottom silicon portion comprises a first silicon layer and a second silicon layer, the first silicon layer having a first dopant concentration, the second silicon layer having a second dopant concentration, the first silicon layer disposed between the top polysilicon portion and the second silicon layer, and the first dopant concentration being less than the second dopant concentration.

5. The semiconductor device of claim 1, wherein the top polysilicon portion has a graded dopant concentration that decreases from a first dopant concentration at an interface of the top polysilicon portion and the bottom silicon portion to a second dopant concentration at a top surface of the top polysilicon portion.

6. The semiconductor device of claim 5, wherein a topmost surface of the top polysilicon portion is free of dopants.

7. The semiconductor device of claim 1, wherein the top polysilicon portion has a tapered width.

8. The semiconductor device of claim 1, wherein the bottom silicon portion has a first portion having a first tapered width, a second portion having a uniform width, and a third portion having a second tapered width, wherein the second portion is disposed between the first portion and the third portion.

9. A semiconductor device, comprising:

a silicon-on-insulator substrate having a first silicon layer, an insulator layer disposed over the first silicon layer, and a second silicon layer disposed over the insulator layer;

a first isolation structure disposed in the silicon-on-insulator substrate, wherein the first isolation structure extends to a first depth in the silicon-on-insulator substrate; and

a second isolation structure disposed in the silicon-on-insulator substrate, wherein the second isolation structure extends through the first isolation structure to a second depth in the silicon-on-insulator substrate, the second depth being greater than the first depth, wherein the second isolation structure comprises a blanket layer of polysilicon disposed over a silicon layer, and wherein a sum of a first thickness of the blanket layer of polysilicon and a second thickness of the silicon layer is equal to the second depth of the second isolation structure.

10. A method of forming a semiconductor device, comprising:

receiving a semiconductor-on-insulator substrate comprising a first semiconductor layer, an insulator layer disposed over the first semiconductor layer, and a second semiconductor layer disposed over the insulator layer;

forming an isolation trench in the semiconductor-on-insulator substrate, wherein the isolation trench extends through the second semiconductor layer and the insulator layer to expose the second semiconductor layer of the semiconductor-on-insulator substrate;

performing a selective deposition process to form a silicon layer filling the bottom of the isolation trench; and

a non-selective deposition process is performed to form a polysilicon layer that fills the top of the isolation trench.

Technical Field

Embodiments of the invention relate to semiconductor devices and methods of forming the same.

Background

The Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in generations of ICs, each of which has smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) generally increases, while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) decreases. Such a scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

This scaling down also increases the complexity of handling and manufacturing the IC. For example, crosstalk has become a significant challenge as more IC devices, circuits, and/or systems having multiple functions are densely packed on a single substrate to meet advanced IC technology requirements. Typically, crosstalk is caused by capacitive, inductive, and/or conductive coupling between IC devices and/or IC components on the same substrate. Semiconductor-on-insulator (SOI) technology has been employed to improve isolation and suppress cross-talk between IC devices and/or IC components. In SOI technology, IC devices are fabricated on semiconductor-insulator-semiconductor substrates, such as silicon-oxide-silicon substrates, rather than bulk semiconductor substrates. Additional isolation structures, such as shallow trench isolation structures and/or deep trench isolation structures, are often further incorporated into the SOI substrate to further improve isolation and suppress crosstalk. While existing isolation structures employed in SOI substrates have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects and have required improvements as IC technology scales.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device including: a semiconductor-on-insulator substrate comprising a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, and an insulator layer disposed between the first semiconductor layer and the second semiconductor layer; and an isolation structure surrounding an active region of the semiconductor-on-insulator substrate, wherein the isolation structure extends through the second semiconductor layer and the insulator layer of the semiconductor-on-insulator substrate to the first semiconductor layer of the semiconductor-on-insulator substrate, and wherein the isolation structure comprises: a first insulator sidewall spacer, a second insulator sidewall spacer, and a multi-layer silicon-containing isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer, wherein the multi-layer silicon-containing isolation structure comprises a top polysilicon portion disposed above a bottom silicon portion.

Another embodiment of the present invention provides a semiconductor device including: a silicon-on-insulator substrate having a first silicon layer, an insulator layer disposed over the first silicon layer, and a second silicon layer disposed over the insulator layer; a first isolation structure disposed in the silicon-on-insulator substrate, wherein the first isolation structure extends to a first depth in the silicon-on-insulator substrate; and a second isolation structure disposed in the silicon-on-insulator substrate, wherein the second isolation structure extends through the first isolation structure to a second depth in the silicon-on-insulator substrate, the second depth being greater than the first depth, wherein the second isolation structure comprises a blanket layer of polysilicon disposed over a silicon layer, and wherein a sum of a first thickness of the blanket layer of polysilicon and a second thickness of the silicon layer is equal to the second depth of the second isolation structure.

Yet another embodiment of the present invention provides a method of forming a semiconductor device, including: receiving a semiconductor-on-insulator substrate comprising a first semiconductor layer, an insulator layer disposed over the first semiconductor layer, and a second semiconductor layer disposed over the insulator layer; forming an isolation trench in the semiconductor-on-insulator substrate, wherein the isolation trench extends through the second semiconductor layer and the insulator layer to expose the second semiconductor layer of the semiconductor-on-insulator substrate; performing a selective deposition process to form a silicon layer filling the bottom of the isolation trench; and performing a non-selective deposition process to form a polysilicon layer filling the top of the isolation trench.

Drawings

The invention is best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 depicts a partial cross-sectional view of the fabrication of part or all of three different polysilicon isolation features that may be integrated into a semiconductor-on-insulator substrate, in accordance with various aspects of the present invention.

Fig. 2 depicts a partial cross-sectional view of the fabrication of a portion or the entirety of a silicon-containing isolation feature that may be integrated into a semiconductor-on-insulator substrate, in accordance with various aspects of the present invention.

Fig. 3 depicts a log-linear plot correlating log defect density to etch/deposition ratio, in accordance with various aspects of the present invention.

Fig. 4A is a partial top view of a portion or the entirety of an isolation feature of an Integrated Circuit (IC) device according to various aspects of the present invention.

Fig. 4B is a partial cross-sectional view of a portion or the entirety of an isolation feature of the IC device of fig. 4A, in accordance with various aspects of the present invention.

Fig. 5 is a schematic cross-sectional view of a portion or the entirety of another isolation feature of an IC device according to aspects of the present invention.

Fig. 6 is a schematic cross-sectional view of a portion or the entirety of another isolation feature of an IC device according to aspects of the present invention.

Fig. 7 is a schematic cross-sectional view of a portion or the entirety of another isolation feature of an IC device according to aspects of the present invention.

Fig. 8 is a schematic cross-sectional view of a portion or the entirety of another isolation feature of an IC device according to aspects of the present invention.

Fig. 9 is a partial top view of a portion or the entirety of another isolation feature of an IC device according to various aspects of the present invention.

Detailed Description

The present invention relates generally to integrated circuit devices, and more particularly to isolation structures for integrated circuit devices, such as deep trench isolation structures for high voltage silicon-on-insulator devices.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, to facilitate describing the relationship of one element to another element of the invention, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "under," "upward," "downward," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are used. Spatially relative terms are intended to encompass different orientations of the device including the component. Further, when values or ranges of values are described with "about", "approximately", etc., the terms are intended to encompass the values within a reasonable range, taking into account variations that inherently occur during manufacture as understood by those of ordinary skill in the art. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having the characteristics associated with the value. For example, a material layer having a thickness of "about 5 nm" may encompass a dimensional range from 4.5nm to 5.5nm, where the manufacturing tolerances associated with depositing the material layer are known to one of ordinary skill in the art to be +/-10%. Still further, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the embodiments and/or configurations discussed.

Crosstalk is caused by capacitive, inductive, and/or conductive coupling between Integrated Circuit (IC) devices and/or IC components on the same substrate. Semiconductor-on-insulator (SOI) technology has been employed to improve isolation and suppress cross-talk between IC devices and/or IC components. In SOI technology, IC devices are fabricated on semiconductor-insulator-semiconductor substrates, such as silicon-oxide-silicon substrates, rather than bulk semiconductor substrates. Additional isolation structures, such as shallow trench isolation Structures (STI) and/or deep trench isolation structures (DTI), are often further incorporated into the SOI substrate to further improve isolation and suppress crosstalk. Fig. 1 depicts a partial cross-sectional view of the fabrication of part or all of three different polysilicon DTIs that may be integrated into an SOI substrate, in accordance with various aspects of the present invention. In fig. 1, fabrication of each polysilicon DTI begins with receiving an SOI substrate 10 (including, for example, an insulator layer 12 disposed between a semiconductor layer 14 and a semiconductor layer 16) and forming a patterned layer 20 over the SOI substrate 10, where the patterned layer 20 has an opening therein that exposes a portion of the SOI substrate 10. The patterned layer 20 may include a pad layer and a mask layer, where the pad layer is disposed on the semiconductor layer 14 and the mask layer is disposed on the pad layer. In some embodiments, the liner layer comprises silicon and oxygen, and the mask layer comprises silicon and nitrogen. For example, the liner layer is a silicon oxide layer formed by thermal oxidation and/or other suitable processes, and the mask layer is a silicon nitride layer or a silicon oxynitride layer formed by Chemical Vapor Deposition (CVD), low pressure CVD (lpcvd), plasma enhanced CVD (pecvd), thermal nitridation (e.g., thermal nitridation of silicon), other suitable processes, or combinations thereof. In some embodiments, the pad layer comprises a material that can promote adhesion between the SOI substrate 105 and the mask layer and can further serve as an etch stop layer when the mask layer is removed. The present invention contemplates other materials and/or methods for forming the pad layer and/or the mask layer.

Openings are formed in the mask layer and the pad layer by performing a photolithography process to form a patterned photoresist layer over the patterned layer 20 and performing an etching process to transfer a pattern formed in the patterned photoresist layer to the patterned layer 20. The photolithography process may include forming a photoresist layer on the mask layer (e.g., by spin coating), performing a pre-exposure bake process, performing an exposure process using the mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiant energy, such as Ultraviolet (UV), Deep Ultraviolet (DUV), or Extreme Ultraviolet (EUV) light, wherein depending on the mask pattern and/or mask type of the mask (e.g., binary mask, phase-shift mask, or EUV mask), the mask blocks, transmits, and/or reflects the radiation to the photoresist layer such that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiant energy, the exposed portions of the photoresist layer chemically change and, depending on the characteristics of the photoresist layer and the characteristics of the developer solution used in the development process, the exposed (or unexposed) portions of the photoresist layer dissolve during the development process. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the mask. The etching process uses the patterned photoresist layer as an etch mask to remove portions of the mask layer and the pad layer to form openings that extend through the patterned layer 20. The etching process may include a dry etching process (e.g., a Reactive Ion Etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof. After the etching process, the patterned photoresist layer may be removed, for example, by a photoresist stripping process. Alternatively, the exposure process may employ maskless lithography, electron beam writing, and/or ion beam writing.

An isolation trench etching process is then performed using the patterned layer 20 as an etch mask to form an isolation trench 30 in the SOI substrate 10. The portion of SOI substrate 10 exposed by the opening in patterned layer 20 is removed by an isolation trench etch process such that isolation trench 30 extends through semiconductor layer 14 and insulator layer 12 to expose semiconductor layer 16. Isolation trench 30 has sidewalls 32 formed from semiconductor layer 14 and insulator layer 12, sidewalls 34 formed from semiconductor layer 14 and insulator layer 12, and a bottom 36 formed from semiconductor layer 16. In fig. 1, the isolation trench etch process slightly etches the semiconductor layer 16 such that the bottom 36 is formed by a concave curved surface of the semiconductor layer 16 that extends below a topmost surface 38 of the semiconductor layer 16. Isolation trenches 30 are high aspect ratio trenches, which generally refers to trenches having one dimension that is significantly larger than another. For example, the isolation trench 30 has a depth defined along the z-direction and a width w defined along the x-direction, wherein the depth d is significantly greater than the width w. In some embodiments, the ratio of the depth d to the width w is greater than about 5. The isolation trench etch process is a dry etch process, a wet etch process, or a combination thereof.

Fabrication then continues with the deposition of an oxide layer 40 over the SOI substrate 10 and the patterned layer 20, wherein the oxide layer 40 partially fills the isolation trench 30. After deposition, oxide layer 40 covers patterned layer 20 and further covers sidewalls 32, sidewalls 34, and bottom 36 of isolation trench 30. An etch process is then performed to remove the oxide layer 40 from the bottom 36 of the isolation trench 30. After the etching process, the oxide layer 40 covers the sidewalls 32 and 34 of the isolation trench 30, but does not cover portions of the bottom 36 of the isolation trench 30. Any suitable deposition process for forming oxide layer 40 is performed, such as CVD, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), high density plasma CVD (hdpcvd), metal organic CVD (mocvd), remote plasma CVD (rpcvd), rapid thermal CVD (rtcvd), PECVD, plasma enhanced ALD (peald), LPCVD, atomic layer CVD (alcvd), atmospheric pressure CVD (apcvd), other suitable methods, or combinations thereof. In the depicted embodiment, the oxide layer 40 is formed by a high aspect ratio deposition process (HARP), such as HDPCVD. HARP generally refers to a deposition process that is capable of adequately filling high aspect ratio structures, such as high aspect ratio trenches, such as isolation trench 30. The etching process is an anisotropic etching process, typically referring to an etching process having different etch rates in different directions, such that the etching process removes material in a particular direction, such as substantially in one direction. For example, the etch has a vertical etch rate that is greater than the horizontal etch rate (in some embodiments, the horizontal etch rate is equal to zero). Thus, the anisotropic etch process removes material substantially in the vertical direction (here, the z-direction) with minimal (or no) material removal in the horizontal direction (here, the x-direction and/or the y-direction). In such embodiments, the anisotropic etch does not remove or minimally removes the oxide layer 40 covering the sidewalls 32 and 34 of the isolation trenches 30, and may partially or completely remove the oxide layer 40 covering the patterned layer 20. In some embodiments, such as depicted in fig. 1, the thickness of the oxide layer 40 at the upper corners of the isolation trenches 30 is slightly reduced by an anisotropic etch process. In some embodiments, the thickness of the oxide layer 40 overlying the patterned layer 20 is reduced by an anisotropic etching process. The anisotropic etching process may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching process is a dry etching process, such as a Reactive Ion Etching (RIE) process.

Fabrication may then continue with process a to form polysilicon DTI 50A, process B to form polysilicon DTI50B, or process C to form polysilicon DTI 50C. Process a includes depositing a polysilicon layer 52A on the oxide layer 40 to fill the remaining portions of the isolation trenches 30 and performing a planarization process to remove portions of the polysilicon layer 52A disposed on the oxide layer 40 such that a top surface of the polysilicon layer 52A and a top surface of the oxide layer 40 are substantially planar. A planarization process (or continued planarization process) is then performed to remove the portion of oxide layer 40 disposed over patterned layer 20 such that the top surface of polysilicon layer 52A, the top surface of oxide layer 40, and the top surface of patterned layer 20 are substantially planar. Thereafter, the patterned layer 20 is removed from above the SOI substrate 10. Thus, the polysilicon DTI 50A has oxide sidewalls 40-1 (i.e., the remaining portion of the oxide layer 40 disposed along the sidewalls 32 of the isolation trenches 30), oxide sidewalls 40-2 (i.e., the remaining portion of the oxide layer disposed along the sidewalls 34 of the isolation trenches 30), and a polysilicon layer 52A disposed between the oxide sidewalls 40-1 and the oxide sidewalls 40-2. The polysilicon layer 52A is in physical contact with the semiconductor layer 16 of the SOI substrate 10. Polysilicon layer 52A comprises polysilicon, also referred to as polycrystalline silicon or polycrystalline silicon. Polycrystalline silicon generally comprises a plurality of silicon grains (crystals) separated by grain boundaries (i.e., monocrystalline silicon grains, which may be randomly oriented and have different crystal orientations).

In process a, the polysilicon layer 52A is formed by a non-selective deposition process, which generally refers to a deposition process that indiscriminately forms material over various surfaces, such as dielectric surfaces, semiconductor surfaces, and metal surfaces. For example, the polysilicon layer 52A is formed by CVD, HDPCVD, LPCVD, RTCVD, or ALD. Due to the high aspect ratio of the isolation trenches 30 (and thus the narrow width of the isolation trenches 30), the polysilicon material formed by the non-selective deposition process may fill or close (pinch off) the top of the isolation trenches 30 before completely filling the isolation trenches, resulting in a polysilicon layer 52A having a gap (void) 54A that travels vertically through the center of the polysilicon layer 52A after deposition. During subsequent processing, such as that associated with fabricating IC devices (e.g., transistors) on the SOI substrate 10, the polysilicon DTI 50A (and thus the polysilicon layer 52A) may be exposed to various high temperature processes, such as a high temperature annealing process. The high temperature (e.g., a temperature greater than about 1000 ℃) may cause thermal migration, growth, and/or recrystallization of the silicon grains of the polysilicon layer 52A, thereby altering the grain structure of the polysilicon layer 52A. For example, in fig. 1, the grain structure of polysilicon layer 52A changes during subsequent processing, resulting in polysilicon layer 52A having voids 56A, 56B, and 56C. Voids 56A, 56B, and/or 56B may have a dimension (e.g., width, length, or height) of about 0.3 μm to about 0.5 μm. Voids 56A-56C may cause IC devices isolated by polysilicon DTI 50A to exhibit higher resistance than IC devices isolated by polysilicon DTI (having a polysilicon layer without such voids). IC devices isolated by polysilicon DTI 50A may therefore exhibit increased resistance-capacitance (RC) delay and reduced device reliability. In some embodiments, a void may be formed at the top of the polysilicon DTI 50A and filled with metal during subsequent processing, which may reduce the reliability of the IC device and/or cause electrical shorts.

Introducing a dopant such as boron into the non-selectively deposited polysilicon layer may reduce resistance and minimize the effect of voids in the polysilicon DTI. For example, process B is similar to process a except that process B introduces dopants into the polysilicon material during the non-selective deposition process, such as p-type dopants (e.g., boron, indium, other p-type dopants, or combinations thereof), n-type dopants (e.g., phosphorus, arsenic, other n-type dopants, or combinations thereof), or combinations thereof. In fig. 1, process B introduces boron into the polysilicon material, thereby forming a boron-doped polysilicon layer 52B. Polysilicon DTI50B thus has oxide sidewall 40-1, oxide sidewall 40-2, and boron doped polysilicon layer 52B disposed between oxide sidewall 40-1 and oxide sidewall 40-2. Due to the high aspect ratio of isolation trench 30 and subsequent high temperature processing, polysilicon DTI50B also includes gap 54B and voids 56D-56F, similar to gap 54A and voids 56A-56C, respectively, of polysilicon DTI 50A. The doping of the polysilicon DTI50B (i.e., the boron doped polysilicon layer 52B) may offset or minimize the increase in resistance caused by the voids 56D-56F. In some embodiments, IC devices isolated by polysilicon DTI50B exhibit less resistance than IC devices isolated by polysilicon DTI 50A. In some embodiments, doping the polysilicon DTI with boron may reduce the resistance by up to three times compared to polysilicon DTI without doping with boron. However, as shown in fig. 1, outgassing (outdiffusion) of the boron dopant into the ambient and/or unintended layers during subsequent processing can also undesirably alter IC device characteristics.

Process C can reduce resistance and minimize the effect of voids in the polysilicon DTI while also minimizing dopant outgassing. Process C is similar to process a and process B except that process C deposits a boron-doped polysilicon layer 52C over the oxide layer 40, wherein the boron-doped polysilicon layer 52C partially fills the isolation trench 30, and then deposits a polysilicon layer 52D over the boron-doped polysilicon layer 52C, wherein the polysilicon layer 52D fills the remaining portion of the isolation trench 30. The boron doped polysilicon layer 52C and the polysilicon layer 52D are formed by a non-selective deposition process such as that described above. Polysilicon DTI 50C thus has oxide sidewall 40-1, oxide sidewall 40-2, and a double-layer polysilicon layer (i.e., boron-doped polysilicon layer 52C and polysilicon layer 52D) disposed between oxide sidewall 40-1 and oxide sidewall 40-2. Boron doped polysilicon layer 52C separates polysilicon layer 52D from oxide sidewall 40-1, oxide sidewall 40-2, and semiconductor layer 16. In fig. 1, boron doped polysilicon layer 52C and polysilicon layer 52D have a substantially u-shaped profile in the x-z plane. Due to the high aspect ratio of isolation trench 30 and subsequent high temperature processing, polysilicon DTI 50C also includes gaps 54C and voids 56G-56I, similar to gaps 54A, 54B and voids 56A-56C, 56D-56F, respectively, of polysilicon DTIs 50A, 50B. The incorporation of dopants into the polysilicon DTI 50C (i.e., the boron doped polysilicon layer 52C) may offset or minimize the increase in resistance caused by the voids 56G-56I, such that IC devices isolated by the polysilicon DTI 50C have a lower resistance than IC devices isolated by the polysilicon DTI 50A. The double polysilicon layer of polysilicon DTI 50C may also exhibit less dopant outgassing than polysilicon DTI 50B. However, as shown in fig. 1, some outgassing (outdiffusion) of the boron dopant into the ambient and/or unintended layers still occurs during subsequent processing and can undesirably alter IC device characteristics.

The present invention proposes silicon-containing DTI which solves the void problem and outgassing problem caused by polysilicon DTI 50A-50C. Turning to fig. 2, fig. 2 depicts a partial cross-sectional view of the fabrication of a portion or the entirety of a silicon-containing DTI 60 that may be integrated into an SOI substrate, in accordance with various aspects of the present invention. In FIG. 2, the fabrication of silicon-containing DTI 60 begins similarly to the fabrication of polysilicon DTIs 50A-50C. For example, fabrication includes forming a patterned layer 20 over an SOI substrate 10, forming an isolation trench 30 in the SOI substrate 10, depositing an oxide layer 40 over the SOI substrate 10 and the patterned layer 20 (where the oxide layer 40 is disposed along sidewalls and a bottom of the isolation trench 30, and the oxide layer 40 partially fills the isolation trench 30), and removing the oxide layer 40 from a bottom 36 of the isolation trench 30, such as described above. In contrast to the fabrication of polysilicon DTIs 50A-50C, the fabrication of silicon-containing DTIs 60 is performed according to process D, wherein SOI substrate 10 having isolation trenches 30 is received in a process chamber and silicon layer 62 is formed in isolation trenches 30. Silicon layer 62 comprises monocrystalline silicon, also referred to as monocrystalline or crystalline silicon. Single crystal silicon generally comprises a single, continuous silicon crystal having one crystal orientation and no grain boundaries, while polycrystalline silicon generally refers to silicon separated by grain boundariesA plurality of silicon crystals (grains) (i.e., single crystal silicon grains, which may be randomly oriented and have different crystal orientations). In some embodiments, silicon layer 62 comprises intrinsic crystalline silicon, which is commonly referred to as undoped or unintentionally doped (UID) silicon. In such embodiments, the silicon layer 62 is substantially free of dopants. In some embodiments, silicon layer 62 comprises crystalline silicon doped with a p-type dopant (e.g., boron, indium, other p-type dopants, or combinations thereof), an n-type dopant (e.g., phosphorus, arsenic, other n-type dopants, or combinations thereof), or combinations thereof. For example, silicon layer 62 may comprise crystalline silicon doped with boron. In some embodiments, silicon layer 62 is a boron dopant concentration of about 1x10¹⁴Dopant/cm³(cm^-3) To about 5X10²⁰cm^-3A boron doped silicon layer. In some embodiments, the dopant concentration, such as the boron concentration, is substantially the same along the thickness of the silicon layer 62. In some embodiments, the silicon layer 62 has a graded dopant concentration, which may gradually increase or decrease along the thickness of the silicon layer 62. In some embodiments, silicon layer 62 includes discrete portions having different dopant concentrations, such as a first silicon portion having a first dopant concentration and a second silicon portion having a second dopant concentration different from the first dopant concentration. It should be noted that silicon layer 62, whether composed of intrinsic or doped crystalline silicon, may include crystal defects, such as dislocations (e.g., irregularities and/or disruptions in the ordered arrangement of silicon atoms of single crystal silicon). The thickness of the silicon layer 62 is less than the depth of the isolation trench 30. In some embodiments, the thickness of silicon layer 62 is less than the sum of the thicknesses of semiconductor layer 14 and insulator layer 12, such that the top surface of silicon layer 62 is below the top surface of SOI substrate 10 (e.g., below the top surface of semiconductor layer 14). In some embodiments, the thickness of the silicon layer 62 is about 6 μm to about 9 μm.

Silicon layer 62 is formed by a selective, bottom-up deposition process. The bottom-up deposition process generally refers to a deposition process that fills the opening from bottom to top (i.e., bottom-up fills the isolation trench 30). The selective bottom-up deposition process avoids inadvertently filling the top of the isolation trench 30 before completely filling the isolation trench 30, and thus avoidsThe problem of pinching off of the gaps 54A-54C in the polysilicon DTIs 50A-50C, respectively, is avoided. For example, in fig. 2, the silicon layer 62 is seamless. The bottom-up deposition process is a silicon Selective Epitaxial Growth (SEG) process that selectively deposits (grows) silicon from a semiconductor surface (e.g., semiconductor layer 16 of SOI substrate 10) while limiting (or preventing) the growth of silicon from a dielectric surface and/or a non-semiconductor surface (e.g., oxide layer 40). For example, silicon is grown from semiconductor layer 16 but not from oxide layer 40 such that silicon layer 62 fills the remaining portion of the bottom of isolation trench 30 without covering the top surface of oxide layer 40 and/or the top surface of patterned layer 20. In some embodiments, the SEG process is a selective CVD process that introduces a silicon-containing precursor and a carrier gas into the process chamber, wherein the silicon-containing precursor interacts with the SOI substrate 10 and the oxide layer 40 to form the silicon layer 62. The silicon-containing precursor comprises Silane (SiH)₄) Disilane (Si)₂H₆) Dichlorosilane (SiH)₂Cl₂) (DCS) and trichlorosilane (SiHCl)₃) Silicon tetrachloride (SiCl)₄) Other suitable silicon-containing precursors, or combinations thereof. The carrier gas may be an inert gas, such as a hydrogen-containing gas (e.g., H)₂) Argon-containing gas (e.g., Ar), helium-containing gas (e.g., He), nitrogen-containing gas (e.g., N)₂) Xenon-containing gas, other suitable inert gas, or combinations thereof. In the depicted embodiment, the SOI substrate 10 and the oxide layer 40 are exposed to a gas including DCS (silicon containing precursor) and H₂(carrier gas) deposition mixture. While various parameters of the selective CVD process may be adjusted to ensure that the silicon-containing precursor selectively nucleates and grows from semiconductor layer 16 and/or nucleates and grows from semiconductor layer 16 faster than from oxide layer 40, some silicon materials may nucleate and grow on oxide layer 40. To prevent or limit such growth, the selective CVD process further introduces an etchant-containing precursor into the process chamber, which precursor may interact with the SOI substrate 10, the oxide layer 40, and/or the silicon material deposited on the SOI substrate 10 and/or the oxide layer 40. The etchant-containing precursor includes chlorine gas (Cl)₂) Hydrogen chloride (HCl), other etchant-containing precursors that can achieve the desired silicon growth selectivity, or combinations thereof. Since on the semiconductor layer 16 andthe growth of silicon material on the oxide layer 40 and from the oxide layer 40 is largely discontinuous and discrete compared to the growth of silicon material on the semiconductor layer 16 (which may be continuous and merged), so the etchant-containing precursor can remove any silicon material from the oxide layer 40 more quickly than silicon material from the semiconductor layer 16. Thus, the selective CVD process simultaneously deposits and etches silicon material, but is configured to have a deposition rate greater than the etch rate to ensure a net deposition of silicon material. In some embodiments, the etchant-containing precursor prevents any nucleation of silicon material on the oxide layer 40. In the depicted embodiment, the deposition mixture further includes HCl, which may etch silicon material nucleated on the oxide layer 40 and/or prevent the nucleation of silicon material on the oxide layer 40, thereby removing and/or preventing the growth of silicon material on the oxide layer 40. In some embodiments, the selective CVD process further introduces a dopant-containing precursor into the process chamber, which can interact with the SOI substrate 10, the oxide layer 40, and/or the silicon material deposited over the SOI substrate 10 and/or the oxide layer 40. The dopant-containing precursor includes boron (e.g., B)₂H₆) Phosphorus (e.g. PH)₃) Arsenic (e.g., AsH)₃) Other suitable dopants, or combinations thereof. For example, the deposition mixture may also include B₂H₆，B₂H₆Facilitating in-situ boron doping of the silicon layer 62.

The target silicon growth (deposition) rate and/or silicon growth selectivity is achieved by adjusting (modulating) various parameters of the selective CVD process, such as the silicon-containing precursor flow, the carrier gas flow, the etchant-containing precursor flow, the dopant-containing precursor flow, the temperature, the pressure, other selective CVD process parameters, or combinations thereof. In some embodiments, the selective CVD process includes heating the SOI substrate 10 to a temperature of about 800 ℃ to about 1050 ℃. In some embodiments, the pressure maintained in the process chamber during the selective CVD process is about 10 torr to about 100 torr. In some embodiments, the selective CVD process is an LPCVD process, wherein the pressure maintained in the process chamber is less than about 50 torr. In some embodiments, the duration of the selective CVD process is about 5 minutes to about 20 minutes. In some casesIn an embodiment, the parameters of the selective CVD process are adjusted to achieve a silicon growth rate of at least 1 μm/min (i.e., a silicon growth rate ≧ 1 μm/min). In some embodiments, the flow rate of the silicon-containing precursor, such as DCS, is between about 50 standard cubic centimeters per minute (sccm) and about 200 sccm. In some embodiments, such as H₂The carrier gas of (a) has a flow rate of about 10000sccm to about 40000 sccm. In some embodiments, the flow rate of the etchant-containing precursor (such as HCl) is about 200sccm to about 500 sccm. In some embodiments, a dopant-containing precursor (such as B)₂H₆) The flow rate of (a) is about 0.01sccm to about 1 sccm. In some embodiments, the flow rate of the dopant-containing precursor is controlled to achieve different dopant concentration profiles in the silicon layer 62, such as a substantially uniform dopant profile along the thickness of the silicon layer 62, a graded dopant profile (i.e., dopant increase or decrease) along the thickness of the silicon layer 62, and/or discrete doped portions (e.g., lightly doped silicon portions and heavily doped silicon portions) of the silicon layer 62. In embodiments where multiple DTIs are formed simultaneously on a wafer, the thickness of the silicon layer formed in the isolation trench may vary depending on the location of the isolation trench on the wafer. For example, a first thickness of a silicon layer formed in an isolation trench located at a center of a wafer may be greater than a second thickness of a silicon layer formed in an isolation trench located at an edge of the wafer. Accordingly, the present invention further contemplates adjusting the selective CVD process to minimize variations in the thickness of the silicon layer formed in the isolation trenches on the wafer, thereby improving thickness uniformity. In some embodiments, the power/temperature ratio employed during the selective CVD process is adjusted to improve the thickness uniformity of the silicon layer in the isolation trenches formed on the wafer. For example, the center power/temperature is adjusted relative to the edge power/temperature to improve thickness uniformity. In some embodiments, reducing the center power/temperature relative to the edge power/temperature by about 5% achieves a center-to-edge thickness uniformity of less than about 20%. For example, when the center power/temperature is about 5% less than the edge power/temperature, the difference between the first thickness and the second thickness is less than about 20%.

In some embodiments, the flow of the silicon-containing precursor (D) that controls the deposition (growth) rate of the silicon material is adjusted and the silicon material is controlledThe etch rate of (a) to enhance the growth kinetics of the silicon layer 62. For example, the ratio of etchant-containing precursor and silicon-containing precursor (E/D ratio) is adjusted to minimize selectivity loss and prevent (or minimize) defects. In some embodiments, the defects are silicon nuclei (i.e., silicon material and/or grains) formed on the oxide layer 40 during the selective CVD process. Since defect density is inversely proportional to the E/D ratio (e.g., defect density decreases as the E/D ratio increases), the flow of etchant-containing precursor (e.g., HCl) may be increased to minimize selectivity loss and/or limit defect density to acceptable levels. For example, FIG. 3 provides a log linear plot 70 relating log defect density to E/D ratio, where the E/D ratio is represented along the x-axis, log defect level (in centimeters per square (cm)²) Log-10 of defects for the wafer area) is represented along the y-axis and the tolerance level for defect density is represented by line 72. In the depicted embodiment, the allowable level of defect density is less than or equal to about 100 (i.e., less than or equal to about 10 defects per square centimeter of wafer). In some embodiments, the defect density above line 72 represents a selectivity loss in a selective CVD process, meaning that silicon material is formed not only in the trench region (i.e., on semiconductor layer 16 in isolation trench 30) but also in the non-trench region (i.e., on the top surface of oxide layer 40), while the defect density below line 72 represents no selectivity in the selective CVD process, meaning that silicon material is formed only in the trench region and not in the non-trench region. In fig. 3, lines 74a and 74b represent the log defect density as a function of the E/D ratio for a first silicon trench opening ratio (i.e., the ratio of trench area to total wafer area) and a second silicon trench opening ratio, where the first silicon trench opening ratio is greater than the second silicon trench opening ratio. Lines 74a, 74b indicate that when the E/D ratio is greater than about 5, the defect density decreases with increasing E/D ratio and the defect density reaches a tolerable level. Lines 74a, 74b also represent the E/D ratio required to achieve an increase in the allowable level of defect density as the silicon trench opening ratio decreases. Thus, in a selective CVD process, the flow rate of an etchant-containing precursor may be increased relative to the flow rate of a silicon-containing precursor to increaseLarge E/D ratios and optimize selectivity (i.e., eliminate or minimize selectivity loss and ensure growth from the semiconductor layer 16 rather than from the silicon material of the oxide layer 40) and minimize defects, but cannot be increased to a level that results in a net etching effect. In some embodiments in FIG. 2, the E/D ratio of the selective CVD process is about 5 to about 10 (in other words, 5 ≦ E/D ratio ≦ 10). An E/D ratio of less than 5 may result in silicon selectivity loss and/or unacceptable defect density levels, while an E/D ratio of greater than 10 may result in insufficient silicon growth from semiconductor layer 16 (and hence insufficient filling of isolation trenches 30) and/or unwanted etching of silicon material from semiconductor surfaces, such as semiconductor layer 16. In some embodiments, instead of or in addition to increasing the E/D ratio, reducing the defect density and selectivity loss may be achieved by reducing the temperature and pressure of the selective CVD process. In some embodiments, heating the SOI substrate 10 to a temperature of about 800 ℃ to 1050 ℃ and maintaining a pressure in the process chamber of about 10 torr to about 100 torr may achieve a silicon growth rate of at least 1 μm/min and prevent the defect density level from rising to 10 defects/cm²The above.

Defects (e.g., native oxides or other contaminants) on the surface of the oxide layer 40 may serve as nucleation sites from which silicon material may undesirably grow during the silicon SEG process. In some embodiments, a cleaning process is performed prior to the silicon SEG process to remove defects from the oxide layer 40 and/or the semiconductor layer 16, such as any native oxide, contaminants, and/or other defects on the oxide layer 40 and/or the semiconductor layer 16. The cleaning process is a baking process performed in an environment containing an etchant, wherein (etching) defects are removed from the oxide layer 40 and/or the semiconductor layer 16 during the baking process. For example, the cleaning process may include heating the SOI substrate 10 to a cleaning temperature and introducing an etchant-containing precursor and a carrier gas into the process chamber. The etchant-containing precursor includes Cl₂HCl, other etchant-containing precursors that can remove defects, or combinations thereof. The carrier gas comprises an inert gas such as a hydrogen-containing gas, an argon-containing gas, a helium-containing gas, a nitrogen-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof. In the implementation depictedIn an example, prior to forming silicon layer 62, a chlorine-based pre-bake process, such as an HCl pre-bake process, is performed on oxide layer 40 to remove (clean) surface nucleation sites on oxide layer 40. Reducing surface nucleation sites on oxide layer 40 may reduce the defect density associated with forming silicon layer 62.

Process D then continues by forming a polysilicon layer 64 over silicon layer 62 and oxide layer 40, wherein polysilicon layer 64 fills the remaining upper portion of isolation trench 30. Polysilicon layer 64 comprises polysilicon, such as described herein. The polysilicon layer 64 is undoped or unintentionally doped (i.e., the polysilicon layer 64 is substantially free of dopants, particularly substantially free of boron dopants). In some embodiments, polysilicon layer 64 comprises polysilicon doped with a p-type dopant, an n-type dopant, or a combination thereof, but the region of the polysilicon layer that will form the topmost surface of silicon-containing DTI 60 is substantially free of dopants. For example, the polysilicon layer 64 may include an undoped polysilicon portion and a doped polysilicon portion, wherein the undoped polysilicon portion is located at a region of the polysilicon layer 64 that forms a topmost surface of the silicon-containing DTI 60. In some embodiments, the doped polysilicon portion comprises boron doped polysilicon. In some embodiments, the boron doped polysilicon portion has a thickness of about 1x10¹⁵cm^-3To about 5X10²⁰cm^-3The boron dopant concentration of (a). In some embodiments, the polysilicon layer 64 has a graded boron concentration that decreases from a first boron concentration at an interface between the silicon layer 62 and the polysilicon layer 64 to a second boron concentration at a top surface of the polysilicon layer 64. In some embodiments, the gradient boron concentration is from about 5x10²⁰cm^-3Reduced to about 1 × 10¹⁷cm^-3. The polysilicon layer 64 has a thickness less than the thickness of the silicon layer 62 and sufficient to fill the remaining portion of the isolation trench 30. Any loss of selectivity that occurs during the formation of the silicon layer 62 may result in the formation of grains (e.g., silicon grains) on the oxide layer 40. In some embodiments, these particles are very large, e.g., having a size of up to 5 μm to 7 μm. To prevent these particles from scratching the wafer surface during the subsequent planarization process, the polysilicon layer 64 is thick enough to cover and inhibit the movement of these particles. For example, polycrystalline siliconThe thickness of layer 64 is about 0.5 μm to about 3 μm to ensure coverage of any particles/contaminants formed during deposition of silicon layer 62.

Polysilicon layer 64 is formed by a non-selective, blanket deposition process, which generally refers to a deposition process that indiscriminately forms material over various surfaces, such as dielectric surfaces, semiconductor surfaces, and metal surfaces. For example, the polysilicon layer 64 covers (blanket) all exposed surfaces, such as the top surface of the oxide layer 40 and the top surface of the silicon layer 62. In some embodiments, the non-selective, blanket deposition process is a blanket CVD process that introduces a silicon-containing precursor and a carrier gas into the process chamber, wherein the silicon-containing precursor interacts with the oxide layer 40 and the silicon layer 62 to deposit a polysilicon material that forms the polysilicon layer 64. The blanket CVD process does not introduce an etchant-containing precursor (such as HCl) into the process chamber. The silicon-containing precursor comprises SiH₄、Si₂H₆、DCS、SiHCl₃、SiCl₄Other suitable silicon-containing precursors, or combinations thereof. The carrier gas may be an inert gas such as a hydrogen-containing gas, an argon-containing gas, a helium-containing gas, a nitrogen-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof. In the depicted embodiment, oxide layer 40 and silicon layer 62 are exposed to a composition comprising DCS (silicon containing precursor) and H₂(carrier gas) deposition mixture. In some embodiments, the blanket CVD process further introduces a dopant-containing precursor into the process chamber, which can interact with the oxide layer 40, the silicon layer 62, and/or the deposited polysilicon material. The dopant-containing precursor includes boron, phosphorus, arsenic, other suitable dopants, or combinations thereof. For example, the deposition mixture may also include B₂H₆，B₂H₆Facilitating in-situ boron doping of the polysilicon layer 64.

Various parameters of the non-selective, blanket deposition process, such as a silicon-containing precursor flow, a carrier gas flow, a dopant-containing precursor flow, a temperature, a pressure, other selective CVD process parameters, or combinations thereof. In some embodiments, the blanket CVD process includes heating the SOI substrate 10 to a temperature of about 650 ℃ to about 1000 ℃. In some embodiments, the process chamber is maintained during a blanket CVD processThe pressure in (a) is about 10 torr to about 100 torr. In some embodiments, the duration of the selective CVD process is about 20 minutes to about 50 minutes. In some embodiments, the parameters of the blanket CVD process are adjusted to achieve a polysilicon growth rate of at least 0.1 μm/min (i.e., the polysilicon growth rate ≧ 2 μm/min). In some embodiments, the flow rate of the silicon-containing precursor (such as DCS) is about 50sccm to about 300 sccm. In some embodiments, such as H₂The carrier gas of (a) has a flow rate of about 10000sccm to about 40000 sccm. In some embodiments, a dopant-containing precursor (such as B)₂H₆) The flow rate of (a) is about 0.01sccm to about 1.0 sccm. In some embodiments, the flow of the dopant-containing precursor is controlled to achieve a dopant-free portion of the polysilicon layer 64, such as the portion of the polysilicon layer 64 that will form the top surface (or region) of the silicon-containing DTI 60. In some embodiments, the flow of the dopant-containing precursor is controlled to achieve a graded dopant concentration in the polysilicon layer 64. For example, the flow rate of the dopant-containing precursor decreases as the thickness of the polysilicon layer 64 increases. In some embodiments, the flow of the dopant-containing precursor is stopped before the polysilicon layer 64 reaches the target thickness.

Thereafter, a planarization process such as CMP is performed to remove portions of polysilicon layer 64, oxide layer 40, and patterned layer 20 from over the top surface of SOI substrate 10. The remaining portions of polysilicon layer 64 form polysilicon overlayer 64' of silicon-containing DTI 60 and the remaining portions of oxide layer 40 form oxide sidewalls 40-1 and 40-2 of silicon-containing DTI 60. At least the top surface (or top region) of the polysilicon blanket layer 64 'is substantially free of dopants such that the polysilicon blanket layer 64' may serve as a sealing layer or barrier layer that prevents outgassing of dopants, such as boron, during subsequent processing. For example, polysilicon overlayer 64' covers any dopant-containing portion of silicon-containing DTI 60 such that there are no exposed dopant-containing portions of silicon-containing DTI 60, such as boron-containing portions, e.g., polysilicon DTIs 50A-50C. In some embodiments, the top surface of the polysilicon cap layer 64' and the top surface of the SOI substrate 10 are substantially planar after the planarization process. In some embodiments, the planarization process includes multiple steps, such as a first planarization stopping at the oxide layer 40, a second planarization stopping at the patterned layer 20, and/or a third planarization stopping at the top surface of the SOI substrate 10. In such an embodiment, the first planarization may form the polysilicon cap layer 64 ', and the second planarization and the third planarization may reduce the thickness of the polysilicon cap layer 64'.

Thus, the silicon-containing DTI 60 has oxide sidewalls 40-1, oxide sidewalls 40-2, and a bilayer silicon-containing layer (i.e., silicon layer 62 and polysilicon cap layer 64') disposed between the oxide sidewalls 40-1 and the oxide sidewalls 40-2. Silicon-containing DTI 60 provides several advantages over polysilicon DTIs, such as polysilicon DTIs 50A-50C. For example, the process for fabricating silicon-containing DTI 60 exhibits better gap-fill characteristics, particularly for high aspect ratio isolation trenches, than the process for fabricating polysilicon DTIs 50A-50C. Thus, silicon-containing DTIs 60 can be fabricated without gaps (or voids), which results in IC devices isolated by the gapless silicon-containing DTIs 60 exhibiting lower resistance than IC devices isolated by polysilicon DTIs 50A-50C, thereby improving device reliability. Even with voids (which may be caused by small gaps) in the silicon-containing DTI 60, such voids are significantly smaller than the voids 56A-56I present in the polysilicon DTIs 50A-50C and still provide an IC device exhibiting lower resistance and improved device reliability. In another example, the silicon-containing DTI 60 may be doped with a dopant, such as boron, to reduce the resistance of the IC device, but does not exhibit outgassing during high temperature thermal processes. In particular, the polysilicon cap layer 64' prevents outgassing of dopants during subsequent processing, such as processing associated with fabricating IC devices. Preventing dopant outgassing reduces dopant contamination. In some embodiments, the polysilicon cap layer 64' prevents outgassing during a high temperature annealing process used to fabricate high voltage IC devices, such as an annealing process that exposes the wafer to temperatures above about 1000 ℃ to drive in dopants and form n-wells and/or p-wells in the SOI substrate. In some embodiments, the polysilicon cap layer 64' prevents outgassing during gate formation (such as gate dielectric formation). In yet another example, forming polysilicon layer 64 after forming silicon layer 62 reduces (and in some embodiments eliminates) scratching of the wafer surface of the wafer in which silicon-containing DTI 60 is incorporated, thereby preventing wafer damage during subsequent processing. In particular, because the polysilicon layer 64 covers any particles (e.g., silicon particles) that may form on the oxide layer 40 due to selectivity losses that occur during formation of the silicon layer 62, the polysilicon layer 64 prevents these particles from moving freely during a subsequent planarization process, thereby preventing (or limiting) the particles from scratching and/or otherwise damaging the wafer surface during the planarization process. Different embodiments may have different advantages and no particular advantage is required of any embodiment.

A silicon layer 62 and a polysilicon layer 64 are formed "in situ" in the isolation trench 30. For example, the selective CVD process and the blanket CVD process are performed in the same process chamber, such as a process chamber of a CVD tool, such that the wafer (e.g., the SOI substrate 10 and the various layers and/or features fabricated thereon) is maintained under vacuum conditions. Thus, "in-situ" also generally refers to performing various processes on a wafer without exposing the wafer to an external environment (e.g., external to the IC processing system), such as oxygen. Thus, performing selective CVD and blanket CVD processes may minimize (or eliminate) exposure to oxygen and/or other external environments during processing. In some embodiments, the cleaning process is also performed in-situ with the selective CVD process and the blanket CVD process. In some embodiments, a purge process is performed at various stages of forming the silicon layer 62 and the polysilicon layer 64, such as before performing a selective CVD process and before performing a blanket CVD process. The purge process may remove any by-products from the process chamber. The purge process introduces an inert gas, such as a hydrogen-containing gas, a nitrogen-containing gas, an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof, into the process chamber to remove any byproducts from the process chamber. In some embodiments, the process proceeds from the selective CVD process to the blanket CVD deposition process by adjusting the deposition mixture supplied to the process chamber. For example, the etchant-containing precursor is removed from the deposition mixture to switch from a selective CVD process to a blanket CVD process.

Fig. 4A is a partial top view of a portion or the entirety of an IC device 100 in accordance with various aspects of the present invention. Fig. 4B is a partial cross-sectional view of a portion or the entirety of the IC device 100 taken along line B-B of fig. 4A in accordance with various aspects of the present invention. The IC device 100 has a semiconductor-on-insulator (SOI) substrate 105 and an isolation feature 110 disposed in the SOI substrate 105, wherein the isolation feature 110 surrounds an active region 115 of the IC device 100. The active region 115 (also referred to as an OD region) is configured for a transistor and may be referred to as a transistor region. In some embodiments, high voltage devices, such as high voltage transistors, are fabricated on the SOI substrate 105 in the active region 115. High voltage devices operate at high voltages, such as transistors operating at voltages greater than about 100V. Processes for manufacturing high voltage devices typically include high temperature thermal processes, some of which may expose the high voltage devices to temperatures greater than about 60 ℃. The IC device 100 includes isolation structures described below and herein that can withstand such high temperature thermal anchor fins and improve the performance, integrity and/or reliability of high voltage devices, such as high voltage transistors. In some embodiments, fig. 4A and 4B are simplified for clarity in order to better understand the inventive concepts of the present invention. Additional components may be added to the IC device 100 and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 100.

The SOI substrate 105 includes a semiconductor layer 120, an insulator layer 122, and a semiconductor layer 124, wherein the insulator layer 122 is disposed between the semiconductor layer 120 and the semiconductor layer 124 and separates the semiconductor layer 120 and the semiconductor layer 124. Insulator layer 122 electrically isolates semiconductor layer 120 from semiconductor layer 124. Semiconductor layer 120 and semiconductor layer 124 comprise a semiconductor material and insulator layer 122 comprises a dielectric material. The semiconductor material may include silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, other suitable semiconductor materials, or combinations thereof. The dielectric material may include silicon, oxygen, nitrogen, carbon, other suitable insulating compositions, or combinations thereof. In the depicted embodiment, semiconductor layer 120 and semiconductor layer 124 comprise the same semiconductor material, such as silicon, and insulator layer 122 comprises oxygen. In such embodiments, the semiconductor layers 120, 124 may be referred to as silicon layers, the insulator layer 122 may be referred to as an oxide layer, and the SOI substrate 105 may be referred to as a silicon-on-insulator substrate. In some embodiments, semiconductor layer 120 and semiconductor layer 124 comprise different semiconductor materials. In some embodiments, the SOI substrate 105 is a Silicon Germanium On Insulator (SGOI) substrate. In some embodiments, the SOI substrate 105 is a Germanium On Insulator (GOI) substrate. The SOI substrate 105 may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and/or other suitable methods. The SOI substrate 105 may include various doped regions depending on the design requirements of the IC device 100. For example, the SOI substrate 105 may include a p-type doped region (referred to as a p-well), an n-type doped region (referred to as an n-well), or a combination thereof. The n-type doped region is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-type doped region is doped with a p-type dopant, such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the SOI substrate 105 includes a doped region formed from a combination of p-type dopants and n-type dopants.

The isolation features 110 surround the active area 115 and electrically isolate the active area 115 from other active and/or inactive areas of the IC device 100. In fig. 4B, an isolation feature 110 is disposed in the SOI substrate 105 and surrounds the active region 115, such that the isolation feature 110 may be referred to as an isolation ring. The isolation features 110 may have any suitable configuration and may include different structures, such as Shallow Trench Isolation (STI) structures, Deep Trench Isolation (DTI) structures, local oxidation of silicon (LOCOS) structures, other suitable isolation structures, or combinations thereof. In some embodiments, the depth of the STI structures is generally less than the thickness of the semiconductor layer 124, while the depth of the DTI structures is generally equal to or greater than the semiconductor layer 124, such that the DTI structures extend at least to the insulator layer 122. In some embodiments, the STI structures have a depth of less than about 0.5 μm, while the DTI structures have a depth of greater than about 5 μm. In the depicted embodiment, isolation feature 110 includes STI structure 130 and DTI structure 135, each of which surrounds active region 115 and may be referred to as an STI ring and a DTI ring, respectively. STI structure 130 has a width w1 and a depth d 1. DTI structure 135 has a width w2 and a depth d2, where width w2 is less than width w1 and depth d2 is greater than depth d 1. In some embodiments, the width w1 is about 0.3 μm to about 3 μm. In some embodiments, the width w2 is about 0.1 μm to about 1 μm. In some embodiments, the depth d1 is about 0.5 μm to about 3 μm. In some embodiments, the depth d2 is about 1 μm to about 50 μm. In fig. 4B, a width w1 and a width w2 are defined along the x-direction between the sidewalls of the STI structure 130 and the DTI structure 135, respectively, and a depth d1 and a depth d2 are defined along the z-direction between the top surface of the semiconductor layer 124 and the bottom of the STI structure 130 and the DTI structure 135, respectively. DTI structure 135 extends through STI structure 130 such that DTI structure 135 is disposed between a first portion of STI structure 130 having a width w3 and a second portion of STI structure 130 having a width w 4. In some embodiments, width w3 is about 0.1 μm to about 1 μm, and width w4 is about 0.1 μm to about 1 μm. In the depicted embodiment, the center of the DTI structure 135 is aligned with the center of the STI structure 130 such that the width w3 is approximately equal to the width w 4. In some embodiments, the center of DTI structure 135 is not aligned with the center of STI structure 130, such that width w3 is different than width w 4. In some embodiments, the sidewalls of the DTI structure 135 are aligned with the sidewalls of the STI structures 130 such that the STI structures 130 are not separated into first and second portions as depicted. In such embodiments, depending on the sidewall alignment, the STI structure 130 is disposed between the active region 115 and the DTI structure 135 and separates the active region 115 from the DTI structure 135, or the DTI structure 135 is disposed between the active region 115 and the STI structure 130 and separates the active region 115 from the STI structure 130.

STI structures 130 comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., comprising silicon, oxygen, nitrogen, carbon, or other suitable isolation compositions), or combinations thereof. The STI structure 130 may be formed by: forming a patterned mask layer over the SOI substrate 105, wherein the patterned mask layer has an opening therein that exposes the semiconductor layer 124 of the SOI substrate 105; etching a trench in the semiconductor layer 124 using the patterned mask layer as an etch mask (e.g., by using a dry etch process and/or a wet etch process); and depositing an insulator material (e.g., by a Chemical Vapor Deposition (CVD) process or a spin-on-glass process) that fills the trench. A Chemical Mechanical Polishing (CMP) process may be performed to remove excess insulator material, such as the insulator material disposed over the top surface of the semiconductor layer 124, and/or to planarize the top surface of the STI structures 130 and/or the top surface of the semiconductor layer 124. In another example, where the SOI substrate 105 is patterned to have various fins (e.g., the active region 115 is one of the fins formed by the semiconductor layer 124), the STI structure 130 may be formed by depositing an insulator material after forming the fins and etching back the insulator material to form the STI structure 130. In such embodiments, the insulator material may fill the gaps (trenches) between the fins. In some embodiments, STI structures 130 include a multi-layer structure that fills the trench, such as a silicon oxide layer disposed over a silicon nitride liner and/or an oxide liner. In another example, the STI structure 130 includes a dielectric layer disposed over a doped liner layer including, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG). In yet another example, STI structure 130 includes a bulk dielectric layer disposed over a dielectric liner. In some embodiments, the STI structures 130 are formed by a Flowable Cvd (FCVD) process that includes, for example, depositing a flowable material (such as a liquid compound) over the SOI substrate 105 and converting the flowable material to a solid material by a suitable technique (such as thermal annealing and/or ultraviolet radiation treatment). In some embodiments, the STI structures 130 are formed by a High Density Plasma (HDP) process and/or a high aspect ratio deposition (HARP) process.

The DTI structure 135 extends through the SOI substrate 105 to at least the insulator layer 122. In some embodiments, the DTI structures 135 are high aspect ratio isolation structures, which generally refer to isolation structures having a ratio of depth to width (D/W) greater than about 5. For example, the ratio of the depth d2 to the width w2 (d2/w2) is about 5 to about 50. In fig. 4B, the DTI structure 135 extends completely through the semiconductor layer 124 and the insulator layer 122 to the semiconductor layer 120 (particularly to the top surface of the semiconductor layer 120). The depth d2 is therefore equal to the sum of the thickness of the semiconductor layer 124 and the thickness of the insulator layer 122. In some embodiments, the depth d2 is greater than the sum of the thickness of the semiconductor layer 124 and the thickness of the insulator layer 122, such that the DTI structure 135 extends completely through the semiconductor layer 124 and the insulator layer 122 and partially through the semiconductor layer 120. In some embodiments, the depth d2 is equal to the sum of the thickness of the semiconductor layer 124, the thickness of the insulator layer 122, and the thickness of the semiconductor layer 120, such that the DTI structure 135 extends completely through the SOI substrate 105 (i.e., completely through the semiconductor layer 124, the insulator layer 122, and the semiconductor layer 120). In some embodiments, the depth d2 is less than the thickness of the semiconductor layer 124 such that the DTI structure extends partially through the semiconductor layer 124. In some embodiments, the depth d2 is equal to the thickness of the semiconductor layer 124, such that the DTI structure 135 extends completely through the semiconductor layer 124 to the top surface of the insulator layer 122. In some embodiments, the depth d2 is greater than the thickness of the semiconductor layer 124 and less than the sum of the thickness of the semiconductor layer 124 and the thickness of the insulator layer 122, such that the DTI structure 135 extends completely through the semiconductor layer 124 and partially through the insulator layer 122.

DTI structure 135 includes an oxide DTI portion 140A and a multi-layer silicon-containing DTI portion 140B, each of which surrounds active region 115. In some embodiments, oxide DTI portion 140A is referred to as an oxide ring and multilayer silicon-containing DTI portion 140B is referred to as a multilayer silicon-containing ring. In fig. 4A and 4B, the active region 115 is surrounded by a single-ring isolation structure, a single-ring STI structure, and a single-ring DTI structure. In some embodiments, active region 115 is surrounded by a multi-ring DTI structure, such as depicted in fig. 9, fig. 9 including two multi-layer silicon-containing rings surrounding active region 115. Oxide DTI portion 140A lines the sidewalls of DTI structure 135 and may therefore be referred to as an oxide liner. In fig. 4B, oxide DTI portion 140A includes oxide layer 142 and oxide layer 144. The oxide layer 142 is disposed between a first sidewall of the multilayer silicon-containing DTI portion 140B and the SOI substrate 105 (e.g., the semiconductor layer 124 and the insulator layer 122) and separates the first sidewall of the multilayer silicon-containing DTI portion 140B from the SOI substrate 105, and the oxide layer 144 is disposed between a second sidewall of the multilayer silicon-containing DTI portion 140B and the SOI substrate 105 and separates the second sidewall of the multilayer silicon-containing DTI portion 140B from the SOI substrate 105. Oxide layer 142 and oxide layer 144 are also disposed between the first and second sidewalls of the multi-layer silicon-containing DTI portion 140B and the STI structure 130, respectively. In some embodiments, oxide layer 142 and oxide layer 144 represent portions of a single continuous oxide layer that wraps/surrounds the multilayer silicon-containing DTI portion 140B. Oxide layer 142 has a thickness t1, and oxide layer 144 has a thickness t 2. Thickness t1 and thickness t2 are defined along the x-direction between respective sidewalls of DTI structure 135 and respective sidewalls of multilayer silicon-containing DTI portion 140B. In the depicted embodiment, thickness t1 is approximately equal to thickness t 2. In some embodiments, thickness t1 is different than thickness t2 depending on the alignment of DTI structure 135 and STI structure 130. Oxide layer 142 has a length defined along the z-direction, and oxide layer 144 has a length defined along the z-direction, wherein the length of oxide layer 142 and the length of oxide layer 144 are approximately equal to depth d 2. Thickness t1 and thickness t2 are defined along the x-direction between respective sidewalls of DTI structure 135 and respective sidewalls of multilayer silicon-containing DTI portion 140B. The oxide layers 142, 144 include a dielectric material having oxygen and another chemical element, such as silicon, nitrogen, carbon, other suitable electrically isolating components, or combinations thereof. For example, each of the oxide layers 142, 144 includes oxygen and silicon and may be referred to as a silicon oxide liner.

The multi-layer silicon-containing DTI portion 140B includes two layers-a silicon layer 146 and a polysilicon cap layer 148-and may be referred to as a dual-layer silicon-containing DTI structure. Each of silicon layer 146 and polysilicon cap layer 148 extends continuously and uninterruptedly along the x-direction from oxide layer 142 to oxide layer 144 to form the bottom and top of the multi-layer silicon-containing DTI portion 140B, respectively. The silicon layer 146 and the polysilicon cap layer 148 are similar to the silicon layer 62 and the polysilicon layer 64, respectively, described above. For example, the silicon layer 146 comprises single crystal silicon and the polysilicon cap layer 148 comprises polysilicon. In the depicted embodiment, the silicon layer 146 comprises intrinsic, undoped crystalline silicon (i.e., the silicon layer 146 is substantially free of dopants), or the silicon layer 146 comprises crystalline silicon doped with p-type dopants, n-type dopants, or a combination thereof. In some embodiments, silicon layer 146 is about 1 × 10¹⁴cm^-3To about 1X10²⁰cm^-3A boron-doped silicon layer of boron dopant concentration. In the depicted embodiment, the polysilicon cap layer 148 is undoped or unintentionally doped. In other words, the polysilicon cap layer 148 is substantially free of dopants, and in particular substantially free of boron dopants. The silicon layer 146 has a thickness t3 defined along the z-direction, and the polysilicon cap layer 148 has a thickness along the z-directionA thickness t4 defined in the z-direction. Thickness t4 is less than thickness t3 and less than depth d 1. In some embodiments, the thickness t3 is about 6 μm to about 8 μm. In some embodiments, the thickness t4 is less than about 2 μm. For example, the thickness t4 is about 0.5 μm to about 1 μm. In fig. 4B, the multilayer silicon-containing DTI portion 140B has a substantially uniform width w5 along the depth d 2. In some embodiments, the width w5 is about 0.1 μm to about 1 μm. In such an embodiment, each of the silicon layer 146 and the polysilicon cap layer 148 has a substantially uniform width (e.g., width w5) along the thickness t3 and the thickness t4, respectively.

A transistor 150 is fabricated in the active region 115. In the depicted embodiment, transistor 150 is a high voltage transistor operating at high voltage. The transistor 150 includes a p-well 152 and an n-well 154 disposed in the semiconductor layer 124 of the SOI substrate 105, various doped regions (e.g., p-doped region 160 and n-doped region 162) disposed in the p-well 152, various doped regions (e.g., n-doped region 164) disposed in the n-well 154, and a gate 170 (including, for example, a gate dielectric 172 and a gate electrode 174). Additional isolation structures may be disposed in the active region 115 to separate and isolate device components, such as STI structures 180 disposed in the p-well 152 and STI structures 182 disposed in the n-well 154. The STI isolation structure 130 extends to the p-well 152 and the n-well 154 and is partially disposed in the p-well 152 and the n-well 154, wherein the p-doped region 160 is disposed between the STI structure 130 and the STI structure 180, the n-doped region 164 is disposed between the STI structure 130 and the STI structure 182, and the STI structure 180 is disposed between the p-doped region 160 and the n-doped region 162. In some embodiments, the gate 170 is disposed between a source region and a drain region of the transistor 150, wherein a channel region is formed in the semiconductor layer 124 of the SOI substrate 105 between the source region and the drain region. The gate 170 engages the channel region so that current can flow between the source and drain regions (collectively referred to as source/drain regions) during operation. In some embodiments, the gate 170 further includes gate spacers disposed along sidewalls of the gate dielectric 172 and the gate electrode 174. In some embodiments, contacts are disposed on the p-doped region 160, the n-doped region 162, and/or the n-doped region 164.

FIG. 5 is a view of each of the devices according to the present inventionA schematic cross-sectional view of a portion or the entirety of the IC device 200 of an aspect. For clarity and simplicity, similar components of the IC device 100 in fig. 4A and 4B and the IC device 200 in fig. 5 are denoted by the same reference numerals. For example, the IC device 200 includes an isolation feature 110 disposed in an active region 115 of the SOI substrate 105 and surrounding the active region 115, wherein the isolation feature 110 includes an STI structure 130 and a DTI structure 135. In contrast to the IC device 100, the DTI structure 135 has an oxide DTI portion 140A and a multilayer silicon-containing DTI portion 240B. The multi-layer silicon-containing DTI portion 240B has a dual-layer DTI structure similar to the multi-layer silicon-containing portion 140B, such as a silicon layer 246 and a polysilicon cap layer 248 disposed over the silicon layer 246. Silicon layer 246 is similar to silicon layer 146 described above, and in the depicted embodiment, is a boron doped silicon layer. The polysilicon cap layer 248 is similar to the polysilicon cap layer 148 described above, except that the polysilicon cap layer 248 has a graded boron dopant concentration that decreases from a first boron concentration at the interface between the silicon layer 246 and the polysilicon cap layer 248 to a second boron concentration at the top surface of the polysilicon cap layer 248. In some embodiments, the second boron concentration is zero (or substantially zero). In some embodiments, the second boron concentration is less than or equal to about 1x10¹⁷cm^-3This is low enough to treat the top surface (or the topmost region of the polysilicon layer 248) as undoped and to avoid outgassing of boron during subsequent processing. In some embodiments, the first dopant concentration is about 6 x10¹⁸cm^-3. In fig. 5, the thickness t5 of the silicon layer 246 is less than the thickness t3, and the thickness t6 of the polysilicon cap 248 is greater than the thickness t 4. In some embodiments, thickness t5 is about 4 μm to about 7 μm, and thickness t6 is about 1 μm to about 6 μm. In some embodiments, silicon layer 246 and polysilicon cap layer 248 have a thickness t3 and a thickness t 4. In some embodiments, such as depicted, silicon layer 246 has a substantially uniform boron concentration along its thickness t6, such as a first dopant concentration along its thickness t 6. Fig. 5 has been simplified for clarity to better understand the inventive concepts of the present invention. Additional components may be added to the IC device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 200.

Fig. 6 is a schematic cross-sectional view of a portion or the entirety of an IC device 200 in accordance with various aspects of the invention. For clarity and simplicity, similar components of the IC device 100 in fig. 4A and 4B and the IC device 300 in fig. 6 are denoted by the same reference numerals. For example, the IC device 300 includes an isolation feature 110 disposed in an active region 115 of the SOI substrate 105 and surrounding the active region 115, wherein the isolation feature 110 includes an STI structure 130 and a DTI structure 135. In contrast to the IC device 100, the DTI structure 135 has an oxide DTI portion 140A and a multilayer silicon-containing DTI portion 340B. The multi-layer silicon-containing DTI portion 340B has a tri-layer DTI structure rather than a bi-layer structure as in the multi-layer silicon-containing portion 140B. For example, the multi-layer silicon-containing DTI portion 340B has a double layer silicon layer 346 and a polysilicon cap layer 348. The dual-layer silicon layer 346 includes a silicon layer 346A having a first boron concentration and a silicon layer 346B having a second boron concentration, wherein the silicon layer 346B is disposed between the silicon layer 346A and the polysilicon cap layer 348 and the first boron concentration is greater than the second boron concentration. In some embodiments, silicon layer 346A and silicon layer 346B may be referred to as a heavily doped silicon layer and a lightly doped silicon layer, respectively. The polysilicon cap 348 is similar to the polysilicon cap 148 described above. In the depicted embodiment, the polysilicon cap layer 348 is an undoped polysilicon layer. Silicon layer 346A has a thickness t7, silicon layer 346B has a thickness t8, and the sum of thickness t7 and thickness t8 is equal to thickness t 3. In some embodiments, the thickness t7 is about 4 μm to about 7 μm. In some embodiments, the thickness t8 is about 0.2 μm to about 2 μm. Fig. 3 has been simplified for clarity to better understand the inventive concepts of the present invention. Additional components may be added to the IC device 300 and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 300.

Fig. 7 is a schematic cross-sectional view of a portion or the entirety of an IC device 400 in accordance with various aspects of the invention. For clarity and simplicity, similar components of the IC device 100 in fig. 4A and 4B and the IC device 400 in fig. 7 are denoted by the same reference numerals. For example, the IC device 400 includes an isolation feature 110, the isolation feature 110 disposed in the active region 115 of the SOI substrate 105 and surrounding the active region 115. The isolation features 110 are adjacent to and in contact with the active region 115. Isolation feature 110 includes STI structure 130 and DTI structure 135. In contrast to the IC device 100, the DTI structure 135 has an oxide DTI portion 140A and a multilayer silicon-containing DTI portion 440B. The multi-layer silicon-containing DTI portion 440B has a dual-layer DTI structure similar to the multi-layer silicon-containing portion 140B except that the profile of the multi-layer silicon-containing DTI portion 440B is different from the profile of the multi-layer silicon-containing portion 140B. For example, multi-layer silicon-containing DTI portion 440B includes a silicon layer 446 and a polysilicon cap layer 448 that are similar to silicon layer 146 and polysilicon cap layer 148 (e.g., undoped) or polysilicon cap layer 248 (e.g., graded dopant concentration), respectively, described above, but the width of multi-layer silicon-containing DTI portion 240B varies along depth d2 of DTI structure 135 rather than being substantially uniform along depth d2 as with multi-layer silicon-containing DTI portion 140B. For example, the multilayer silicon-containing DTI portion 440B is divided into a top end T, a bottom end B, and a middle M disposed between the top end T and the bottom end B. The middle has a thickness t9 and a substantially uniform width along its thickness t9, such as width w 5. The tip T has a thickness T10, wherein the width of the tip T decreases along the thickness T10 from a width w6 to a width w 5. The bottom end B has a thickness t11, wherein the width of the bottom end B decreases from a width w5 to a width w7 along the thickness t 11. The multi-layer silicon-containing DTI portion 440B has a wider top end (portion) and a narrower bottom end (portion). In fig. 7, portions of the polysilicon blanket layer 448 and the silicon layer 446 form a top end T. In such embodiments, the silicon layer 446 has an intermediate disposed between the tapered ends. In some embodiments, only the polysilicon blanket 448 forms the top T. Fig. 7 has been simplified for clarity to better understand the inventive concepts of the present invention. Additional components may be added to the IC device 400 and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 400.

Fig. 8 is a schematic cross-sectional view of a portion or the entirety of an IC device 500 in accordance with various aspects of the invention. For clarity and simplicity, similar components of the IC device 100 in fig. 4A and 4B and the IC device 800 in fig. 8 are denoted by the same reference numerals. For example, the IC device 500 includes an isolation feature 110 disposed in an active region 115 of the SOI substrate 105 and surrounding the active region 115, wherein the isolation feature 110 includes an STI structure 130 and a DTI structure 135. In contrast to IC device 100, DTI structure 135 has an oxide DTI portion 140A and a multilayer silicon-containing DTI portion 540B. The multi-layer silicon-containing DTI portion 540B has a three-layer DTI structure similar to the multi-layer silicon-containing portion 340B of the IC device 300 except that the profile of the multi-layer silicon-containing DTI portion 540B is different from the profile of the multi-layer silicon-containing portion 340B. For example, the multi-layer silicon-containing DTI part 540B has a double layer silicon layer 546 (e.g., silicon layer 546A and silicon layer 546B) and a polysilicon cap layer 548. Silicon layer 546A, silicon layer 546B, and polysilicon cap layer 548 are similar to silicon layer 346A, silicon layer 346B, and polysilicon cap layer 348, respectively, as described above, but the width of multi-layer silicon-containing DTI portion 540B varies along depth d2 of DTI structure 135 rather than being substantially uniform along depth d2 as with multi-layer silicon-containing DTI portion 340B. For example, in fig. 8, the multi-layer silicon-containing DTI portion 540B is divided into a top T, a bottom B, and a middle M located between the top T and the bottom B, which are similar to the top T, the bottom B, and the middle M of the multi-layer silicon-containing DTI portion 440B described above. The multi-layer silicon-containing DTI part 540B has a wider top end (portion) and a narrower bottom end (portion). In the depicted embodiment, the polysilicon cap layer 548 and a first portion of the silicon layer 546B form a top end T, a second portion of the silicon layer 546B and a first portion of the silicon layer 546A form an intermediate, and a second portion of the silicon layer 546A forms a bottom. In such an embodiment, each of the silicon layers 546A and 546B has a tapered width portion and a substantially uniform width portion. In some embodiments, only the polysilicon cap layer 548 forms the top end T. In some embodiments, the polysilicon cap layer 548, the silicon layer 546A, and the silicon layer 546B form a top end T. Fig. 8 has been simplified for clarity to better understand the inventive concepts of the present invention. Additional components may be added to the IC device 500 and some of the components described below may be replaced, modified, or eliminated in other embodiments of the IC device 500.

IC device 100, IC device 200, IC device 300, IC device 400, IC device 500, and/or IC device 600 may be included in a microprocessor, memory, and/or other IC device. In some embodiments, IC device 100, IC device 200, IC device 300, IC device 400, IC device 500, and/or IC device 600 may be part of an IC chip, SoC, or portion thereof that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof.

The present invention provides many different embodiments. Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multi-layer silicon-containing isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multi-layer silicon-containing isolation structure includes a top polysilicon portion disposed above a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process and the top polysilicon portion is formed by a non-selective deposition process.

In some embodiments, a semiconductor-on-insulator substrate comprises: a first semiconductor layer; a second semiconductor layer disposed over the first semiconductor layer; and an insulator layer disposed between the first semiconductor layer and the second semiconductor layer. In such an embodiment, the isolation structure extends through the second semiconductor layer and the insulator layer of the semiconductor-on-insulator substrate to the first semiconductor layer of the semiconductor-on-insulator substrate. In some embodiments, the top polysilicon portion has a first thickness, the bottom silicon portion has a second thickness, a sum of the first thickness and the second thickness is equal to a depth of the isolation structure in the semiconductor-on-insulator substrate, and the second thickness is greater than the first thickness. In some embodiments, the bottom silicon portion includes a dopant, such as boron, and the top polysilicon portion is free of the dopant. In some embodiments, the bottom silicon portion includes a first silicon layer having a first dopant concentration and a second silicon layer having a second dopant concentration, the first silicon layer is disposed between the top polysilicon portion and the second silicon layer, and the first dopant concentration is less than the second dopant concentration. In some embodiments, the top polysilicon portion has a graded dopant concentration that decreases from a first dopant concentration at an interface of the top polysilicon portion and the bottom silicon portion to a second dopant concentration at a top surface of the top polysilicon portion. In such embodiments, the topmost surface of the top polysilicon portion may be substantially free of dopants. In some embodiments, the top polysilicon portion has a tapered width. In some embodiments, the bottom silicon portion has a first portion having a first tapered width, a second portion having a substantially uniform width, and a third portion having a second tapered width, wherein the second portion is disposed between the first portion and the third portion.

An exemplary device includes a silicon-on-insulator substrate having a first silicon layer, an insulator layer disposed over the first silicon layer, and a second silicon layer disposed over the insulator layer. The device also includes a first isolation structure and a second isolation structure disposed in the silicon-on-insulator substrate. The first isolation structure extends to a first depth into the silicon-on-insulator substrate and the second isolation structure extends through the first isolation structure to a second depth into the silicon-on-insulator substrate, the second depth being greater than the first depth. The second isolation structure includes a polysilicon cap layer disposed over the silicon layer. The sum of the first thickness of the polysilicon cap layer and the second thickness of the silicon layer is equal to the second depth of the second isolation structure. In some embodiments, the second isolation structure further comprises an oxide layer separating a first sidewall of the polysilicon cap layer from the first isolation structure and further separating a second sidewall of the silicon layer from the first isolation structure and the silicon-on-insulator substrate. In some embodiments, the length of the oxide layer is equal to the second depth of the second isolation structure.

In some embodiments, the first thickness of the polysilicon cap layer is less than the first depth of the first isolation structure. In some embodiments, the first isolation structure and the second isolation structure form an isolation ring surrounding an active region of the silicon-on-insulator substrate. The device may be disposed in the active region. In some embodiments, the second isolation structure is in physical contact with the second silicon layer of the silicon-on-insulator substrate. In some embodiments, the top end of the second isolation structure is wider than the bottom end of the second isolation structure. In some embodiments, the silicon layer is a boron doped silicon layer and the polysilicon cap layer is boron free.

An exemplary method includes receiving a semiconductor-on-insulator substrate comprising a first semiconductor layer, an insulator layer disposed over the first semiconductor layer, and a second semiconductor layer disposed over the insulator layer. The method also includes forming an isolation trench in the semiconductor-on-insulator substrate. An isolation trench extends through the second semiconductor layer and the insulator layer to expose the second semiconductor layer of the semiconductor-on-insulator substrate. The method also includes performing a selective deposition process to form a silicon layer filling a bottom of the isolation trench and performing a non-selective deposition process to form a polysilicon layer filling a top of the isolation trench. In some embodiments, the selective deposition process and the non-selective deposition process are performed in-situ. In some embodiments, performing the selective deposition process comprises using a silicon-containing precursor and an etchant-containing precursor, and performing the non-selective deposition process comprises using the silicon-containing precursor but not the etchant-containing precursor. In some embodiments, the insulator layer is a first insulator layer, and the method may further include forming a second insulator layer along sidewalls of the isolation trench prior to performing the selective deposition process. In such embodiments, the silicon layer fills the remaining portion of the bottom of the isolation trench and the polysilicon layer fills the remaining portion of the top of the isolation trench.

Another exemplary device includes a silicon-on-insulator substrate including a first silicon layer, a second silicon layer disposed over the first silicon layer, and a first insulator layer disposed between the first silicon layer and the second silicon layer. The device also includes a multi-layer polysilicon-containing isolation structure surrounding and isolating the active device region. The multi-layer polysilicon-containing isolation structure extends through the second silicon layer and the first insulator layer of the silicon-on-insulator substrate to the first silicon layer of the silicon-on-insulator substrate. The multi-layer polysilicon containing isolation structure includes a top polysilicon containing portion disposed above a bottom polysilicon containing portion. The top polysilicon containing portion is different from the bottom polysilicon containing portion. The device also includes a second insulator layer disposed between and separating the bottom polysilicon containing portion from the second silicon layer. Second insulationThe bulk layer is also disposed between and separates the top polysilicon containing portion from the second silicon layer. In some embodiments, the top polysilicon containing portion has a first boron concentration, the bottom polysilicon containing portion has a second boron concentration, and the first boron concentration is less than the second boron concentration. In some embodiments, the first boron concentration decreases from an interface between the top and bottom polysilicon containing portions to a topmost surface of the top polysilicon containing portion. In some embodiments, the first boron concentration at the topmost surface of the top polysilicon containing portion is less than about 6 x10¹⁸Atom/cm³. In some embodiments, the total depth of the multi-layer polysilicon containing isolation structure is the sum of a first thickness of the top polysilicon containing portion and a second thickness of the bottom polysilicon containing portion, wherein the first thickness is less than the second thickness.

In some embodiments, the bottom polysilicon containing portion comprises a first bottom polysilicon containing portion and a second bottom polysilicon containing portion. The first bottom polysilicon containing portion is disposed between the second bottom polysilicon containing portion and the top polysilicon containing portion. In such embodiments, the top polysilicon containing portion may have a first boron concentration, the first bottom polysilicon containing portion may have a second boron concentration, and the second bottom polysilicon containing portion may have a third boron concentration, wherein the first boron concentration is less than the second boron concentration and the first boron concentration is less than the third boron concentration. In some embodiments, the second boron concentration of the first bottom polysilicon containing portion is less than the third boron concentration of the second bottom polysilicon containing portion. In some embodiments, the bottom polysilicon containing portion includes a dopant and the top polysilicon containing portion is free of a dopant. In some embodiments, the top polysilicon containing portion comprises a first top polysilicon containing portion and a second top polysilicon containing portion. The first top polysilicon containing portion is disposed between the second top polysilicon containing portion and the bottom polysilicon containing portion. The first top polysilicon containing portion and the bottom polysilicon containing portion are doped layers and the second top polysilicon containing portion is an undoped layer. In some embodiments, a first width of a top end of the multi-layer polysilicon-containing isolation structure is greater than a second width of a bottom end of the multi-layer polysilicon-containing isolation structure. In some embodiments, the first width is tapered. In some embodiments, the second width is tapered. In some embodiments, the multi-layer polysilicon containing isolation structure extends partially through the first silicon layer of the silicon-on-insulator substrate.

Another exemplary method includes providing a silicon-on-insulator substrate comprising a first silicon layer, a second silicon layer disposed over the first silicon layer, and a first insulator layer disposed between the first silicon layer and the second silicon layer. The method also includes forming an isolation trench in the silicon-on-insulator substrate. The isolation trench extends through the second silicon layer and the first insulator layer of the silicon-on-insulator substrate to the first silicon layer of the silicon-on-insulator substrate. The method also includes forming a second insulator layer partially filling the isolation trench and forming a multi-layer polysilicon containing isolation structure over the second insulator layer. The multi-layer polysilicon-containing isolation structure fills the remaining portion of the isolation trench and surrounds and isolates the active device region. In some embodiments, forming the multi-layer polysilicon-containing isolation structure includes performing a selective deposition process to form a first silicon-containing layer over the first silicon layer and the second insulator layer of the silicon-on-insulator substrate, and performing a non-selective deposition process to form a second silicon-containing layer over the first silicon-containing layer and the second insulator layer. The first silicon-containing layer fills a lower portion of the remaining portion of the isolation trench, and the second silicon-containing layer fills an upper portion of the remaining portion of the isolation trench. The method also includes forming a device in the active device region. In some embodiments, parameters of the selective deposition process are adjusted to promote growth of a first silicon-containing layer from a first silicon layer of a silicon-on-insulator substrate. In some embodiments, performing a selective deposition process includes using a deposition precursor and an etch precursor, and performing a non-selective deposition process includes using only a deposition precursor. In some embodiments, performing the selective deposition process further comprises using a dopant precursor. In some embodiments, the selective deposition process and the non-selective deposition process are performed in-situ. In some embodiments, forming the multi-layer polysilicon containing isolation structure further comprises performing a planarization process to remove the second silicon-containing layer from over the top surface of the silicon-on-insulator substrate.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent arrangements do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.