阅读说明：本技术 一种多模式输入的eeprom芯片 (EEPROM chip with multi-mode input ) 是由 王明宇 任卫东 于 2021-05-11 设计创作，主要内容包括：本发明公开了一种多模式输入的EEPROM芯片,特点是包括串行输入模块、并行输入模块、数据选择器、地址译码模块、数据总合模块和存储模块,地址译码模块用于将外部输入的串行数据或并行数据包含的地址信息转换成对应的块选地址信号、行地址信号和具有预设位数的位地址信号,数据选择器用于根据接收到的外部使能信号选择与当前的外部使能信号对应的串行数据或并行数据从数据输出端传输至数据总合模块,数据总合模块根据接收到的行地址信号将接收到的数据扩展到位宽与存储模块的位宽相一致的待存储数据并发送至存储模块,存储模块根据接收到的块选地址信号将待存储数据存储至对应的存储位置；优点是拥有两种不同的输入模式,实用性和切换灵活性较高。(The invention discloses an EEPROM chip with multi-mode input, which is characterized by comprising a serial input module, a parallel input module and a data selector, the device comprises an address decoding module, a data summation module and a storage module, wherein the address decoding module is used for converting address information contained in externally input serial data or parallel data into a corresponding block selection address signal, a row address signal and a bit address signal with a preset bit number; the advantage is that possess two kinds of different input modes, and the practicality is higher with switching flexibility.)

1. An EEPROM chip with multi-mode input is characterized by comprising a serial input module, a parallel input module, a data selector, an address decoding module, a data summation module and a storage module, wherein the address decoding module is used for converting address information contained in externally input serial data or parallel data into corresponding block selection address signals, row address signals and bit address signals with preset bits, the address decoding module respectively sends the bit address signals to the serial input module according to data acquisition clock signals sent from the outside, the row address signals are sent to the parallel input module and the data summation module, the block selection address signals are sent to the storage module, the parallel input module is provided with a parallel data input end with the bits consistent with the preset bits of the bit address signals, the data selector is provided with a first input end, a second input end and a second input end, and the first input end is connected with the second input end through the data summation module and the second input end is connected with the first input end and the second input end, The serial input module is used for receiving externally input serial data corresponding to a data acquisition clock signal according to an externally sent data acquisition clock signal and sending the serial data to the first input end of the data selector according to a bit address signal, the parallel input module is used for receiving externally input parallel data and sending the parallel data to the second input end of the data selector according to a row address signal, the enable signal input end of the data selector is used for receiving an external enable signal, the data selector is used for selecting the serial data or the parallel data corresponding to the current external enable signal according to the received external enable signal and transmitting the serial data or the parallel data to the data summation module from the data output end, and the data summation module expands the received data to be in a bit width phase with the bit width phase of the storage module according to the received row address signal And the consistent data to be stored is sent to the storage module, and the storage module stores the data to be stored to the corresponding storage position according to the received block selection address signal.

2. The EEPROM chip of claim 1, wherein the serial input module includes a first inverter, a second input AND gate, and N NMOS transistors in a number corresponding to a predetermined number of bits of the bit address signal, the parallel input module includes an S input NOR gate, a second inverter, and a first N bit transmission gate, wherein the capacity of each row of the memory module is defined as Y, when Y/N is an integer, S = Y/N, and when Y/N is not an integer, S is an integer greater than and closest to the result obtained by Y/N, the data selector includes a third inverter, a first N bit buffer, a second N bit transmission gate, and a third N bit transmission gate, an input terminal of the first inverter is for receiving an external data collection clock signal, and an output terminal of the first inverter is connected to a first input terminal of the second input AND gate, the second input end of the two-input AND gate is used for receiving serial data input from outside, the output end of the two-input AND gate is connected with the drain electrode of the NMOS tube, the grid electrode of each NMOS tube is used for receiving a corresponding bit signal IN the bit address signals sent by the address decoding module one by one IN sequence, the source electrode of the NMOS tube is connected with an IN pin of the second N-bit transmission gate, the IN pin of the first N-bit transmission gate is used for receiving parallel data input from outside, S input ends of the S-input NOR gate are used for receiving a corresponding bit signal IN the row address signals sent by the address decoding module one by one IN sequence, the output end of the S-input NOR gate, the input end of the second inverter and the GP pin of the first N-bit transmission gate are connected, and the output end of the second inverter is connected with the GN pin of the first N-bit transmission gate, the output pin of the second N-bit transmission gate is connected with the input end of the first N-bit buffer, and the output end of the third N-bit transmission gate is connected with the input end of the second N-bit buffer and the output end of the first N-bit buffer and the output end of the second N-bit buffer is connected with the output end of the second N-bit buffer and serves as the data output end of the data selector.

Technical Field

The invention relates to a memory chip, in particular to an EEPROM chip with multi-mode input.

Background

The EEPROM chip is a charged erasable programmable read-only memory, is a memory chip with no data loss after power failure, can erase existing information on a computer or special equipment, is reprogrammed and is generally used for plug and play.

The traditional EEPROM chip is divided into a serial EEPROM chip and a parallel EEPROM chip, wherein the data input/output of the serial EEPROM chip is carried out by 2-wire, 3-wire, 4-wire or SPI bus interface mode when the serial EEPROM chip reads and writes, and the data input/output of the parallel EEPROM chip is carried out by the parallel bus; the serial and parallel have respective advantages and disadvantages, and the serial interface EEPROM chip has the highest flexibility, fewer pins, smaller package and lower power consumption in the currently used nonvolatile memory, and is widely applied to relevant markets of automobiles, telecommunications, medical treatment, industry, personal computers and the like; the parallel interface EEPROM chip has higher flexibility, and is characterized by long data retention, high reliability, and faster than the serial interface protocol, and can be widely applied to aviation and military application; due to the difference between the two input forms, the timing of the serial input and the timing of the parallel input of the EEPROM are incompatible from the viewpoint of the operation timing.

Disclosure of Invention

The technical problem to be solved by the invention is to provide the multi-mode input EEPROM chip with two different input modes, namely a serial input mode and a parallel input mode, which does not need different time sequence relations and improves the practicability and switching flexibility of the EEPROM chip.

The technical scheme adopted by the invention for solving the technical problems is as follows: an EEPROM chip with multi-mode input comprises a serial input module, a parallel input module, a data selector, an address decoding module, a data summation module and a storage module, wherein the address decoding module is used for converting address information contained in externally input serial data or parallel data into corresponding block selection address signals, row address signals and bit address signals with preset bits, the address decoding module respectively sends the bit address signals to the serial input module according to data acquisition clock signals sent externally, sends the row address signals to the parallel input module and the data summation module, and sends the block selection address signals to the storage module, the parallel input module is provided with a parallel data input end with the bits consistent with the preset bits of the bit address signals, the data selector is provided with a first input end, a second input end, a third input end and a fourth input end, and the fourth input end is connected with the serial input module and the serial input module respectively, The serial input module is used for receiving externally input serial data corresponding to a data acquisition clock signal according to an externally sent data acquisition clock signal and sending the serial data to the first input end of the data selector according to a bit address signal, the parallel input module is used for receiving externally input parallel data and sending the parallel data to the second input end of the data selector according to a row address signal, the enable signal input end of the data selector is used for receiving an external enable signal, the data selector is used for selecting the serial data or the parallel data corresponding to the current external enable signal according to the received external enable signal and transmitting the serial data or the parallel data to the data summation module from the data output end, and the data summation module expands the received data to be in a bit width phase with the bit width phase of the storage module according to the received row address signal And the consistent data to be stored is sent to the storage module, and the storage module stores the data to be stored to the corresponding storage position according to the received block selection address signal.

The serial input module comprises a first inverter, a second input AND gate and N NMOS tubes, the number of the NMOS tubes is consistent with the preset number of bits of a bit address signal, the parallel input module comprises an S input NOR gate, a second inverter and a first N bit transmission gate, wherein the capacity of each row of the storage module is defined as Y, when Y/N is an integer, S = Y/N, when Y/N is not an integer, S is an integer which is larger than the result obtained by Y/N and is closest to the result, the data selector comprises a third inverter, a first N bit buffer, a second N bit transmission gate and a third N bit transmission gate, the input end of the first inverter is used for receiving an external data acquisition clock signal, the output end of the first inverter is connected with the first input end of the second input AND gate, the second input end of the second input AND gate is used for receiving external input serial data, the output end of the second input AND gate is connected with the drain electrode of the NMOS tube, the grid electrode of each NMOS tube is used for receiving a corresponding bit signal IN the bit address signals sent by the address decoding module one by one IN sequence, the source electrode of each NMOS tube is connected with the IN pin of the second N-bit transmission gate, the IN pin of the first N-bit transmission gate is used for receiving externally input parallel data, the S input ends of the S input NOR gate are used for receiving a corresponding bit signal IN the row address signals sent by the address decoding module one by one IN sequence, the output end of the S input NOR gate, the input end of the second inverter and the GP pin of the first N-bit transmission gate are connected, the output end of the second inverter is connected with the GN pin of the first N-bit transmission gate, the OUT pin of the first N-bit transmission gate is connected with the IN pin of the third N-bit transmission gate, the input end of the third inverter, the GP pin of the second N-bit transmission gate, and the GN pin of the third N-bit transmission gate are connected and used for accessing an external enable signal, the output end of the third inverter, the GN pin of the second N-bit transmission gate, and the GP pin of the third N-bit transmission gate are connected, the OUT pin of the second N-bit transmission gate is connected with the input end of the first N-bit buffer, the OUT pin of the third N-bit transmission gate is connected with the input end of the second N-bit buffer, and the output end of the first N-bit buffer and the output end of the second N-bit buffer are connected and used as the data output end of the data selector. The serial input module consists of a 1-bit phase inverter, a 1-bit AND gate and N NMOS (N-channel metal oxide semiconductor) tubes, and is matched with an externally input bit address signal to realize serial time sequence input of data through the switching characteristic of the NMOS; the parallel input module is composed of an S input NOR gate, an inverter and an N bit transmission gate which are respectively responsible for logic relation processing and data transmission, and the parallel input of N bit data is realized by cooperation with an externally input row address signal; the data selector mainly comprises a 1-bit inverter, 2N-bit BUFs and 2N-bit transmission gates which are respectively responsible for logic processing, data stabilization and data transmission, and controls the on and off of the transmission gates through the high and low levels of enable signals to realize data gating.

Compared with the prior art, the invention has the advantages that the invention has two different input modes of a serial input mode and a parallel input mode, does not need different time sequence relations and improves the practicability of the EEPROM chip; meanwhile, the input mode is freely switched under the control of an externally input enable signal, so that the method has better flexibility; in addition, the method can be directly established on the basis of the structure of the EEPROM chip in the original serial input mode, the internal structures of the data master module and the storage module are basically not changed, and the number of MOS (metal oxide semiconductor) tubes is not greatly increased, so that the power consumption and the area are smaller, and the cost is lower;

the address decoding module respectively generates a bit address signal and a row address signal, the data input of the serial input module is 1-bit serial data, the bit address signal can be input by adopting an 8-bit address signal, the data acquisition clock signal is responsible for matching the serial data with the bit address signal so that the data can complete the continuous input of 1bit, when the serial input mode is selected under the control of the enable signal, the data output by the serial input module is selected, the row to be written is selected by the corresponding row address at the moment, the N-bit data are sequentially written into the row, the change of the row address is written into the other row after the writing is completed, the writing of the S row is sequentially realized, and the storage of the serial data is realized; similarly, the data input of the parallel input module is 8-bit data, when the parallel input mode is selected by the enable signal control, the data output by the parallel input module is selected, at this time, although the data of N bits reaches the data summation module at one time, because the data input is N bits simultaneous writing, namely one line simultaneous writing, the control of a bit address signal is not needed, and the line address signal is directly used for realizing 1 line simultaneous writing, so that the written data is ensured to be correct, at this moment, it needs to be noted that when each line address is stable, the stability of the data input should be kept, and the stable time enables the parallel integral writing time and the serial writing time to be consistent, so that the problem of time sequence conflict is solved, and further circuit change and time sequence modification are not needed; and finally, the data enters a storage module for storage.

Drawings

FIG. 1 is a block diagram of the overall structure of the present invention;

FIG. 2 is a circuit diagram of the serial input module according to the present invention;

FIG. 3 is a circuit diagram of a parallel input module according to the present invention;

fig. 4 is a circuit configuration diagram of a data selector in the present invention.

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.

As shown in figure 1, the EEPROM chip with multi-mode input comprises a serial input module 1, a parallel input module 2, a data selector 3, an address decoding module 4, a data summation module 5 and a storage module 6, wherein the address decoding module 4 is used for converting address information contained in externally input serial data or parallel data into corresponding block selection address signals, row address signals and bit address signals with preset bits, the address decoding module 4 respectively sends the bit address signals to the serial input module 1 according to externally sent data acquisition clock signals, the row address signals are sent to the parallel input module 2 and the data summation module 5, the block selection address signals are sent to the storage module 6, the parallel input module 2 is provided with a parallel data input end with the same number of bits as the preset bits of the bit address signals, the data selector 3 is provided with a first input end, the data selector 3 is provided with a second input end, and the data selector 3 is connected with a second input end, A second input end, an enable signal input end and a data output end, the serial input module 1 is used for receiving externally input serial data corresponding to a data acquisition clock signal according to the externally transmitted data acquisition clock signal and transmitting the serial data to the first input end of the data selector 3 according to a bit address signal, the parallel input module 2 is used for receiving externally input parallel data and transmitting the parallel data to the second input end of the data selector 3 according to a row address signal, the enable signal input end of the data selector 3 is used for receiving an external enable signal, the data selector 3 is used for selecting the serial data or the parallel data corresponding to the current external enable signal according to the received external enable signal and transmitting the serial data or the parallel data to the data output end to the data summation module 5, the data summation module 5 expands the received data to be stored which is consistent with the bit width of the storage module 6 according to the received row address signal and transmits the data to the storage module 6, and the storage module 6 stores the data to be stored to the corresponding storage position according to the received block selection address signal.

As shown in fig. 2 to 4, the serial input block 1 includes a first inverter INV1, a two-input AND gate AND1, AND N NMOS transistors QN of which number is identical to a preset number of bits of a bit address signal, the parallel input block 2 includes an S-input NOR gate NOR1, a second inverter INV2, AND a first N-bit transfer gate Q1, wherein capacity per row of the memory block 6 is defined as Y, S = Y/N when Y/N is an integer, S is an integer greater than AND closest to the result obtained by Y/N when Y/N is not an integer, the data selector 3 includes a third inverter INV3, a first N-bit buffer BUF1, a second N-bit buffer BUF2, a second N-bit transfer gate Q2, AND a third N-bit transfer gate Q3, an input terminal of the first inverter INV1 is configured to receive an external data collection clock signal, an output terminal of the first inverter INV1 is connected to a first input terminal of the second AND gate QN 1, a second input terminal of the two-input AND gate AND1 is used for receiving serial data inputted externally, an output terminal of the two-input AND gate AND1 is connected to the drain of the NMOS transistor QN, the gate of each NMOS transistor QN is used for receiving a corresponding one-bit signal of the bit address signal sent by the address decoding block 4 one by one IN sequence, the source of the NMOS transistor QN is connected to the IN pin of the second N-bit transfer gate Q2, the IN pin of the first N-bit transfer gate Q1 is used for receiving parallel data inputted externally, the S input terminals of the S-input NOR gate NOR1 are used for receiving a corresponding one-bit signal of the row address signal sent by the address decoding block 4 one by one IN sequence, the output terminal of the S-input NOR gate NOR1, the input terminal of the second inverter INV2 AND the GP pin of the first N-bit transfer gate Q1 are connected, the output terminal of the second inverter INV2 is connected to the GN pin of the first N-bit transfer gate Q1, the OUT pin of the first N-bit transfer gate Q1 is connected to the IN pin of the third N-bit transfer gate Q3, an input terminal of the third inverter INV3, a GP pin of the second N-bit transfer gate Q2, a GN pin of the third N-bit transfer gate Q3 are connected and used for receiving an external enable signal, an output terminal of the third inverter INV3, a GN pin of the second N-bit transfer gate Q2, and a GP pin of the third N-bit transfer gate Q3 are connected, an OUT pin of the second N-bit transfer gate Q2 is connected with an input terminal of the first N-bit buffer BUF1, an OUT pin of the third N-bit transfer gate Q3 is connected with an input terminal of the second N-bit buffer BUF2, and an output terminal of the first N-bit buffer BUF1 and an output terminal of the second N-bit buffer BUF2 are connected and serve as a data output terminal of the data selector 3.

The specific principle is as follows:

the serial input module 1 is used for acquiring serial Data through a Data acquisition clock signal wrBF transmitted from the outside, the Data of N bits output after the Data acquired by the serial input module 1 is acquired by matching with a bit address signal is defined as Data _ A < N-1:0>, wherein N is a preset bit number of the bit address signal and can be selected by oneself, the parallel input module 2 is used for inputting N bits and is used for acquiring parallel Data, and the Data acquired and output by the parallel input module 2 is defined as Data _ B < N-1:0 >; respectively inputting Data _ A < N-1:0> and Data _ B < N-1:0> into the Data selector 3, defining an enabling signal of the Data selector 3 as Data _ input _ sel, selecting one Data corresponding to the Data _ input _ sel in the preset state and taking the selected Data as the output of the Data selector 3, marking the selected Data as Data _2_1< N-1:0>, combining the corresponding row address signal and bit address signal into the storage module 6 by Data _2_1< N-1:0>, and then erasing the corresponding address Data by matching with the high voltage generated by the charge pump to finish the writing process of the Data into the storage module 6; the Data _ input _ sel is a voltage signal, when the Data _ input _ sel is a high-level signal, Data _ A < N-1:0> is selected, namely the input mode is a serial input mode, and when the Data _ input _ sel is a low-level signal, Data _ B < N-1:0> is selected, namely the input mode is a parallel input mode;

the used data acquisition clock wrBF signal has obvious effect when being selected as serial input, serial data is input bit by bit along with the change of wrBF, but when the data is input in parallel, the data is input with N bits, the wrBF signal is mainly used for the logic relation with a byte address signal at the moment, and the signal obtained after the logic relation can carry out time sequence control on the parallel data, namely one byte address corresponds to the input of one byte data;

the row address bit width is mainly determined by the storage capacity of the storage module 6 required by the EEPROM, assuming that the storage module 6 has a capacity of X × Y bit, and X rows are total, and the capacity of each row is Y bit, at this time, the corresponding row address is S, if the S result is between two adjacent integers, a larger integer is taken as the row address bit width, that is, assuming that X =16, Y =33, and N =8, and the row address bit width is calculated to be 5 bits, that is, S = 5.