Electronic paper panel with high pixel capacitance and manufacturing method thereof
阅读说明：本技术 一种高像素电容的电子纸面板及其制作方法 (Electronic paper panel with high pixel capacitance and manufacturing method thereof ) 是由 何维 胡自萍 于 2021-10-12 设计创作，主要内容包括：本发明公开了一种高像素电容的电子纸面板及其制作方法,电子板面板包括：基板；基板上间隔设置栅极层和第二像素电极；栅极层和第二像素电极上方设有绝缘层,绝缘层内设有与栅极层相匹配的源极层、漏极层和半导体层,第二像素电极上方的绝缘层内设有公共电极；绝缘层上方设有第一像素电极,绝缘层内设有一用于连接第一像素电极和漏极层的第一过孔以及一用于连接第一像素电极和第二像素电极的第二过孔。本发明在相同面积下的基板上,通过增设第二像素电极,同时与第一像素电极连接,使公共电极能够与第一像素电极和第二像素电极形成像素电容,提高像素电容大小。(The invention discloses an electronic paper panel with high pixel capacitance and a manufacturing method thereof, wherein the electronic paper panel comprises: a substrate; a grid layer and a second pixel electrode are arranged on the substrate at intervals; an insulating layer is arranged above the gate layer and the second pixel electrode, a source electrode layer, a drain electrode layer and a semiconductor layer which are matched with the gate layer are arranged in the insulating layer, and a common electrode is arranged in the insulating layer above the second pixel electrode; a first pixel electrode is arranged above the insulating layer, and a first through hole and a second through hole are arranged in the insulating layer and used for connecting the first pixel electrode and the drain layer. According to the invention, the second pixel electrode is additionally arranged on the substrate with the same area and is simultaneously connected with the first pixel electrode, so that the common electrode, the first pixel electrode and the second pixel electrode can form a pixel capacitor, and the size of the pixel capacitor is improved.)
1. The utility model provides a high pixel capacitance's electronic paper panel which characterized in that: the electronic board panel includes:
a substrate (1);
a grid layer (21) and a second pixel electrode (3) are arranged on the substrate (1) at intervals;
an insulating layer is arranged above the gate layer (21) and the second pixel electrode (3), a source layer (22), a drain layer (23) and a semiconductor layer (24) which are matched with the gate layer (21) are arranged in the insulating layer, the source layer (22) and the drain layer (23) are respectively connected with two sides of the semiconductor layer (24), and a common electrode (4) is arranged in the insulating layer above the second pixel electrode (3);
a first pixel electrode (8) is arranged above the insulating layer, and a first through hole (91) and a second through hole (92) are arranged in the insulating layer and used for connecting the first pixel electrode (8) and the drain layer (23) and the first pixel electrode (8) and the second pixel electrode (3).
2. The electronic paper panel with high pixel capacitance of claim 1, wherein: the insulating layer includes a first insulating layer (5), and the first insulating layer (5) is provided between the second pixel electrode (3) and the common electrode (4), between the source layer (22) and the substrate (1), between the drain layer (23) and the substrate (1), and between the semiconductor layer (24) and the gate layer (21).
3. The electronic paper panel with high pixel capacitance of claim 2, wherein: the insulating layer further comprises a second insulating layer (6), the second insulating layer (6) being arranged between the common electrode (4) and the first pixel electrode (8) and between the source layer (22), the drain layer (23) and the semiconductor layer (24) and the first pixel electrode (8).
4. The electronic paper panel with high pixel capacitance of claim 3, wherein: the insulating layer further comprises a third insulating layer (7), the third insulating layer (7) being arranged between the second insulating layer (6) and the first pixel electrode (8).
5. The electronic paper panel with high pixel capacitance as claimed in claim 4, wherein: be equipped with a through-hole in third insulating layer (7), the through-hole is located second insulating layer (6) top at common electrode (4) place, be equipped with bodiness first pixel electrode (91) in the through-hole, bodiness first pixel electrode (91) upper end is connected with first pixel electrode (8), bodiness first pixel electrode (91) lower extreme and second insulating layer (6) butt.
6. The electronic paper panel with high pixel capacitance of claim 5, wherein: the first via hole (91) and the second via hole (92) are arranged on the second insulating layer (6), the first via hole (91) is used for connecting the thickened first pixel electrode (91) above the second insulating layer (6) and the drain layer (23) below the second insulating layer (6), and the second via hole (92) is used for connecting the thickened first pixel electrode (91) above the second insulating layer (6) and the second pixel electrode (3) below the second insulating layer (6).
7. The electronic paper panel with high pixel capacitance of claim 1, wherein: the common electrode (4) is positioned right above the second pixel electrode (3), and any cross section area of the common electrode (4) is smaller than any cross section area of the second pixel electrode (3).
8. A manufacturing method of an electronic paper panel with high pixel capacitance is characterized by comprising the following steps: the method comprises the following steps:
s1, providing a substrate (1), and forming a gate layer (21) and a second pixel electrode (3) on the substrate (1) at intervals;
s2, arranging a first insulating layer (5) on the grid layer (21) and the second pixel electrode (3); providing a semiconductor layer (24) over the first insulating layer (5) on which the gate layer (21) is located;
s3, forming a common electrode (4) on the first insulating layer (5) where the second pixel electrode (3) is located, forming a source layer (22) and a drain layer (23) on the semiconductor layer (24), wherein the source layer (22) is connected with one side of the semiconductor layer (24), and the drain layer (23) is connected with the other side of the semiconductor layer (24);
s4, forming a second insulating layer (6) on the common electrode (4), the source layer (22), the drain layer (23) and the semiconductor layer (24), forming a first via hole (91) connected with the drain layer (23) in the second insulating layer (6), and forming a second via hole (92) connected with the second pixel electrode (3) in the second insulating layer (6);
and S5, manufacturing and forming a first pixel electrode (8) on the second insulating layer (6), wherein the first pixel electrode (8) is connected with the drain layer (23) through a first through hole (91), and the first pixel electrode (8) is connected with the second pixel electrode (3) through a second through hole (92).
9. The method for manufacturing the electronic paper panel with high pixel capacitance according to claim 8, wherein the method comprises the following steps: a third insulating layer (7) is formed on the second insulating layer (6), and then a first pixel electrode (8) is formed on the third insulating layer (7).
10. The method for manufacturing the electronic paper panel with high pixel capacitance according to claim 9, wherein the method comprises the following steps: the third insulating layer (7) is provided with a through hole above the second insulating layer (6) where the partial area or the whole area of the drain layer (23) is located, the third insulating layer (7) is also provided with a through hole above the second insulating layer (6) where the partial area or the whole area of the common electrode (4) is located, and the first pixel electrode (8) is also abutted to the second insulating layer (6) through the through hole.
Technical Field
The invention relates to the field of electronic paper display, in particular to an electronic paper panel with high pixel capacitance and a manufacturing method thereof.
Background
The electronic paper display mode is different from the conventional LCD liquid crystal, the refresh frequency is very low, but the pixel needs to keep the electric potential for a long time after being charged, so the pixel of the electronic paper panel usually needs to be designed with a larger pixel capacitor. In the conventional design, the first metal layer is used as a common electrode, and the second metal layer (thin film transistor layer) and the pixel ITO (Indium Tin Oxide, ITO for short) are connected through a via hole to be used as a pixel electrode. A pixel capacitor is formed between the pixel electrode and the common electrode to store charges. When the pixel size is small, the first metal layer and the second metal layer serving as the capacitor portion have a limited area, and the capacitance may be insufficient.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the electronic paper panel with the high pixel capacitance is provided, and the problem that the pixel capacitance of the electronic paper panel is insufficient in conventional design when the pixel size is small is solved.
The technical scheme adopted by the invention for solving the problems is as follows: the electronic board panel includes: a substrate; a grid layer and a second pixel electrode are arranged on the substrate at intervals; an insulating layer is arranged above the gate layer and the second pixel electrode, a source electrode layer, a drain electrode layer and a semiconductor layer which are matched with the gate layer are arranged in the insulating layer, the source electrode layer and the drain electrode layer are respectively connected with two sides of the semiconductor layer, and a common electrode is arranged in the insulating layer above the second pixel electrode; the pixel structure comprises an insulating layer, a drain layer and a first pixel electrode, wherein the insulating layer is provided with a first through hole and a second through hole, the first pixel electrode is arranged above the insulating layer, and the first through hole is used for connecting the first pixel electrode with the drain layer.
Compared with the prior art, the invention has the advantages that: on the substrate with the same area, the second pixel electrode is additionally arranged and is simultaneously connected with the first pixel electrode, so that the common electrode, the first pixel electrode and the second pixel electrode can form a pixel capacitor, and the size of the pixel capacitor is improved; meanwhile, the first pixel electrode and the second pixel electrode are respectively arranged on the upper side and the lower side of the common electrode, so that the interference between the first pixel electrode and the second pixel electrode is avoided.
Preferably, the insulating layer includes a first insulating layer disposed between the second pixel electrode and the common electrode, between the source layer and the substrate, between the drain layer and the substrate, and between the semiconductor layer and the gate layer. Therefore, the second pixel electrode and the common electrode can be combined to form a pixel capacitor through the arrangement of the first insulating layer, so that the effective area of the whole pixel capacitor is increased, and the capacitance value of the whole pixel capacitor is improved; meanwhile, the connection among the grid layer, the source layer, the drain layer and the semiconductor layer can be isolated, and the thin film transistor can work as a thin film transistor.
Preferably, the insulating layer includes a second insulating layer disposed between the common electrode and the first pixel electrode and between the source layer, the drain layer, and the semiconductor layer and the first pixel electrode. Therefore, the second insulating layer is arranged, so that the common electrode and the first pixel electrode can be combined to form a pixel capacitor, and the second pixel electrode is combined to obtain a larger effective area of the pixel capacitor and improve the capacitance value of the whole pixel capacitor; while the second insulating layer also serves to isolate the source layer, the drain layer and the influence between the semiconductor layer and the first pixel electrode.
Preferably, the insulating layer includes a third insulating layer disposed between the second insulating layer and the first pixel electrode. Therefore, the third insulating layer is further added, so that the operation of the thin film transistor is ensured not to influence the first pixel electrode.
Preferably, a through hole is formed in the third insulating layer, the through hole is located above the second insulating layer where the common electrode is located, a thickened first pixel electrode is arranged in the through hole, the upper end of the thickened first pixel electrode is connected with the first pixel electrode, and the lower end of the thickened first pixel electrode is abutted to the second insulating layer. Therefore, the through holes are formed, so that the corresponding areas of the first pixel electrode and the common electrode can be directly abutted by the second insulating layer, the distance between the first pixel electrode and the drain layer and between the first pixel electrode and the common electrode is reduced, and the capacitance value of the pixel capacitor is improved.
Preferably, the first via hole and the second via hole are disposed on the second insulating layer, the first via hole is used for connecting the thickened first pixel electrode above the second insulating layer and the drain layer below the second insulating layer, and the second via hole is used for connecting the thickened first pixel electrode above the second insulating layer and the second pixel electrode below the second insulating layer. Therefore, the first via hole and the second via hole are directly arranged in the second insulating layer, the arrangement of multiple layers of via holes is reduced, and the manufacture is convenient.
Preferably, the common electrode is located right above the second pixel electrode, and any cross-sectional area of the common electrode is smaller than any cross-sectional area of the second pixel electrode. Therefore, the area of the second pixel electrode is larger than that of the common electrode, the effective area of the capacitor between the second pixel electrode and the common electrode can be increased to the maximum extent, and the capacity of the pixel capacitor for storing charges is improved.
The second technical problem to be solved by the present invention is: the method for manufacturing the electronic paper panel with the high pixel capacitance is provided, and the problem that the pixel capacitance of the electronic paper panel is insufficient in conventional design when the pixel size is small is solved.
The technical scheme adopted by the invention for solving the problems is as follows: a manufacturing method of an electronic paper panel with high pixel capacitance comprises the following steps:
s1, providing a substrate, and forming a gate layer and a second pixel electrode on the substrate at intervals;
s2, disposing a first insulating layer on the gate layer and the second pixel electrode; a semiconductor layer is arranged above the first insulating layer where the grid layer is located;
s3, forming a common electrode on the first insulating layer where the second pixel electrode is located, forming a source electrode layer and a drain electrode layer on the semiconductor layer, wherein the source electrode layer is connected with one side of the semiconductor layer, and the drain electrode layer is connected with the other side of the semiconductor layer;
s4, forming a second insulating layer on the common electrode, the source layer, the drain layer and the semiconductor layer, forming a first via hole connected with the drain layer in the second insulating layer, and forming a second via hole connected with the second pixel electrode in the second insulating layer;
and S5, forming a first pixel electrode on the second insulating layer, wherein the first pixel electrode is connected with the drain layer through the first via hole, and the first pixel electrode is connected with the second pixel electrode through the second via hole.
Thus, the pixel capacitance can be greatly improved without changing the common photomask process and the technique of the electronic paper panel. A second pixel electrode is additionally arranged to form a pixel capacitor with the common electrode, so that the charge storage capacity of the pixel capacitor is improved; the common electrode is arranged in the same layer with the grid layer, the common electrode is modified to be arranged in the same layer with the source layer and the drain layer, the second pixel electrode occupies space, the upper side face and the lower side face of the common electrode are fully utilized, the upper side face of the common electrode and the first pixel electrode form a pixel capacitor, the lower side face of the common electrode and the second pixel electrode also form a pixel capacitor, the effective area of the pixel electrode is increased, and the utilization rate is increased.
Preferably, a third insulating layer is formed on the second insulating layer, and then the first pixel electrode is formed on the third insulating layer. Therefore, the third insulating layer is further added to ensure that the operation of the thin film transistor influences the first pixel electrode.
Preferably, the third insulating layer forms a through hole above the second insulating layer in which the partial region or the entire region of the drain layer is located, the third insulating layer forms a through hole above the second insulating layer in which the partial region or the entire region of the common electrode is located, and the first pixel electrode penetrates the through hole and abuts against the second insulating layer. Therefore, the through holes are formed, so that the corresponding areas of the first pixel electrode, the drain layer and the common electrode can be directly abutted through the second insulating layer, the distance between the first pixel electrode and the drain layer and between the first pixel electrode and the common electrode is reduced, and the capacitance value of the pixel capacitor is improved.
Drawings
FIG. 1 is a schematic diagram of a second pixel electrode and a gate layer in an electronic paper panel with high pixel capacitance according to the present invention;
FIG. 2 is a schematic diagram of a structure of a semiconductor layer covering a gate layer in the high pixel capacitance electronic paper panel according to the present invention;
FIG. 3 is a schematic diagram of the thin film transistor and common electrode structure in the high pixel capacitance electronic paper panel of the present invention;
FIG. 4 is a schematic diagram of the connection of the first via and the second via in the high pixel capacitance electronic paper panel of the present invention;
FIG. 5 is a schematic diagram of the connection of a third insulating layer structure in the electronic paper panel with high pixel capacitance according to the present invention;
FIG. 6 is a schematic diagram of the overall structure of the high pixel capacitance electronic paper panel of the present invention;
fig. 7 is a cross-sectional view of the high pixel capacitance electronic paper panel of the present invention.
The reference numbers in the figures illustrate: 1. the pixel structure comprises a substrate, 2, a thin film transistor, 21, a gate layer, 22, a source layer, 23, a drain layer, 24, a semiconductor layer, 3, a second pixel electrode, 4, a common electrode, 5, a first insulating layer, 6, a second insulating layer, 7, a third insulating layer, 8, a first pixel electrode, 81, a thickened first pixel electrode, 91, a first via hole, 92 and a second via hole.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. Embodiments of the present invention are further described below with reference to the accompanying drawings.
Example one
As shown in fig. 1 to 7, the present embodiment relates to an electronic paper panel with high pixel capacitance, the electronic paper panel including:
a substrate 1;
a gate layer 21 and a second pixel electrode 3 are arranged on the substrate 1 at intervals;
an insulating layer is arranged above the gate layer 21 and the second pixel electrode 3, a source layer 22, a drain layer 23 and a semiconductor layer 24 which are matched with the gate layer 21 are arranged in the insulating layer, the semiconductor layer 24 is arranged above the gate layer 21, the source layer 22 and the drain layer 23 are arranged above the semiconductor layer 24 and are respectively connected with two sides of the semiconductor layer 24, and a common electrode 4 is arranged in the insulating layer above the second pixel electrode 3;
the first pixel electrode 8 is disposed above the insulating layer, a first via hole 91 for connecting the first pixel electrode 8 and the drain layer 23 is disposed in the insulating layer, and a second via hole 92 for connecting the first pixel electrode 8 and the second pixel electrode 3 is also disposed in the insulating layer.
In the present embodiment, the gate layer 21, the source layer 22, the drain layer 23 and the semiconductor layer 24 are all internal structures of the thin film transistor 2, and the internal structures are conventional in design and will not be described in detail herein. The thin film transistor 2 and the common electrode 4 are both arranged in the insulating layer, and are not overlapped and connected. The common electrode 4 is disposed under the thin film transistor 2, compared to the conventional thin film transistor 2 covering the entire substrate 1. According to the design, the thin film transistor 2 and the common electrode 4 are separately arranged on the same layer, the common electrode 4 is used for replacing a part of the coverage area of the traditional thin film transistor 2, and the second pixel electrode 3 is used for replacing the position of the traditional common electrode 4, so that the whole thickness of the electronic paper panel is unchanged.
The drain layer 23 is connected to the first pixel electrode 8 through the first via hole 91. When a positive voltage is input to the gate layer 21 and a voltage is input to the source layer 22, the TFT 2 is turned on to charge the drain layer 23, and the drain layer 23 is connected to the first pixel electrode 8 through the first via 91, so that a pixel capacitor is formed between the first pixel electrode 8 and the common electrode 4 to store the charges.
On the substrate 1 with the same area, the effective area of the pixel capacitor is increased by adding the second pixel electrode 3. In the conventional design, the first pixel electrode 8 is connected to the drain layer 23 of the tft 2 through a via hole, and a pixel capacitor is formed between the common electrode 4 and the first pixel electrode 8, which has a limited effective area.
In this embodiment, the added second pixel electrode 3 is disposed on the other side of the common electrode 4, the second pixel electrode 3 is connected to the first pixel electrode 8 through a via hole, and the effective area includes a pixel capacitor formed between the common electrode 4 and the first pixel electrode 8 and a pixel capacitor formed between the common electrode 4 and the second pixel electrode 3, so that the effective area is greatly increased, and the capacitance value of the pixel capacitor is also increased. Meanwhile, the first pixel electrode 8 and the second pixel electrode 3 are respectively arranged at the upper side and the lower side of the common electrode 4, so that the interference between the first pixel electrode 8 and the second pixel electrode 3 is avoided.
Wherein the insulating layer includes a first insulating layer 5, and the first insulating layer 5 is disposed between the second pixel electrode 3 and the common electrode 4, between the source layer 22 and the substrate 1, between the drain layer 23 and the substrate 1, and between the semiconductor layer 24 and the gate layer 21.
The common electrode 4 and the second pixel electrode 3 are insulated by the first insulating layer 5, so that a pixel capacitor can be formed between the common electrode 4 and the second pixel electrode 3. Further, the capacitance value of the pixel capacitance formed between the common electrode 4 and the second pixel electrode 3 can be changed by changing the thickness of the first insulating layer 5 between the common electrode 4 and the second pixel electrode 3.
The electronic paper panel manufactured by the high-pixel capacitor has enough charge storage capacity, so that the potential can be kept, the electronic paper panel can be reliably driven to display, and the stability of the display effect is ensured. In the present embodiment, a glass substrate may be used as the substrate 1.
Meanwhile, the first insulating layer 5 may also isolate the connection among the gate layer 21, the source layer 22, the drain layer 23, and the semiconductor layer 24, thereby ensuring that the tft 2 can operate as a thin film transistor.
In practical design, the first insulating layer 5 between the second pixel electrode 3 and the common electrode 4, the first insulating layer 5 between the source layer 22 and the substrate 1, the first insulating layer 5 between the drain layer 23 and the substrate 1, and the first insulating layer 5 between the semiconductor layer 24 and the gate layer 21 may all be connected into a whole, which is convenient for manufacturing.
In the present embodiment, both the gate layer 21 and the second pixel electrode 3 are directly disposed on the substrate 1. The manufacturing and forming in the same manufacturing process are facilitated, the observation is also facilitated, and the grid layer 21 and the second pixel electrode 3 are not overlapped.
Wherein the insulating layer includes a second insulating layer 6, and the second insulating layer 6 is disposed between the common electrode 4 and the first pixel electrode 8, and between the source layer 22, the drain layer 23, and the semiconductor layer 24 and the first pixel electrode 8. The second insulating layer 6, like the first insulating layer 5, also serves as an isolation insulating function to ensure that the common electrode 4 and the first pixel electrode 8 can form a pixel electrode.
The common electrode 4, the gate layer 21, the source layer 22, the drain layer 23, and the semiconductor layer 24 are all disposed between the first insulating layer 5 and the second insulating layer 6. In the actual production process, for the convenience of design, the insulating glue used by the second insulating layer 6 and the first insulating layer 5 is the same, so that when the laminating manufacture is carried out, the first insulating layer 5 and the second insulating layer 6 can be combined at the part connected together, the thin film transistor 2 and the common electrode 4 between the two can be wrapped, and the insulating effect is better.
Wherein the insulating layer comprises a third insulating layer 7, and the third insulating layer 7 is disposed between the second insulating layer 6 and the first pixel electrode 8. By further adding the third insulating layer 7, it is ensured that the operation of the thin film transistor 2 does not affect the first pixel electrode 8. The material of the third insulating layer 7 is different from that used for the second insulating layer 6 in order to further improve the insulating property.
As an embodiment, the third insulating layer 7 may cover the second insulating layer 6 completely, and the manufacturing process of the conventional electronic paper panel may be reduced. In this case, the first via hole 91 and the second via hole 92 need to penetrate the second insulating layer 6 and be connected to the first pixel electrode 8 through the third insulating layer 7.
As another example thereof, the third insulating layer 7 may partially cover the second insulating layer 6. The method specifically comprises the following steps: a through hole is arranged in the third insulating layer 7, the through hole is positioned above the second insulating layer 6 where the common electrode 4 is positioned, a thickened first pixel electrode 81 is arranged in the through hole, the upper end of the thickened first pixel electrode 81 is connected with the first pixel electrode 8, and the lower end of the thickened first pixel electrode 81 is abutted against the second insulating layer 6. The via is also located above the second insulating layer 6 where the drain layer 23 is located. The through holes are formed, so that the areas corresponding to the first pixel electrode 8, the drain layer 23 and the common electrode 4 can be directly abutted through the second insulating layer 6, the distance between the first pixel electrode 8 and the drain layer 23 and the common electrode 4 is reduced, and the capacitance value of the pixel capacitor is improved.
In the above process, the first via hole 91 and the second via hole 92 are disposed on the second insulating layer 6, the first via hole 91 is used to connect the thickened first pixel electrode 81 above the second insulating layer 6 and the drain layer 23 below the second insulating layer 6, and the second via hole 92 is used to connect the thickened first pixel electrode 81 above the second insulating layer 6 and the second pixel electrode 3 below the second insulating layer 6. The first via hole 91 and the second via hole 92 are directly arranged in the second insulating layer 6, so that the arrangement of multiple layers of via holes is reduced, and the manufacture is convenient.
In this embodiment, the common electrode 4 is located right above the second pixel electrode 3, and any cross-sectional area of the common electrode 4 is smaller than any cross-sectional area of the second pixel electrode 3. Through the design, the area of the second pixel electrode 3 is larger than that of the common electrode 4, the effective area of the capacitor between the second pixel electrode 3 and the common electrode 4 can be increased to the maximum extent, and the capacity of the pixel capacitor for storing charges is improved.
Example two
Referring to fig. 1 to 7, a method for manufacturing an electronic paper panel with high pixel capacitance includes the following steps:
s1, providing a substrate 1, and forming a gate layer 21 and a second pixel electrode 3 on the substrate 1 at intervals.
This process is illustrated in fig. 1, in order to increase the effective area of the pixel capacitor, the area of the second pixel electrode 3 is as large as possible. The second pixel electrode 3 and the gate layer 21 are collectively referred to as a first metal layer.
S2, providing the first insulating layer 5 on the gate layer 21 and the second pixel electrode 3; a semiconductor layer 24 is provided over the first insulating layer 5 on which the gate layer 21 is located.
This process is illustrated in fig. 2, and this step mainly forms the first insulating layer 5 and the semiconductor layer 24, since the first insulating layer 5 has a larger area and is not shown in fig. 2.
S3, forming the common electrode 4 on the first insulating layer 5 where the second pixel electrode 3 is located, forming the source layer 22 and the drain layer 23 on the semiconductor layer 24, wherein the source layer 22 is connected to one side of the semiconductor layer 24, and the drain layer 23 is connected to the other side of the semiconductor layer 24.
This process is illustrated in fig. 3, where the semiconductor layer 24 is mainly used to turn on the source layer 22 and the drain layer 23. The common electrode 4 is disposed on the second pixel electrode 3, and the common electrode 4 and the second pixel electrode 3 form a pixel capacitor through the first insulating layer 5, thereby increasing the effective area of the pixel capacitor.
S4, a second insulating layer 6 is formed on the common electrode 4, the source layer 22, and the drain layer 23, a first via 91 connected to the drain layer 23 is formed in the second insulating layer 6, and a second via 92 connected to the second pixel electrode 3 is formed in the second insulating layer 6.
This process is mainly performed to form the first via hole 91, the second via hole 92, and the second insulating layer 6, as shown in fig. 4. However, the second insulating layer 6 is not shown in fig. 4 because of its large area.
S5, a first pixel electrode 8 is formed on the second insulating layer 6, the first pixel electrode 8 is connected to the drain layer 23 through the first via 91, and the first pixel electrode 8 is connected to the second pixel electrode 3 through the second via 92.
The specific step S5 includes the following steps:
s51, the third insulating layer 7 is formed on the second insulating layer 6, and then the first pixel electrode 8 is formed on the third insulating layer 7.
This process is further illustrated in fig. 5, and the third insulating layer 7 is further formed to ensure that the tft 2 and the common electrode 4 can be isolated and insulated from the first pixel electrode 8 to be formed later, and also to ensure that the operation of the tft 2 does not affect the first pixel electrode 8.
S52, forming a through hole in the third insulating layer 7 above the second insulating layer 6 where part or all of the drain layer 23 is located, forming a through hole in the third insulating layer 7 above the second insulating layer 6 where part or all of the common electrode 4 is located, and contacting the first pixel electrode 8 with the second insulating layer 6 through the through hole; the first pixel electrode 8 is connected to the drain layer 23 through a first via 91, and the first pixel electrode 8 is connected to the second pixel electrode 3 through a second via 92.
This process is illustrated in fig. 6, where the first pixel electrode 8 is on the top and covers all the layers below, so as to maximize the effective area of the first pixel electrode 8. The through holes are formed, so that the areas corresponding to the first pixel electrode 8, the drain layer 23 and the common electrode 4 can be directly abutted through the second insulating layer 6, the distance between the first pixel electrode 8 and the drain layer 23 and the common electrode 4 is reduced, and the capacitance value of the pixel capacitor is improved.
The pixel capacitance can be greatly improved without changing the common photomask process and technique of the electronic paper panel. A second pixel electrode 3 is additionally arranged to form a pixel capacitor with the common electrode 4, so that the charge storage capacity of the pixel capacitor is improved; the common electrode 4 is arranged in the same layer with the gate layer 21, and is modified to be arranged in the same layer with the source layer 22 and the drain layer 23, so that the second pixel electrode 3 occupies space, the upper side and the lower side of the common electrode 4 are fully utilized, the upper side of the common electrode 4 and the first pixel electrode 8 form a pixel capacitor, the lower side of the common electrode 4 and the second pixel electrode 3 also form a pixel capacitor, the effective area of the pixel electrode is increased, and the utilization rate is increased.
In this embodiment, the common electrode 4, the gate layer 21, the source layer 22, the drain layer 23, and the semiconductor layer 24 are disposed between the second insulating layer 6 and the first insulating layer 5 to form a surrounding shape, which is more effective in insulation. Meanwhile, in order to further improve the degree of combination of the two, the insulating glue used by the second insulating layer 6 and the first insulating layer 5 is the same. Thus, when the laminating manufacturing is carried out, the first insulating layer 5 and the second insulating layer 6 can be combined at the commonly connected part, the thin film transistor 2 and the common electrode 4 between the first insulating layer and the second insulating layer can be wrapped, and the insulating effect is better.
The material of the third insulating layer 7 is different from that used for the second insulating layer 6 in order to further improve the insulating property.
The electronic paper panel is manufactured by the manufacturing method, for example, by using a pixel size of 0.138 x 0.138mm as an example, and the conventional pixel capacitor area 8459um213015um new pixel capacitor effective area2The area is increased 53.86%. If the second insulating layer 6 and the first insulating layer 5 have the same thickness, the pixel storage capacitance is raised 53.86%.
The invention has the beneficial effects that: on the substrate 1 with the same area, the second pixel electrode 3 is additionally arranged and is simultaneously connected with the first pixel electrode 8, so that the common electrode 4, the first pixel electrode 8 and the second pixel electrode 3 can form a pixel capacitor, and the size of the pixel capacitor is improved; meanwhile, the first pixel electrode 8 and the second pixel electrode 3 are respectively arranged at the upper side and the lower side of the common electrode 4, so that the interference between the first pixel electrode 8 and the second pixel electrode 3 is avoided.
The foregoing description shows and describes several preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Although the present disclosure has been described above, the scope of the present disclosure is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and such changes and modifications will fall within the scope of the present invention.