Power semiconductor device with auxiliary gate structure
阅读说明：本技术 具有辅助栅极结构的功率半导体器件 (Power semiconductor device with auxiliary gate structure ) 是由 弗洛林·乌德雷亚 马丁·阿诺德 洛伊佐斯·埃夫蒂米乌 焦尔贾·隆戈巴尔迪 保罗·瑞安 于 2020-05-07 设计创作，主要内容包括：本公开涉及GaN技术中的功率半导体器件。本公开提出集成的辅助(双)栅极端子和下拉网络以实现具有高于2V的阈值电压、低栅极漏电流和增强的开关性能的常关(E模式)GaN晶体管。高阈值电压GaN晶体管具有高压有源GaN器件和低压辅助GaN器件,其中,高压GaN器件具有与集成的辅助低压GaN的源极(12)连接的栅极(10)晶体管和作为外部高压漏极端子(9)的漏极以及作为外部源极端子(8)的源极,而低压辅助GaN晶体管具有连接至漏极(第二辅助电极16)的用作外部栅极端子的栅极(第一辅助电极15)。在实施例中,用于关断高阈值电压GaN晶体管的下拉网络由附加的辅助低压GaN晶体管(34)以及与低压辅助GaN晶体管并联或串联连接的电阻元件形成。(The present disclosure relates to power semiconductor devices in GaN technology. The present disclosure proposes an integrated auxiliary (dual) gate terminal and pull-down network to achieve normally-off (E-mode) GaN transistors with threshold voltages above 2V, low gate leakage current, and enhanced switching performance. The high threshold voltage GaN transistor has a high voltage active GaN device having a gate (10) transistor connected to a source (12) of integrated auxiliary low voltage GaN and a drain as an external high voltage drain terminal (9) and a source as an external source terminal (8), and a low voltage auxiliary GaN device having a gate (first auxiliary electrode 15) serving as an external gate terminal connected to a drain (second auxiliary electrode 16). In an embodiment, a pull-down network for turning off the high threshold voltage GaN transistor is formed by an additional auxiliary low voltage GaN transistor (34) and a resistive element connected in parallel or in series with the low voltage auxiliary GaN transistor.)
1. A group III nitride power semiconductor based heterojunction device, comprising:
an active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising:
a first group III-nitride semiconductor region including a first heterojunction including an active two-dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the group III-nitride semiconductor region;
a second terminal laterally spaced apart from the first terminal and operatively connected to the group III-nitride semiconductor region;
an active gate region formed over the group III-nitride semiconductor region, the active gate region formed between the first terminal and the second terminal;
an auxiliary heterojunction transistor formed on the substrate or another substrate, the auxiliary heterojunction transistor comprising:
a second group III-nitride semiconductor region including a second heterojunction including an auxiliary two-dimensional carrier gas of a second conductivity type;
a first additional terminal operatively connected to the second group III-nitride semiconductor region;
a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second group III-nitride semiconductor region;
an auxiliary gate region formed over the second group III-nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;
wherein the first additional terminal is operatively connected with the auxiliary gate region, and wherein the second additional terminal is operatively connected with the active gate region; and is
Wherein the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and wherein the heterojunction power device further comprises a second auxiliary heterojunction transistor operatively connected in parallel with the first auxiliary transistor, and wherein a first additional terminal of the first auxiliary heterojunction transistor is operatively connected with a source terminal of the second auxiliary heterojunction transistor and a second additional terminal of the first auxiliary heterojunction transistor is operatively connected with a drain terminal of the second auxiliary heterojunction transistor.
2. A depletion mode ill-nitride semiconductor-based heterojunction device, comprising:
a substrate;
a group III-nitride semiconductor region formed over the substrate, wherein the group III-nitride semiconductor region includes a heterojunction including at least one two-dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the group III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the group III-nitride semiconductor region;
at least two highly doped semiconductor regions of a first conductivity type formed over the group III-nitride semiconductor region, the at least two highly doped semiconductor regions formed between the first terminal and the second terminal; and
an active gate region formed over the at least two highly doped semiconductor regions;
wherein the at least two highly doped semiconductor regions are spaced apart from each other in a second dimension, and wherein the second dimension is perpendicular to the first dimension.
3. The heterojunction power device of claim 1, further comprising a first resistor in series with the second auxiliary transistor, and the first resistor is located between the gate terminal and the drain terminal of the second auxiliary transistor.
4. The heterojunction power device of claim 3, further comprising a second resistor operatively connected between the drain terminal of the second auxiliary transistor and the second terminal of the active (high-voltage) transistor.
5. The heterojunction power device of claim 1, further comprising a third auxiliary transistor in series with the second auxiliary transistor and located between the gate and drain terminals of the second auxiliary transistor.
6. The heterojunction power device of claim 5, wherein the gate terminal of the third auxiliary transistor is connected to a source terminal or a drain terminal of the third auxiliary transistor.
7. The heterojunction power device of claim 5, wherein the third auxiliary transistor is configured to: reducing an active gate capacitance discharge time during turn-off of the heterojunction power device by increasing a potential of a gate terminal of the second auxiliary transistor compared to a drain terminal of the second auxiliary transistor.
8. The heterojunction power device of claim 5 wherein the third auxiliary transistor is a depletion-mode transistor according to a depletion-mode group III nitride semiconductor-based heterojunction device, comprising:
a substrate;
a group III-nitride semiconductor region formed over the substrate, wherein the group III-nitride semiconductor region includes a heterojunction including at least one two-dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the group III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the group III-nitride semiconductor region;
at least two highly doped semiconductor regions of a first conductivity type formed over the group III-nitride semiconductor region, the at least two highly doped semiconductor regions formed between the first terminal and the second terminal; and
an active gate region formed over the at least two highly doped semiconductor regions;
wherein the at least two highly doped semiconductor regions are spaced apart from each other in a second dimension, and wherein the second dimension is perpendicular to the first dimension.
9. The heterojunction power device of claim 5, further comprising an additional resistor operatively connected between the drain terminal of the second auxiliary transistor and the second terminal of the active (high-voltage) transistor.
10. The heterojunction power device of claim 1, further comprising a voltage limiting circuit comprising at least two resistors forming a voltage divider enhancement mode and a low voltage transistor actively ground switched.
11. The heterojunction power device of claim 10, wherein a drain terminal of the low-voltage enhancement-mode transistor of the active ground switch is connected with a gate terminal of the active high-voltage transistor, and a source terminal of the low-voltage enhancement-mode transistor of the active ground switch is connected with a source terminal of the active high-voltage transistor.
12. The heterojunction power device of claim 10, wherein the voltage divider is operatively connected between the first additional terminal of the first auxiliary heterojunction transistor and the second terminal of the active high voltage transistor.
13. The heterojunction power device of claim 10, wherein a midpoint of the voltage divider is operatively connected to a gate terminal of the low-voltage enhancement-mode transistor.
14. The heterojunction power device of claim 1, further comprising a voltage limiting circuit comprising at least two resistors forming a voltage divider and a low voltage depletion mode transistor.
15. The heterojunction power device of claim 1, further comprising an over-current protection circuit comprising a current sense resistor and an actively ground switched low-voltage enhancement mode transistor.
16. The heterojunction power device of claim 15, wherein the low-voltage enhancement-mode transistor of the active ground switch is connected between the gate terminal of the active high-voltage transistor and the second terminal of the current sense resistor, and wherein the low-voltage enhancement-mode transistor of the active ground switch is connected to the first terminal of the current sense resistor.
17. The heterojunction power device of claim 1, further comprising an over-current protection circuit comprising a current sense resistor and a low-voltage depletion mode transistor.
18. The heterojunction power device of claim 1, further comprising an active miller clamp comprising a logic inverter and a transistor that functions as an active ground switch of a pull-down network, and wherein the logic inverter comprises a resistor or resistive element and an enhancement mode transistor.
19. The heterojunction power device of claim 18, wherein the resistor is a 2DEG resistor monolithically integrated in the heterojunction power device.
20. A method of fabricating a group III nitride semiconductor based heterojunction power device, the method comprising:
forming an active heterojunction power transistor on a substrate, the active heterojunction power transistor comprising:
a first group III-nitride semiconductor region including a first heterojunction including an active two-dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the group III-nitride semiconductor region;
a second terminal laterally spaced apart from the first terminal and operatively connected to the group III-nitride semiconductor region;
an active gate region formed over the group III-nitride semiconductor region, the active gate region formed between the first terminal and the second terminal;
forming a first auxiliary heterojunction transistor on the substrate or on a further substrate, the auxiliary heterojunction transistor comprising:
a second group III-nitride semiconductor region including a second heterojunction including an auxiliary two-dimensional carrier gas of a second conductivity type;
a first additional terminal operatively connected to the second group III-nitride semiconductor region;
a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second group III-nitride semiconductor region;
an auxiliary gate region formed over the second group III-nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;
forming a second auxiliary heterojunction transistor on the substrate or the further substrate,
operatively connecting the first additional terminal with the auxiliary gate region, an
Operatively connecting the second additional terminal with the active gate region,
operatively connecting the second auxiliary heterojunction transistor in parallel with the first auxiliary transistor,
operatively connecting a first additional terminal of the first auxiliary heterojunction transistor with a source terminal of the second auxiliary heterojunction transistor, an
Operatively connecting a second additional terminal of the first auxiliary heterojunction transistor with a drain terminal of the second auxiliary heterojunction transistor.
21. A heterojunction chip having at least three terminals including a high-voltage terminal, a low-voltage terminal, and a control terminal, wherein the heterojunction chip further comprises:
at least one main power heterojunction transistor, wherein the at least one main power heterojunction transistor comprises an internal gate terminal, a source terminal, and a drain terminal, wherein the source terminal of the at least one main power heterojunction transistor is operatively connected with the low voltage terminal and the drain terminal of the at least one main power heterojunction transistor is operatively connected with the high voltage terminal;
an auxiliary gate circuit comprising at least one first low voltage heterojunction transistor, wherein the auxiliary gate circuit is operatively connected with an internal gate terminal of the at least one main power heterojunction transistor and the control terminal;
a pull-down circuit comprising at least one non-linear element and at least one second low-voltage heterojunction transistor, the non-linear element comprising a voltage divider for driving a gate terminal of the at least one second low-voltage heterojunction transistor, wherein the pull-down circuit is operatively connected with an internal gate terminal of the at least one first low-voltage heterojunction transistor and a source terminal of the at least one main power heterojunction transistor;
a current control circuit comprising at least one resistor, wherein the current control circuit is operatively connected with the control terminal and the pull-down circuit; and is
Wherein the auxiliary gate and current control circuit at least partially controls voltage and current into an internal gate of the at least one main power heterojunction transistor; and
wherein the current control circuit at least partially controls current into the pull-down circuit and at least partially determines a control terminal voltage level at which the pull-down circuit actively pulls down a gate voltage of the at least one first low-voltage heterojunction transistor to clamp an internal gate voltage of the at least one main power heterojunction transistor.
22. The heterojunction chip of claim 21, wherein the voltage divider comprises at least one of a resistive, capacitive, diode, or transistor element; and is
The voltage divider has at least one connection to an internal gate connection of the at least one second low voltage heterojunction transistor.
23. The heterojunction chip of claim 21 or claim 22, wherein the voltage divider is operatively connected with at least one of the current control circuit, an internal gate of the at least one main power heterojunction transistor, and the control terminal.
24. The heterojunction chip of any of claims 21 to 23, wherein the current control circuit comprises at least one of:
a resistor;
at least one third low voltage heterojunction transistor;
wherein each or both of the resistor and the at least one third low voltage heterojunction transistor act as a current source and control the action of the pull-down circuit.
25. The heterojunction chip of claim 24, wherein the current control circuit further comprises at least one current mirror circuit.
26. The heterojunction chip of any of claims 21 to 25, wherein at least one of the auxiliary gate circuit, the pull-down circuit and the current control circuit comprises at least one low-voltage depletion-mode heterojunction transistor.
27. The heterojunction chip of any of claims 21 to 26, wherein at least one of the auxiliary gate circuit, the pull-down circuit and the current control circuit comprises at least one capacitor.
28. The heterojunction chip of any of claims 21 to 27, wherein the heterojunction chip further comprises at least one monolithic integrated component, the at least one monolithic integrated component being one or more of a DC-to-DC converter circuit, a voltage regulator, and a gate voltage to logic signal clamp circuit.
29. The heterojunction chip of any of claims 21 to 28, wherein at least one of the auxiliary gate circuit, the pull-down circuit or the current control block is integrated under one or more of an internal gate, a source terminal and a drain terminal of the at least one main power heterojunction transistor.
30. The heterojunction chip of any of claims 21 to 29, wherein the at least one main power heterojunction transistor comprises two main power heterojunction transistors connected in a half-bridge, and wherein at least one of the two main power heterojunction transistors comprises at least one of the auxiliary gate circuit, the pull-down circuit, and the current control circuit.
31. The heterojunction chip of any of claims 21 to 29, wherein the at least one main power heterojunction transistor comprises four main power heterojunction transistors connected in a full bridge, and wherein at least one of the four main power heterojunction transistors comprises at least one of the auxiliary gate circuit, the pull-down circuit, and the current control circuit.
32. The heterojunction chip of any of claims 21 to 29, wherein the at least one main power heterojunction transistor comprises at least six main power heterojunction transistors connected in a three-phase half-bridge configuration, and wherein at least one of the six main power heterojunction transistors comprises at least one of the auxiliary gate circuit, the pull-down circuit, and the current control circuit.
33. The heterojunction chip of any of claims 21 to 32, wherein the chip further comprises a monolithically integrated miller clamp, and wherein the miller clamp has one connection to an internal gate of the main power heterojunction transistor and bypasses the pull-down circuit during the device off-state or off-transient.
34. The heterojunction chip of claim 33, wherein the miller clamp circuit comprises at least one miller clamp low voltage transistor, wherein a drain terminal of the at least one miller clamp low voltage transistor is operatively connected with an internal gate of the at least one main power heterojunction transistor.
35. The heterojunction chip of claim 34, wherein an internal gate terminal of the miller-clamp low-voltage transistor is operatively connected with an output of an additional circuit integrated on the heterojunction chip, wherein the additional circuit is at least one of:
an overcurrent protection circuit;
an under-voltage lockout circuit;
a power supply voltage overvoltage protection circuit; and
a logic inverter circuit.
36. The heterojunction chip of any of claims 21 to 35, wherein the heterojunction chip further comprises a monolithically integrated additional circuit, and wherein the at least one second low-voltage heterojunction transistor is operatively connected with an output of the monolithically integrated additional circuit, the monolithically integrated additional circuit being one of:
an overcurrent protection circuit;
an under-voltage lockout circuit;
a power supply voltage overvoltage protection circuit; and
a logic inverter circuit.
37. The heterojunction chip of any of claims 21 to 36, wherein the auxiliary gate circuit further comprises at least one additional low-voltage transistor, wherein an internal gate terminal and a source terminal of the at least one additional low-voltage transistor are operatively connected to cause turn-off of the at least one main power heterojunction transistor.
38. The heterojunction chip of any of claims 21 to 37, further comprising one or more monolithically integrated temperature compensation circuits, wherein the one or more monolithically integrated temperature compensation circuits comprise:
a low voltage heterojunction transistor;
a first resistor connected in series with the low voltage heterojunction transistor; and
a second resistor connected in parallel with the low-voltage heterojunction transistor; and is
Wherein the one or more monolithically integrated temperature compensation circuits each reduce an effect of temperature variations on a circuit behavior of the connection component.
39. The heterojunction chip of claim 38, wherein the one or more monolithically integrated temperature compensation circuits comprise a portion of at least one of the voltage divider, the auxiliary gate circuit, the pull-down circuit, and the current control circuit.
Technical Field
The present invention relates to a power semiconductor device, for example to a heterostructure aluminum gallium nitride/gallium nitride (AlGaN/GaN) High Electron Mobility Transistor (HEMT) or rectifier.
Background
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronics (e.g. dc-to-ac inverters for motor control, or dc-to-dc converters for switched mode power supplies). Power semiconductor devices are typically used in a "commutating mode" (i.e. it is either on or off) and therefore have a design optimized for this type of use.
Typically, the voltage rating of the power device (i.e. the potential difference that the device must withstand in the off state between its main terminals) exceeds 20V and conducts more than 100mA during the on state. More commonly, power devices are rated for over 60V and over 1A. These values make the power device very different from low power devices, which operate at voltages below 5V and typical currents below 1mA, and more commonly in the μ As or sub- μ As range. Another difference between power devices and other types of devices such as low power or RF is that they operate primarily with large signals and they behave like switches. Exceptions are found in high voltage or power amplifiers that use dedicated power transistors.
Silicon Bipolar Junction Transistors (BJTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) are common types of power semiconductor switching devices. Their fields of application range from portable consumer electronics, household appliances, hybrid and electric vehicles, motor control and power supplies to radio frequency and microwave circuits and telecommunication systems.
Gallium nitride (GaN) is increasingly considered to be a very promising material for the field of power devices with the potential to increase power density, reduce on-resistance and high frequency response. Wide band gap (E) of the materialg3.39eV) results in a high critical electric field (E)c3.3MV/cm) this high critical electric field may result in designing devices with shorter drift regions and hence lower on-state resistance if compared to silicon-based devices with the same breakdown voltage [1]]. The use of AlGaN/GaN heterostructures also allows the formation of a two-dimensional electron gas (2DEG) at the heterointerface where carriers can reach very high mobilities (μ 2000 cm)2/(Vs)) value [1]. Furthermore, the piezoelectric polarization charges present at the AlGaN/GaN heterostructure result in high electron density in the 2DEG layer (e.g., 1x1013cm-2). These characteristics allow the development of very competitive performance parameters [2]]、[3]A High Electron Mobility Transistor (HEMT) and a schottky barrier diode. Much research has focused on the development of power devices using AlGaN/GaN heterostructures.
However, the 2DEG inherently present at the AlGaN/GaN heterointerface presents challenges when attempting to design normally off devices rather than normally on devices. Nevertheless, since normally-off transistors are preferred in most power electronic applications, several approaches have been proposed that can result in enhancement mode devices, including the use of metal-insulator-semiconductor structures [4], the use of fluorine treatments [5], recessed gate structures [6], and the use of p-type cap layers [7] [8 ]. Because of the relative maturity and controllability of pGaN layer epitaxial growth (compared to other technologies), pGaN/AlGaN/GaN HEMTs are considered to be the leading structures for commercialization.
Fig. 1 schematically shows a cross-section of the active region of a prior art pGaN HEMT. The device shown is a lateral three terminal device with an AlGaN/GaN heterostructure epitaxially grown on a standard silicon wafer 4. The transition layer 3 serves to allow growth of the high quality GaN layer 2 despite the significant lattice mismatch between GaN and Si. Carbon p-type doping is typically added to the GaN layer [9]]. Finally, a thin cap GaN layer 11 is typically added to form a layer with greater than 1x1019cm-3A gate of magnesium (Mg) p-type doping density.
A typical pGaN gate device has a threshold voltage of about 1.5 to 2V and a gate open bias of about 8V. Threshold voltages and gate open-circuit voltages in enhancement mode GaN devices are of great concern because if the threshold voltage is low, some problems may arise in operation, such as the accidental turn-on of the device when it should be turned off. Second, gate turn-on can be a problem due to the non-insulated gate structure. It is therefore apparent that pGaN gate devices operate at gate voltages in the range of 2V to 8V, and preferably between 5V and 7V, to minimize the on-state resistance of the device while ensuring a low leakage voltage (below the open circuit voltage) through the gate.
In prior art devices, there is a trade-off between the threshold voltage of the device and the carrier density in the 2DEG of the device and the on-state resistance of the device. Previous studies have shown that for greater than 1x1019cm-3The threshold voltage of pGaN doping is not significantly changed by using different gate metals or pGaN layer thicknesses [10]]. Thus, it is possible to provideTheir silicon counterparts [12]]Instead, a narrow operating window (with a gate voltage in the range of 4V to 7V relative to the source) is specified in these devices 11]. The lower boundary is defined by the gate bias required to fully form the channel (2DEG) under the gate (this is referred to as the threshold voltage Vth), while the upper boundary is limited by the point at which the gate turns on and a substantial current begins to flow through it.
Another area of interest for AlGaN/GaN HEMTs is their fast switching capability. The high mobility of the carriers in the 2DEG and the shorter drift region result in a very low drift region charge Qgd for a given breakdown due to the higher critical electric field. Furthermore, the device gate charge Qg is about an order of magnitude lower than the corresponding prior art silicon devices [11], [12 ]. Thus, GaN HEMTs can switch at much higher speeds than silicon MOSFETs. While this is beneficial in many applications, it can lead to unwanted oscillations due to the presence of parasitic components in both the device and circuit stages [13 ]. To avoid oscillatory behavior, one possible solution proposed is to add an external gate resistance to the device to reduce the observed dV/dt and dI/dt rates [13 ].
In [14]]Attempts have been made to expand the operating window defined by the threshold voltage and the open circuit of the pGaN/AlGaN junction by changing the composition of the gate metal. Such as [10]]As discussed in (1), the results of such attempts were unsuccessful, [10]]For greater than 1x1019cm-3The threshold voltage cannot be changed significantly by using different gate metals or by changing the thickness of the pGaN layer.
In [16], a higher Vth on P-gate technique is achieved via a "regrown gate through recess (TRRG)" technique. The process technique is based on the complete removal of the AlGaN barrier layer and subsequent regrowth thereof by epitaxial regrowth. This indicates that the threshold voltage is more stable at elevated temperatures and that it is possible to reach Vth as high as 2.3V by controlling the thickness of the AlGaN layer. Although this is an interesting process technique to obtain a stable threshold voltage, it does affect Ron when Vth > 2V is reached. Furthermore, the high Vth solution proposed in [16] does not solve the problems of oscillation associated with Rg during fast switching of high voltage transistors, nor does it solve the high gate leakage problem of pGaN gate technology.
In [17], an integrated dual-gate technique for achieving high Vth (> 2.8V) is demonstrated. [17] The double gate technology proposed in (a) is based on the integration of high voltage normally-on (D-mode) and low voltage normally-off (E-mode) GaN transistors. However, in this configuration, the two transistors are in series, so the total on-state resistance will be affected by the series contribution of the on-state resistance of the low voltage device.
Other proposed double-gate technologies exist in the literature and they are so called because they have a second gate electrode located on the gate passivation layer [18] or buried heterostructure stack [19 ]. These devices are primarily intended to improve the dynamic performance of the transistor by mitigating the current collapse phenomenon. When the device is repeatedly subjected to high voltage in the off state, the current collapse phenomenon is actually a decrease in current in the on state.
In [20] it was attempted to increase the Vth of a normally-off (enhancement mode-E mode) GaN transistor using a circuit configuration with a diode and a second gate electrode. In this document, a diode is used as a voltage switcher and is connected in series with the gate of a high voltage GaN device. Devices implementing the voltage switch with a transistor are also described. However, in this particular case, the drain terminal of the voltage switcher transistor is connected with the high voltage drain terminal of the GaN device. The implication of this connection is that the drive device will have to sustain a high voltage in the blocking mode and is therefore designed as a high voltage transistor with a longer drift region than the low voltage device. The device will therefore have an increased area consumption and the reliability of the additional transistor has to be taken into account. In addition, the upper boundary limit is not mentioned in [20 ].
Resistive loads connected between the gate and source of a GaN HEMT or power MOSFET are also generally known, and their goals may be to reduce oscillations during high voltage switching, protect the device from electrostatic discharge, and generally ensure robust operation. For example, in the data sheet of GaN system component [21], it is proposed to add a 3k Ω resistor between the gate terminal (gate bus) and the source (or ground).
In US9882553B2 and US10411681B2 devices are described that enlarge the operating window of III-V semiconductor devices.
In US10374591B2, a gate drive circuit for controlling the operation of a wide bandgap semiconductor switch is described.
In US2020007119a1, a voltage regulation circuit is described that is implemented using GaN HEMT technology to provide a stable output voltage suitable for applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits.
Disclosure of Invention
The object of the present invention is to propose a solution for a p-gate GaN E-mode transistor that simultaneously results in the following features: (i) a reduction in gate leakage current, (ii) an increase in threshold voltage, and (iii) an increase in gate voltage operating window. The result of these three features is (i) to avoid turn-on re-triggering during turn-off and to limit oscillation under certain turn-off conditions where high dV/dt rates exist, (ii) to improve switching performance through the overall configuration of the integrated pull-down network.
In accordance with the present invention, we propose a GaN power device with a high threshold voltage, a very large gate voltage operating range with little or no risk of p-GaN junction opening, and the ability to switch behavior without or with reduced oscillation. Details of the present invention will be discussed in view of, but not limited to, pGaN gate E-mode technology.
GaN transistors utilizing the present disclosure are intended for, but not limited to, applications in the medium and low voltage range. Low voltage capable devices (< 200V but above 20V) will be suitable for point-of-load applications, i.e. low voltage DC-DC converters for IT or consumer electronics applications. Such devices can also be used in linear electronics to improve efficiency, however, for applications such as Power Factor Correction (PFC), Uninterruptible Power Supply (UPS), motor drives, and Photovoltaic (PV) system inverters, there is a huge market potential in the 600V range. The 600VGaN device may also be used as a charger for Hybrid Electric Vehicles (HEV) and/or Electric Vehicles (EV), which is a rapidly growing market. GaN transistors with breakdown capability up to 1.2kV and power rating up to 7.2kW can result in GaN transistors being used for EV and HEV converters and inverters where high frequency operation will allow for a reduction in system size, which is an important parameter when considering mobile systems. Finally, GaN transistors may find application in wind turbines (1.7kV) if the power rating is large enough. Applications that recently require reliable operation in the MHz range, such as wireless charging in the IT (mobile phone, laptop) and automotive (EV, HEV) fields, may be well suited for the present disclosure. Further, applications other than power conversion are also contemplated, such as class D audio amplifiers.
Broadly, the present disclosure relates to power semiconductor devices using GaN technology. The present disclosure proposes an integrated auxiliary gate terminal and pull-down network to achieve normally-off (E-mode) GaN transistors with threshold voltages above 2V, low gate leakage currents, and possibly enhanced switching performance. The high threshold voltage GaN transistor has a high voltage active GaN device having a gate transistor connected to a source of integrated auxiliary GaN and a drain as an external high voltage drain terminal and a source as an external source terminal, and an auxiliary GaN device (preferably a low voltage device) having a gate (first auxiliary electrode) serving as an external gate terminal connected to the drain (second auxiliary electrode). In other embodiments, the pull-down network for turning off the high threshold voltage GaN transistor is formed by a diode, a resistor, or a parallel connection of both in parallel connection with the auxiliary GaN transistor.
In other embodiments, the pull-down network for turning off the active (high voltage) GaN transistor is formed by an additional auxiliary low voltage GaN transistor, and a resistive element connected in parallel or in series with the low voltage auxiliary GaN transistor.
In other embodiments, the pull-down network for turning off the active (high voltage) GaN transistor is formed by an active miller clamp.
In other embodiments, the overvoltage protection circuit is formed by a resistor or resistive element and a low voltage enhancement mode (or depletion mode) transistor to limit the maximum potential at the gate of the active (high voltage) transistor.
In other embodiments, the over-current protection circuit is formed by a current sense resistor or resistive element and a low voltage enhancement mode (or active depletion mode) transistor to act as protection from over-current events.
According to a second aspect of the present invention, there is provided a heterojunction (gallium nitride) chip (also called or referred to as GaN chip or GaN power integrated circuit or GaN smart device or GaN high voltage integrated circuit) having at least three terminals (high voltage terminal, low voltage terminal and control terminal),
and includes at least one high voltage active GaN device (also referred to as a main power heterojunction transistor) having an internal gate (with its source and drain connected to the low and high voltage terminals, respectively, of the GaN chip), a pull-down circuit, an auxiliary gate circuit including at least one low voltage heterojunction transistor, and a current control circuit, wherein:
an auxiliary gate circuit having one connection to the internal gate of the at least one main power heterojunction transistor, a second connection to the control terminal, and at least one more connection connecting the gate of the at least one low voltage heterojunction transistor to the pull-down circuit;
a pull-down circuit having at least one connection to the current control circuit and at least one connection to the source terminal of the at least one main power heterojunction transistor;
the current control circuit having a connection to the control terminal
And wherein the auxiliary gate partially controls the voltage and current level into the internal gate of the at least one main power heterojunction transistor, the current control circuit controls the current level into the pull-down circuit, and determines, in conjunction with the pull-down circuit design, the voltage level applied to the control terminal at which the pull-down circuit actively pulls down the gate voltage of the at least one low-voltage heterojunction transistor to clamp the voltage of the internal gate of the at least one main power heterojunction transistor.
The auxiliary gate block (circuit) integrated in the GaN chip is composed of an auxiliary GaN transistor (preferably a low voltage device), wherein the gate of the high voltage active GaN device (main power heterojunction transistor) is connected to the source of the integrated auxiliary GaN transistor and the drain of the auxiliary GaN transistor is connected to the GaN chip control terminal.
An integrated current control block (circuit) is connected between the drain and gate terminals of the auxiliary GaN transistor.
An integrated pull-down circuit block (circuit) is connected between the gate terminal of the auxiliary GaN transistor and the source terminal of the high voltage active GaN device.
The threshold voltage of the GaN chip (the potential applied to the control terminal of the GaN chip relative to the low voltage terminal at which the main power heterojunction transistor begins to conduct current) may be higher than the intrinsic threshold voltage of the main power heterojunction single transistor alone. When a voltage signal is applied to the control terminal (also referred to as the external gate terminal) of the GaN chip, this can be achieved by an additional voltage drop on the integrated auxiliary gate block so that the potential on the internal gate (also referred to as the active gate terminal) is lower than the potential applied to the GaN chip control terminal.
When the voltage signal on the external gate terminal (control terminal) increases linearly, the voltage drop on the auxiliary gate block (circuit) is non-linear.
Low gate leakage current of high voltage active GaN devices (main power heterojunction transistors) is achieved by limiting the potential on the internal gate (active gate) terminal. This is achieved by allowing a voltage drop across the integrated auxiliary gate block. The limitation of the potential of the active gate terminal is defined by appropriately designing the current control block and the pull-down circuit block so that the gate of the auxiliary gate transistor is pulled down when the gate signal of the external gate terminal (control terminal of the GaN chip) increases beyond a certain level. Therefore, the gate voltage operation window (i.e., the voltage operation window applied to the control terminal) of the GaN chip is increased as compared with the gate voltage operation window of the conventional GaN HEMT.
The maximum voltage signal that can be applied to the device external gate (control terminal of the GaN chip) can be designed to be 10V or more (e.g., 20V) so that the GaN chip can be driven using a conventional silicon gate driver and controller.
Furthermore, the current control block (and other circuitry) needs to be designed appropriately in order to balance between fast turn-on, avoiding overshoot of the active gate terminal (internal gate terminal) during turn-on, and low gate driver power consumption during on-state operation of the device.
The integrated current control circuit (current control block) may be a resistive element or incorporate a resistive element. Alternatively, the current control circuit may be or comprise a current source. The current source may be composed of a low-voltage depletion mode HEMT and a resistive element. The resistive element may be connected between the gate and source terminals of the low-voltage depletion mode HEMT. The drain terminal of the depletion mode HEMT is connected to the drain terminal of the auxiliary gate HEMT, and the gate terminal of the depletion mode HEMT is connected to the gate terminal of the auxiliary gate HEMT.
In a similar embodiment, an RCL network in parallel with a resistive element or current source may be included to improve the dynamic characteristics during device turn-on or turn-off transients.
The current control block may also include circuitry to generate additional voltage drops. The current control block may also include circuitry to adapt the current in the current control block according to operating conditions (e.g., switching, on or off conditions). Such a current adaptation circuit may include a depletion mode HEMT or an enhancement mode HEMT in series or parallel with a resistive element in the current source.
In some embodiments, the integrated pull-down circuit (block) may be or include one or more HEMTs in parallel or series. Controlling a gate potential of the pull-down HEMT to set a voltage drop across the pull-down HEMT to set a gate voltage of the auxiliary gate block and a voltage drop across the auxiliary gate block.
The pull-down circuit block may also include elements to compensate for or reduce the effect of temperature on the voltage drop across the pull-down circuit block.
In another embodiment, the auxiliary gate may comprise a low voltage depletion mode transistor instead of a low voltage enhancement mode transistor. This embodiment may not be as effective in achieving increased threshold voltages for GaN chips, but may achieve an increased operating range by allowing an increase in the maximum allowable control signal (external gate signal) level. Since there is a channel in the depletion mode transistor when the potential on the active gate is high and the potential on the external gate terminal is low, the GaN transistor can be used as part of the device turn-off network.
In other embodiments, some or all of the described functional blocks may be used together to add enhanced functionality.
Although the auxiliary GaN transistors are preferably low voltage devices, the source and drain terminals may be interchanged as they are typically made in a symmetrical (or similar) manner. Low voltage devices refer to devices with a rated breakdown voltage typically below 20V and limited current capability (below 100 mA). It should be appreciated, however, that the auxiliary gate may be a high power or high voltage device, although this may add cost and complexity.
Most embodiments according to the present disclosure described herein relate to integrated auxiliary transistors whereby the auxiliary transistor and the active transistor are fabricated on the same substrate (in the same chip). Although integration of the two may have several advantages (e.g., fewer pads, low area consumption, compact size, lower cost, and lower complexity), the auxiliary transistor may also be fabricated on a separate substrate and connected to the active transistor in a discrete or mixed manner. The auxiliary transistor and the active transistor may be located side-by-side in the same package or module, or discretely connected on a board, and not necessarily integrated in the same GaN chip.
This also applies to the other functional blocks described.
According to an aspect of the present invention, there is provided a group III nitride semiconductor-based heterojunction power device including:
an active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising:
a first group III-nitride semiconductor region including a first heterojunction including an active two-dimensional carrier gas of a second conductivity type;
a first terminal operatively connected to the group III-nitride semiconductor region;
a second terminal laterally spaced apart from the first terminal and operatively connected to the group III-nitride semiconductor region;
an active gate region formed over the group III-nitride semiconductor region, the active gate region formed between the first terminal and the second terminal;
an auxiliary heterojunction transistor formed on the substrate or another substrate, the auxiliary heterojunction transistor comprising:
a second group III-nitride semiconductor region including a second heterojunction including an auxiliary two-dimensional carrier gas of a second conductivity type;
a first additional terminal operatively connected to the second group III-nitride semiconductor region;
a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second group III-nitride semiconductor region;
an auxiliary gate region formed over the second group III-nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;
wherein the first additional terminal is operatively connected to the auxiliary gate region, and wherein the second additional terminal is operatively connected to the active gate region,
wherein the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and wherein the heterojunction power device further comprises a second auxiliary heterojunction transistor operatively connected in parallel with the first auxiliary transistor, and wherein a first additional terminal of the first auxiliary heterojunction transistor is operatively connected with a source terminal of the second auxiliary heterojunction transistor and a second additional terminal of the first auxiliary heterojunction transistor is operatively connected with a drain terminal of the second auxiliary heterojunction transistor,
wherein the auxiliary heterojunction transistor is configured to (or add an auxiliary heterojunction transistor) cause an increase in a threshold voltage of the heterojunction power device and/or an increase in an operating voltage range of the first additional terminal.
The term "operatively connected" here means that the terminals are electrically connected. In other words, the first additional terminal is electrically connected to the auxiliary gate, and the second additional terminal is electrically connected to the active gate region. Further, in one embodiment, the first terminal is a source terminal of the active transistor and the second terminal is a drain terminal of the active transistor. On the other hand, the first additional terminal is a drain terminal of the auxiliary transistor, and the second additional terminal is a source terminal of the auxiliary transistor. In an embodiment, the connected first additional terminal and the auxiliary gate region form a high voltage terminal (or form an external gate terminal) wherein a relatively higher voltage is applied compared to the second additional terminal. Thus, the second additional terminal may be referred to as the low voltage terminal of the auxiliary transistor. Here, the term "group III nitride semiconductor region" generally refers to the entire region including the GaN layer and the AlGaN layer formed on the GaN layer. A two-dimensional carrier gas is typically formed at the interface between the GaN layer and the AlGaN layer within a group III nitride semiconductor region. In embodiments, the two-dimensional carrier gas refers to a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2 DHG).
When integrated on the same substrate (monolithic integration), the heterojunction power device may further comprise an isolation region between the active heterojunction transistor and the auxiliary heterojunction transistor. The isolation zone separates the active two-dimensional carrier gas and the auxiliary two-dimensional carrier gas. The isolation region may separate the first and second group III nitride semiconductor regions.
In use, when the first additional terminal and the auxiliary gate region may be biased at a potential (or voltage), the carrier density in a portion of the auxiliary two-dimensional carrier gas below the auxiliary gate region is controlled such that an auxiliary two-dimensional carrier gas connection is established between the first and second additional terminals. Typically, a two-dimensional electron gas (2DEG) is formed below the first and second additional terminals. When a voltage is applied to the auxiliary gate region (or high voltage terminal), it will control the carrier density in the 2DEG under the auxiliary gate, so that a 2DEG connection is formed between the 2DEG under the first and second additional terminals.
The active gate region may be configured to conduct through an auxiliary two-dimensional carrier gas (e.g., 2DEG) connection between the first and second additional terminals. The change in resistance of the 2DEG connection under the auxiliary gate region can also turn on the active gate. The auxiliary 2DEG connection can be used as an internal resistance of the active gate region. This internal gate resistance can be used to slow down the fast dV/dt or prevent high oscillations caused by di/dt effects during switching.
The first additional terminal and the auxiliary gate region may be configured such that a part of the potential is used to form the auxiliary 2DEG connection and another part of the potential is used to turn on the active gate region.
The first group III-nitride semiconductor region may include an active aluminum gallium nitride (AlGaN) layer in direct contact with the first terminal, the active gate region, and the second terminal.
The second group III-nitride semiconductor region may include an auxiliary aluminum gallium nitride (AlGaN) layer in direct contact with the first additional terminal, the auxiliary gate region, and the second additional terminal.
The thicknesses of the active AlGaN layer and the auxiliary AlGaN layer may be the same or different.
The doping concentrations of the active AlGaN layer and the auxiliary AlGaN layer may be the same or different.
The aluminum mole fraction of the active AlGaN layer and the auxiliary AlGaN layer may be the same or different.
The active gate region may include a p-type gallium nitride (pGaN) material. The metal contact on the active pGaN gate may be schottky or ohmic. Alternatively, the active gate region may include a recessed schottky contact.
The first terminal, the second terminal, the first additional terminal, and the second additional terminal may each include a surface ohmic contact. Alternatively, the first terminal, the second terminal, the first additional terminal, and the second additional terminal may each include a recessed ohmic contact.
The auxiliary gate region may comprise a field plate extending towards the first additional terminal and wherein the field plate extends over the field oxide region.
The power device may have a staggered layout in which the gate metal pad is directly connected to the auxiliary gate region and the first additional terminal, and the active gate region includes a gate finger connected to the second additional terminal. Alternatively, the device may have a staggered layout with the auxiliary gate region, the first additional terminal and the second additional terminal located below the source metal pad. Advantageously, no additional wafer area is required to include the auxiliary gate structure as compared to prior art designs.
In an embodiment, the second additional terminal and the active gate region may be connected in a third dimension of the device.
The active heterojunction transistor may be a high voltage transistor and the auxiliary heterojunction transistor may be a low voltage transistor, as compared to the active heterojunction transistor.
The heterojunction power device may further comprise a diode connected in parallel between the first and second additional terminals of the auxiliary heterojunction transistor. The parallel diodes act as a pull-down network during the turn-off of the entire configuration connected from the gate terminal of the active GaN transistor to ground. When a forward bias (conducting state) is applied to the auxiliary gate, the diode will be reverse biased and zero current will flow through it, which does not affect the electrical behavior of the entire high voltage configuration. When zero bias (off state) is applied to the auxiliary gate, the diode will be forward biased and the off current flowing through it will discharge the gate capacitance of the active transistor, thereby enabling the entire arrangement to be switched off. In the off state, the gate of the active transistor will remain biased to a minimum voltage (equal to the turn-on voltage of the diode). Therefore, the diode is designed such that its turn-on voltage will be as low as possible, ideally a few millivolts. The diode may be formed monolithically with the device. The diode may be a simple schottky diode. The diode normally pulls the active gate down to the diode V during turn-offthTherefore, the diode needs to be designed to have a threshold voltage as low as possible. One feature that can achieve this is the use of a recessed anode to make direct contact with the 2 DEG.
Alternatively, normally-on (depletion mode) GaN power devices not available in the prior art may be used. Such normally-on devices may include a gate structure based on a discontinuous p-GaN layer (or discontinuous region of a first conductivity type) that includes islands within stripes or closed shapes around cells that, when a gate voltage is applied, serve to modulate the conductive path given by the 2D electron gas (or two-dimensional carrier gas of a second conductivity type) between the high and low voltage terminals. All such islands may be connected to the same gate electrode. It should be understood that discontinuous islands means that there is no p-GaN layer between adjacent islands, and thus, there is a direct, unobstructed conductive path between the source and drain terminals provided by the 2D electron gas. However, adjacent islands are located together in a direction that intersects (is orthogonal to) the current path, such that a potential applied to the p-GaN gate island modulates the conductive region between the islands, thereby modulating the direct path between the source and drain. The p-GaN layers in the continuous and discontinuous gate structures are completed in the same process step and the distinction between continuous and discontinuous is achieved by layout variations of the same mask.
The operation of this normally-on (depletion mode) device is characterized by the presence of two threshold voltages. The first threshold voltage may be negative and equivalent to the threshold voltage of a classical normally-on transistor, indicating a transition from an off state to an on state. The second threshold voltage is preferably positive and is characterized by a sharp current increase. The second threshold voltage may be the same value as for an integrated normally-off device with a continuous p-GaN gate.
The two threshold voltages are discussed and identified clearly in more detail below.
In addition to epitaxial/process modifications, a first threshold voltage, referred to herein as the device threshold voltage, may be adjusted by layout modifications. Furthermore, the depletion-mode (normally-on) devices proposed herein may allow for an increased positive gate bias (> 7V) to be applied before the main conduction state channel changes from drain-source to gate-source. Such a device can be implemented in a manufacturing process where no schottky contact is provided on the AlGaN layer surface.
Alternatively, normally-on depletion devices using discontinuous pGaN islands can be used in diode mode by connecting the gate and source together (or the anode terminal due to the symmetry of connecting the drain and gate together). The distance (pitch) between pGaN islands can be used to adjust the voltage level at which the diode conducts current in the forward mode. This is particularly advantageous over the prior art using a continuous pGaN layer, which results in a large forward voltage. For example, the spacing between pGaN islands (or multiple stripes of pGaN islands) can be used to adjust this open forward voltage to 0.3 to 0.5V, which is characteristic of schottky diodes in silicon. To avoid an undesirable negative open circuit voltage of the diode, the spacing between pGaN islands should be very small (on the order of tens or hundreds of nanometers), or the source of the HEMT connected in a diode configuration may have a schottky contact.
When a 2DEG is formed under the pGaN layer, a second increase in current occurs at a higher voltage level (above the open circuit voltage level) during forward conduction. In forward conduction, it is desirable for the diode to operate above this second voltage level to minimize on-state resistance.
In all embodiments, the contacts to the pGaN islands may be made of ohmic or schottky metallization.
The first additional terminal (or drain (gate) terminal) and the second additional terminal (or source terminal) of the (first) auxiliary heterojunction transistor may each serve as an external gate terminal.
In the present invention, the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and the heterojunction device further comprises a second auxiliary heterojunction transistor operatively connected in parallel with the first auxiliary transistor, and a first additional terminal (or drain (gate) terminal) of the first auxiliary heterojunction transistor may be connected with a source terminal of the second auxiliary heterojunction transistor, and a second additional terminal (or source terminal) of the first auxiliary heterojunction transistor may be operatively connected with a drain (gate) terminal of the second auxiliary heterojunction transistor.
The pull-down network through the second auxiliary heterojunction transistor may further comprise a resistor added in series with the second auxiliary transistor between the gate and drain terminals of the second auxiliary transistor. The resistor is between the gate and drain terminals of the second auxiliary transistor. Thus, the resistor does not form a common junction between the gates of the first auxiliary transistor and the active transistor. The resistor functions to reduce the active gate capacitance discharge time through the pull-down network during the heterojunction power device turn-off. The additional resistive element performs this function by generating an increased potential of the gate terminal of the second auxiliary transistor compared to the drain terminal of the second auxiliary transistor during turn-off. An additional resistor may be connected between the drain terminal of the second auxiliary transistor and the source terminal of the active power transistor. During the active device turn off, the additional resistor acts as a parallel pull down network. It will therefore be appreciated that the additional resistor is not connected through a common junction connecting the source of the first auxiliary transistor and the gate of the active transistor. The additional resistor may act as a voltage limiting component to protect the gate terminal of the active device during its on and conducting states.
The pull-down network through the second auxiliary heterojunction transistor may further comprise a third auxiliary transistor added in series with the second auxiliary transistor between the gate and drain terminals of the second auxiliary transistor. The third auxiliary transistor functions to reduce the active gate capacitance discharge time through the pull-down network during the heterojunction power device turn-off. The third auxiliary transistor performs this function by generating an increased potential of the gate terminal of the second auxiliary transistor compared to the drain terminal of the second auxiliary transistor during turn-off. The third auxiliary transistor may be a depletion mode low voltage transistor. Depletion mode devices can be made using p-GaN islands as shown in fig. 18, or can be diodes as shown in fig. 19. The gate terminal of the third auxiliary transistor may be connected with the source or drain terminal of the third auxiliary transistor. An additional resistor may be connected between the drain terminal of the second auxiliary transistor and the source terminal of the active (high voltage) transistor. In other words, it is understood that the additional resistor is not connected through a common node connecting the source of the first auxiliary transistor and the gate of the active transistor. During the active device turn off, the additional resistor acts as a parallel pull down network. The additional resistor may act as a voltage limiting component to protect the gate terminal of the active device during its on and conducting states.
The heterojunction power device further comprises a voltage limiting circuit comprising two resistors forming a voltage divider and a low-voltage enhancement mode transistor actively switched to ground. The drain-source path of the low-voltage enhancement mode transistor of the active ground switch is connected between the gate and the source of the active power transistor. The voltage divider is connected between the first additional terminal (or drain (gate) terminal) of the first auxiliary heterojunction transistor and the source terminal of the active (high voltage) transistor. The midpoint of the voltage divider is connected to the gate terminal of the low voltage enhancement mode transistor. When the voltage of the first additional terminal (or drain (gate) terminal) rises above a certain value, which can be controlled by the choice of resistors in the described voltage divider, the enhancement mode transistor can be switched on, thereby adjusting the resistance between the active device gate terminal and the active (high voltage) device source terminal. This function may protect the active gate terminal from overvoltage events.
The heterojunction power device may further comprise a voltage limiting circuit as described above, wherein the low-voltage enhancement-mode transistor is replaced by a low-voltage depletion-mode transistor. In this embodiment, when the potential of the first additional terminal (or drain (gate) terminal) of the first auxiliary heterojunction transistor is increased, the resistance of the depletion mode transistor may be decreased, thereby adjusting the resistance between the gate terminal of the active (high voltage) device and the source terminal of the active device. The potential on the gate terminal of the depletion mode transistor is determined by a voltage divider formed by a resistor. The described circuit can protect the active gate terminal from an overvoltage event.
The heterojunction power device may further comprise an over-current protection circuit consisting of a current sense resistor and an actively ground switched low-voltage enhancement mode transistor. The active region of the active (high voltage) transistor is divided into two regions, which form two transistors in parallel. The drain and gate terminals of the two transistors are electrically connected. The two transistors in parallel are a low resistance (main power) transistor and a high resistance (current sense) transistor, respectively. A first terminal of the current sense resistor is connected with a source terminal of the high resistance transistor. An enhancement mode transistor of the active ground switch is connected between a gate terminal of the active (high voltage) transistor and a second terminal of the current sense resistor. A gate terminal of the low voltage enhancement mode transistor is connected with a first terminal of a current sense resistor. As the current through the high resistance transistor increases, the potential drop across the current sense resistor increases, raising the potential at the gate of the low voltage enhancement mode resistor, thereby adjusting its resistance. The low voltage enhancement mode transistor can be turned on by the critical current of the low voltage transistor, limiting the potential on the gate of the active power transistor. The described circuit may protect the circuit from an overcurrent event. The described components may be included monolithically in the design.
The heterojunction power device may further comprise an over-current protection circuit as described above, wherein the low-voltage enhancement mode transistor is replaced by a low-voltage depletion mode transistor. Similarly, the potential at the gate terminal of the depletion mode transistor increases with increasing current through the current sense resistor. As the current through the current sense resistor increases, the resistance of the depletion mode transistor decreases, decreasing the resistance of the path between the gate and source of the active (high voltage) device, thereby limiting the potential on the active gate terminal. The described circuit may protect the circuit from an overcurrent event.
The heterojunction power device may also include an active miller clamp to provide an additional pull-down network for the active (high voltage) device gate terminal during the device turn-off transient. The active miller clamp is comprised of a logic inverter and transistors that function as active ground switches for the pull-down network. The logic inverter may be comprised of a resistor or resistive element (i.e., a load transistor) and an enhancement mode transistor.
The actively switched transistors may be enhancement mode or depletion mode transistors. In operation, the active miller clamp utilizes the voltage bias of the external gate terminal (i.e., the terminal connected to the gate driver) to adjust the resistance of the transistors of the active ground switch, thereby providing a low resistance pull-down path when the main power device is being turned off or in an off state. When the gate driver signal is high, the bias on the gate of the actively switched transistor in the miller clamp is low (and therefore its resistance is high), and vice versa.
The resistor (in any of the embodiments shown herein) may be made of an in-process metal layer, an AlGaN layer, or preferably a 2 DEG. The resistor may be shaped in a meandering manner for high packing density. The functional blocks described above may be included in the design discreetly, monolithically, or in a hybrid package.
The depletion mode transistor in the described functional block may be a schottky gate HEMT as described in the prior art.
Furthermore, the normally-on (depletion mode) transistors in the described functional blocks may be the pGaN island transistors described above.
It should be understood that as already mentioned, the auxiliary heterojunction transistor may have an interchangeable source and drain. Unlike active (high voltage) transistors, the source and drain in the auxiliary heterojunction can be symmetric or fabricated and arranged in a similar manner so that the source can act as the drain, and vice versa.
According to a second aspect of the present disclosure there is provided a gallium nitride (GaN) chip comprising a group III nitride semiconductor based heterojunction power device according to the preceding aspect and an auxiliary low voltage transistor according to the preceding aspect, but wherein the auxiliary gate region terminal is operatively connected with the control circuit (block) and the pull-down circuit (block).
The current control block may be connected between the first additional terminal and the auxiliary gate region. The pull-down circuit block may be connected between the auxiliary gate terminal and a first terminal (source) of the heterojunction power device (same as the low voltage terminal of the GaN chip).
The GaN chip may further include an over-current protection circuit as described above, wherein the low voltage transistor is connected in parallel with the pull-down circuit.
The GaN chip may also include integrated current control circuitry (block). As described above, the current control block provides current to charge and discharge the gate of the auxiliary HEMT in the auxiliary gate circuit. A current control block may be connected between the first additional terminal and the gate of the auxiliary HEMT.
In some embodiments, the integrated current control block may be a resistive element. The resistive element may be made using a metal layer or a 2DEG layer.
In other embodiments, the current control block may be or include a current source. The current source may be composed of a low-voltage depletion mode HEMT and a resistive element. The drain of the low-voltage HEMT may be connected to the first additional terminal, the source connected to the first terminal of the resistive element, and the gate connected to the second terminal of the resistive element. The second terminal of the resistive element may also be connected to the gate terminal of the auxiliary HEMT.
In a similar embodiment, an RCL network in parallel or in series with a resistive element or current source may be included to improve the characteristics of the current control block.
The current control block may also include circuitry to generate additional voltage drops. Such a circuit can be one or several low-voltage diodes, one or several low-voltage HEMTs with the gate connected to the source, or a low-voltage enhancement mode HEMT with the voltage divider connected between the drain and source terminals of the HEMT (where the midpoint of the voltage divider is connected to the gate terminal of the HEMT).
The current control block may also include circuitry to adapt the current in the current control block. Such a current reduction circuit may include a depletion mode HEMT or an enhancement mode HEMT in series or parallel with a resistive element in the current source. The gate of the HEMT may be connected with a voltage divider between the gate of the auxiliary HEMT and the first terminal or with a node within the integrated pull-down circuit.
The heterojunction GaN chip may also include an integrated pull-down circuit block. The pull-down circuit block may be connected between the gate of the auxiliary HEMT and a first terminal (the source terminal of the main power heterojunction transistor-being the same as the low voltage terminal of the GaN chip).
In some embodiments, the integrated pull-down circuit block may be one or more normally-on or normally-off HEMTs in parallel or series. There may be an additional capacitor or resistor in series with the HEMT. Controlling a gate potential of the pull-down HEMT to set a voltage drop across the pull-down HEMT to set a gate voltage of the auxiliary gate block and a voltage drop across the auxiliary gate block.
In one embodiment, the gate terminal of the pull-down HEMT can be connected with an output of a voltage divider between the gate terminal and the first terminal of the auxiliary HEMT.
In another embodiment, the gate terminal of the pull-down HEMT may be connected with the output of a voltage divider between the source terminal and the first terminal of the HEMT in the current source of the current control block.
In further embodiments, the gate terminal of the pull-down HEMT can be connected to the output of a voltage divider between the active gate and the first terminal.
In a fourth embodiment, the gate terminal of the pull-down HEMT can be connected to the output of the voltage divider between the first additional terminal and the first terminal.
In a further embodiment, an additional current control block is connected to the first additional terminal. The additional current control block is connected to an additional pull-down circuit (connected to the first terminal). In this embodiment, the gate terminal of the first pull-down HEMT can be connected to the output of the voltage divider on the additional pull-down circuit.
In all of these embodiments of the pull-down circuit, the voltage divider may be comprised of a resistive element, such as a resistor formed of metal or 2 DEG; a capacitor; a current source formed of a depletion mode HEMT having a source connected to the first terminal of the resistive element and a gate connected to the second terminal; a Schottky diode, an enhancement mode HEMT having a gate terminal connected to a source terminal; a HEMT having its gate terminal connected to the output of the voltage divider between its drain and source; or similar voltage divider circuit.
The pull-down circuit or current control or auxiliary gate circuit may also include elements to compensate or reduce temperature effects. This element is a specific embodiment of a voltage divider that is part of the pull-down circuit. The first portion of the voltage divider may include an integrated resistor and the second portion of the voltage divider may include a current source consisting of a normally-on HEMT (with its source connected to the first terminal of the additional resistor and its gate connected to the second terminal of the resistor). The first part of the voltage divider may also comprise a similar current source in parallel with the resistor. The second part of the voltage divider may further comprise a resistor in parallel with the current source.
Both parts of the voltage divider will increase the voltage drop with increasing temperature at a given current. But the current source and resistor change the voltage drop at different rates. By sizing the normally-on HEMT and the resistor, the output of the voltage divider can be made less temperature dependent by the design being set to the voltage drop on the pull-down circuit and/or the voltage drop on the auxiliary HEMT.
In further embodiments, the gate of the pull-down HEMT is controlled by an over-current protection circuit or an over-temperature protection circuit.
In further embodiments, the gate of the pull-down HEMT is controlled directly or indirectly by external circuitry or by additional circuitry integrated on the GaN device.
The GaN chip may include more than one primary power device. For example, a half-bridge configuration is possible in which a low-side power device is connected in series with a high-side main power device. A full bridge consisting of two half-bridge arms or a three-phase GaN chip configuration is also possible. According to this aspect of the invention, at least one main power device in these configurations (half-bridge or full-bridge or three-phase) includes an auxiliary gate circuit, a pull-down circuit and a current control circuit as described above.
According to another aspect of the present disclosure, there is provided a method of fabricating a group III nitride semiconductor-based heterojunction power device, the method comprising:
forming an active heterojunction power transistor on a substrate, the active heterojunction power transistor comprising:
a first group III-nitride semiconductor region including a first heterojunction including an active two-dimensional carrier gas;
a first terminal operatively connected to the group III-nitride semiconductor region;
a second terminal laterally spaced apart from the first terminal and operatively connected to the group III-nitride semiconductor region;
an active gate region formed over the group III-nitride semiconductor region, the active gate region formed between the first terminal and the second terminal;
forming a first auxiliary heterojunction transistor on the substrate or on a further substrate, the auxiliary heterojunction transistor comprising:
a second group III-nitride semiconductor region including a second heterojunction including an auxiliary two-dimensional carrier gas;
a first additional terminal operatively connected to the second group III-nitride semiconductor region;
a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second group III-nitride semiconductor region;
an auxiliary gate region formed over the second group III-nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;
forming a second auxiliary heterojunction transistor on the substrate or the further substrate,
operatively connecting the first additional terminal with the auxiliary gate region, an
Operatively connecting the second additional terminal with the active gate region,
operatively connecting the second auxiliary heterojunction transistor in parallel with the first auxiliary transistor,
operatively connecting a first additional terminal of the first auxiliary heterojunction transistor with a source terminal of the second auxiliary heterojunction transistor, an
Operatively connecting a second additional terminal of the first auxiliary heterojunction transistor with a drain terminal of the second auxiliary heterojunction transistor.
The method may further include forming an isolation region between the active heterojunction transistor and the auxiliary heterojunction transistor that separates the active two-dimensional carrier gas and the auxiliary two-dimensional carrier gas.
The method may further include forming the first group III-nitride semiconductor region at the same time as forming the second group III-nitride semiconductor region.
The method may further include forming an active gate region at the same time as forming the auxiliary gate region.
The method may further include simultaneously forming metallization layers for the first terminal, the second terminal, the first additional terminal, and the second additional terminal.
Drawings
The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings, which, however, should not be taken to limit the disclosure to the specific embodiments shown, but are for explanation and understanding only.
Fig. 1 schematically shows a cross-section in the active region of a prior art pGaN HEMT;
fig. 2 shows a schematic representation of a cross-section of an active region of the proposed disclosure according to an embodiment of the present disclosure;
FIG. 3 shows a schematic representation of a circuit of one embodiment of the proposed disclosure as shown in the schematic cross-section of FIG. 2;
fig. 4A shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a low on-state voltage diode is connected in parallel between the drain and the source of the auxiliary transistor;
FIG. 4B shows a 3D schematic representation of the embodiment of FIG. 4A;
FIG. 4C shows a cross section of a low voltage diode used in the embodiment of FIG. 4A;
fig. 5 shows a schematic circuit representation of a further embodiment of the proposed disclosure, wherein the drain (gate) terminal and the source terminal of the auxiliary transistor can be used as external gate terminals;
fig. 6 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a second auxiliary transistor is connected in parallel with the first auxiliary transistor, wherein the drain (gate) terminal of the first low auxiliary transistor is connected with the source terminal of the second auxiliary transistor and the source terminal of the first low auxiliary transistor is connected with the drain (gate) terminal of the second auxiliary transistor;
fig. 7 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a resistor is added between the drain terminal and the gate terminal of the second auxiliary transistor;
fig. 8 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein an additional resistor is added between the source terminal of the auxiliary transistor (the drain terminal of the second auxiliary transistor) and the source terminal of the active device;
fig. 9 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a third auxiliary transistor is added between the drain terminal and the gate terminal of the second auxiliary transistor; a gate terminal of the third auxiliary transistor is connected to a source terminal of the third auxiliary transistor;
fig. 10 presents a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a third auxiliary transistor is added between the drain terminal and the gate terminal of the second auxiliary transistor; a gate terminal of the third auxiliary transistor is connected to a drain terminal of the third auxiliary transistor;
FIG. 11 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which a voltage limiting circuit consisting of two resistors forming a voltage divider and a low voltage enhancement mode transistor actively switched is implemented;
FIG. 12 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which a voltage limiting circuit consisting of two resistors forming a voltage divider and a low voltage depletion mode transistor actively switched to ground is implemented;
FIG. 13 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which an over-current protection circuit consisting of a resistor and an actively switched low-voltage enhancement mode transistor is implemented;
FIG. 14 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which an over-current protection circuit consisting of a resistor and an actively switched low voltage depletion mode transistor is implemented;
FIG. 15 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which an active Miller clamp circuit consisting of a resistor, an actively ground switched low voltage enhancement mode transistor and an actively ground switched depletion mode transistor is implemented;
FIG. 16 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which an active Miller clamp circuit consisting of a resistor, an actively ground switched low voltage enhancement mode transistor and an actively ground switched depletion mode transistor is implemented;
figure 17 shows a schematic representation of a cross-section of the active region of a depletion mode device of a transistor proposed in the prior art that can be used as an actively ground switch;
fig. 18 shows a three-dimensional schematic representation of the active region of a depletion mode device with pGaN islands (not found in the prior art) for a proposed transistor that can be used as an actively switched transistor;
FIG. 19 shows a three-dimensional schematic representation of the active region of a depletion mode device having the pGaN island shown in FIG. 18 operating in diode mode; and
fig. 20 shows the transfer characteristics of the depletion mode device shown in fig. 18.
Fig. 21 shows a schematic representation of a cross-section of an active region of the proposed disclosure according to another embodiment of the present disclosure. In this embodiment, the first additional terminal 16 is not operatively connected with the auxiliary gate terminal 15.
Fig. 22 shows a schematic representation of the circuitry of one embodiment of the proposed disclosure as shown in the schematic cross-section of fig. 21.
Fig. 23 shows a schematic representation of a second aspect of an embodiment of the proposed disclosure, wherein the gate terminal of the auxiliary gate block is controlled by a current control block and a pull-down circuit block.
Fig. 24 shows the relationship between the external gate voltage bias and the active gate voltage.
Fig. 25 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the current control block is composed of resistive elements and the pull-down circuit comprises a HEMT in a threshold multiplier configuration.
Fig. 26 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the current control block comprises a resistive element with a resistive element in parallel with a capacitive element, and wherein the pull-down circuit comprises a HEMT in a threshold multiplier configuration, with an additional capacitive element.
FIG. 27 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the current control block comprises a normally-on HEMT and a resistive element in series, wherein the gate of the normally-on HEMT is connected to the second terminal of the resistive element; and wherein the pull-down circuit includes the HEMT in a threshold multiplier configuration. In this embodiment, the auxiliary gate block includes an enhancement mode low voltage HEMT and a schottky diode in parallel.
Fig. 28 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the current control block comprises a normally-on HEMT and a resistive element in series, wherein the gate of the normally-on HEMT is connected to the second terminal of the resistive element; and wherein the pull-down circuit includes the HEMT in a threshold multiplier configuration.
Fig. 29 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the auxiliary gate block comprises a second auxiliary transistor connected in parallel with the first auxiliary transistor, wherein the gate terminal of the second auxiliary transistor is connected with the source terminal of the first auxiliary transistor;
fig. 30 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the pull-down circuit comprises a HEMT in a threshold multiplier configuration. In this embodiment, the voltage divider of the pull-down circuit includes a temperature compensation circuit that includes a current source in parallel with a resistive element.
Fig. 31 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which the voltage divider of the pull-down circuit is connected to the source terminal of the HEMT of the current control block.
FIG. 32 shows a schematic representation of one embodiment of the proposed disclosure in which the gate terminal of the auxiliary gate block is controlled by a current control block and a pull-down circuit block; and wherein the miller clamp HEMT is controlled by the logic inverter. The logic inverter is powered by the output voltage of the integrated DC/DC voltage regulator. Further, the input of the logic inverter is the output of the VG to Vlogic voltage regulators, limiting the voltage from the first additional terminal to a level optimized for the integrated GaN HEMT included in the inverter circuit.
Fig. 33 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the auxiliary gate block comprises a normally-on HEMT.
Fig. 34 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the auxiliary gate block comprises a normally-on HEMT and wherein the auxiliary gate block comprises a second auxiliary transistor connected in parallel with the first auxiliary transistor, wherein the gate terminal the source of the second auxiliary transistor is connected to the source terminal of the first auxiliary transistor;
fig. 35 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the auxiliary gate block comprises a normally-on HEMT and wherein the auxiliary gate block comprises a second auxiliary normally-on HEMT connected in parallel with the first auxiliary transistor, wherein the gate terminal of the second auxiliary transistor is connected with the first terminal;
fig. 36 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the voltage divider of the pull-down circuit is connected to the active gate terminal.
Fig. 37 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the voltage divider of the pull-down circuit is connected to the active gate terminal, and wherein the voltage divider comprises a series of source-gate connected E-HEMTs.
Fig. 38 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the voltage divider of the pull-down circuit is connected with the active gate terminal, and wherein the voltage divider comprises the HEMT in a threshold multiplier configuration.
Fig. 39 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the voltage divider of the pull-down circuit is connected with the first additional terminal, and wherein the voltage divider comprises the HEMT in a threshold multiplier configuration.
Fig. 40 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein the voltage divider of the pull-down circuit is connected with the first additional terminal, and wherein the voltage divider comprises a current source (formed by a normally-on HEMT and a resistor) and a HEMT in a threshold multiplier configuration. In this embodiment, the output of the voltage divider is the gate terminal of the HEMT in a threshold multiplier configuration.
FIG. 41 illustrates an interleaved device layout incorporating an auxiliary gate structure with a current control block and a pull-down circuit block according to a further embodiment of the present disclosure.
FIG. 42 shows an interleaved device layout of a further embodiment of the present disclosure, where the auxiliary gate with current control block and pull-down circuit blocks and terminal areas is located under the source pad metal.
Fig. 43 shows a block diagram of further embodiments of the proposed disclosure, where any one of the embodiments of the GaN chip power device according to the present disclosure is located in a half-bridge configuration.
Fig. 44 shows a block diagram of further embodiments of the proposed disclosure, where any one of the embodiments of the GaN chip power device according to the present disclosure is located in a three-phase half-bridge configuration.
Detailed Description
Fig. 2 shows a schematic representation of a cross-section of an active region according to an embodiment of the present disclosure of the proposed disclosure. In use, current flows in the active region of the semiconductor device. In this embodiment, the device includes a semiconductor (e.g., silicon) substrate 4 defining a major (horizontal) surface at the bottom of the device. Under the substrate 4 there is a substrate terminal 5. The device comprises a first region of the transition layer 3 above the semiconductor substrate 4. The transition layer 3 comprises a combination of III-V semiconductor materials which is used as an intermediate step to allow subsequent growth of high quality III-V semiconductor materials.
Above the transition layer 3 there is a second zone 2. The second region 2 is a high quality III-V semiconductor (e.g. GaN) and comprises several layers. A third region 1 of the III-V semiconductor comprising a mole fraction of aluminum is formed over the second region 2. The third region 1 is formed such that a heterostructure is formed at the interface between the second region 2 and the third region 1, thereby forming a two-dimensional electron gas (2 DEG).
A fourth region 11 of a highly p-doped III-V semiconductor is formed in contact with the third region 1. This has the effect of reducing the 2DEG carrier concentration when the device is unbiased, and in this example is pGaN material. The gate control terminal 10 is configured above the fourth region 11 to control the carrier density of the 2DEG at the interface of the second region 2 and the third region 1. The high voltage drain terminal 9 is arranged in physical contact with the third region 1. The high voltage drain terminal forms an ohmic contact with the 2 DEG. The low voltage source terminal 8 is also arranged in physical contact with the third region 1 and also forms an ohmic contact with the 2 DEG.
A portion of the surface passivation dielectric 7 is formed over the fourth region 1 and between the drain terminal 9 and the source terminal 8. SiO 22A passivation layer 6 is formed over the surface passivation dielectric 7 and the source and drain terminals 8 and 9.
The device is divided into two cross sections by vertical cutting lines. The two cross-sections do not necessarily lie in the same plane. The above-described feature is on one side (e.g., the right hand side) of the vertical cut line. This is referred to as active device 205.The other side of the vertical cutting line (e.g. the left-hand side) is referred to as auxiliary device 210, which further comprises semiconductor substrate 4, transition layer 3, second region 2 and SiO2A passivation region 6.
A fifth region 17 of the III-V semiconductor comprising a mole fraction of aluminum is located over the second region 2 in the auxiliary device such that a heterostructure is formed at an interface between the fifth region 17 and the second region 2. This results in a second two-dimensional electron gas (2DEG) being formed in a region that will be referred to as the auxiliary gate. This AlGaN layer 17 of the auxiliary device 210 may be the same as or different from the AlGaN layer 1 in the active device 205. AlGaN layer thickness and aluminum mole fraction are key parameters because they affect the carrier density of electrons in 2DEG [15 ].
A sixth region 14 of highly p-doped III-V semiconductor is formed over the fifth region 17 and in contact with the fifth region 17. This has the function of reducing the 2DEG carrier concentration when the auxiliary gate is unbiased. The auxiliary gate control terminal 15 is configured above the sixth region 14 to control the carrier density of the 2DEG at the interface of the fifth region 17 and the second region 2. The auxiliary gate pGaN layer 14 may be the same as or different from the active gate pGaN layer 11. Key parameters that may be different include, but are not limited to, pGaN doping and width along the x-axis (as shown).
Isolation regions 13 are formed down the vertical cutting lines. This cuts off the electrical connection between the 2DEG formed in the active device 205 and the 2DEG formed in the auxiliary device 210.
The first additional terminal 16 is arranged above the fifth region 17 of the auxiliary device 210 and is in physical contact with the fifth region 17. This forms an ohmic contact to the 2DEG of the auxiliary device 210 and is also electrically connected (via an interconnect metal) to the auxiliary gate control terminal 15 that is configured over the sixth region (pGaN) 14. The first additional terminal 16 is biased at the same potential as the auxiliary gate terminal 15 of the auxiliary device. The second additional terminal 12 is also arranged over and in physical contact with the fifth region 17 of the auxiliary device 210. This forms an ohmic contact to the 2DEG of the auxiliary device 210 and is electrically connected (via the interconnect metal) to the active gate control terminal 10 that is configured over the fourth region 11 of the active device 205. The interconnection between the second additional terminal 12 of the auxiliary device 210 and the active gate terminal 10 of the active device 205 may be made in a third dimension and different metal layers may be used in the process. Note that this interconnect is not shown in the schematic representation of fig. 2. A similar, but not necessarily identical AlGaN/GaN structure is used in the auxiliary gate.
The auxiliary gates 14, 15 drive the active gates 10, 11 when the device is in use. The portion of the auxiliary 2DEG layer formed between the first and second additional terminals 16 and 12 and below the auxiliary p-GaN gate 14 is controlled by the potential applied to the auxiliary gate terminal 15.
When the auxiliary gate terminal 15 and the shorted first additional terminal 16 are at 0V, the portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 is depleted. As the auxiliary gate bias (both terminals 15, 16) increases, a 2DEG begins to form under the pGaN gate 14, which pGaN gate 14 is connected to the already formed 2DEG layer, which 2DEG layer is connected to the first additional terminal 16 and the second additional terminal 12. The 2DEG connection is now located between the first additional terminal 16 and the second additional terminal 12.
When the second additional terminal 12 is connected to the active gate 10, the device can now be switched on. A positive (and desirable) shift in the threshold voltage of the device is observed with this structure because not all of the potential applied to the auxiliary gate 15 is transferred to the active gate 10. A part of this potential is used to form an auxiliary 2DEG under the auxiliary gate 15 and only a part is transferred to the second additional terminal 12 connected to the active gate 10.
The auxiliary gate provides the additional advantage of being able to more easily control the gate resistance of the device. This can be achieved by changing the field plate design or the distance between terminals 12 and 15 or 15 and 16. This can be used to control the unexpected oscillations observed due to the fast switching of these devices.
Different embodiments of the device may include terminals 10, 15 that are schottky or ohmic contacts or any combination of the two.
Fig. 3 shows a schematic representation of a circuit of one embodiment of the proposed disclosure as shown in the schematic cross-section of fig. 2. The features shown in fig. 3 have the same reference numerals as the features in fig. 2.
Fig. 4A shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a low on-state voltage diode is connected in parallel between the drain and source of the auxiliary transistor, as shown in the schematic 3D illustration in fig. 4B. Many features of this embodiment are similar to those of fig. 2 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2A passivation layer 6, an isolation region 13, an auxiliary A1GaN layer 17, an auxiliary pGaN layer 14, an auxiliary gate 15, a first additional terminal 16, and a second additional terminal 12. However, in this embodiment, the low on-state voltage diode 31 is connected in parallel between the drain 16 and the source 12 of the auxiliary transistor. During the turn-off of the entire configuration connecting the gate terminal 10 of the active GaN transistor to ground, the parallel diode 31 acts as a pull-down network. When a forward bias (referred to as the on-state) is applied to the auxiliary gate, the diode will be reverse biased and zero current will flow through it, which does not affect the electrical behavior of the entire high voltage configuration. When zero bias (off state) is applied to the auxiliary gate 15, the diode 31 will be forward biased and the off current flowing through it will discharge the gate capacitance of the active transistor, thereby enabling the entire arrangement to be switched off. In the off state, the gate of active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. The diode 31 is therefore designed such that its turn-on voltage is as low as possible, ideally a few millivolts. Fig. 4B shows how the diode 31 may be monolithically comprised. The diode may be a simple schottky diode or may be a normal p-n diode. Diode 31 pulls active gate 10 down to diode V during turn-offthTherefore, the diode needs to be designed to have a threshold voltage as low as possible. One feature that can achieve this is to use a recessed anode to make direct contact with the 2DEG, as shown in fig. 4C.
Fig. 5 shows a schematic circuit representation of a further embodiment of the proposed disclosure, wherein the drain (gate) terminal of the auxiliary transistor16 and the source terminal 12 may serve as external gate terminals. Many features of this embodiment are similar to those of fig. 2 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2Passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. However, in this case, the external gate terminal is divided into two terminals. Component 31 in fig. 4 may (or may not) be omitted since the gate driver receiver output pin may now be directly connected to the source terminal of the auxiliary transistor providing the pull-down path.
Fig. 6 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a second auxiliary transistor 34 (which may advantageously be a low voltage) is connected in parallel with the first auxiliary transistor, wherein the drain (gate) terminal 16 of the first auxiliary transistor is connected with the source terminal of the second auxiliary transistor, and the source terminal 12 of the first low auxiliary transistor is connected with the drain (gate) terminal of the second auxiliary transistor. Many features of this embodiment are similar to those of fig. 2 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2Passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16 and second additional terminal 12. In this case, however, the pull-down network during the turn-off of the entire configuration is the second auxiliary transistor 34.
Fig. 7 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a resistor 41 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor 34. Many features of this embodiment are similar to those of fig. 6 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal10. Surface passivation medium 7, low-voltage source electrode terminal 8, high-voltage drain electrode terminal 9 and SiO2Passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, the resistor 41 functions to reduce the active gate capacitance discharge time through the pull-down network during the active device turn-off. The additional resistor performs this function by generating an increased potential of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12 during turn-off.
Fig. 8 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein an additional resistor 42 is added between the source terminal of the auxiliary transistor (the drain terminal 12 of the second auxiliary transistor) and the source terminal 8 of the active device. Many features of this embodiment are similar to those of fig. 7 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, A1GaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2Passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, second auxiliary transistor 34, and resistive element 41. In this embodiment, the additional resistive element 42 acts as an additional pull-down network during the off period of the active device. The additional resistor 42 may act as a voltage limiting component to protect the gate terminal of the active device during its on and conducting states.
Fig. 9 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a third auxiliary transistor 58 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor. Many features of this embodiment are similar to those of fig. 8 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2A passivation layer 6, an isolation region 13, an auxiliary AlGaN layer 17, an auxiliary pGaN layer 14, an auxiliary gate 15, a fifth electrodeAn additional terminal 16, a second additional terminal 12, a second auxiliary transistor 34 and an additional resistive element 41. In this embodiment, the third auxiliary transistor functions to reduce the active gate capacitance discharge time through the pull-down network during the heterojunction power device turn-off. The third auxiliary transistor 58 performs this function by generating an increased potential of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12 during turn-off. The third auxiliary transistor is a depletion mode device. The gate terminal of the third auxiliary transistor is connected to the source terminal of the third auxiliary transistor.
Fig. 10 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein a third auxiliary transistor 59 is added between the drain terminal 12 and the gate terminal 10 of the second auxiliary transistor. Many features of this embodiment are similar to those of fig. 8 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, A1GaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2A passivation layer 6, an isolation region 13, an auxiliary A1GaN layer 17, an auxiliary pGaN layer 14, an auxiliary gate 15, a first additional terminal 16, a second additional terminal 12, a second auxiliary transistor 34, and an additional resistance element 41. In this embodiment, the third auxiliary transistor functions to reduce the active gate capacitance discharge time through the pull-down network during the heterojunction power device turn-off. The third auxiliary transistor 59 performs this function by generating an increased potential of the second auxiliary transistor gate terminal 10 compared to the second auxiliary transistor drain terminal 12 during turn-off. The third auxiliary transistor is a depletion mode device. The gate terminal of the third auxiliary transistor is connected to the drain terminal of the third auxiliary transistor.
Fig. 11 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which a voltage limiting circuit consisting of a resistor 44, a resistor 45 (forming a voltage divider) and an actively switched low voltage enhancement mode transistor 43 is implemented. Many features of this embodiment are similar to those of fig. 6 and therefore have the same reference numerals, i.e., the semiconductor substrate 4, the substrate terminal 5, the transition layer 3, the,GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation medium 7, low-voltage source terminal 8, high-voltage drain terminal 9, SiO2Passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, when the potential of the first additional terminal 16 (or the drain (gate) terminal 16) rises above a certain value, which value can be controlled by the choice of resistors (44, 45) in the described voltage divider, the enhancement mode transistor 43 can be switched on, thereby adjusting the resistance between the active device gate terminal 10 and the active device source terminal 8. This function may protect the active gate terminal from overvoltage events.
Fig. 12 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which a voltage limiting circuit comprising a resistor 44, a resistor 45 (forming a voltage divider) and an actively switched low voltage depletion mode transistor 46 is implemented. Many features of this embodiment are similar to those of fig. 6 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, A1GaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2Passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, when the potential of the first additional terminal 16 (or the drain (gate) terminal 16) of the first auxiliary heterojunction transistor increases, the resistance of the depletion mode transistor 46 may be reduced, thereby adjusting the resistance between the active device gate terminal 10 and the active device source terminal 8. The potential on the gate terminal of the depletion mode transistor 46 is determined by a voltage divider formed by two resistors (44, 45). The described circuit can protect the active gate terminal from an overvoltage event.
Fig. 13 shows a schematic circuit representation of a further embodiment of the proposed disclosure, in which an over-current protection circuit consisting of a current sense resistor 48 and an actively switched low voltage enhancement mode transistor 49 is implemented. License of this embodimentThe multi-features are similar to those of fig. 6 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation medium 7, low voltage source terminal 8, high voltage drain terminal 9, SiO2A passivation layer 6, an isolation region 13, an auxiliary A1GaN layer 17, an auxiliary pGaN layer 14, an auxiliary gate 15, a first additional terminal 16, a second additional terminal 12, and a second auxiliary transistor 34. In this embodiment, the active region of the active (high voltage) transistor is divided into two regions, which form two transistors in parallel. The drain and gate terminals of the two transistors are electrically connected. The two transistors in parallel are a low resistance (main power) transistor 55 and a high resistance (current sense) transistor 54, respectively. A first terminal of the current sense resistor 48 is connected to a source terminal of a high resistance transistor 54. The potential at the gate terminal of the enhancement mode transistor 49 increases with increasing current through the current sense resistor 48. When the current through the resistive element 48 reaches a critical value, the enhancement mode transistor 49 is turned on, providing a reduction in the resistance of the path between the gate 10 and the source 8 of the active (high voltage) device, thereby limiting the potential on the active gate terminal 10. The described circuit may protect the circuit from an overcurrent event.
Fig. 14 shows a schematic circuit representation of a further embodiment of the proposed disclosure, in which an over-current protection circuit consisting of a current sense resistor 48 and an actively switched low voltage depletion mode transistor 47 is implemented. Many features of this embodiment are similar to those of fig. 6 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2Passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, second additional terminal 12, and second auxiliary transistor 34. In this embodiment, the active region of the active (high voltage) transistor is divided into two isolation regions, which form two transistors in parallel. The drain and gate terminals of the two transistors are electrically connected. The two transistors connected in parallel are respectively of low resistance (main power)Rate) transistor 55 and a high resistance (current sense) transistor 54. A first terminal of the current sense resistor 48 is connected to a source terminal of a high resistance transistor 54. The potential at the gate terminal of depletion mode transistor 47 increases with increasing current through resistive element 48. As the current through the resistive element 48 increases, the resistance of the depletion mode transistor 49 decreases, providing a decrease in the resistance of the path between the gate 10 and the source 8 of the active (high voltage) device, thereby limiting the potential on the active gate terminal 10. The described circuit may protect the circuit from an overcurrent event.
Fig. 15 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which an active miller clamp circuit consisting of a resistor 52, an actively switched low-voltage enhancement mode transistor 50 and an actively switched depletion mode transistor 51 is implemented. Many features of this embodiment are similar to those of fig. 6 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, AlGaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2A passivation layer 6, an isolation region 13, an auxiliary A1GaN layer 17, an auxiliary pGaN layer 14, an auxiliary gate 15, a first additional terminal 16, a second additional terminal 12, and a second auxiliary transistor 34. In this embodiment, an active miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during the device turn-off transient.
Fig. 16 shows a circuit schematic representation of a further embodiment of the proposed disclosure, in which an active miller clamp circuit consisting of a resistor 52, an actively switched low-voltage enhancement-mode transistor 50 and an actively switched enhancement-mode transistor 53 is implemented. Many features of this embodiment are similar to those of fig. 6 and therefore have the same reference numerals, i.e., semiconductor substrate 4, substrate terminal 5, transition layer 3, GaN layer 2, A1GaN layer 1, active pGaN layer 11, active gate terminal 10, surface passivation dielectric 7, low voltage source terminal 8, high voltage drain terminal 9, SiO, and so forth2Passivation layer 6, isolation region 13, auxiliary AlGaN layer 17, auxiliary pGaN layer 14, auxiliary gate 15, first additional terminal 16, and second additional terminalTerminal 12 and a second auxiliary transistor 34. In this embodiment, an active miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during the device turn-off transient.
Fig. 17 shows a schematic representation of a cross-section of the active region of a depletion mode device of a transistor proposed in the prior art that can be used as an actively switched in positions 46, 47, 51, 58, 59, 60.
Fig. 18 shows a three-dimensional schematic representation of the active region of a depletion mode device with pGaN islands (not found in the prior art) of the proposed transistor that can be used as an actively switched in locations 46, 47, 51, 58, 59.
Fig. 19 shows a three-dimensional schematic representation of the active region of a depletion mode device having the pGaN island shown in fig. 18 operating in diode mode and used at locations 34, 58, 59.
Fig. 20 shows the transfer characteristics of the depletion mode device shown in fig. 18.
Fig. 21 shows a cross-section of an additional embodiment according to the second aspect of the proposed invention. Features shown in figure 21 have the same reference numerals as those shown in figure 2. In this embodiment, the first additional terminal 16 is not operatively connected with the auxiliary gate terminal 15.
Fig. 22 shows a schematic representation of the structure of fig. 21, and corresponding features of the figure are given the same reference numerals. In this embodiment, a series of components may be added between the auxiliary gate terminal 15 and the first additional terminal 16. By way of example only, these components may include, but are not limited to, any one or more of resistive elements, passive elements, and current sources. Further illustrative examples of such embodiments are presented herein.
In fig. 23, a gallium nitride (GaN) chip 1000 (also referred to as a smart GaN power device or GaN power or high voltage integrated circuit) according to an embodiment of the second aspect of the invention is shown. The GaN chip may include at least three terminals. The at least three terminals may include one or more of a high voltage terminal, a low voltage terminal, and a control terminal. The chip 1000 may also include one or more main power heterojunction transistors 500 with internal gates. The source and drain terminals of transistor 500 may be connected to the low and high voltage terminals of the GaN chip, respectively. The chip 1000 may also include a current control circuit 530, a pull-down circuit 520, and/or an auxiliary gate circuit 510. The auxiliary gate circuit 510 may include at least one low voltage heterojunction transistor (also referred to as an auxiliary transistor) having an internal gate.
The auxiliary gate circuit 510 may be operatively connected with at least the internal gate of the one main power heterojunction transistor 500 through a first connection, and may further include a second connection operatively connecting the auxiliary gate 510 with a control terminal. The third connection of the auxiliary gate circuit 510 may operatively connect the internal gate of the low voltage heterojunction transistor of the auxiliary gate circuit 510 with the pull-down circuit 520.
The pull-down circuit 520 may include at least one connection to the current control circuit and at least one connection to the source terminal of the main power heterojunction transistor 500 in addition to at least one connection to the auxiliary gate circuit.
The current control circuit 530 may include at least one connection to each of the control terminal, the auxiliary gate circuit 510, and the pull-down circuit 520.
The auxiliary gate 510 may partially control the voltage and current levels entering the internal gate of the main power heterojunction transistor 500. The current control circuit 530 may control the level of current into the pull-down circuit 520 and, in conjunction with the pull-down circuit, may further determine the voltage level applied to the internal gate of the low-voltage heterojunction transistor of the auxiliary gate 510. The pull-down circuit may in turn actively pull down the gate voltage of the low voltage heterojunction transistor so as to clamp the voltage of the internal gate of the main power heterojunction transistor.
Referring to fig. 22 and 23, in some embodiments, the auxiliary gate terminal 15 of the auxiliary gate block 510 may be connected with the first additional terminal 16 of the auxiliary gate block 510 through or via a current control block 530. The auxiliary gate terminal 15 may also be connected with the source terminal 8 of the active device block 500 through or via the pull-down circuit block 520.
When the auxiliary gate terminal 15 is at or near 0V, the portion of the auxiliary 2DEG under the auxiliary pGaN gate 14 may be depleted. As the first additional terminal bias is increased, the potential on both bias terminals 15, 16 may increase and a 2DEG may begin to form under the pGaN gate 14. The 2DEG formed under the pGaN gate 14 may be connected with the 2DEG layer (already formed) under the first and second additional terminals 16 and 12. By connecting these 2DEG layers, a 2DEG connection can be formed between the first additional terminal 16 and the second additional terminal 12.
When the second additional terminal 12 is connected to the active gate 10, the device can now be switched on. A positive shift in the threshold voltage of the device is observed using this structure because not all of the potential applied to the first additional terminal 16 is transferred to the active gate (internal gate) 10. A part of this potential drops on the auxiliary gate 510 and only a part is transferred to the second additional terminal 12 connected to the active gate (internal gate) 10. Advantageously, this enables the threshold voltage to be increased without compromising the on-state resistance of the device, as described below.
Fig. 24 shows an example of the relationship between an external gate voltage bias (GaN chip control terminal bias) 2501 and an active gate voltage (internal gate voltage) 2502 according to one embodiment of the present invention. When the external gate voltage signal initially rises (up to the auxiliary gate transistor Vth), the auxiliary gate transistor has a high resistance. Most of the applied potential drops across the auxiliary gate transistor and the potential of the active gate terminal remains close to 0V. When the external gate voltage signal reaches the auxiliary gate transistor Vth, the resistance of the auxiliary transistor becomes small, and the potential of the active gate terminal starts to rise.
Therefore, threshold voltage increase is achieved in the GaN chip multi-block HEMT without affecting the on-state resistance of the device. A positive shift in the threshold voltage of the device is observed with this structure (as shown in figure 2500) because not all of the potential applied to the external gate is transferred to the active gate (a portion of this potential is used to form the auxiliary 2DEG under the auxiliary gate) and only a portion is transferred to the terminal 12 connected to the active gate 10.
When the external gate 16 bias voltage reaches the pre-designed level, the pull-down circuit block 520 starts operating and pulls the gate 15 of the auxiliary transistor towards the potential of the active transistor source terminal 8. The auxiliary transistor has a high resistance in this case, so any additional external gate potential drops across the auxiliary transistor, and the active gate terminal potential remains approximately constant, e.g., at least about 20V, as the external gate voltage signal rises.
The design of the current control block 530 and the pull-down circuit block 520 determine the potential at which the active gate terminal is clamped.
Several illustrative examples of different implementations with functional blocks 510, 520, 530 are included herein. Note that the list of examples is not exhaustive and any combination of different implementations of each block may be considered within the scope of the invention. This includes several examples of the auxiliary gates described above. In addition, any or all of the protection and control circuits described above (over-voltage, over-current, miller clamp) may also be combined with the functional block shown in fig. 23.
Fig. 25 shows a schematic representation of one embodiment of a GaN chip 1000a of the proposed invention. The auxiliary gate block 510a includes an enhancement mode low voltage HEMT, the current control block 530a includes a resistor, and the pull-down circuit 520a includes a HEMT in a threshold multiplier configuration. The threshold multiplier configuration in this embodiment includes a voltage divider and a pull-down enhancement mode HEMT, where the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT. In this embodiment, the top of the voltage divider is connected to the drain of the pull-down enhancement mode HEMT and the gate terminal of the auxiliary gate block HEMT.
Fig. 26 shows a schematic representation of a further embodiment of the GaN chip 1000b of the proposed invention, wherein the auxiliary gate block 510b comprises an enhancement mode low-voltage HEMT. The current control block 530b includes a resistor in parallel with the RC circuit. The parallel RC circuit may improve the dynamic characteristics of the device during turn-on and turn-off transients. The pull-down circuit 520b includes a HEMT with parallel passive elements in a threshold multiplier configuration. The passive elements may improve the dynamic characteristics of the device during turn-on and turn-off transients.
Fig. 27 shows a schematic representation of a further embodiment of a GaN chip 1000c of the proposed invention. The auxiliary gate block 510c includes an enhancement mode low voltage HEMT and a schottky or p-n diode in parallel. In this embodiment a low on-state voltage diode is connected in parallel between the drain 16 and the source 12 of the auxiliary transistor. During the turn-off of the entire configuration connecting the gate terminal 10 of the active GaN transistor to ground, the parallel diode acts as a pull-down network. When a forward bias (referred to as the on-state) is applied to the outer gate terminal 16, the diode will be reverse biased and zero current will flow through it, so as not to affect the electrical characteristics of the overall high voltage configuration. When zero bias (off state) is applied to the auxiliary gate 15, the diode is forward biased and the off current flowing through it will discharge the gate capacitance of the active transistor, thereby enabling the entire arrangement to be switched off. In the off state, the gate of active device 10 will remain biased to a minimum voltage equal to the turn-on voltage of the diode. Therefore, the diode is designed such that its turn-on voltage will be as low as possible, ideally a few millivolts. The current control block 530c includes a current source using a low-voltage depletion mode HEMT and a resistor. The value of the resistor may be adjusted to set the maximum current level that may flow through the current source. The pull-down circuit 520c includes a HEMT in a threshold multiplier configuration.
Fig. 28 shows a schematic representation of a further embodiment of the GaN chip 1000d of the proposed invention, wherein the auxiliary gate block 510d comprises an enhancement mode low-voltage HEMT. The current control block 530d includes a current source and a resistor using a low-voltage depletion mode HEMT. The pull-down circuit 520d includes a HEMT in a threshold multiplier configuration.
Fig. 29 shows a schematic representation of a further embodiment of the proposed inventive GaN chip 1000e, wherein the auxiliary gate block 510e comprises an enhancement mode low-voltage HEMT. Furthermore, in this embodiment a second auxiliary transistor (which may advantageously be a low voltage) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, wherein the drain terminal 16 of the first auxiliary transistor is connected with the drain terminal of the second auxiliary transistor and the source terminal 12 of the first auxiliary transistor is connected with the source (gate) terminal of the second auxiliary transistor. In this embodiment, the pull-down network during the turn-off of the entire configuration is the second auxiliary transistor. This is similar to the embodiment shown in fig. 27, but uses a second auxiliary transistor instead of a diode. The current control block 530e includes a current source and a resistor using a low-voltage depletion mode HEMT. The pull-down circuit 520e includes a HEMT in a threshold multiplier configuration.
Fig. 30 shows a schematic representation of a further embodiment of the GaN chip 1000f of the proposed invention, wherein the auxiliary gate block 510f comprises an enhancement mode low-voltage HEMT. Further, in this embodiment, as described in the embodiment of fig. 29, the second auxiliary transistor is connected in parallel with the first auxiliary transistor. The current control block 530f includes a current source and a resistor using a low-voltage depletion mode HEMT. The pull-down circuit 520f includes a HEMT in a threshold multiplier configuration. In this embodiment, the threshold multiplier further comprises a current source in parallel with one of the resistors in the voltage divider of the threshold multiplier circuit. The inclusion of a current source provides temperature stability in the value of the clamping voltage realized on the active gate of the high voltage transistor 500 when the voltage signal on the external gate terminal is high.
Fig. 31 shows a schematic representation of a further embodiment of the proposed inventive GaN chip 1000j, wherein the auxiliary gate block 510j comprises an enhancement mode low-voltage HEMT. The current control block 530j includes a current source using a low-voltage depletion mode HEMT and a resistor. The pull-down circuit 520j includes a HEMT in a threshold multiplier configuration similar to the previous embodiments including a voltage divider and an enhancement mode pull-down HEMT. However, in this embodiment, the resistor at the top of the voltage divider, which in the previous embodiments was connected to the drain terminal of the enhancement mode pull down HEMT, is alternatively connected to the source terminal of the depletion mode HEMT used in the current source of the control block.
Fig. 32 shows a block schematic representation of a further embodiment of the proposed invention. In this embodiment, some additional functional blocks are included compared to the embodiment shown in fig. 23. In this embodiment, as in the previous embodiments, an auxiliary gate block, a current control block, and a pull-down circuit block are included. An integrated active miller clamp is also included.
An active miller clamp circuit is implemented to provide an additional pull-down network for the active device gate terminal 10 during device turn-off transients. The active miller clamp circuitry may include a monolithically integrated miller clamp transistor 570, a logic inverter 560, an external gate signal to logic signal converter 540, and/or a dc to dc block 550 that generates the appropriate inverter VDD rail.
As shown in this embodiment, the transistor 570 may comprise a low-voltage enhancement mode HEMT. The logic inverter 560 may include a low-voltage enhancement mode HEMT and a resistor (similar to the inverter circuit shown in fig. 16). However, this is provided merely as an example configuration, and other logic inverter designs may be used instead of or in addition to other logic inverter designs. Enhancement mode devices used in the inverter may be formed in the same process step as the active high voltage transistors. Therefore, the upper limit of the voltage signal that can be applied to the gate of the inverter transistor can be lower than the external gate signal. Vg to logic block 540 may be used to reduce the external gate voltage signal to a voltage signal suitable for use with p-GaN technology enhancement mode HEMTs.
When the output of the inverter is high, the integrated miller clamp transistor may receive a signal near VDD to its gate terminal. Thus, if the available VDD rail is higher than the peak gate voltage that the integrated clamp resistor can withstand, DC/DC step 550 can be integrated into a GaN chip multi-block power device to reduce the VDD rail to a desired level.
Fig. 33 shows a schematic representation of a further embodiment of the proposed inventive GaN chip 3000a, wherein the auxiliary gate block 610a comprises a depletion-mode low-voltage HEMT. Current control block 630a includes a resistive element. The pull-down circuit 620a includes a HEMT in a threshold multiplier configuration. The operation of the GaN chip multi-block power device shown in this example is similar to the following operation of the device shown in fig. 25: when the external voltage signal exceeds a predetermined (by design) level, a clamping voltage signal is realized on the active gate terminal (internal gate terminal) of the high-voltage HEMT (main power heterojunction transistor) 500. The use of a depletion mode transistor in the auxiliary gate block in this embodiment may be less effective in providing an increased threshold voltage for the GaN chip power device 3000a compared to the GaN chip power device 1000 a. When the potential on the active gate is high and the potential at the external gate terminal is low, the low-voltage depletion-mode HEMT may be more efficient in providing the turn-off path as part of the turn-off network of the device due to the presence of the channel in the depletion-mode transistor.
Fig. 34 shows a schematic representation of a further embodiment of the proposed inventive GaN chip 3000b, wherein the auxiliary gate block 610b comprises a depletion-mode low-voltage HEMT. In this embodiment, a second auxiliary transistor (which may advantageously be a low voltage transistor) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, wherein the drain terminal 16 of the first auxiliary transistor is connected with the drain terminal of the second auxiliary transistor and the source terminal 12 of the first auxiliary transistor is connected with the source (gate) terminal of the second auxiliary transistor. In this embodiment, a second auxiliary transistor is included as an additional pull-down network during the turn-off of the high voltage transistor 500. The current control block 630e includes a current source and a resistor using a low-voltage depletion mode HEMT. The pull-down circuit 620e includes a HEMT in a threshold multiplier configuration.
Fig. 35 shows a schematic representation of a further embodiment of the proposed inventive GaN chip 3000d, wherein the auxiliary gate block 610d comprises a depletion-mode low-voltage HEMT. Furthermore, in this embodiment a second depletion mode auxiliary transistor (which may advantageously be low voltage) is connected in parallel with the first auxiliary transistor in the auxiliary gate block, wherein the drain terminal 16 of the first auxiliary transistor is connected with the drain terminal of the auxiliary gate block and the source terminal 12 of the first auxiliary transistor is connected with the source terminal of the second auxiliary transistor. The gate terminal of the second auxiliary transistor is connected to the source terminal of the high-voltage transistor 500. In this embodiment, a second depletion mode auxiliary transistor is included as an additional current path during the turn-on of the high voltage transistor 500. When the external gate signal goes high, the second depletion mode transistor is in saturation mode and provides an additional conduction path for charging the gate-source capacitance of the high voltage transistor 500. When the voltage of the active gate terminal rises above the threshold voltage of the second depletion mode transistor, the conduction path becomes very resistive. The current control block 630e includes a current source and a resistor using a low-voltage depletion mode HEMT. The pull-down circuit 620e includes a HEMT in a threshold multiplier configuration.
Fig. 36 shows a schematic representation of a further embodiment of the proposed inventive GaN chip 5000b, wherein the auxiliary gate block 810b comprises an enhancement mode low voltage HEMT. The current control block 830b includes a current source using a low-voltage depletion mode HEMT and a resistor. The pull-down circuit 820b includes a HEMT in a threshold multiplier configuration that includes a voltage divider and a pull-down enhancement mode HEMT, where the midpoint of the voltage divider is connected to the gate terminal of the pull-down HEMT. In this embodiment, the top of the voltage divider is connected to the active gate terminal instead of the drain of the pull-down enhancement mode HEMT in the previous embodiment.
In FIG. 37, the top of the voltage divider, which includes a plurality of E-HEMTs 821c connected with source-gates in series with resistors as shown in the previous embodiments, is connected to the active gate terminal. Although fig. 37 shows two HEMTs in series, a different number may be used. These HEMTs are one possible method for adjusting the voltage level that needs to be reached on the active gate terminal before the pull-down enhancement mode HEMT starts to operate.
Fig. 38 shows another method for adjusting the voltage level that needs to be reached on the active gate terminal before the pull-down enhancement mode HEMT begins operation. Fig. 38 uses an additional HEMT in the threshold multiplier configuration 821 d.
Fig. 39 shows a schematic representation of a further embodiment of the GaN chip 6000a of the proposed invention, wherein the auxiliary gate block 910a comprises an enhancement mode low voltage HEMT. The current control block 930a includes a current source using a low-voltage depletion mode HEMT and a resistor. The pull-down circuit 920a includes a HEMT in a threshold multiplier configuration that includes a voltage divider with the midpoint of the voltage divider connected to the gate terminal of the pull-down HEMT (similar to the previous embodiments). However, in this embodiment, the voltage divider is connected to the external gate terminal instead of the gate terminal of the auxiliary transistor. Further, additional HEMTs in a threshold multiplier configuration may be included between the gate and source terminals of the enhancement mode pull-down HEMTs. The additional threshold multiplier is used to limit the voltage on the gate terminal of the pull-down transistor. The additional threshold multiplier may alternatively be implemented using one or more diodes in series.
Fig. 40 shows a schematic representation of a further embodiment of the GaN chip 6000b of the proposed invention, wherein the auxiliary gate block 910b comprises an enhancement mode low voltage HEMT. The current control block 930b includes a current source using a low-voltage depletion mode HEMT and a resistor. The pull-down circuit 920b includes a pull-down enhancement mode HEMT with its gate connected to the output of a voltage divider (similar to other embodiments). In this embodiment, the voltage divider is connected to the external gate terminal and consists of a HEMT in a current source and threshold multiplier configuration. The current source is implemented using a low-voltage depletion mode HEMT and a resistor. The output of the voltage divider (divider) is the gate of the additional low voltage HEMT.
In further embodiments, the gate of the pull-down HEMT may be controlled by an additional external signal, preferably through a VG-to-Vlogic regulator as described above, or the gate of the pull-down HEMT may be controlled by the output of additional circuitry integrated on the GaN device that provides functions such as overcurrent protection, undervoltage lockout, supply voltage overvoltage protection, logic inverters, or others.
Fig. 41 illustrates a staggered device layout including auxiliary gate structures of further embodiments of the present disclosure. Many features of this embodiment are similar to those shown in fig. 21 and therefore have the same reference numerals, namely, the active gate terminal 10, the low voltage source terminal 8, the high voltage drain terminal 9, the first additional terminal 16 and the second additional terminal 12. Also shown in this illustration are source pad metal 18, drain pad metal 19 and gate pad metal 20. However, in this embodiment, unlike the gate pad metal 20 in the prior art device which is in direct contact with the gate finger 10, it is connected to the auxiliary gate terminal 16. The gate fingers in the interleaved structure are directly connected to the second additional terminal 12. Note that in this layout, as in the cross-section in the previous embodiment, an isolation layer is present between the auxiliary gate and the 2DEG in the active device. Additional operational blocks in the device are also shown: auxiliary gate block 510, pull-down circuit block 520, current control block 530. The interconnection metal layer 210 may be used to make connections of the different blocks.
Fig. 42 shows a staggered device layout of a further embodiment of the present disclosure, where the auxiliary gate and terminal regions are located under the source pad metal. Similarly, these circuits may be located under a gate pad or a drain pad (not shown). Many features of this embodiment are similar to those shown in fig. 41 and therefore have the same reference numerals, i.e., active gate terminal 10, low voltage source terminal 8, high voltage drain terminal 9, first additional terminal 16, second additional terminal 12, source pad metal 18, drain pad metal 19, gate pad metal 20, auxiliary gate block 510, pull-down circuit block 520, current control block 530, interconnect metal 210. However, in this embodiment, the auxiliary gate block, the current control block, and the pull-down circuit block are located below the source pad metal 18. The inter-metal vias 220 may connect the blocks at different metal layers in the process. Less additional wafer area will be required to include additional blocks compared to prior art designs. Note that in this illustration, the additional block is located below the source pad metal, however the present disclosure is intended to include: additional blocks may be located in the design below other pads present in the integrated circuit layout.
Fig. 43 shows a block diagram of a further embodiment of the proposed disclosure, where any one of the embodiments of the GaN chip power device 35 is located in a half-bridge configuration, where the external gates of both power devices (high and low side) are connected to a gate drive block, which in turn is connected to a logic block. The different components and blocks included in the figures may be discrete components or connected monolithically. This shows different examples of possible monolithic integration 36, 37, 38, while using the concept of auxiliary gates.
Fig. 44 shows a circuit schematic representation of a further embodiment of the proposed disclosure, wherein GaN chip power devices 35 according to the present disclosure are connected in a standard three-phase half-bridge configuration.
It should be understood that the auxiliary transistors described above for all embodiments may be low voltage transistors or high voltage transistors.
It will be further understood that terms such as "top" and "bottom", "above" and "below", "lateral" and "vertical", and "below" and "above", "front" and "back", "underlying", and the like, may be used conventionally in this specification and do not imply a particular physical orientation of the device as a whole.
While the disclosure has been described in terms of preferred embodiments, as set forth above, it should be understood that these embodiments are illustrative only, and that the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and substitutions in light of the present disclosure, which are to be considered as falling within the scope of the appended claims. Each feature disclosed or illustrated in this specification may be incorporated in the disclosure, either individually or in any suitable combination with any other feature disclosed or illustrated herein.
Reference to the literature
[1] Mishra et al, GaN-Based RF power devices and amplifiers, Proc. IEEE, vol 96, no 2, pp 287-305, 2008.
[2] Kwan et al, CMOS-Compatible GaN-on-Si Field-Effect Transistors for High Voltage Power Applications, IEDM, San Fran., Dec.2014, pp 17.6.1-17.6.4.
[3] Lenci et al, Au-free AlGan/GaN power diode 8-in Si substrate with gated edge termination, Elec. Dev. Lett., vol 34, no 8, pp 1035, 2013.
[4] Oka and t. nozawa, IEEE Electron Device lett, 29, 668 (2008).
[5] Y.cai, y.zhou, k.j.chen, and k.m.lau, IEEE Electron Device lett, 26, 435 (2005).
[6] Saito, y.takada, m.kuraguchi, k.tsuda, and i.omura, IEEE trans.electron Devices, 53, 356, (2006).
[7] Y.uemoto, m.hikita, h.ueno, h.matsuo, h.ishida, m.yanagihara, t.ueda, t.tanaka, and d.ueda, IEEE trans.electron Devices, 54, 3393 (2007).
[8] Hwang, h.choi, j.lee, h.s.choi, j.kim, j.ha, c.y.um, s.k.hwang, j.oh, j.y.kim, j.k.shin, y.park, u.i.chung, i.k.yoo, and k.kim, proc.ispsd, Bruges, Belgium, p.41 (2012).
[9] Urea, mo. morek, and m.kuball, IEEE trans.electron Devices, 59, 3327 (2012).
[10] L.Efthygiouo et al, On the physical operation and optimization of the p-GaN gate in normal-off GaN HEMT devices, appl.Phys.Lett., 110, 123502(2017)
[11]GS66504B，GaN Systems，Ottawa，Cabada。
[12]Infineon 650V CoolMOS C7 Power Tramsistor IPL65R130C7.
[13] L. Efthygmiou et al, On the Source of society Behaviour reducing Switching of Power Enhancement Mode GaN HEMTs, Energies, vol.10, No.3, 2017.
[14] Lee, L.Y.Su, C.H.Wang, Y.R.Wu, and J.Huang, "Impact of gate metal on the performance of p-GaN/AlGaN/GaN High Electron mobility transducers," IEEE Electron Device Lett., vol.36, No.3, pp.232-234, 2015.
[15] Ambacher, j.smart, j.r.shell, n.g.weimann, k.chu, m.murphy, w.j.schaff, l.f.eastman, r.dimitrov, l.wittman, m.stutzmann, w.rieger, and j.hilsenbeck, "Two-dimensional electron gates induced by quantum catalysis and piezoelectric polarization catalysts in N-and Ga-face AlGaN/GaN semiconductors," j.application.phys, vol.85, No.6, p.3222, 1999.
[16] Okita, h., Hikita, m., Nishio, a., Sato, t., Matsunaga, k, Matsuo, h., Mannoh, m, and Uemoto, y, 2016, june.through accessed and regeneration gate technology for regenerating process status of GaN-gits.in Power Semiconductor Devices and ICs (ISPSD), IEEE, 201628th International Symposium on (pp.23-26).
[17] Lu, b., Saadat, o.i. and Palacios, t., 2010.High-performance integrated dual-gate AlGaN/GaN ebhanding-mode transmitter. ieee Electron devices Letters, 31(9), pp.990-992.
[18] Yu, g., Wang, y, Cai, y, Dong, z, Zeng, c, and Zhang, b, 2013.Dynamic characteristics of AlGaN/GaN HEMTs with their green sheets using a double-gate structure ieee Electron devices Letters, 34(2), pp.217-219.
[19] Feng, P, Teo, K.H., Oishi, T., Yamanaka, K, and Ma, R., 2013, May.design of enhancement mode single-gate and double multi-channel GaN HEMTs with vertical polarity inversion hierarchy (ISPSD), 201325th International Symposium on (pp.203-206) IEEE.
[20] Xiaobin, x.i.n., pophritic, m. and Shur, m., Power Integrations, inc., 2013. Enhancement-mode HFET circuit arrangement having high power and high threshold voltage.u.s.patent 8, 368, 121.
[21]GaN Systems，GN001Application Guide Design with GaN Enhancement mode HEMT。
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