Integrated circuit structure and method of forming an integrated circuit structure

文档序号：489248 发布日期：2022-01-04 浏览：3次中文

阅读说明：本技术 集成电路结构和形成集成电路结构的方法 (Integrated circuit structure and method of forming an integrated circuit structure ) 是由陈建源谢豪泰于 2021-01-26 设计创作，主要内容包括：一种集成电路(IC)结构包括第一晶体管和第二晶体管。第一晶体管包含第一有源区域和安置在第一有源区域上的第一栅极,其中,第一栅极沿平行于第一有源区域的纵向方向的第一方向具有第一有效栅极长度。第二晶体管包含第二有源区域和安置在第二有源区域上的第二栅极,并且包含沿第一方向布置并且彼此分离的多个栅极结构,其中,第二栅极沿第一方向具有第二有效栅极长度,第二有效栅极长度是第一有效栅极长度的n倍,并且n为大于1的正整数。根据本申请的其他实施例,还提供了形成集成电路结构的方法。(An Integrated Circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a longitudinal direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1. According to other embodiments of the present application, methods of forming integrated circuit structures are also provided.)

1. An integrated circuit structure, comprising:

a first transistor comprising:

a first active region; and

a first gate disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a longitudinal direction of the first active region; and

a second transistor comprising:

a second active region; and

a second gate disposed on the second active region, and the second transistor includes a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.

2. The integrated circuit structure of claim 1, wherein the gate structures of the second gates are electrically connected to a same voltage node.

3. The integrated circuit structure of claim 1, wherein each of the gate structures has a gate length substantially the same as the first effective gate length, and wherein the number of gate structures is n.

4. The integrated circuit structure of claim 1, wherein the second transistor further comprises a plurality of gate spacers adjacent opposing sidewalls of each of the gate structures of the second gate.

5. The integrated circuit structure of claim 1, wherein the second transistor further comprises a plurality of source/drain regions in the second active region, the source/drain regions being respectively adjacent outermost two of the gate structures of the second gate, and a portion of the second active region between the outermost two of the gate structures of the second gate having a lower dopant concentration than the source/drain regions.

6. The integrated circuit structure of claim 1, wherein a first group of the gate structures of the second gate have a first gate length that is m times the first effective gate length, a second group of the gate structures have a second gate length that is o times the first effective gate length, wherein m and o are different positive integers.

7. The integrated circuit structure of claim 6, wherein, along the first direction, the first group of the gate structures is not located between two adjacent ones of the gate structures of the second group.

8. The integrated circuit structure of claim 1, wherein the first effective gate length is a minimum gate length in the integrated circuit structure.

9. An integrated circuit structure, comprising:

a first transistor comprising:

a first active region and a second active region separated by an isolation structure, wherein the first active region and the second active region extend along a first direction;

a gate having a plurality of gate structures disposed on the first active region and the second active region, respectively, wherein, along the first direction, an effective gate length of the gate is n times a critical dimension of a technology node of the first transistor, and n is a positive integer and greater than 1;

a plurality of gate spacers adjacent to each of the gate structures of the gate; and

a first source/drain region in the first active region; and

a second source/drain region in the second active region; and

a second transistor having a gate length substantially equal to the critical dimension of the technology node of the first transistor.

10. A method of forming an integrated circuit structure, comprising:

forming a first active region and a second active region extending in a first direction over a substrate, wherein the first active region and the second active region are separated by an isolation structure;

forming a first gate structure over the first active region;

forming a plurality of second gate structures over the second active region, wherein, along the first direction, a sum of gate lengths of the second gate structures is n times a gate length of the first gate structure, and n is a positive integer and greater than 1;

forming a first source/drain region in the first active region; and

forming a second source/drain region in the second active region, wherein a portion of the second active region between two adjacent second gate structures has a lower dopant concentration than the second source/drain region.

Technical Field

Embodiments of the present application relate to integrated circuit structures and methods of forming integrated circuit structures.

Background

As integrated circuits become smaller, the layout of the integrated circuits is changed to reduce the total area occupied by the integrated circuits. The reduction in layout area is achieved by replacing the integrated circuit elements with new structures that are smaller than previous versions of the integrated circuit elements. The reduction in layout area is also achieved by reducing the distance between circuit elements in the integrated circuit layer.

Disclosure of Invention

Embodiments of the present application relate to integrated circuit layouts and methods thereof.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A and 1B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the present invention.

Fig. 1C shows an equivalent circuit of fig. 1A and 1B.

Fig. 2A and 2B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 2C shows an equivalent circuit of fig. 2A and 2B.

Fig. 3A and 3B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 3C shows an equivalent circuit of fig. 3A and 3B.

Fig. 4A and 4B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 4C shows an equivalent circuit of fig. 4A and 4B.

Fig. 5A and 5B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 5C shows an equivalent circuit of fig. 5A and 5B.

Fig. 6A and 6B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 6C shows an equivalent circuit of fig. 6A and 6B.

Fig. 7A and 7B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 7C shows an equivalent circuit of fig. 7A and 7B.

Fig. 8A and 8B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 8C shows an equivalent circuit of fig. 8A and 8B.

Fig. 8D is a block diagram of an integrated circuit according to some embodiments of the invention.

Fig. 9A and 9B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 9C shows an equivalent circuit of fig. 9A and 9B.

Fig. 9D is a block diagram of an integrated circuit according to some embodiments of the invention.

Fig. 10A and 10B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 10C shows an equivalent circuit of fig. 10A and 10B.

11A and 11B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 11C shows an equivalent circuit of fig. 11A and 11B.

Fig. 12A and 12B illustrate top and cross-sectional views of an integrated circuit according to some embodiments of the invention.

Fig. 12C shows an equivalent circuit of fig. 12A and 12B.

Fig. 13 is a schematic diagram of an Electronic Design Automation (EDA) system 1300 according to some embodiments of the invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Field Effect Transistors (FETs) are components of some integrated circuits. A FET contains a channel region and also a source region and a drain region (collectively referred to as source/drain regions) separated by the channel region. The gate electrode is located over the channel region. By applying a voltage to the gate electrode, the conductivity of the channel region increases to allow current to flow from the source region to the drain region. The FET utilizes a conductive gate contact electrically connected to the gate electrode to apply a gate voltage to the FET and utilizes source/drain contacts electrically connected to the source/drain regions to conduct current to and from the FET.

Fig. 1A, 1B, and 1C illustrate an integrated circuit 100A according to some embodiments of the invention, where fig. 1A is a top view of the integrated circuit 100A and fig. 1B is a cross-sectional view along line B-B of fig. 1A. Fig. 1C shows an equivalent circuit of the integrated circuit 100B shown in fig. 1A and 1B.

The integrated circuit 100A includes a first transistor T1 and a second transistor T2. The first transistor T1 includes an active region 112 and the second transistor T2 includes an active region 114. Active regions 112 and 114 extend in the X direction. Here, the X direction is a longitudinal direction of the active regions 112 and 114, and the Y direction is a longitudinal direction of the gate structures 122 and 124, wherein the X direction is perpendicular to the Y direction. In some embodiments, active regions 112 and 114 are arranged along the X direction, but embodiments of the present invention are not limited thereto. In some embodiments, active regions 112 and 114 may protrude from the substrate and may be separated by a plurality of isolation structures made of oxide that provide electrical isolation between different active regions. Accordingly, in some embodiments, active regions 112 and 114 may also be referred to as Oxide Definition (OD) regions. For example, in fig. 1B, active regions 112 and 114 are separated by at least isolation structure 105. In some embodiments, the isolation structure 105 is a Shallow Trench Isolation (STI) structure formed by, for example: one or more trenches are etched in the substrate, one or more dielectric materials (e.g., silicon oxide) are deposited into the one or more trenches, and a Chemical Mechanical Polishing (CMP) process is then performed to level the deposited one or more dielectric materials with the substrate.

The active region 112 of the first transistor T1 includes a source region and a drain region, wherein the source region and the drain region are collectively referred to as a source/drain region 132. Similarly, the active region 114 of the second transistor T2 includes a source region and a drain region, wherein the source region and the drain region are collectively referred to as source/drain regions 134.

The first transistor T1 includes a gate structure 122 located over and across the active region 112. Similarly, the second transistor T2 includes a gate structure 124 located over and across the active region 114. In fig. 1B, a plurality of gate spacers 106 are disposed on opposing sidewalls of gate structures 122 and 124, respectively.

The gate structure 122 of the first transistor T1 has a gate length LG1, and the gate structure 124 of the second transistor T2 has a gate length LG 2. Here, "gate length" means the length (or width, depending on the viewing angle) of gate structures 122 and/or 124 measured in the X-direction. The gate lengths LG1 and LG2 are different from each other. The gate length LG2 is greater than the gate length LG 1. The channel region is defined as the overlap region between the gate structure and the active region. Since the gate length LG1 of the first transistor T1 is smaller than the gate length LG2 of the second transistor T2, the channel length of the first transistor T1 is smaller than the channel length of the second transistor T2. Accordingly, the first transistor T1 may be referred to as a short channel device, and the second transistor T2 may be referred to as a long channel device. In some embodiments, the gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 is n LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (e.g., n ═ 2, 3, 4 … …).

In some embodiments, gate length LG1 is the minimum gate length in integrated circuit 100A. In some embodiments, the gate length LG1 of the gate structure 122 is the Critical Dimension (CD) in the technology node (e.g., 10nm node, 7nm node, 5nm node, 3nm node, or greater). Here, the term "critical dimension" is the minimum (minimum) dimension of a pattern feature such as the gate lengths LG1 and LG 2. The critical dimension contributes to the overall pattern layout size and pattern layout density. In the depicted embodiment, each feature of the pattern (e.g., gate structures 122 and/or 124) has a dimension or size, such as a length along the X-direction. The size of each feature may be greater than or equal to a critical dimension of the pattern. As described above, the gate length LG1 is a critical dimension. That is, the gate length LG1 of the gate structure 122 of the first transistor T1 is the minimum (or smallest) gate length of the gate structure in the corresponding technology node. Because the gate length LG2 is greater than the gate length LG1, the gate length LG2 is greater than the critical dimension.

In some embodiments, a long channel device, such as the second transistor T2, may be used as a transistor in the header circuit because the long channel device may save leakage in the header circuit. In some other embodiments, a long channel device, such as the second transistor T2, may be used as an n-channel metal oxide semiconductor (NMOS) device in a skewed inverter. In a skewed inverter, if a p-channel metal oxide semiconductor (PMOS) device in the skewed inverter is designed to be stronger than an NMOS device in the skewed inverter, the NMOS device may be a long-channel device and the PMOS device may be a short-channel device. For example, the NMOS device of the skewed inverter may be the second transistor T2 described herein, and the PMOS device of the skewed inverter may be the first transistor T1 described herein. In still other embodiments, a long channel device, such as the second transistor T2, may be used as a transistor in the variation tolerant circuit because a long channel may provide less variation. Here, the variation tolerant circuit may include a sense amplifier in the memory device, a comparator in an analog-to-digital converter (ADC), and the like.

Active regions 112 and 114 may be formed on a substrate including, but not limited to, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a silicon germanium substrate. Other semiconductor materials including group III, group IV, and group V elements are within the scope of various embodiments. For example, active regions 112 and 114 may be formed by patterning a substrate, e.g., using photolithography and etching techniques. In some embodiments, active regions 112 and 114 are electrically isolated from each other by isolation structures (not shown). In some embodiments, the isolation structure is a Shallow Trench Isolation (STI) structure, including a trench filled with one or more dielectric materials. In some embodiments, the STI structures comprise silicon dioxide, silicon nitride, silicon oxynitride, or any other suitable insulating material.

Source/drain regions 132 and 134 are doped semiconductor regions positioned on opposite sides of corresponding gate structures 122 and 124. In some embodiments, the source/drain regions 132 and 134 comprise a p-type dopant, such as boron, used to form a p-type FET. In other embodiments, source/drain regions 132 and 134 comprise an n-type dopant, such as phosphorus, used to form an n-type FET.

In some embodiments, source/drain regions 132 and 134 may be epitaxially grown regions. For example, gate spacers 106 may be formed alongside dummy gate structures (which will be replaced by the final gate structures 122 and 124) by depositing and anisotropically etching spacer material, and subsequently, source/drain regions 132 and 132 by first having active regionsThe domains 112 and 114 are etched to form recesses, and then a crystalline semiconductor material is deposited in the recesses to be self-aligned to the gate spacers 106 by a Selective Epitaxial Growth (SEG) process, which in some embodiments may fill the recesses in the active regions 112 and 114 and may also extend beyond the original surfaces of the active regions 112 and 114 to form raised source/drain epitaxial structures. The crystalline semiconductor material may be elemental (e.g., Si or Ge, etc.) or an alloy (e.g., Si_1-xC_xOr Si_1-xGe_xEtc.). The SEG process may use any suitable epitaxial growth method, such as vapor/solid/liquid phase epitaxy (VPE, SPE, LPE), metalorganic cvd (mocvd), or Molecular Beam Epitaxy (MBE), among others.

Gate structures 122 and 124 extend across active regions 112 and 114, respectively, in the Y-direction. In some embodiments, gate structures 122 and 124 are high-k metal gate (HKMG) gate structures that may be formed using a gate-last process flow (interchangeably referred to as a gate replacement flow). In a gate last process flow, sacrificial dummy gate structures (e.g., polysilicon gates, not shown) are formed over active regions 112 and 114, respectively. Each of the dummy gate structures may include a dummy gate dielectric, a dummy gate electrode (e.g., a polysilicon gate), and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, etc.) may be deposited. Next, a dummy electrode material (e.g., polysilicon) may be deposited over the dummy gate dielectric and then planarized (e.g., by CMP). A hard mask layer (e.g., silicon nitride, silicon carbide, etc.) may be formed over the dummy gate material. A dummy gate structure is then formed by patterning the hard mask layer and transferring the pattern to the dummy gate dielectric and dummy gate material using suitable photolithography and etching techniques. After forming source/drain regions 132 and 134, the dummy gate structures are replaced with HKMG gate structures 122 and 124 as shown herein. The materials used to form the dummy gate structures and the hard mask can be deposited using any suitable method such as CVD, plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), plasma enhanced ALD (peald), or by thermal oxidation of the semiconductor surface, or combinations thereof.

In some embodiments, each of HKMG gate structures 122 and 124 includes a high-k gate dielectric material, a work function metal layer, and a fill metal. Exemplary high-k gate dielectric materials include, but are not limited to, silicon nitride, silicon oxynitride, hafnium oxide (HfO)₂)、LaHfO_x、ZrO₂Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxide, metal nitride, metal silicate, transition metal oxide, transition metal nitride, transition metal silicate, metal oxynitride, metal aluminate, zirconium silicate, zirconium aluminate, zirconium oxide, titanium oxide, aluminum oxide, hafnium oxide-aluminum oxide (HfO)₂-Al₂O₃) Alloys, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, HKMG gate structures 122 and 124 may also include an interfacial layer between the high-k gate dielectric material and active regions 112 and 114, respectively. The interfacial layer may comprise SiO₂SiON, etc.

Exemplary work function metal layers include TiN (for PMOS), TiAl (for NMOS), and the like. In some embodiments, the work function metal layer may comprise Rb, Eu, Sr, Ba, Sm, Tb, Y, Nd, La, Sc, Lu, Mg, Tl, Hf, Al, Mn, Zr, Bi, Pb, Ta, Ag, V, Zn, Ti, Nb, Sn, W, Cr, Fe, Mo, Cu, Ru, Sb, Os, TaN, TiN/TaN, Ta/Si/N, Te, Re, Rh, Be, Co, Au, Pd, Ni, Ir, Pt, Se.

Exemplary fill metals include, for example, copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN), or molybdenum nitride (MoN).

In some embodiments, the gate spacers 106 may be made of SiO₂、Si₃N₄、SiO_xN_ySiC, SiCN film, SiOC, silicon oxycarbonitride film and/or combinations thereof or may comprise SiO₂、Si₃N₄、SiO_xN_ySiC, SiCN films, SiOC, silicon oxycarbonitride films, and/or combinations thereof. The gate spacers 106 may be formed by, for example, depositing a dielectric layer over the dummy gate structuresAre deposited (as discussed above) and then an etch process is performed to remove horizontal portions of the dielectric material. In some embodiments, HKMG gate structures 122 and 124 may also include a barrier layer located between the workfunction metal layer and the fill metal. The barrier layer may comprise TiN, TaN, Ti, Co, etc.

Fig. 2A, 2B, and 2C illustrate an integrated circuit 100B according to some embodiments of the invention, where fig. 2A is a top view of the integrated circuit 100B and fig. 2B is a cross-sectional view along line B-B of fig. 2A. Fig. 2C shows an equivalent circuit of the integrated circuit 100A shown in fig. 2A and 2B. Some elements of fig. 2A, 2B and 2C are similar to those described in fig. 1A, 1B and 1C, and therefore relevant details are not repeated for the sake of brevity.

The integrated circuit 100B includes a first transistor T1 and a second transistor T3. The first transistor T1 described in fig. 2A, 2B, and 2C is the same as the first transistor T1 described in fig. 1A, 1B, and 1C. It is noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

The second transistor T3 has an active region 214. The active region 214 extends in the X direction. The second transistor T3 includes a plurality of gate structures 224 disposed on the active region 214. In some embodiments, each of the gate structures 224 has a gate length LG 1. That is, the gate length of each of the gate structures 224 of the second transistor T3 is the same as the gate length of the gate structure 122 of the first transistor T1, wherein the gate length LG1 is the critical dimension in the corresponding technology node. In some embodiments, the gate spacers 106 are disposed on opposing sidewalls of each of the gate structures 224.

In some embodiments, the gate structures 224 are electrically connected (e.g., by one or more metal lines and one or more vias, not shown, in a back-end-of-line (BEOL) interconnect structure) and thus may be collectively referred to as a gate 220, where the gate 220 serves as the gate of transistor T3. In some embodiments, gate structures 224 are electrically connected to the same voltage node. In other words, the gate 220 of transistor T3 may be viewed as having several portions (e.g., gate structures 224) arranged along the X-direction, where each portion has spacers 106 disposed on opposing sidewalls thereof. As mentioned above, each of the gate structures 224 has a gate length LG 1. Thus, if the number of gate structures 224 is n, the effective gate length of the gate 220 of the transistor T3 is n × LG1, where n is a positive integer greater than 1. Accordingly, the first transistor T1 may be referred to as a short channel device, and the second transistor T3 may be referred to as a long channel device.

Transistor T3 has a plurality of source/drain regions 234 disposed in active region 214. In more detail, the source/drain regions 234 are disposed on opposite sides of the gate 220 of the transistor T3. That is, source/drain regions 234 are disposed adjacent the outermost gate structure 224. As an example in fig. 2A and 2B, one source/drain region 234 is disposed adjacent the rightmost gate structure 224, while the other source/drain region 234 is disposed adjacent the leftmost gate structure 224. It should be noted that in some embodiments, there is no source/drain region between any two adjacent gate structures 224 of transistor T3. In other words, portions of active region 214 located between any two adjacent gate structures 224 are undoped or less doped, wherein the dopant concentration of these portions is less than the dopant concentration of source/drain regions 234. In practice, a first voltage and a second voltage may be applied to the source/drain region 234, respectively, and a third voltage may be applied to the gate 220 to operate the transistor T3. That is, a single voltage (e.g., a third voltage as described herein) is applied to the gate structure 224.

Fig. 3A, 3B, and 3C illustrate an integrated circuit 100C according to some embodiments of the invention, where fig. 3A is a top view of the integrated circuit 100C and fig. 3B is a cross-sectional view along line B-B of fig. 3A. Fig. 3C shows an equivalent circuit of the integrated circuit shown in fig. 3A and 3B. Some elements of fig. 3A, 3B, and 3C are similar to those described in fig. 1A, 1B, and 1C, and thus, for the sake of brevity, relevant details are not repeated.

Integrated circuit 100C includes transistor T4. Although not shown in fig. 3A to 3C, the integrated circuit 100C may include the transistor T1 as described in fig. 1A to 1C. It is noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

The transistor T4 has an active region 314. The active region 314 extends in the X-direction. Transistor T4 includes a plurality of gate structures 324, a plurality of gate structures 326, and a plurality of gate structures 328 disposed on active region 314. In some embodiments, the number of gate structures 324 may be x, the number of gate structures 326 may be y, and the number of gate structures 328 may be z, where x, y, z are positive integers. In some embodiments, each of the gate structures 324 has a gate length LG1, wherein the gate length LG1 is a critical dimension in the corresponding technology node. The gate length LG2 of each of the gate structures 326 is greater than the gate length LG1 of the gate structures 324. In some embodiments, the gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 is n LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (e.g., n ═ 2, 3, 4 … …). On the other hand, the gate length LG3 of each of the gate structures 328 is greater than the gate length LG1 of the gate structure 324. In some embodiments, the gate length LG2 is m times the gate length LG1, where m is a positive integer. That is, LG3 is m LG1, where m is a positive integer. In some embodiments, m is a positive integer and is greater than 1 (e.g., m — 2, 3, 4 … …). In the embodiment of fig. 3A to 3C, n is greater than m. For example, n may be 3, and m may be 2, but the present invention is not limited thereto.

The gate structures 324 form a first group GR1, the gate structures 326 form a second group GR2, and the gate structures 328 form a third group GR 3. In some embodiments, each of the groups GR1, GR2, and GR3 includes at least one gate structure having substantially the same gate length, while the gate length of one group is different from the gate length of the other groups. In some embodiments, groups Gr1, Gr2, and Gr3 are arranged sequentially along the X direction. In some embodiments, gate structures 324, 326, and 328 are electrically connected (e.g., by one or more metal lines and one or more vias in a BEOL interconnect structure, not shown) and thus may be collectively referred to as gate 320, where gate 320 serves as the gate of transistor T4. In some embodiments, gate structures 324, 326 and 328 are electrically connected to the same voltage node. From another perspective, the gate 320 of transistor T4 may be viewed as having several portions (e.g., gate structures 324, 326, and 328) arranged along the X-direction, where each portion has spacers 106 disposed on opposing sidewalls thereof. Also, the sections may be divided into several groups (e.g., groups GR1, GR2, and GR3), where the sections in each group have substantially the same gate length.

As mentioned above, the number of gate structures 324, 326 and 328 is x, y and z, respectively, where x, y and z are positive integers. Therefore, the effective gate length of the gate 320 of the transistor T4 is x × LG1+ y × LG2+ z × LG 3. From another perspective, the gate length LG2 of the gate structure 326 can be denoted as n × LG1, and the gate length LG3 of the gate structure 328 can be denoted as m × LG 1. Therefore, the effective gate length of the gate 320 of the transistor T4 can also be represented by x × LG1+ y × n LG1+ z × m LG1, i.e., (x + y × n + z × m) LG 1. Since x, y, z, n, m are all positive integers, the term x + y n + z m is also a positive integer. That is, the effective gate length of the gate 320 of the transistor T4 is several times (e.g., x + y × n + z × m times) the gate length LG1 with the critical dimension. Therefore, the transistor T4 may be referred to as a long channel device. It should be noted that the integrated circuit 100C of fig. 3A-3C may also include a short channel device, such as the transistor T1 depicted in fig. 1A-1C.

Transistor T4 has a plurality of source/drain regions 334 disposed in active region 314. In more detail, the source/drain regions 334 are disposed on opposite sides of the gate 320 of the transistor T4. That is, the source/drain regions 334 are disposed adjacent the outermost gate structure. As an example in fig. 3A and 3B, one source/drain region 334 is disposed adjacent the leftmost gate structure 324, while the other source/drain region 334 is disposed adjacent the rightmost gate structure 328. It should be noted that in some embodiments, there is no source/drain region between any two adjacent gate structures 324, 326 and 328 of transistor T4. In other words, portions of the active region 314 located between any two adjacent gate structures 324, 326, and 328 are undoped or less doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source/drain regions 334. In practice, the first and second voltages may be applied to the source/drain regions 334, respectively, and the third voltage may be applied to the gate 320 to operate the transistor T4. That is, a single voltage (e.g., the third voltage described herein) is applied to gate structures 324, 326, and 328.

Fig. 4A, 4B, and 4C illustrate an integrated circuit 100D according to some embodiments of the invention, where fig. 4A is a top view of the integrated circuit 100D and fig. 4B is a cross-sectional view along line B-B of fig. 4A. Fig. 4C shows an equivalent circuit of the integrated circuit 100D shown in fig. 4A and 4B. Some elements of fig. 4A, 4B and 4C are similar to those described in fig. 1A, 1B and 1C, and therefore, for the sake of brevity, relevant details are not repeated.

As shown in fig. 4A, 4B and 4C. The integrated circuit 100D includes a transistor T5. Although not shown in fig. 4A to 4C, the integrated circuit 100D may include the transistor T1 as described in fig. 1A to 1C. It is noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

The transistor T5 has an active region 414 extending in the X direction. The transistor T5 includes a gate structure 424 having a gate length LG1, a gate structure 426 having a gate length LG2, and a gate structure 428 having a gate length LG3, wherein the gate length LG1 is the critical dimension in the corresponding technology node. In some embodiments, the gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 is n LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (e.g., n ═ 2, 3, 4 … …). On the other hand, the gate length LG3 of each of the gate structures 328 is greater than the gate length LG1 of the gate structure 324. In some embodiments, the gate length LG2 is m times the gate length LG1, where m is a positive integer. That is, LG3 is m LG1, where m is a positive integer. In some embodiments, m is a positive integer and is greater than 1 (e.g., m — 2, 3, 4 … …). For example, n may be 2, and m may be 3, but the present invention is not limited thereto.

The gate structures 424 form a first group GR1, the gate structures 426 form a second group GR2, and the gate structures 428 form a third group GR 3. In some embodiments, each of the groups GR1, GR2, and GR3 includes at least one gate structure having substantially the same gate length, while the gate length of one group is different from the gate length of the other groups. In some embodiments, groups Gr1, Gr2, and Gr3 are arranged sequentially along the X direction. That is, gate structure 426 and/or gate structure 428 may not be present between two gate structures 424, and vice versa. In some embodiments, gate structures 424, 426, and 428 are electrically connected and may be collectively referred to as gate 420, where gate 420 serves as the gate of transistor T5. In some embodiments, gate structures 424, 426, and 428 are electrically connected to the same voltage node. From another perspective, the gate 420 of transistor T5 may be viewed as having several portions (e.g., gate structures 424, 426, and 428) arranged along the X-direction, where each portion has spacers 106 disposed on opposing sidewalls thereof. Also, the sections may be divided into several groups (e.g., groups GR1, GR2, and GR3), where the sections in each group have substantially the same gate length.

The effective gate length of the gate 420 of the transistor T5 is 3 × LG1+2 × LG2+1 × LG 3. From another perspective, the gate length LG2 of the gate structure 426 may be denoted as n × LG1, and the gate length LG3 of the gate structure 428 may be denoted as m × LG 1. Therefore, the effective gate length of the gate 420 of the transistor T5 can also be represented by 3 × LG1+2 × n LG1+1 × m LG1, i.e., (3+2 × n +1 × m) LG 1. In some embodiments, where n-2 and m-4, the effective gate length of the gate 420 of the transistor T5 is 11 times (e.g., 3+2 x 2+1 x 4 times) the gate length LG1 having the critical dimension. Therefore, the transistor T5 may be referred to as a long channel device. It should be noted that the integrated circuit 100D of fig. 4A-4C may also include a short channel device, such as the transistor T1 depicted in fig. 1A-1C.

Transistor T5 has a plurality of source/drain regions 434 disposed in active region 414. In more detail, the source/drain regions 434 are disposed on opposite sides of the gate 420 of the transistor T5. That is, the source/drain regions 434 are disposed adjacent the outermost gate structure. As an example in fig. 4A and 4B, one source/drain region 434 is disposed adjacent the leftmost gate structure 424, while the other source/drain region 434 is disposed adjacent the rightmost gate structure 428. It should be noted that in some embodiments, there is no source/drain region between any two adjacent gate structures 424, 426 and 428 of transistor T5. In other words, the portions of the active region 414 located between any two adjacent gate structures 424, 426, and 428 are undoped or less doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source/drain regions 434. In practice, a first voltage and a second voltage may be applied to the source/drain region 434, respectively, and a third voltage may be applied to the gate 420 to operate the transistor T5. That is, a single voltage (e.g., the third voltage described herein) is applied to gate structures 424, 426, and 428.

Fig. 5A, 5B, and 5C illustrate an integrated circuit 100E according to some embodiments of the invention, where fig. 5A is a top view of the integrated circuit 100E and fig. 5B is a cross-sectional view along line B-B of fig. 5A. Fig. 5C shows an equivalent circuit of the integrated circuit 100E shown in fig. 5A and 5B. Some elements of fig. 5A, 5B, and 5C are similar to those described in fig. 1A, 1B, and 1C, and thus, for the sake of brevity, relevant details are not repeated.

As shown in fig. 5A, 5B and 5C. The integrated circuit 100D includes a transistor T6. Although not shown in fig. 5A to 5C, the integrated circuit 100E may include the transistor T1 as described in fig. 1A to 1C. It is noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

Transistor T6 includes an active region 514 and a plurality of gate structures 524, 526, and 528 disposed on active region 514. The gate structure 524 having the gate length LG1 is similar to the gate structure 424 of fig. 4A-4C, the gate structure 526 having the gate length LG2 is similar to the gate structure 426 of fig. 4A-4C, and the gate structure 528 having the gate length LG3 is similar to the gate structure 428 of fig. 4A-4C, and therefore, for the sake of brevity, relevant details are not repeated. Gate structures 526, and 528 are electrically connected and may be collectively referred to as gate 520, where gate 520 serves as the gate of transistor T6. In some embodiments, gate structures 524, 526, and 528 are electrically connected to the same voltage node.

The transistor T6 of fig. 5A to 5C differs from the transistor T5 of fig. 4A to 4C at least in that the gate structures 524, 526, and 528 are randomly arranged in the X direction. That is, for example, the gate structures 524 and/or the gate structures 528 may exist between two gate structures 524 having the same gate length LG1, and vice versa.

Transistor T6 has a plurality of source/drain regions 534 disposed in active region 514. In more detail, the source/drain regions 534 are disposed on opposite sides of the gate 520 of the transistor T5. That is, the source/drain regions 534 are disposed adjacent to the outermost gate structure. As an example in fig. 5A and 5B, one source/drain region 534 is disposed adjacent the leftmost gate structure 524, while the other source/drain region 534 is disposed adjacent the rightmost gate structure 524. It should be noted that in some embodiments, there is no source/drain region between any two adjacent gate structures 524, 526, and 528 of transistor T5. In other words, portions of the active region 514 located between any two adjacent gate structures 524, 526, and 528 are undoped or less doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source/drain regions 534. In practice, a first voltage and a second voltage may be applied to the source/drain region 534, respectively, and a third voltage may be applied to the gate 520 to operate the transistor T6. That is, a single voltage (e.g., the third voltage described herein) is applied to gate structures 524, 526, and 528.

Fig. 6A, 6B, and 6C illustrate an integrated circuit 100F according to some embodiments of the invention, where fig. 6A is a top view of the integrated circuit 100F and fig. 6B is a cross-sectional view along line B-B of fig. 6A. Fig. 6C shows an equivalent circuit of the integrated circuit shown in fig. 6A and 6B. Some elements of fig. 6A, 6B, and 6C are similar to those described in fig. 1A, 1B, and 1C, and thus, for the sake of brevity, relevant details are not repeated.

Integrated circuit 100F includes transistor T7. Although not shown in fig. 6A to 6C, the integrated circuit 100F may include the transistor T1 as described in fig. 1A to 1C. It is noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

The transistor T7 has active regions 614 and 616 extending in the X direction, wherein the active regions 614 and 616 are arranged in the Y direction. Transistor T7 has contacts 640 disposed on active regions 614 and 616, respectively, and metal lines 650 over the contacts and electrically connecting contacts 640. Thus, active region 614 is electrically connected to active region 616 through contacts 640 and metal lines 650. In some embodiments, the contacts 640 and the metal lines 650 are formed from a suitable metal, such as copper, aluminum, tungsten, or the like, or combinations thereof.

The second transistor T7 includes a plurality of gate structures 624 disposed on the active regions 614 and 616. In some embodiments, each of the gate structures 624 has a gate length LG 1. That is, each of the gate structures 224 of the second transistor T7 has substantially the same gate length, where the gate length LG1 is the critical dimension in the corresponding technology node. In some embodiments, the gate spacers 106 are disposed on opposing sidewalls of each of the gate structures 624.

In some embodiments, gate structure 624 is electrically connected and thus may be collectively referred to as gate 620 in the equivalent circuit of fig. 6C, where gate 620 serves as the gate of transistor T7. In some embodiments, gate structure 624 is electrically connected to the same voltage node. In other words, the gate 620 of transistor T7 may be viewed as having several portions (e.g., gate structures 624) arranged along the X-direction, where each portion has spacers 106 disposed on opposing sidewalls thereof. As mentioned above, each of the gate structures 624 has a gate length LG 1. Thus, if the number of gate structures 624 is n, the effective gate length of the gate 620 of the transistor T7 is n × LG1, where n is a positive integer greater than 1. Therefore, the transistor T7 may be referred to as a long channel device. It should be noted that the integrated circuit 100F of fig. 6A-6C may also include a short channel device, such as the transistor T1 depicted in fig. 1A-1C.

The transistor T7 has a plurality of source/drain regions 634 disposed in the active regions 614 and 616, respectively. In more detail, one source/drain region 634 is disposed on a first side of the active region 614, with the contact 640 disposed on a second side of the active region 614 opposite the first side of the active region 614. On the other hand, another source/drain region 634 is disposed on a first side of the active region 616, with a contact 640 disposed on a second side of the active region 616 opposite the first side of the active region 616. That is, the source/drain regions 634 are disposed on two separate active regions 614 and 614. It should be noted that in some embodiments, there are no source/drain regions between any two adjacent gate structures 624 of the transistor T7. In other words, portions of the active regions 614 and 616 between any two adjacent gate structures 624 are undoped or less doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source/drain regions 634. In the operation of the transistor T7, a first voltage and a second voltage may be applied to the source/drain region 634, respectively, and a third voltage may be applied to the gate 620 to operate the transistor T7. That is, a single voltage (e.g., the third voltage described herein) is applied to the gate structure 624. For example, current may flow from source/drain region 634 on active region 614 to source/drain region 634 on active region 616 through contacts 640 and metal lines 650.

Fig. 7A, 7B, and 7C illustrate an integrated circuit 100G according to some embodiments of the invention, where fig. 7A is a top view of the integrated circuit 100G and fig. 7B is a cross-sectional view along line B-B of fig. 7A. Fig. 7C shows an equivalent circuit of the integrated circuit 100G shown in fig. 7A and 7B. Some elements of fig. 7A, 7B and 7C are similar to those described in fig. 1A, 1B and 1C, and therefore, for the sake of brevity, relevant details are not repeated.

The integrated circuit 100G includes a transistor T8. Although not shown in fig. 7A to 7C, the integrated circuit 100G may include the transistor T1 as described in fig. 1A to 1C. It is noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

Similar to the transistor T7 of fig. 6A-6C, the transistor T8 has separate active regions 714 and 716. Transistor T8 has a contact 740 disposed on active areas 714 and 716, respectively, and a metal line 750 over contact 740 and electrically connecting contact 740.

Transistor T8 includes a plurality of gate structures 724, a plurality of gate structures 726, and a plurality of gate structures 728 disposed on active regions 714 and 716, respectively. Gate structures 724, 726 and 726 are electrically connected. In some embodiments, gate structures 724, 726, and 728 are electrically connected to the same voltage node. In some embodiments, the number of gate structures 724 may be x, the number of gate structures 726 may be y, and the number of gate structures 728 may be z, where x, y, z are positive integers. In some embodiments, each of the gate structures 724 has a gate length LG1, wherein the gate length LG1 is a critical dimension in the corresponding technology node. The gate length LG2 of each of the gate structures 726 is greater than the gate length LG1 of the gate structure 724. In some embodiments, the gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 is n LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (e.g., n ═ 2, 3, 4 … …). On the other hand, the gate length LG3 of each of the gate structures 728 is greater than the gate length LG1 of the gate structure 724. In some embodiments, the gate length LG2 is m times the gate length LG1, where m is a positive integer. That is, LG3 is m LG1, where m is a positive integer. In some embodiments, m is a positive integer and is greater than 1 (e.g., m — 2, 3, 4 … …). In the embodiment of fig. 7A to 7C, n is greater than m. For example, n may be 3, and m may be 2, but the present invention is not limited thereto.

The gate structures 724 form a first group GR1, the gate structures 726 form a second group GR2, and the gate structures 728 form a third group GR 3. In some embodiments, each of the groups GR1, GR2, and GR3 includes at least one gate structure having substantially the same gate length, while the gate length of one group is different from the gate length of the other groups. In some embodiments, the groups GR1, GR2, and GR3 are arranged sequentially along the X direction. In some embodiments, gate structures 724, 726, and 726 are electrically connected and may be collectively referred to as a gate 720, where gate 720 serves as the gate of transistor T8. In some embodiments, gate structures 724, 726, and 728 are electrically connected to the same voltage node. From another perspective, the gate 720 of transistor T8 may be viewed as having several sections (e.g., gate structures 724, 726, and 728) arranged along the X-direction, where each section has spacers 106 disposed on opposing sidewalls thereof. Also, the sections may be divided into several groups (e.g., groups GR1, GR2, and GR3), where the sections in each group have substantially the same gate length.

As mentioned above, the number of gate structures 724, 726, and 728 are x, y, and z, respectively, where x, y, and z are positive integers. Therefore, the effective gate length of the gate 720 of the transistor T8 is x × LG1+ y × LG2+ z × LG 3. From another perspective, the gate length LG2 of the gate structure 726 can be denoted as n × LG1, and the gate length LG3 of the gate structure 728 can be denoted as m × LG 1. Therefore, the effective gate length of the gate 720 of the transistor T8 can also be represented by x × LG1+ y × n LG1+ z × m LG1, i.e., (x + y × n + z × m) LG 1. Since x, y, z, n, m are all positive integers, the term x + y n + z m is also a positive integer. That is, the effective gate length of the gate 720 of the transistor T8 is several times (e.g., x + y × n + z × m times) the gate length LG1 with the critical dimension. Therefore, the transistor T8 may be referred to as a long channel device. It should be noted that the integrated circuit 100G of fig. 7A-7C may also include a short channel device, such as the transistor T1 depicted in fig. 1A-1C.

In some embodiments, the gate structures 724, 726, and 728 are randomly arranged along the X-direction. That is, for example, a gate structure 724 and/or a gate structure 728 may exist between two gate structures 724 having the same gate length LG1, and vice versa. In some other embodiments, gate structure 726 and/or gate structure 728 may not be present between two gate structures 724, and vice versa.

The transistor T8 has a plurality of source/drain regions 734 disposed in the active regions 714 and 716, respectively. In more detail, one source/drain region 734 is disposed on a first side of the active region 714, with the contact 740 disposed on a second side of the active region 714 opposite the first side of the active region 714. On the other hand, another source/drain region 734 is disposed on a first side of the active region 716, wherein the contact 740 is disposed on a second side of the active region 716 opposite the first side of the active region 716. That is, the source/drain region 734 is disposed on two separate active regions 714 and 716. It should be noted that in some embodiments, there is no source/drain region between any two adjacent gate structures 724, 726, and 728 of transistor T8. In other words, the portions of the active regions 714 and 716 located between any two adjacent gate structures 724, 726, and 728 are undoped or less doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source/drain regions 734. In the operation of the transistor T7, a first voltage and a second voltage may be applied to the source/drain region 734, respectively, and a third voltage may be applied to the gate 720 to operate the transistor T8. That is, a single voltage (e.g., a third voltage as described herein) is applied to the gate structures 724, 726, and 728. For example, current may flow from the source/drain region 734 on the active region 714 to the source/drain region 734 on the active region 716 through the contact 740 and the metal line 750.

Fig. 8A, 8B, and 8C illustrate an integrated circuit 100H according to some embodiments of the invention, where fig. 8A is a top view of the integrated circuit 100H and fig. 8B is a cross-sectional view along line B-B of fig. 8A. Fig. 8C shows an equivalent circuit of the integrated circuit 100H shown in fig. 8A and 8B. Some elements of fig. 8A, 8B, and 8C are similar to those described in fig. 1A, 1B, and 1C, and thus, for the sake of brevity, relevant details are not repeated.

Integrated circuit 100H includes transistor T9. Although not shown in fig. 8A to 8C, the integrated circuit 100H may include the transistor T1 as described in fig. 1A to 1C. It is noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

The transistor T9 has active regions 814, 816 and 818 extending in the X direction, wherein the active regions 814, 816 and 818 are arranged in the Y direction. Transistor T9 has contacts 842 disposed on active areas 814 and 816, respectively, and a metal line 852 above contacts 842 and electrically connecting contacts 842. Thus, active area 814 is electrically connected to active area 816 through contacts 842 and metal lines 852. On the other hand, the transistor T9 also has contacts 844 disposed on the active regions 816 and 818, respectively, and a metal line 854 over and electrically connecting the contacts 844. Thus, active region 816 is electrically connected to active region 818 through contacts 844 and metal lines 854.

The transistor T9 includes gate structures 821, 822, 823, 824, 825, 826, 827, 828, and 829 that are electrically connected using, for example, one or more metal lines and vias in a BEOL interconnect structure. In some embodiments, gate structures 821-829 are electrically connected to the same voltage node. Gate structures 821, 822, and 823 are disposed on the active area 814, gate structures 824, 825, and 826 are disposed on the active area 816, and gate structures 827, 828, and 829 are disposed on the active area 818.

In some embodiments, each of gate structures 821-829 may comprise a short gate length or a long gate length. As an example of fig. 8A and 8B, gate structures 821, 824, 825, and 828 have long gate lengths, while gate structures 822, 823, 826, 827, and 829 have short gate lengths. In some embodiments, the gate structures 822, 823, 826, 827, and 829 have substantially the same gate length LG1, where the gate length LG1 is the critical dimension in the corresponding technology node. On the other hand, gate structures 821, 824, 825, and 828 have substantially the same gate length LG 2. The gate length LG2 is greater than the gate length LG 1. In some embodiments, the gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 is n LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (e.g., n ═ 2, 3, 4 … …).

In some embodiments, gate structures 821-829 are electrically connected and may be collectively referred to as gate 820, wherein gate 820 serves as the gate of transistor T9. In some embodiments, gate structures 821-829 are electrically connected to the same voltage node. In other words, the gate 820 of transistor T9 may be viewed as having several sections (e.g., gate structures 821-829) arranged along the X-direction, wherein each section has spacers 106 disposed on opposing sidewalls thereof.

In some embodiments, the transistor T9 may include an x-gate structure having a short gate length LG1 and a y-gate structure having a long gate length LG2 (e.g., in this case, x-5 and y-4). Therefore, the effective gate length of the gate 820 of the transistor T9 is x × LG1+ y × LG 2. From another perspective, because gate length LG2 may be denoted as n × LG1, the effective gate length of gate 820 of transistor T9 may also be denoted as x × LG1+ y × n LG1, i.e., (x + y × n) LG 1. Since x, y, n are all positive integers, the term x + y n + z m is also a positive integer. That is, the effective gate length of the gate 820 of the transistor T9 is several times (e.g., x + y × n times) the gate length LG1 having the critical dimension. Therefore, the transistor T9 may be referred to as a long channel device. It should be noted that the integrated circuit 100H of fig. 8A-8C may also include a short channel device, such as the transistor T1 depicted in fig. 1A-1C.

The transistor T9 has a plurality of source/drain regions 834 disposed in the active regions 814 and 818, respectively. In more detail, one source/drain region 734 is disposed on a first side of the active region 814, wherein the contact 842 is disposed on a second side of the active region 814 opposite the first side of the active region 814. On the other hand, another source/drain region 734 is disposed on a first side of the active region 818, wherein the contact 844 is disposed on a second side of the active region 818 opposite the first side of the active region 818. That is, the source/drain regions 834 are disposed on two separate active regions 814 and 818. In addition, the active region 816 between the active region 814 and the active region 818 does not include source/drain regions 834. In other words, the dopant concentration of the entire active region 816 is lower than the dopant concentration of the source/drain regions 834. It should be noted that in some embodiments, there is no source/drain region between any two adjacent gate structures 821-829 of the transistor T9. In other words, the portions of the active regions 814, 816, and 818 between any two adjacent gate structures 821-829 are undoped or less doped, wherein the dopant concentration of these portions is less than the dopant concentration of the source/drain regions 834. In the operation of the transistor T8, a first voltage and a second voltage may be applied to the source/drain region 834, respectively, and a third voltage may be applied to the gate 820 to operate the transistor T9. That is, a single voltage (e.g., the third voltage described herein) is applied to gate structures 821-829. For example, current may flow from source/drain regions 834 on active region 814 to source/drain regions 834 on active region 818 through active region 816. In addition, active area 814 is electrically connected to active area 816 through contacts 842 and metal lines 852, and active area 816 is electrically connected to active area 818 through contacts 844 and metal lines 854.

Fig. 8D is a block diagram of the integrated circuit 100H of fig. 8A and 8D. As shown in fig. 8D, boxes 821A, 822A, 823A, 824A, 825A, 826A, 827A, 828A, and 829A are shown, wherein each of the boxes 821A-829A corresponds to a gate structure. For example, blocks 821A-829A may correspond to gate structures 821-829 of fig. 8A, respectively. In some embodiments, each of the boxes 821A-829A may comprise a short gate length or a long gate length. For example, the short gate length may be the gate length LG1 described in fig. 8A and 8B, and the long gate length may be the gate length LG2 described in fig. 8A and 8B. Thus, each of the boxes 821A-829A may contain two possibilities of gate length (e.g., short gate length or long gate length). In this regard, the combination of blocks 821A-829A of integrated circuit 100H may comprise 29 variations.

Fig. 9A, 9B, and 9C illustrate an integrated circuit 100I according to some embodiments of the invention, where fig. 9A is a top view of the integrated circuit 100I and fig. 9B is a cross-sectional view along line B-B of fig. 9A. Fig. 9C shows an equivalent circuit of the integrated circuit 100I of fig. 9A and 9B. Some elements of fig. 9A, 9B, and 9C are similar to those described in fig. 1A, 1B, and 1C, and thus, for the sake of brevity, relevant details are not repeated.

The integrated circuit 100I includes a transistor T10. Although not shown in fig. 9A to 9C, the integrated circuit 100I may include the transistor T1 as described in fig. 1A to 1C. It is noted that the gate length LG1 of the first transistor T1 is a critical dimension in the corresponding technology node.

Similar to the transistor T9 of fig. 8A through 8C, the transistor T10 has separate active regions 914, 916, and 918. Active region 914 is electrically connected to active region 916 through contacts 942 and metal lines 952. Active region 916, on the other hand, is electrically connected to active region 918 through contact 944 and metal line 954.

The transistor T10 includes gate structures 921, 922, 923, 924, 925, 926, 927, 928, and 929. Gate structures 921, 922, and 923 are disposed on active region 914, gate structures 924, 925, and 926 are disposed on active region 916, and gate structures 927, 928, and 929 are disposed on active region 918, respectively.

In some embodiments, the gate structures 921-929 have substantially the same gate length LG1, where the gate length LG1 is the critical dimension in the corresponding technology node.

In some embodiments, the gate structures 921-929 are electrically connected and may be collectively referred to as gates 920, where the gates 920 serve as the gates of the transistor T10. In some embodiments, gate structures 921-929 are electrically connected to the same voltage node. In other words, the gate 920 of transistor T10 may be viewed as having several portions (e.g., gate structures 921-929) arranged along the X-direction, where each portion has spacers 106 disposed on opposing sidewalls thereof.

In some embodiments, the transistor T10 may include x gate structures having a gate length LG1 (e.g., in this case, x ═ 9). Therefore, the effective gate length of the gate 920 of the transistor T10 is x LG 1. Therefore, the transistor T10 may be referred to as a long channel device. It should be noted that the integrated circuit 100I of fig. 9A to 9C may also include a short channel device, such as the transistor T1 described in fig. 1A to 1C.

In some embodiments, the gate structures 921-929 may comprise different threshold voltages. The threshold voltage of each gate structure 921-929 may depend on the material composition and/or thickness of the gate dielectric and the one or more work function metal layers therein. Thus, the equivalent threshold voltage of gate 920 depends on the threshold voltages of gate structures 921-929.

The transistor T9 has a plurality of source/drain regions 934 disposed in the active regions 914 and 918, respectively. The relationship between source/drain regions 934, active regions 914, 916, 918, gate structures 921-929, contacts 942, 944 and bit lines 952, 954 is similar to the relationship between source/drain regions 834, active regions 814, 816, 818, gate structures 821-829, contacts 842, 844 and metal lines 852, 854, and thus, for brevity, the relevant structural details are not repeated.

Fig. 9D is a block diagram of the integrated circuit 100I of fig. 9A and 9D. As shown in fig. 9D, blocks 921A, 922A, 923A, 924A, 925A, 926A, 927A, 928A, and 929A are shown, where each of the blocks 921A to 929A corresponds to a gate structure. For example, blocks 921A-929A may correspond to gate structures 921-929 of fig. 9A, respectively. As described above, each of blocks 921A to 929A may represent gate structures having different threshold voltages. For example, for the N7 technology node, there are three classes of threshold voltages, such as ultra-low threshold voltage (ULVT), low threshold voltage (LVT), and standard threshold voltage (SVT). In this regard, each of blocks 921A through 929A may contain three possibilities for threshold voltages. Thus, the combination of blocks 921A to 929A of integrated circuit 100I may contain 39 variants. On the other hand, with respect to the N5 technology node, there may be five classes of threshold voltages. Thus, the combination of blocks 921A to 929A of integrated circuit 100I may contain 59 variants.

10A, 10B, and 10C illustrate an integrated circuit 100J according to some embodiments of the invention, where FIG. 10A is a top view of the integrated circuit 100J and FIG. 10B is a cross-sectional view along line B-B of FIG. 10A. Fig. 10C shows an equivalent circuit of fig. 10A and 10B. Some elements of fig. 10A, 10B, and 10C are similar to those described in fig. 1A, 1B, and 1C, and thus, for the sake of brevity, relevant details are not repeated.

Integrated circuit 100J includes an active region 1014 and gate structures 1022, 1024, 1026 and 1028 disposed on active region 1014. The integrated circuit 100J also includes source/drain regions 1031, 1032, 1033, 1034, and 1035 disposed in the active region 114. Source/drain regions 1031 and 1032 are on opposite sides of the gate structure 1022, wherein the gate structure 1022 and the source/drain regions 1031 and 1032 form a transistor T111. Source/drain regions 1032 and 1033 are on opposite sides of gate structure 1024, where gate structure 1024 and source/drain regions 1032 and 1033 form transistor T112. The source/drain regions 1033 and 1034 are on opposite sides of the gate structure 1026, wherein the gate structure 1026 and the source/drain regions 1033 and 1034 form a transistor T113. Source/drain regions 1034 and 1035 are on opposite sides of gate structure 1028, where gate structure 1028 and source/drain regions 1034 and 1035 form transistor T114.

In some embodiments, the gate structures 1022 and 1028 have substantially the same gate length LG1, wherein the gate length LG1 is the critical dimension in the corresponding technology node. On the other hand, gate structures 1024 and 1026 have substantially the same gate length LG 2. The gate length LG2 is greater than the gate length LG 1. Accordingly, the transistors T111 and T114 may be referred to as short channel devices, and the transistors T112 and T113 may be referred to as long channel devices. In some embodiments, the gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 is n LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (e.g., n ═ 2, 3, 4 … …).

The integrated circuit 100J also includes contacts 1042 disposed on the source/drain regions 1031 and 1035, respectively, and metal lines 1052 above the contacts 1042 and electrically connecting the contacts 1042.

11A, 11B, and 11C illustrate an integrated circuit 100K according to some embodiments of the invention, where FIG. 11A is a top view of the integrated circuit 100K and FIG. 11B is a cross-sectional view along line B-B of FIG. 11A. Fig. 11C shows an equivalent circuit of the integrated circuit 100K shown in fig. 11A and 11B. Some elements of fig. 11A, 11B, and 11C are similar to those described in fig. 1A, 1B, and 1C, and thus, for the sake of brevity, relevant details are not repeated.

The integrated circuit 100K includes active regions 1114 and 1116 arranged along the Y-direction, gate structures 1122 and 1124 disposed on the active region 1114, and gate structures 1126 and 1128 disposed on the active region 1116. The integrated circuit 100J also includes source/drain regions 1131, 1132, 1133 disposed in the active region 1114, and source/drain regions 1134, 1135, and 1136 disposed in the active region 1116. The source/drain regions 1131 and 1132 are on opposite sides of the gate structure 1122, wherein the gate structure 1122 and the source/drain regions 1131 and 1132 form the transistor T121. Source/drain regions 1132 and 1133 are on opposite sides of the gate structure 1124, wherein the gate structure 1124 and the source/drain regions 1132 and 1133 form a transistor T122. Source/drain regions 1134 and 1135 are on opposite sides of the gate structure 1126, wherein the gate structure 1126 and the source/drain regions 1134 and 1135 form the transistor T123. Source/drain regions 1135 and 1136 are on opposite sides of the gate structure 1128, wherein the gate structure 1128 and the source/drain regions 1135 and 1136 form the transistor T124.

In some embodiments, the gate structures 1122 and 1128 have substantially the same gate length LG1, where the gate length LG1 is the critical dimension in the corresponding technology node. On the other hand, gate structures 1124 and 1126 have substantially the same gate length LG 2. The gate length LG2 is greater than the gate length LG 1. Accordingly, the transistors T121 and T124 may be referred to as short channel devices, and the transistors T122 and T123 may be referred to as long channel devices. In some embodiments, the gate length LG2 is n times the gate length LG1, where n is a positive integer. That is, LG2 is n LG1, where n is a positive integer. In some embodiments, n is a positive integer and is greater than 1 (e.g., n ═ 2, 3, 4 … …).

Integrated circuit 100J also includes contacts 1142 disposed on source/drain regions 1033 and 1034, respectively, and metal lines 1152 over contacts 1142 and electrically connecting contacts 1142.

Fig. 12A, 12B, and 12C illustrate an integrated circuit 100L according to some embodiments of the invention, where fig. 12A is a top view of the integrated circuit 100L and fig. 12B is a cross-sectional view along line B-B of fig. 12A. Fig. 12C shows an equivalent circuit of fig. 12A and 12B. Some elements of fig. 12A, 12B and 12C are similar to those described in fig. 1A, 1B and 1C, and therefore, for the sake of brevity, relevant details are not repeated.

The integrated circuit 100L includes semiconductor fins 1211, 1212, 1213, 1214, and 1215 arranged in the Y direction. In some embodiments, semiconductor fins 1211, 1212, and 1213 are longer than semiconductor fins 1214 and 1215 along the X-direction. Integrated circuit 100L also includes gate structures 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, and 1229, wherein gate structures 1220, 1221, 1222, 1223 intersect semiconductor fins 1211, 1212, and 1213, and gate structures 1224, 1225, 1226, 1227, 1228, and 1229 intersect semiconductor fins 1211, 1212, 1213, 1214, and 1215. In some embodiments, the gate structures 1220-1229 have substantially the same gate length LG1, where the gate length LG1 is the critical dimension in the corresponding technology node.

The integrated circuit 100L also includes source/drain regions 1231, 1232, and 1233. In some embodiments, the source/drain regions 1231 are disposed in the semiconductor fins 1211, 1212, and 1213 and adjacent to the gate structure 1220. Source/drain regions 1232 are disposed in semiconductor fins 1211, 1212, 1213, 1214, and 1215 and between gate structures 1223 and 1225. Source/drain regions 1233 are disposed in semiconductor fins 1211, 1212, and 1213 and adjacent to gate structure 1229.

In some embodiments, the gate structures 1220-1223 are electrically connected and may be collectively referred to as a gate 1242, wherein the gate 1242 and the source/drain regions 1231 and 1232 form the transistor T131. In some embodiments, gate structures 1220-1223 are electrically connected to the same voltage node on the other hand, gate structures 1224-1229 are electrically connected and may be collectively referred to as gates 1244, where gates 1244 and source/drain regions 1232 and 1233 form transistor T132. In some embodiments, gate structures 1224-1229 are electrically connected to the same voltage node from another perspective, gate 1242 of transistor T131 may be viewed as having several sections (e.g., gate structures 1220-1223) arranged along the X-direction, where each section has spacers 106 disposed on opposing sidewalls thereof. As mentioned above, each of the gate structures 1220 to 1223 has a gate length LG 1. Therefore, the effective gate length of the gate 1242 of the transistor T131 is 4 × LG 1. For example, if the gate length LG1 is about 5nm, the effective gate length of the gate 1242 is about 20 nm. On the other hand, each of the gate structures 1224 to 1229 has a gate length LG 1. Therefore, the effective gate length of the gate 1244 of the transistor T132 is 6 × LG 1. For example, if the gate length LG1 is about 5nm, the effective gate length of the gate 1244 is about 30 nm. Thus, in the embodiment of fig. 12A to 12C, the transistor T131 has three semiconductor fins 1211, 1212, 1213, and the gate 1242 of the transistor T131 has four portions (e.g., gate structures 1220 to 1223). On the other hand, the transistor T132 has five semiconductor fins 1211, 1212, 1213, 1214, and 1215, and the gate 1244 of the transistor T132 has six sections (e.g., gate structures 1224 to 1229).

Fig. 13 is a schematic diagram of an Electronic Design Automation (EDA) system 1300 according to some embodiments. According to one or more embodiments, the methods of generating a design layout (e.g., a layout of integrated circuits 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H) described herein may be implemented, for example, using EDA system 1300 according to some embodiments. In some embodiments, the EDA system 1300 is a general purpose computing device that includes a hardware processor 1302 and a non-volatile computer-readable storage medium 1304. The computer-readable storage medium 1304 is encoded with, i.e., stored on, a set of executable instructions 1306, a design layout 1307, a Design Rule Check (DRC) platform 1309, or any intermediate data for executing a set of instructions, among other uses. Each design layout 1307 includes a graphical representation, such as a GSII file, of an integrated chip (e.g., integrated circuits 100A-100H). Each DRC platform 1309 includes a series of design rules that are specific to the semiconductor process selected for manufacturing the design layout 1307. The execution of the instructions 1306, the design layout 1307, and the DRC platform 1309 by the hardware processor 1302 represents (at least in part) an EDA tool that implements some or all of the methods described herein, for example, in accordance with one or more (hereinafter, described processes and/or methods).

The processor 1302 is electrically connected to the computer-readable storage medium 1304 by a bus 1308. The processor 1302 is also electrically coupled to an input/output (I/O) interface 1310 via a bus 1308. The network interface 1312 is also electrically coupled to the processor 1302 via the bus 1308. The network interface 1312 interfaces with the network 1314 such that the processor 1302 and the computer-readable storage medium 1304 can be coupled to external elements via the network 1314. The processor 1302 is configured to execute instructions 1306 encoded in the computer-readable storage medium 1304 to make the EDA system 1300 available to perform layout design operations. In one or more embodiments, processor 1302 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, Application Specific Integrated Circuit (ASIC), and/or suitable processing unit.

In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). The computer-readable storage medium 1304 includes, for example, a semiconductor or solid state memory, magnetic tape, a removable disk, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1304 comprises a compact disk read only memory (CD-ROM), a read-write compact disk memory (CD-R/W), and/or a Digital Video Disk (DVD).

In one or more embodiments, the computer-readable storage medium 1304 stores instructions 1306, a design layout (e.g., a layout of the integrated circuits 100A-100H previously discussed), a DRC platform 1309 configured to make the EDA system 1300 (where such execution (at least in part) represents an EDA tool) available to perform some or all of the processes and/or methods.

The EDA system 1300 includes an I/O interface 1310. The I/O interface 1310 is electrically connected to external circuitry. In one or more embodiments, I/O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for communicating information and commands to processor 1302.

The EDA system 1300 also includes a network interface 1312 coupled to the processor 1302. The network interface 1312 allows the EDA system 1300 to communicate with a network 1314 connected to one or more other computer systems. The network interface 1312 may include a wireless network interface, such as bluetooth, WIFI, WIMAX, GPRS, or WCDMA, or a limited network interface, such as ETHERNET. In one or more embodiments, some or all of the processes and/or methods are performed in two or more EDA systems 1300.

The EDA system 1300 is configured to receive information through the I/O interface 1310. The information received via I/O interface 1310 includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters processed by processor 1302. Information is transferred to processor 1302 via bus 1308. The EDA system 1300 is configured to receive information related to a User Interface (UI)13113 through an I/O interface 1310. The information is stored in the computer-readable medium 1304 as the UI 1316.

In some embodiments, a layout comprising standard cells is obtained by using a layout such as that available from CADENCE DESIGN SYSTEMS, IncOr another suitable layout generation tool.

In some embodiments, these processes are implemented as program functions stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/built-in storage devices or memory units, for example, one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, a RAM, a memory card, and the like.

Also shown in FIG. 13 is a mask chamber 1330 that receives the verified layout generated from the EDA system 1300, for example, over the network 1314. The mask chamber 1330 has a mask fabrication tool 1332 (e.g., a mask writer) for fabricating one or more photomasks (e.g., for fabricating photomasks such as ICs 100A-100H) based on the verified layout generated from the EDA system 1300. An IC manufacturer ("Fab") 1320 may be connected to the mask chamber 1330 and the EDA system 1300 through, for example, a network 1314. The Fab 1320 includes an IC fabrication tool 1322 for fabricating IC chips (e.g., ICs 100A-100H) using photomasks fabricated by the mask chamber 1330. By way of example, and not limitation, IC fabrication tool 1322 may be a cluster tool for fabricating IC chips. The cluster tool may be a multi-chamber type complex apparatus that includes a polyhedral transfer chamber into which a wafer processing robot is inserted at the center thereof, a plurality of processing chambers (e.g., CVD chambers, PVD chambers, etching chambers, annealing chambers, etc.) positioned at each wall of the polyhedral transfer chamber; and a lock loading chamber installed at a different wall surface of the transfer chamber.

In some embodiments, two or more of the EDA system 1300, the mask chamber 1330, and the FAB 1320 are owned by a single company. For example, two or more of the EDA system 1300, the mask room 1330, and the FAB 1320 coexist in a common facility and use common resources. In some other embodiments, the EDA system 1300 is owned by a design room that is a different entity than the mask room 1330 and the FAB 1320. In such embodiments, each of the mask chamber 1330, the FAB 1320, and the design chamber owning the EDA system 1300 interact with and provide services to and/or receive services from one or more of the other entities.

The integrated circuit structure as discussed above is some examples for describing layout styles with long channel device layout patterns suitable for advanced technology nodes. The concepts described above may also be integrated into other semiconductor devices, such as gate all-ring (GAA) FETs and/or nanowire FETs, and may be implemented in multiple technology nodes, such as 10nm, 7nm, 5nm, 3nm technology nodes.

Based on the above discussion, it can be seen that the present invention provides advantages. It is to be understood, however, that other embodiments may provide additional advantages, and that not all advantages need be disclosed herein and that no particular advantage is required for all embodiments. One advantage is that the gate of a long channel transistor can be divided into several sections arranged on one or more active areas. Each of the sections may contain a gate length equal to the critical dimension of the corresponding technology node or may be a multiple of the critical dimension. On the other hand, each of the sections may contain a different threshold voltage. This allows for more flexible circuit layout design.

In some embodiments of the present invention, an Integrated Circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a longitudinal direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, wherein the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.

In some embodiments of the present invention, an IC structure includes a first transistor and a second transistor. The first transistor includes a first active region, a first gate, a plurality of gate spacers, a first source/drain region, and a second source/drain region. The first active region and the second active region are separated by an isolation structure and extend along a first direction. The first gate has a plurality of gate structures disposed on the first active region and the second active region, respectively, wherein, along the first direction, an effective gate length of the gate is n times a critical dimension of a technology node of the first transistor, and n is a positive integer and greater than 1. A gate spacer is disposed adjacent each of the gate structures of the first gate. The first source/drain region is in the first active region. The second source/drain region is in the second active region. The second transistor has a gate length substantially equal to a critical dimension of the technology node of the first transistor.

In some embodiments of the present invention, a first active region and a second active region are formed over a substrate and extend along a first direction, wherein the first active region and the second active region are separated by an isolation structure; forming a first gate structure over the first active region; forming a plurality of second gate structures over the second active region, wherein, along the first direction, a sum of gate lengths of the second gate structures is n times a gate length of the first gate structure, and n is a positive integer and greater than 1; forming a first source/drain region in the first active region; and forming a second source/drain region in the second active region, wherein a portion of the second active region between two adjacent second gate structures has a lower dopant concentration than the second source/drain region.

According to an embodiment of the present application, there is provided an Integrated Circuit (IC) structure, including: a first transistor comprising: a first active region; and a first gate disposed on the first active region, wherein the first gate has a first effective gate length along a first direction parallel to a longitudinal direction of the first active region; and a second transistor including: a second active region; and a second gate disposed on the second active region, and the second transistor includes a plurality of gate structures arranged in the first direction and separated from each other, wherein the second gate has a second effective gate length in the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1. In some embodiments, the gate structure of the second gate is electrically connected to the same voltage node. In some embodiments, each of the gate structures has a gate length substantially the same as the first effective gate length, and wherein the number of gate structures is n. In some embodiments, the second transistor further comprises a plurality of gate spacers adjacent opposing sidewalls of each of the gate structures of the second gate. In some embodiments, the second transistor further includes a plurality of source/drain regions in the second active region, the source/drain regions being adjacent to outermost two of the gate structures of the second gate, respectively, and a portion of the second active region located between the outermost two of the gate structures of the second gate has a lower dopant concentration than the source/drain regions. In some embodiments, the first set of gate structures of the second gate has a first gate length that is m times the first effective gate length, and the second set of gate structures has a second gate length that is o times the first effective gate length, where m and o are different positive integers. In some embodiments, wherein along the first direction, the first group of gate structures is not located between two adjacent ones of the second group of gate structures. In some embodiments, the first effective gate length is a minimum gate length in the IC structure. In some embodiments, the first active region includes one or more semiconductor fins. In some embodiments, the second active region includes one or more semiconductor fins.

According to another embodiment of the present application, there is provided an integrated circuit structure comprising: a first transistor comprising: a first active region and a second active region separated by an isolation structure, wherein the first active region and the second active region extend along a first direction; a gate having a plurality of gate structures disposed on the first active region and the second active region, respectively, wherein, along the first direction, an effective gate length of the gate is n times a critical dimension of a technology node of the first transistor, and n is a positive integer and greater than 1; a plurality of gate spacers adjacent to each of the gate structures of the gate; and a first source/drain region in the first active region; and a second source/drain region in the second active region; and a second transistor having a gate length substantially equal to a critical dimension of a technology node of the first transistor. In some embodiments, the gate structure of the first transistor has a gate length substantially the same as a critical dimension of the technology node of the first transistor. In some embodiments, at least two of the gate structures of the first transistor have different threshold voltages. In some embodiments, wherein the first set of gate structures has a first gate length that is m times a critical dimension of the technology node of the first transistor, the second set of gate structures has a second gate length that is o times the critical dimension of the technology node of the first transistor, wherein m and o are different positive integers. In some embodiments, the number of gate structures of the first set is different from the number of gate structures of the second set. In some embodiments, the integrated circuit structure further comprises: a first contact disposed on the first active region, wherein the first contact is at a first side of the first active region and the first source/drain region is at a second side of the first active region opposite the first side of the first active region; a second contact disposed on the second active region, wherein the second contact is at a first side of the second active region and the second source/drain region is at a second side of the second active region opposite the first side of the second active region; and a metal line electrically connecting the first contact and the second contact.

According to yet another embodiment of the present application, there is provided a method of forming an integrated circuit structure, comprising: forming a first active region and a second active region extending in a first direction over a substrate, wherein the first active region and the second active region are separated by an isolation structure; forming a first gate structure over the first active region; forming a plurality of second gate structures over the second active region, wherein, along the first direction, a sum of gate lengths of the second gate structures is n times a gate length of the first gate structure, and n is a positive integer and greater than 1; forming a first source/drain region in the first active region; and forming a second source/drain region in the second active region, wherein a portion of the second active region between two adjacent second gate structures has a lower dopant concentration than the second source/drain region. In some embodiments, wherein forming the second gate structures is performed such that each of the gate lengths of the second gate structures is substantially the same as the gate length of the first gate structures. In some embodiments, wherein forming the second gate structures is performed such that the gate lengths of the first set of second gate structures are each m times the gate length of the first gate structure and the gate lengths of the second set of second gate structures are each o times the gate length of the first gate structure. In some embodiments, the method of forming an integrated circuit structure further comprises forming gate spacers on opposing sidewalls of the second gate structure.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

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