阅读说明：本技术 集成电路及其形成方法 (Integrated circuit and forming method thereof ) 是由 吴国晖 卢麒友 陈庭榆 田丽钧 于 2021-02-07 设计创作，主要内容包括：公开了一种集成电路及其形成方法。该集成电路包括第一对电源轨、导电线组和第一组有源区,导电线组与第一对电源轨平行地被布置在第一层中。该集成电路还包括第一栅极,第一栅极在第二方向上被布置在第一对电源轨之间且穿过布局视图中的第一组有源区,其中,第一栅极被配置为由属于第一类型的第一晶体管和属于第二类型的第二晶体管共用；以及第二栅极和第三栅极,其中,第二栅极被配置为第三晶体管的控制端子,并且第三栅极被配置为第四晶体管的控制端子,第四晶体管的控制端子耦合至第三晶体管的控制端子。(An integrated circuit and a method of forming the same are disclosed. The integrated circuit includes a first pair of power rails, a set of conductive lines arranged in a first layer parallel to the first pair of power rails, and a first set of active regions. The integrated circuit further includes a first gate disposed between the first pair of power rails in the second direction and passing through the first set of active regions in the layout view, wherein the first gate is configured to be shared by a first transistor belonging to the first type and a second transistor belonging to the second type; and a second gate and a third gate, wherein the second gate is configured as a control terminal of the third transistor and the third gate is configured as a control terminal of the fourth transistor, the control terminal of the fourth transistor being coupled to the control terminal of the third transistor.)

1. An integrated circuit, comprising:

a first pair of power rails extending in a first direction in a first layer and separated from each other in a second direction different from the first direction;

a set of conductive lines arranged in the first layer in parallel with the first pair of power rails, wherein the set of conductive lines is arranged in three metal tracks between the first pair of power rails;

a first set of active regions extending in the first direction and separated from each other in the second direction;

a first gate arranged in a second layer different from the first layer along the second direction and crossing the first group of active regions in a layout view, wherein the first gate is configured to be shared by a first transistor of a first type and a second transistor of a second type; and

a second gate and a third gate extending in the second direction and parallel to the first gate and arranged in the second layer, wherein the second gate is configured to be a control terminal of a third transistor and the third gate is configured to be a control terminal of a fourth transistor coupled to the control terminal of the third transistor, the control terminal of the fourth transistor.

2. The integrated circuit of claim 1, wherein the second gate and the third gate are two portions of a continuous gate structure;

wherein the integrated circuit further comprises:

a Shallow Trench Isolation (STI) region extending in the first direction and disposed between the first set of active regions; and

a set of gate vias coupled between the first gate, the gate structure, and the set of conductive lines, wherein the set of gate vias overlaps the shallow trench isolation region.

3. The integrated circuit of claim 1, further comprising:

shallow trench isolation regions extending in the first direction and arranged between the first set of active regions; and

a set of gate vias coupled between the first gate, the second gate, the third gate, and the set of conductive lines, wherein the set of gate vias overlaps the shallow trench isolation region.

4. The integrated circuit of claim 1, further comprising:

a second power rail disposed in the first layer between the first pair of power rails; and

a second set of active regions extending in the first direction and arranged between the second power rail and one of the first pair of power rails;

wherein the second gate and the third gate are two parts of a continuous gate structure and cross over the second set of active regions in the layout view, an

The gate structure and the first gate are separated from each other in the second direction;

wherein the second power rail overlaps the first gate and the gate structure.

5. The integrated circuit of claim 4, further comprising:

a shallow trench isolation region extending in the first direction and arranged between the first set of active regions and the second set of active regions; and

a set of gate vias coupled between the first gate, the gate structure, and the set of conductive lines, wherein the set of gate vias overlaps the shallow trench isolation region;

wherein the first gate further spans the second set of active regions and the shallow trench isolation regions, and the gate structure further spans the first set of active regions and the shallow trench isolation regions.

6. The integrated circuit of claim 1, further comprising:

a second power rail disposed in the first layer between the first pair of power rails;

wherein the second gate and the third gate are located at opposite sides of the second power rail.

7. The integrated circuit of claim 1, further comprising:

a set of gate vias coupled between the first, second, and third gates and the set of conductive lines, wherein the set of gate vias overlaps at least one active region of the first set of active regions.

8. The integrated circuit of claim 1, wherein the first pair of power rails, the set of conductive lines, and the first set of active regions are included in a first cell;

wherein the integrated circuit further comprises a second cell comprising:

a second set of active regions parallel to the first set of active regions;

a second pair of power rails disposed adjacent to one of the first pair of power rails and separated from each other in the second direction; and

a further set of conductive lines arranged in three tracks between the second pair of power rails;

wherein the second pair of power rails spans the first gate, the second gate, the third gate, or a combination thereof in the layout view.

9. An integrated circuit, comprising:

first to fourth transistors each including a gate, wherein the gates of the first to fourth transistors extend in a first direction and are separated from each other in a second direction different from the first direction;

a plurality of power rails extending in the second direction and separated from each other in the first direction;

a first set of conductive lines extending in the second direction, wherein the first set of conductive lines are arranged between the plurality of power rails and are separated from each other in the first direction;

a shallow trench isolation region extending in the second direction and disposed between the plurality of power rails; and

a plurality of gate vias disposed on the gates of the first through fourth transistors, wherein at least two of the plurality of gate vias overlap the shallow trench isolation region.

10. A method of forming an integrated circuit, comprising:

forming a plurality of active regions extending in a first direction;

forming a plurality of gates extending in a second direction different from the first direction;

forming a second set of gate vias over the plurality of gates, wherein the second set of gate vias overlaps the plurality of active regions;

forming a first set of power rails overlapping the plurality of gates, the first set of power rails extending in the first direction and separated from each other in the second direction; and

forming a first set of conductive lines in three tracks disposed between the first pair of power rails.

Technical Field

Embodiments of the invention relate to integrated circuits and methods of forming the same.

Background

Integrated circuits are widely used for a variety of purposes, requiring faster processing speeds and lower power consumption within a defined area. Thus, optimized metal routing for integrated circuit layout design is achieved through a variety of methods.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided an integrated circuit including: a first pair of power rails extending in a first direction in a first layer and separated from each other in a second direction different from the first direction; a set of conductive lines arranged in the first layer in parallel with the first pair of power rails, wherein the set of conductive lines is arranged in three metal tracks between the first pair of power rails; a first group of active regions extending in a first direction and separated from each other in a second direction; a first gate arranged in a second layer different from the first layer along the second direction and crossing the first group of active regions in the layout view, wherein the first gate is configured to be shared by a first transistor of the first type and a second transistor of the second type; and a second gate and a third gate extending in a second direction and parallel to the first gate and arranged in a second layer, wherein the second gate is configured to be a control terminal of a third transistor, and the third gate is configured to be a control terminal of a fourth transistor coupled to the control terminal of the third transistor, the control terminal of the fourth transistor.

According to another aspect of an embodiment of the present invention, there is provided an integrated circuit including: first to fourth transistors each including a gate, wherein the gates of the first to fourth transistors extend in a first direction and are separated from each other in a second direction different from the first direction; a plurality of power rails extending in a second direction and separated from each other in a first direction; a first set of conductive lines extending in a second direction, wherein the first set of conductive lines are arranged between the plurality of power rails and are separated from each other in the first direction; a shallow trench isolation region extending in a second direction and arranged between the plurality of power rails; and a plurality of gate vias arranged on gates of the first to fourth transistors, wherein at least two of the plurality of gate vias overlap the shallow trench isolation region.

According to yet another aspect of embodiments of the present invention, there is provided a method of forming an integrated circuit, including: forming a plurality of active regions extending in a first direction; forming a plurality of gates extending in a second direction different from the first direction; forming a first gate through hole group on the plurality of gates, wherein the first gate through hole group overlaps the plurality of active regions; forming a first set of power rails overlapping the plurality of gates, the first set of power rails extending in a first direction and separated from each other in a second direction; and forming a first set of conductive lines in the three tracks disposed between the first pair of power rails.

Drawings

The embodiments of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is an equivalent circuit of a portion of an integrated circuit according to various embodiments.

Fig. 2A is a layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments. Fig. 2B-2C are cross-sectional views of an integrated circuit corresponding to a portion of fig. 2A, in accordance with various embodiments.

Fig. 3 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 4 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 5 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 6 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 7 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 8 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 9 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 10A is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments. Fig. 10B is a cross-sectional view of an integrated circuit corresponding to a portion of fig. 10A, in accordance with various embodiments.

Fig. 11A is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments. Fig. 11B is a cross-sectional view of an integrated circuit corresponding to a portion of fig. 10A, in accordance with various embodiments.

Fig. 12 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 13 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 14 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 15 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 16 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 17 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 18 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 19 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 20 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 21 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

Fig. 22 is another layout diagram of a plan view of a portion of an integrated circuit corresponding to a portion of fig. 1, in accordance with various embodiments.

FIG. 23 is a flow diagram of a method of generating a layout design for use in fabricating an integrated circuit, according to some embodiments of the present disclosure.

Fig. 24 is a flow chart of a method for fabricating an integrated circuit according to some embodiments of the present disclosure.

Fig. 25 is a block diagram of a system for designing a layout design of an integrated circuit, according to some embodiments of the present disclosure.

Fig. 26 is a block diagram of an integrated circuit manufacturing system and integrated circuit manufacturing flow associated therewith, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification have their ordinary meanings in the art and in the specific text used for each term. The examples used in this description, including examples of any terms discussed herein, are illustrative only and in no way limit the scope and meaning of the disclosure or of any exemplary terms. Also, the present disclosure is not limited to the various embodiments presented in this specification.

Furthermore, for ease of description, spatially relative terms, such as "below," "lower," "below," "above," "upper," and the like, are used herein to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein interpreted accordingly. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, "about," "approximately," or "substantially" shall generally mean any approximation of a given value or range that varies depending on the respective field to which it pertains, and whose scope is to be accorded the broadest interpretation as understood by those skilled in the art to encompass all such modifications and similar structures. In some embodiments, the given value or range should generally be within 20%, preferably within 10%, more preferably within 5%. Numerical values set forth herein are approximate, meaning that the terms "about," "approximately" or "substantially" can be inferred, or mean other approximations, if not expressly stated.

Reference is now made to fig. 1. FIG. 1 is an equivalent circuit of a portion of an integrated circuit according to some embodiments. For illustrative purposes, the integrated circuit 100 includes transistors M1-M4. The gate of transistor M1 is coupled to the gate of transistor M3. The gate of transistor M2 is coupled to the gate of transistor M4. The drain/source of transistor M1 is coupled to the drain/source of transistor M4. The source/drain of the transistor M1 is coupled to the drain/source of the transistor M2, and the source/drain of the transistor M3 is coupled to the source/drain of the transistor M4. The source/drain of transistor M2 is coupled to the drain/source of transistor M3. In some embodiments, integrated circuit 100 is a transmission gate circuit. The above implementation of integrated circuit 100 is for illustration purposes. Various implementations of the integrated circuit 100 are within the intended scope of the present disclosure. For example, in some embodiments, integrated circuit 100 is a logic gate circuit that includes an and, or, nand, multiplexer, flip-flop, latch, Buffer (BUFF), inverter, or is of any other type of logic circuit.

In some embodiments, transistors M1-M2 are Field Effect Transistors (FETs) of a first conductivity type (e.g., P-type), and transistors M3-M4 are Field Effect Transistors (FETs) of a second conductivity type (e.g., N-type) different from the first conductivity type. The above implementation of integrated circuit 100 is for illustration purposes. Various implementations of the integrated circuit 100 are within the intended scope of the present disclosure. For example, transistors M1-M2 are of the second conductivity type, and transistors M3-M4 are of the first conductivity type.

Reference is now made to fig. 2A. Fig. 2A is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. For illustration, the integrated circuit 100 includes the active region 110, the conductive pattern (i.e., the defined metal species, MD)201, 209, the gate 301, 306, the conductive line (i.e., the metal-0, M0)401, 403a-403b, 404a-404b, 405a-405b, the conductive portion (i.e., the metal-1, M1)501, the conductive track (i.e., the metal-2, M2)601, 602, and the vias VD1-VD8, VG1-VG6, VM1-VM4, and VN1-VN 4. In some embodiments, the active regions 110-120 are disposed in a first layer. The conductive patterns 201 and 205 and the gates 301 and 304 are disposed over the active region 110. The conductive patterns 203, 206, 207, and 208, and the gates 302, 303, 305, and 306 are disposed over the active region 120. Conductive lines 401-402, 403a-403b, 404a-404b, 405a-405b are disposed in the second layer and over the conductive pattern 201-209 and the gate 301-306. The conductive portions 501 and 504 are disposed in the third layer and over the second layer. The conductive portions 601 and 602 are disposed in the fourth layer and above the third layer.

Referring to fig. 1 and 2A, active region 110 is configured to form transistors M1-M2, and active region 120 is configured to form transistors M3-M4. The conductive pattern 202 corresponds to the drain/source of the transistor M1. The conductive pattern 203 corresponds to the source/drain of the transistors M1, M3, and M4 and the drain/source of the transistor M2. The conductive pattern 204 corresponds to the source/drain of the transistor M2. The conductive pattern 207 corresponds to the drain/source of the transistor M3. The conductive pattern 208 corresponds to the drain/source of the transistor M4. In some embodiments, the conductive patterns 201, 205, 206, and 209 are referred to as metal wiring structures of the integrated circuit 100. The gate 302 corresponds to the gates of transistors M1 and M3. The gate 303 corresponds to the gates of the transistors M2 and M4. Alternatively, it is stated that transistors M1 and M3 share gate 302 and transistors M2 and M4 share gate 303. Gates 301, 304, 305, and 306 are referred to as dummy gates, where in some embodiments the "dummy" gates are referred to as not being electrically connected as Metal Oxide Semiconductor (MOS) devices while not functioning in the circuit. In some various embodiments, gates 301, 304, 305, and 306 are included in transistors, while operating as switches to input supply voltages to integrated circuit 100.

As shown in fig. 2A, the active regions 110 and 120 extend in the x-direction and are separated from each other in the y-direction, which is different from the x-direction, for illustration. In some embodiments, the active regions 110 and 120 are disposed on a substrate (not shown). The substrate comprises a material including, for example, silicon, and/or doped with phosphorus, arsenic, germanium, gallium, indium arsenide, or combinations thereof. In various embodiments, active region 110 is doped with a p-type dopant, such as boron, indium, aluminum, gallium, or combinations thereof, and active region 120 is doped with an n-type dopant, such as phosphorus, arsenic, or combinations thereof.

The conductive patterns 201 and 209 extend in the y-direction and are separated from each other in the x-direction. For illustration, in the y direction, the conductive patterns 201 and 206 are separated from each other, the conductive patterns 202 and 207 are separated from each other, the conductive patterns 204 and 208 are separated from each other, and the conductive patterns 205 and 209 are separated from each other.

The gates 301-306 extend in the y-direction and are separated from each other in the x-direction. For illustration purposes, in the y-direction, gates 301 and 305 are separated from each other, and gates 304 and 306 are separated from each other. The gates 302-303 are arranged on opposite sides of the conductive pattern 203. In some embodiments, the gates 301-306 are made of polysilicon, and thus, in some embodiments, the gates 301-306 are also referred to as polysilicon portions. In some other embodiments, the gates 301-306 are fabricated from other materials, and thus, the above materials for the gates 301-306 are for illustration purposes only.

Conductive lines 401, 403a-403b, 404a-404b, 405a-405b extend in the x-direction and are separated from each other in the y-direction. For illustration, in the layout view, the conductive line 401 overlaps the active region 110, the conductive pattern 201-. Conductive lines 403a-403b, 404a-404b, 405a-405b are disposed between conductive lines 401-402. The conductive line 403a passes through the conductive pattern 201-202 and the gate 301. The conductive line 403b passes through the conductive pattern 204 and 205 and the gate 304. Conductive line 404a passes through gate 302 and conductive line 404b passes through gate 303. The conductive line 405a passes through the conductive pattern 206-207 and the gate 305. The conductive line 405b passes through the conductive pattern 208 and 209 and the gate 306. Alternatively, it is stated that the conductive lines 403a-403b, 404a-404b, 405a-405b are arranged in three tracks between the conductive lines 401-402.

In some embodiments, by providing a space between conductive lines 403a and 403b, a space between conductive lines 404a and 404b, or a space between conductive lines 405a and 405b by performing a shear layer (not shown) for a space of smaller width, the width of the space of smaller width is smaller than the width of the space provided without the additional shear layer. Alternatively, it is stated that in various embodiments, the conductive lines 403a and 403b, the conductive lines 404a and 404b, or the conductive lines 405a and 405b are formed without using a pattern mask.

For illustration, the conductive portions 501 and 504 extend in the y-direction and are separated from each other in the x-direction. The conductive portion 501 overlaps the conductive patterns 201 and 206 and passes through the conductive lines 403a, 404a, and 405 a. The conductive portion 502 overlaps the conductive patterns 202 and 207 and passes through the conductive lines 403a, 404a, and 405 a. The conductive portion 503 overlaps the conductive patterns 204 and 208 and passes through the conductive lines 403b, 404b, and 405 b. The conductive portion 504 overlaps the conductive patterns 205 and 209 and passes through the conductive lines 403b, 404b, and 405 b.

Conductive tracks 601 and 602 extend in the x-direction and are separated from each other in the x-direction. As shown in fig. 2A, conductive track 601 passes through conductive portions 502 and 503, and conductive track 602 passes through conductive portion 501 and 504. In some embodiments, conductive track 602 overlaps conductive lines 404a-404 b.

As shown in fig. 2A, vias VD1 and VD4 couple conductive patterns 201 and 205 to conductive line 401. In some embodiments, conductive lines 401 output a supply voltage VDD to conductive patterns 201 and 205. Vias VD5 and VD8 couple conductive patterns 206 and 209 to conductive line 402. In some embodiments, conductive line 402 receives a supply voltage VSS, wherein in some embodiments, for conductive patterns 206 and 209, supply voltage VSS is less than supply voltage VDD.

Also, the structure shown with respect to fig. 2A is configured to be included in the first unit. In some embodiments, the conductive lines 401 and 402 in fig. 2A are shared by two adjacent cells of the integrated circuit 100, such as the first cell and the second cell, to output and/or receive the power supply voltage, wherein the conductive lines 401 and 402 are referred to as, for example, the power supply access structure. Details of the power entry structure are discussed in the following figures.

With continued reference to fig. 2A, via VD2 couples conductive pattern 202 to conductive line 403a, and via VM2 couples conductive line 403a to conductive portion 502. Vias VN2 couple conductive portions 502 to conductive tracks 601. Vias VN3 couple conductive tracks 601 to conductive portions 503. Via VM3 couples conductive portion 503 to conductive line 405 b. Via VD7 couples conductive line 405b to conductive pattern 208. Thus, through the above discussion, the conductive pattern 202 referred to as the drain/source of transistor M1 is coupled to the conductive pattern 208 referred to as the drain/source of transistor M4.

Likewise, via VD3 couples conductive pattern 204 to conductive line 403b, and via VM4 couples conductive line 403b to conductive portion 504. The vias VN4 couple the conductive portions 504 to the conductive tracks 602. Vias VN1 couple conductive tracks 602 to conductive portions 501. Via VM1 couples conductive portion 501 to conductive line 405 a. Via VD6 couples conductive line 405a to conductive pattern 207. Thus, through the above discussion, the conductive pattern 204 referred to as the source/drain of transistor M2 is coupled to the conductive pattern 207 referred to as the drain/source of transistor M3.

To illustrate, vias VG1 and VG4 couple gates 301 and 304 to conductive line 401, and vias VG5 and VG6 couple gates 305 and 306 to conductive line 402. Via VG2 couples gate 302 to conductive line 404a, and via VG3 couples gate 303 to conductive line 404 b. In some embodiments, the conductive lines 404a-404b are also coupled to signals for operating the transistors M1-M4 through the gates 302-303.

As shown in fig. 2A, the integrated circuit 100 further includes a Shallow Trench Isolation (STI) region 710 between the active regions 110 and 120. For illustration purposes, the shallow trench isolation regions extend in the x-direction. With such embodiments, vias VG2-VG3 are arranged to overlap shallow trench isolation region 710 in the layout view.

In some approaches, at least four tracks of conductive lines corresponding to conductive lines 403a-403b, 404a-404b, and 405a-405b are implemented for metal routing of integrated circuit 100 between power rails (i.e., conductive lines 401-402). In contrast to some approaches, with the configuration of FIG. 2A, three tracks of conductive lines in the layout view, e.g., conductive lines 403a-403b, 404a-404b, and 405a-405b, are sufficient to implement integrated circuit 100.

Reference is now made to fig. 2B. Fig. 2B is a cross-sectional view of the integrated circuit 100 along line AA' corresponding to a portion of fig. 2A, in accordance with various embodiments. As shown in fig. 2B, conductive lines 404a-404B are disposed in layers above the gates 302-303 and are coupled to the gates 302-303 through vias VG2-VG 3. Conductive portions 501-504 are disposed in a layer above conductive lines 404a-404 b. Conductive tracks 602 are disposed over conductive portions 501-504 and are coupled to conductive portions 501 and 504 by vias VN1 and VN 4.

Reference is now made to fig. 2C. Fig. 2C is a cross-sectional view of integrated circuit 100 corresponding to a portion of fig. 2A along line BB' according to various embodiments. As shown in fig. 2C, shallow trench isolation regions 710 are inserted between the active regions 110 and 120. The conductive patterns 202 and 207 overlap the active regions 110 and 120, respectively. Conductive lines 401, 402, 403a, 404a and 405a are arranged in layers above the conductive patterns 202 and 207, the active regions 110, 120 and the shallow trench isolation regions 710. Conductive lines 403a and 405a are coupled to conductive patterns 202 and 207 through vias VD2 and VD6, respectively. Conductive portion 502 is disposed in a layer above conductive lines 401-402, 403a, 404a, and 405a, and is coupled to conductive line 403a through via VM 2. Conductive tracks 601-602 are disposed over the conductive portion 502 and are coupled to the conductive portion 502 by vias VN 2.

The configuration of fig. 2A-2C is for illustration purposes. The various embodiments of fig. 2A-2C are within the intended scope of the present disclosure. For example, in some embodiments, the integrated circuit 100 includes a plurality of transistors to implement the transistors M1, M2, M3, or M4, and also includes corresponding structures. In various embodiments, vias VG1 and VG4 are arranged to overlap active region 110, and vias VG5 and VG6 are arranged to overlap active region 120.

Reference is now made to fig. 3. Fig. 3 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiment of fig. 2A, like elements in fig. 3 are assigned the same reference numerals for ease of understanding. For the sake of brevity, specific operation of like elements discussed in detail in the above paragraphs is omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 3.

In contrast to the embodiment in fig. 2A, the integrated circuit 100 in fig. 3 further comprises a second unit having a corresponding structure, instead of coupling the conductive pattern 202 to the conductive pattern 208 via the conductive track 601 and the conductive pattern 204 to the conductive pattern 207 via the conductive track 602, the corresponding structure being referred to as a metal wiring between the conductive patterns 202, 204, 207 and 208. In some embodiments, the first cell and the second cell are referred to as a first region and a second region. Specifically, the integrated circuit 100 further includes the active region 130-. In some embodiments, active regions 130 and 140 are configured with respect to active regions 120 and 110, respectively. The conductive pattern 210 is disposed 214 with respect to, for example, the conductive pattern 206, and the conductive pattern 215 is disposed 219 with respect to, for example, the conductive pattern 201. Gate 307- "310" is configured with respect to, for example, gate 305, and gate 311- "314" is configured with respect to, for example, gate 301. Conductive line 406 is configured with respect to, for example, conductive line 402, and conductive lines 407- & 409 are configured with respect to, for example, conductive lines 403a-403b, 404a-404b, and/or 405a-405 b. Regarding the through hole VD1, for example, through holes VD9-VD18 are provided. Regarding the through hole VD1, for example, through holes VD7-VD14 are provided. Regarding, for example, the via VM1, the vias VM5-VM8 are configured.

For illustration purposes, the active regions 130-140 extend in the x-direction and are separated from each other in the y-direction. In some embodiments, active region 130 is doped with n-type dopants and active region 140 is doped with p-type dopants.

The conductive patterns 210 and 219 extend in the y direction and are separated from each other in both the x direction and the y direction. The conductive pattern 210 and 214 passes through the active region 130, and the conductive pattern 215 and 219 passes through the active region 140. In some embodiments, as shown in fig. 3, the conductive patterns 210 and 219 are respectively aligned with the conductive patterns 201 and 209.

The gates 307-314 extend in the y-direction and are separated from each other in both the x-direction and the y-direction. Gate 307-310 passes through active region 130 and gate 311-314 passes through active region 140. In some embodiments, as shown in FIG. 3, the gates 307-314 are respectively aligned with the gates 310-306.

Conductive lines 406-409 extend in the x-direction and are separated from each other in the y-direction. To illustrate, conductive lines 407 and 409 are disposed between conductive lines 401 and 406. The conductive line 407 passes through the conductive pattern 210 and 214 and the gate 307 and 310. Conductive line 408 overlaps gate 307-314. The conductive line 409 passes through the conductive pattern 215-. Alternatively, it is stated that conductive lines 407 and 409 are arranged in three tracks between conductive lines 401 and 406.

Also, the conductive portions 501 and 504 extend from the first cell to the second cell in the y-direction, as compared to the configuration in fig. 2A. Specifically, the conductive portion 501 and 504 further pass through the active region 130 and 140 and the conductive lines 401 and 407 and 409. For illustration, the conductive portion 501 also overlaps with the conductive patterns 210 and 215, the conductive portion 502 also overlaps with the conductive patterns 211 and 216, the conductive portion 503 also overlaps with the conductive patterns 213 and 218, and the conductive portion 504 also overlaps with the conductive patterns 214 and 219.

Vias VD9-VD13 couple conductive pattern 210-214 to conductive line 406. In some embodiments, the conductive line 406 receives the power supply voltage VSS for the conductive patterns 210-214. Vias VD14-VD18 couple conductive patterns 215-219 to conductive line 401. In some embodiments, the conductive line 401 outputs the power supply voltage VDD to the conductive patterns 215-219.

In some embodiments, vias VD7-VD10 couple gates 307-310 to conductive line 406. Vias VD11-VD14 couple gates 311-314 to conductive line 401.

The integrated circuit 100 further includes shallow trench isolation regions 720-730. In some embodiments, the shallow trench isolation regions 720-730 are configured with respect to, for example, the shallow trench isolation regions 710. Shallow trench isolation region 720 is disposed between active regions 130 and 140, and shallow trench isolation region 730 is disposed between active regions 110 and 140. With such embodiments, vias VG11-VG14 are arranged to overlap shallow trench isolation region 730 in the layout view.

Conductive portions 502 and 503 are also coupled to conductive line 407 by vias VM6 and VM7, respectively, for illustration purposes. In such embodiments, conductive pattern 202 is coupled to conductive line 408 by via VD2, conductive line 403a, via VM2, conductive portion 502, via VM6, conductive line 407, via VM7, conductive portion 503, via VM3, conductive line 405b, and via VD 7.

Likewise, conductive portions 501 and 504 are also coupled to conductive line 409 by vias VM5 and VM8, respectively. In such embodiments, conductive pattern 204 is coupled to conductive line 407 by via VD3, conductive line 403b, via VM4, conductive portion 504, via VM9, conductive line 409, via VM5, conductive portion 501, via VM1, conductive line 405a, and via VD 6.

In contrast to the configuration in fig. 2A, the embodiment of fig. 3 also preserves the routing resources of the metal layer in the third layer by not implementing conductive tracks 601-.

The configuration of fig. 3 is for illustration purposes. Various embodiments of fig. 3 are within the intended scope of the present disclosure. For example, in some embodiments, conductive line 408 is not included.

Reference is now made to fig. 4. Fig. 4 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-3, similar elements in fig. 4 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operation of like elements discussed in detail in the preceding paragraphs is omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 4.

In contrast to the embodiment in fig. 3, the integrated circuit 100 further comprises the conductive pattern 220 and the vias VD19, VG15, VM9-VM11, instead of coupling the conductive pattern 202 to the conductive pattern 208 through the conductive portion 502 and having corresponding structures, for example, comprising the conductive patterns 202 and 216, the conductive line 404a and the vias VD2, VD15, VG2, VM2, VM5-VM 8. In some embodiments, the conductive patterns 202 and 216 in fig. 3 are referred to as two portions of the conductive pattern 220. For example, the through hole VD19 is disposed in the through hole VD2 of fig. 3. For example, via VG15 is disposed with respect to via VG2 of fig. 3. Regarding, for example, the through holes VM5, VM7-VM8 of fig. 3, the through holes VM9-VM11 are configured.

Further, in contrast to the embodiment in fig. 3, the conductive line 403a extends in the layout view and also passes through the gate 302.

For illustration, the conductive pattern 220 extends in the y-direction and passes through the active regions 110 and 140 and the conductive line 401 in a layout view.

A via VG15 couples gate 302 to conductive line 403 a. In some embodiments, vias VG15 are arranged to overlap active region 110.

As shown in fig. 3, via VD19 couples conductive pattern 220 to conductive line 409. Via VM10 couples conductive line 409 to conductive portion 503. Thus, conductive pattern 220 is coupled to conductive pattern 208 by via VD19, conductive line 409, via VM10, conductive portion 503, via VM3, conductive line 405b, and via VD 7.

Vias VM9 and VM11 couple conductive line 408 to conductive portions 501 and 504, respectively. Thus, conductive pattern 204 is coupled to conductive line 207 by via VD3, conductive line 403b, via VM4, conductive portion 504, via VM11, conductive line 408, via VM9, conductive portion 501, via VM1, conductive line 405a, and via VD 6.

In contrast to the configuration in fig. 3, the embodiment of fig. 4 also preserves the routing resources of the metal layer in the second layer by not implementing the conductive portion 502.

The configuration of fig. 4 is for illustration purposes. Various embodiments of fig. 4 are within the intended scope of the present disclosure. For example, in some embodiments, conductive line 404a in FIG. 3 is included.

Reference is now made to fig. 5. Fig. 5 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-4, similar elements in fig. 5 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operation of like elements discussed in detail in the above paragraphs is omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 5.

Compared with the embodiment in FIG. 3, the integrated circuit 100 further includes the conductive pattern 221-. In some embodiments, the conductive patterns 221 and 216 in fig. 3 are referred to as two portions of the conductive pattern 221. As for the conductive pattern 203 in fig. 3, for example, the conductive pattern 222 is arranged. Gates 315 and 316 are configured with respect to, for example, gates 302 and 303 of fig. 3, respectively. Gates 304 and 314 in fig. 3 are referred to as two portions of gate 317. With respect to, for example, conductive lines 408 of FIG. 3, conductive lines 408a-408b are configured. With respect to, for example, conductive lines 403a-403b, conductive line 410 is configured. With respect to, for example, conductive lines 405a-405b, conductive line 411 is configured. Regarding the through hole VD2, for example, through holes VD20-VD25 are provided. Vias VG16-VG17 are configured with respect to, for example, vias VG2-VG3, respectively. With respect to, for example, the through holes VM6-VM7 of fig. 3, the through holes VM12-VM13 are configured.

In some embodiments, the conductive pattern 221 corresponds to a drain/source of the transistor M3. The conductive pattern 222 corresponds to the drain/source of the transistor 2 and the source/drain of the transistors M1, M3-M4. The conductive pattern 213 corresponds to the drain/source of the transistor M4. The conductive pattern 223 corresponds to the drain/source of the transistor M1. The conductive pattern 204 corresponds to the source/drain of the transistor M2. The gate 315 corresponds to the gates of transistors M1 and M3, and the gate 316 corresponds to the gates of transistors M2 and M4. In some embodiments, the portion of gates 315 and 316 above active regions 120 and 140 are configured as dummy gates.

For illustration, the conductive patterns 221-224 extend in the y direction and are separated from each other in both the x direction and the y direction. The conductive pattern 221 passes through the active region 130-140. The conductive pattern 222 passes through the active regions 110 and 130 and 140. The conductive pattern 223 passes through the active region 110-120.

Gates 315-317 extend in the y-direction and are separated from each other in the x-direction. For illustration purposes, the gate 315 and 316 pass through the active region 110 and 140. Gate 317 passes through active regions 110 and 140.

The conductive line 407 is shortened, and the conductive line 407 passes through the conductive patterns 210, 221 and the gate 307. The conductive lines 408a-408b, 410-. The conductive lines 408a-408b are separated from each other in the x-direction and pass through the gates 315-316, respectively. In addition, in the layout view, the conductive line 401 passes through the gate 315-.

Vias VG16-VG17 couple gates 315-316 to conductive lines 408a-408b, respectively. In some embodiments, vias VG16-VG17 are arranged to overlap shallow trench isolation region 720.

To illustrate, the conductive patterns 208, 223, and 224 are coupled to the conductive line 411 by vias VD7, VD6, and VD25, respectively. The via VM3 couples the conductive line 411 to the conductive portion 503. The via VM3 couples the conductive portion 503 to the via VD23 and further to the conductive pattern 213. Thus, the conductive pattern 223 is coupled to the conductive pattern 213.

Likewise, via VD3 couples conductive pattern 204 to conductive line 410. The via VM2 couples the conductive line 410 to the conductive portion 502. The vias VM12 couple the conductive portions 502 to the conductive lines 407. Via VD20 couples conductive line 407 to conductive pattern 221. Thus, the conductive pattern 204 is coupled to the conductive pattern 221.

Compared to the configuration in fig. 3, the embodiment of fig. 5 also preserves the wiring resources of the metal layer in the second layer by not implementing the conductive portions 501 and 504.

The configuration of fig. 5 is for illustration purposes. Various embodiments of fig. 5 are within the intended scope of the present disclosure. For example, in some embodiments, another conductive line 404 is disposed between via VD23 and VM 13.

Reference is now made to fig. 6. Fig. 6 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-5, similar elements in fig. 6 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operation of like elements discussed in detail in the above paragraphs is omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 6.

In contrast to the embodiment in fig. 2A, the integrated circuit 100 further includes the conductive pattern 225-226, the gate 318, the conductive line 405c, and the vias VD26-VD28, VM14-VM15, VG18, and VN5-VN 6. With respect to, for example, the conductive pattern 202, the conductive pattern 225 and 226 are arranged. With respect to, for example, gate 302, gate 318 is configured. With respect to, for example, the conductive line 405a, a conductive line 405c is configured. Regarding the through hole VD2, for example, through holes VD26-VD28 are provided. Regarding, for example, the via VM2, the vias VM14-VM15 are configured. For example, via VG18 is disposed as via VG 2. Regarding, for example, the through-hole VN1, the through-holes VN5-VN6 are arranged.

Further, in some embodiments, while a portion of the gate 302 disposed above the active region 120 is referred to as a dummy gate, the gate 302 corresponds to the gate of the transistor M1. While a portion of the gate 318 disposed above the active region 110 is referred to as a dummy gate, the gate 318 corresponds to the gate of the transistor M3. A portion of the gate 303 over the active region 110 corresponds to the gate of the transistor M2, and another portion of the gate 303 over the active region 120 corresponds to the gate of the transistor M4. The conductive pattern 202 corresponds to the drain/source of the transistor M1. The conductive pattern 203 corresponds to the source/drain of the transistors M1 and M4 and the drain/source of the transistor M2. The conductive pattern 204 corresponds to the source/drain of the transistor M2. The conductive pattern 207 corresponds to the source/drain of the transistor M3. The conductive pattern 226 corresponds to the drain/source of the transistor M3.

For illustration, the conductive patterns 225 and 226 extend in the y direction and are separated from each other in the y direction. The conductive patterns 225 and 226 are arranged to be interposed between the gates 301, 305, and 318. The conductive patterns 225 and 226 pass through the active regions 110 and 120, respectively.

The gate 318 extends in the y-direction and passes through the active regions 110-120. The gate 318 is arranged to be interposed between the gates 310-302.

Conductive line 403a also passes through conductive pattern 225 and gate 318, and conductive line 403a also passes through gate 303. Conductive line 404a also passes through gate 318, and conductive line 404b also passes through conductive pattern 203. The conductive line 405a also passes through the conductive pattern 226. Conductive line 405c is disposed between conductive lines 405a-405b and passes through conductive patterns 203 and 226 and gate 302.

The conductive portion 501 overlaps with the conductive patterns 225 and 226 instead of the conductive patterns 201 and 206. The conductive portion 502 also passes through the conductive line 405 c.

As shown in fig. 6, conductive track 601 also passes through conductive pattern 205, and conductive track 602 also passes through gate 318.

While via VG2 couples gate 302 to conductive line 404a, via VG18 couples gate 318 to conductive line 404 a. Thus, gate 318 is coupled to gate 302.

With continued reference to fig. 6, via VD2 couples conductive pattern 202 to conductive line 403a, and via VM2 couples conductive line 403a to conductive portion 502. Vias VN2 couple conductive portions 502 to conductive tracks 601. Vias VN6 couple conductive traces 601 to conductive portions 504. Via VM15 couples conductive portion 504 to conductive line 405 b. Via VD7 couples conductive line 405b to conductive pattern 208. Thus, through the above discussion, the conductive pattern 202 is coupled to the conductive pattern 208.

Via VD3 couples conductive pattern 204 to conductive line 403b, and via VM14 couples conductive line 403b to conductive portion 503. The vias VN5 couple the conductive portions 503 to the conductive tracks 602. Vias VN1 couple conductive tracks 602 to conductive portions 501. Via VM1 couples conductive portion 501 to conductive line 405 a. Via VD27 couples conductive line 405a to conductive pattern 226. Thus, through the above discussion, the conductive pattern 204 is coupled to the conductive pattern 226.

Vias VD2 and VD26 couple conductive patterns 202 and 225, respectively, to conductive line 403 a. Thus, the conductive pattern 202 is coupled to the conductive pattern 225. Vias VD6 and VD28 couple conductive patterns 207 and 203, respectively, to conductive line 405 c. Thus, the conductive pattern 207 is coupled to the conductive pattern 203.

The configuration in fig. 6 is for illustrative purposes. The various embodiments in fig. 6 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 403b does not pass through the conductive pattern 203 and the gate 303.

Reference is now made to fig. 7. Fig. 7 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-6, similar elements in fig. 7 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 7.

In contrast to the embodiment of fig. 3 and 6, instead of having conductive lines 405a-405b and structures such as conductive line 404b, conductive portions 501 and 503 and 504, the integrated circuit 100 further includes conductive pattern 227 and 229, gate 319 and 321, conductive portion 505 and vias VD29-VD31, VG19, VM16-VM 18. As for, for example, the conductive pattern 203, the conductive pattern 227 and 229 are arranged. Gates 319-321 are configured with respect to, for example, gates 302, 305, and 318, respectively. For example, the conductive portion 505 is disposed in the conductive portion 502. Regarding the through hole VD28, for example, through holes VD29-VD31 are provided. Regarding, for example, the via VM2, the vias VM16-VM18 are configured. For example, via VG19 is disposed as via VG 6.

Further, in some embodiments, the gate 319 corresponds to the gate of the transistor M1. While a portion of the gate 321 disposed above the active region 140 is referred to as a dummy gate, the gate 321 corresponds to the gate of the transistor M3. A portion of the gate 303 over the active region 110 corresponds to the gate of the transistor M2, and another portion of the gate 303 over the active region 120 corresponds to the gate of the transistor M4. The conductive pattern 203 corresponds to the source/drain of the transistors M1 and M4 and the drain/source of the transistor M2. The conductive pattern 208 corresponds to the drain/source of the transistor M4. The conductive pattern 213 corresponds to the source/drain of the transistor M3. The conductive pattern 227 corresponds to the drain/source of the transistor M3. The conductive pattern 228 corresponds to the source/drain of the transistor M2. The conductive pattern 229 corresponds to the drain/source of the transistor M1.

For illustration, the conductive patterns 227 and 229 extend in the y-direction. The conductive pattern 227 is arranged to be interposed between the gates 308, 312, and 321 and pass through the active region 130 and 140. The conductive pattern 228 is arranged to be interposed between the gates 308, 312, and 321 and pass through the active regions 110 and 140. The conductive pattern 229 is arranged to be interposed between the gates 301, 305, and 319 and 120 and pass through the active region 110 and 120.

Gates 319-321 are elongated in the y-direction. Gates 319-320 pass through active regions 110 and 120, respectively. The gate 321 passes through the active region 130-140.

Conductive line 403a also passes through conductive pattern 229 and gate 319 rather than through conductive patterns 202 and 225 and gate 318. The conductive line 403b also passes through the conductive pattern 228 rather than through the conductive pattern 203-204. Conductive line 404a passes through conductive patterns 203 and 229 rather than through gates 302 and 318. The conductive line 405c is also passed through the conductive patterns 203, 208, and 229 and the gates 303 and 320, instead of passing through the conductive pattern 207.

The conductive portion 502 overlaps with the conductive patterns 211, 216, and 229 and also passes through the conductive lines 401 and 408, instead of overlapping with the conductive patterns 202 and 207. The conductive portion 505 overlaps the conductive patterns 203 and 227 and passes through the conductive lines 401, 404a, 405c, and 407 and 409.

For illustration, vias VG2 and VG3 overlap active region 110 while vias VG18 overlap shallow trench isolation region 720. Via VG2 couples gate 319 to conductive line 403 a. Via VM2 couples conductive line 403a to conductive portion 502. Via VM16 couples conductive portion 502 to conductive line 408. Vias VG18 couple conductive line 408 to gate 321. Thus, gate 319 is coupled to gate 321.

Vias VG19 couple gates 320 to conductive line 402. In some embodiments, conductive line 402 also receives a supply voltage VSS for gate 320.

With continued reference to fig. 7, via VD6 couples conductive pattern 229 to conductive line 405c, and via VD7 couples conductive line 405c to conductive portion 208. Thus, the conductive pattern 229 is coupled to the conductive pattern 208.

Vias VD29 couple conductive pattern 213 to conductive line 407. Via VM17 couples conductive line 407 to conductive portion 505. Via VM18 couples conductive portion 505 to conductive line 404 a. Via VD31 couples conductive line 404a to conductive pattern 203. Thus, the conductive pattern 213 is coupled to the conductive pattern 203.

Via VD28 couples conductive pattern 227 to conductive line 409, and via VD29 couples conductive pattern 228 to conductive line 409. Thus, the conductive pattern 227 is coupled to the conductive pattern 228.

Compared to the configuration in fig. 6, the embodiment of fig. 7 also preserves the wiring resources of the metal layer in the second layer by not implementing the conductive portions 501 and 504.

The configuration in fig. 7 is for illustrative purposes. The various embodiments in fig. 7 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 404a does not pass through the conductive pattern 229.

Reference is now made to fig. 8. Fig. 8 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-7, similar elements in fig. 8 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 8.

In contrast to the embodiment in fig. 7, the integrated circuit 100 further comprises the conductive pattern 230-. With respect to, for example, the conductive pattern 227, the conductive pattern 230 and 234 are arranged. For example, gate 302, gate 322 and 323 are configured. Regarding the through hole VD28, for example, through holes VD32-VD35 are provided. Regarding, for example, the via VM2 in fig. 7, the vias VM19-VM23 are configured.

Further, in some embodiments, a portion of the gate 302 over the active region 110 corresponds to the gate of the transistor M1, and another portion of the gate 302 over the active region 120 corresponds to the gate of the transistor M4. While a portion of the gate electrode 303 disposed above the active region 120 is referred to as a dummy gate, the gate electrode 303 corresponds to the gate electrode of the transistor M2. While a portion of the gate 321 disposed above the active region 140 is referred to as a dummy gate, the gate 321 corresponds to the gate of the transistor M4.

In some embodiments, the conductive pattern 213 corresponds to a source/drain of the transistor M4. The conductive pattern 227 corresponds to the drain/source of the transistor M4. The conductive pattern 230 corresponds to the drain/source of the transistor M1. The conductive pattern 231 corresponds to the source/drain of the transistor M1 and the drain/source of the transistor M2. The conductive pattern 232 corresponds to the source/drain of the transistor M3. The conductive pattern 233 corresponds to the drain/source of the transistor M3. The conductive pattern 234 corresponds to the source/drain of the transistor M2.

For illustration purposes, the conductive patterns 230 and 234 extend in the y-direction. The conductive pattern 230 is arranged to be interposed between the gates 301, 311, and 312 and pass through the active regions 110 and 140. The conductive patterns 231 and 232 are arranged to be inserted between the gates 302 and 303 and pass through the active regions 110 and 120, respectively. The conductive pattern 233 is arranged to be interposed between the gates 302 and 305 and to pass through the active region 120.

The gates 322 and 323 are elongated in the y-direction and separated from each other in the y-direction. Gate 322 passes through active region 130-.

The conductive line 403a also passes through the conductive pattern 230-231 and the gate 302 instead of passing through the conductive pattern 229 and the gate 319.

The conductive line 404a passes through the gate 302 instead of through the conductive pattern 229. The conductive line 404b passes through the conductive pattern 234 and the gates 303 and 323. Conductive line 405a passes through conductive patterns 206 and 233 and gate 305, and conductive line 405b passes through conductive patterns 209, 232, and 234 and gates 303 and 323.

The conductive portion 502 also overlaps with the conductive patterns 230 and 233 instead of the conductive patterns 216 and 229, and also passes through the conductive lines 405a, 407, and 409 instead of the conductive line 408. The conductive portion 503 overlaps the conductive patterns 213, 218, and 234 and passes through the conductive lines 401, 404b, 405b, and 407 and 409.

For illustration purposes, vias VG2-VG3 overlap shallow trench isolation region 710 and via VG18 overlaps shallow trench isolation region 720. Via VG2 couples gate 302 to conductive line 404 a. Via VG3 couples gate 303 to conductive line 404 b. Vias VG18 couple conductive line 408 to gate 321.

With continued reference to fig. 8, vias VD32 couple conductive pattern 213 to conductive line 407. The vias VM19 couple the conductive lines 407 to the conductive portions 502. Via VM21 couples conductive portion 502 to conductive line 403 a. Via VD34 couples conductive line 403a to conductive pattern 231. Further, via VM22 couples conductive portion 502 to conductive line 405 a. Via VD6 couples conductive line 405a to conductive pattern 233. Thus, the conductive pattern 213 is coupled to the conductive patterns 231 and 233.

Vias VD28, VD30, and VD33 couple conductive line 409 to conductive patterns 227, 218, and 230, respectively. Thus, the conductive pattern 227 is coupled to the conductive pattern 231.

Vias VD7 and VD35 couple conductive patterns 234 and 232 to conductive line 405 b. Accordingly, the conductive patterns 232 and 234 are coupled to each other.

The configuration in fig. 8 is for illustrative purposes. The various embodiments in fig. 8 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 405b does not overlap the gate 323.

Reference is now made to fig. 9. Fig. 9 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-8, similar elements in fig. 9 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 9.

In contrast to the embodiment of FIG. 8, instead of having conductive patterns 218, 230, and 233, gate 322, 323, and corresponding structures for routing, integrated circuit 100 further includes conductive patterns 208, 216, 228, 229, gates 304, 306, 310, and 314, vias VD36-VD37, and VM24-VM 28. Regarding the through hole VD32, for example, through holes VD36-VD37 are provided. Regarding, for example, the via VM2, the vias VM24-VM28 are configured.

In some embodiments, while a portion of the gate 302 disposed over the active region 110 is referred to as a dummy gate, the gate 302 corresponds to the gate of the transistor M4. A portion of the gate 303 over the active region 110 corresponds to the gate of the transistor M1, and another portion of the gate 303 over the active region 120 corresponds to the gate of the transistor M3. While a portion of the gate 321 disposed over the active region 130 is referred to as a dummy gate, the gate 321 disposed over the active region 140 corresponds to the gate of the transistor M2.

In some embodiments, the conductive pattern 227 corresponds to a source/drain of the transistor M2. The conductive pattern 228 corresponds to the source/drain of the transistor M1 and the drain/source of the transistor M2. The conductive pattern 229 corresponds to the drain/source of the transistor M4. The conductive pattern 231 corresponds to the drain/source of the transistor M1. The conductive pattern 232 corresponds to the source/drain of the transistors M3 and M4. The conductive pattern 208 corresponds to the drain/source of the transistor M3.

The conductive pattern 208 is arranged between the gates 303 and 316. The conductive pattern 216 is disposed between the gate electrodes 311-312. The conductive pattern 228 is disposed between the gates 303, 304, 314, and 321. The conductive pattern 229 is disposed between the gate electrodes 301-.

The conductive line 403a passes through the conductive pattern 229 instead of passing through the conductive pattern 230. The conductive line 404a also passes through the conductive pattern 229. The conductive line 404a does not electrically conduct the pattern 234 and the gate 323. The conductive line 405a also passes through the conductive patterns 229 and 232 and the gate 302, not through the conductive pattern 233. Conductive line 405b passes through conductive pattern 208 and gate 306 rather than through conductive patterns 232 and 234 and gates 303 and 323.

The conductive portion 501 overlaps the conductive patterns 201, 206, 210, and 215. The conductive portion 502 overlaps the conductive patterns 211, 215, and 229. The conductive portions 501-502 pass through the conductive lines 403a, 404a, 405a, and 407-409. The conductive portion 503 overlaps the conductive patterns 213, 218, and 234 and passes through the conductive lines 404b, 405b, and 407 and 409.

For illustration purposes, a via VG2 couples gate 302 to conductive line 404 a. Via VM27 couples conductive line 404a to conductive portion 501. Via VM25 couples conductive portion 501 to conductive line 408. Vias VG18 couple conductive line 408 to gate 321. Thus, gate 302 is coupled to gate 321. Via VG3 is coupled to conductive line 404 b.

With continued reference to fig. 9, vias VD2 and VD34 couple conductive patterns 229 and 231, respectively, to conductive line 403 a. Accordingly, the conductive patterns 229 and 231 are coupled to each other.

Via VD35 couples conductive pattern 232 to conductive line 405 a. Via VM22 couples conductive line 405a to conductive portion 502. Via VM26 couples conductive portion 502 to conductive line 409. Via VD36 couples conductive line 409 to conductive pattern 228. Thus, the conductive pattern 232 is coupled to the conductive pattern 228.

Via VD7 couples conductive pattern 208 to conductive line 405 b. Via VM28 couples conductive line 405b to conductive portion 503. Vias VM24 couple conductive portions 501 to conductive lines 407. Vias VD32 and VD37 couple conductive line 407 to conductive portions 213 and 227, respectively. Thus, the conductive pattern 208 is coupled to the conductive patterns 213 and 227.

The configuration in fig. 9 is for illustrative purposes. The various embodiments in fig. 9 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 407 does not overlap the gate 307-308.

Reference is now made to fig. 10A. Fig. 10A is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-9, elements in fig. 10A are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 10A.

Compared with the embodiment in FIG. 9, the integrated circuit 100 further includes the conductive pattern 231-. With respect to, for example, the conductive pattern 232, the conductive pattern 235 and 239 are arranged. Regarding the through hole VD35, for example, through holes VD38-VD41 are provided. Regarding, for example, the via VM22 in fig. 9, the vias VM29-VM32 are configured.

In some embodiments, a portion of the gate 303 over the active region 110 corresponds to the gate of the transistor M1, and another portion of the gate 303 over the active region 120 corresponds to the gate of the transistor M3. A portion of the gate 321 over the active region 130 corresponds to the gate of the transistor M4, and another portion of the gate 321 over the active region 140 corresponds to the gate of the transistor M2.

In some embodiments, the conductive pattern 231 corresponds to the drain/source of the transistor M1. The conductive pattern 232 corresponds to the drain/source of the transistor M3. The conductive pattern 235 corresponds to the source/drain of the transistors M1, M3, and M4 and the drain/source of the transistor M2. The conductive pattern 238 corresponds to the drain/source of the transistor M4. The conductive pattern 239 corresponds to a source/drain of the transistor M2.

The conductive pattern 231 is disposed between the gates 319 and 303, and the conductive pattern 232 is disposed between the gates 320 and 303. The conductive patterns 235 and 239 extend in the y-direction. The conductive pattern 235 is disposed between the gates 303, 306, 310, 321, and 324. The conductive pattern 236 is disposed adjacent to the gate 319. The conductive pattern 237 is disposed adjacent to the gate electrode 320. The conductive pattern 238 is disposed between the gates 308 and 321. The conductive pattern 239 is disposed between the gates 312 and 321.

As shown in fig. 10A, a conductive line 403a passes through the conductive patterns 231 and 236 and the gate 319. Conductive line 404a passes through gate 303. The conductive line 405a passes through the conductive patterns 232, 235, and 237 and the gates 303 and 320. The conductive line 407 passes through the conductive patterns 211 and 238 and the gates 308 and 321. Conductive line 408 passes through gate 321. The conductive line 409 passes through the conductive patterns 216, 239, and 235 and the gates 308 and 321.

The conductive portion 503 overlaps the conductive patterns 231 and 232 and 238 and 239 and passes through the conductive lines 403a, 404a, 405a and 407 and 409. The conductive portion 505 overlaps the conductive pattern 235 and passes through the conductive lines 401, 405a, and 409.

A via VG3 is coupled between conductive line 404a and gate 321. A via VG18 is coupled between conductive line 408 and gate 321.

Via VD40 couples conductive pattern 236 to conductive line 401, and via VD41 couples conductive pattern 237 to conductive line 402. In some embodiments, conductive lines 401 output a supply voltage VDD to conductive patterns 236, and conductive lines 402 receive a supply voltage VSS for conductive patterns 237.

With continued reference to fig. 10A, vias VD34 couple conductive pattern 236 to conductive line 403 a. Via VM31 couples conductive line 403a to conductive portion 503. Vias VM29 couple conductive portions 503 to conductive lines 407. Vias VD38 couple conductive lines 407 to conductive patterns 238. Thus, the conductive pattern 236 is coupled to the conductive pattern 238.

Via VD35 couples conductive pattern 232 to conductive line 405 a. Via VM32 couples conductive line 405a to conductive portion 505. Via VM30 couples conductive portion 505 to conductive line 409. Via VD39 couples conductive line 409 to conductive pattern 239. Thus, the conductive pattern 232 is coupled to the conductive pattern 239.

The embodiment shown in fig. 10A also preserves the wiring resources of the metal layer in the second layer by not implementing the conductive portions 501, and also preserves the layout area in the integrated circuit 100 by implementing fewer elements than the configuration in fig. 9.

Reference is now made to fig. 10B. Fig. 10B is a cross-sectional view of integrated circuit 100 along line CC' corresponding to a portion of fig. 10A, in accordance with various embodiments. As shown in fig. 10B, the shallow trench isolation region 720 is inserted between the active regions 130 and 140, and the shallow trench isolation region 730 is inserted between the active regions 110 and 140. The gate 321 overlaps the active regions 130-140 and the shallow trench isolation region 720, and the gate 303 overlaps the active regions 110-120 and the shallow trench isolation region 710. Conductive lines 401, 402, 404a, 405a, and 406, 407 are disposed in layers above the gates 303 and 321. Conductive lines 404a and 408 are coupled to gates 303 and 321 through vias VG3 and VG18, respectively.

The configuration of fig. 10A-10B is for illustration purposes. The various embodiments of fig. 10A-10B are within the intended scope of the present disclosure. For example, in some embodiments, conductive lines 403a and 405a do not overlap gates 319 and 320.

Reference is now made to fig. 11A. Fig. 11A is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-10B, elements in fig. 11A are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 11A.

Compared with the embodiment in fig. 10A, the integrated circuit 100 further includes the conductive patterns 240 and 241, the gates 325 and 326, the vias VD42 and VM33, and the conductive lines 412 and 415 instead of the conductive patterns 231 and 232 and 238 and 239, the gates 321, the conductive lines 401 and 402 and 406, the conductive portions 505, and the corresponding structures for wiring. With respect to, for example, the conductive pattern 227 in fig. 9, the conductive pattern 240-241 is arranged. With respect to, for example, gate 319 in FIG. 7, gate 325-326 is configured. As for the through hole VD39, for example, a through hole VD42 is arranged. With respect to, for example, via VM29, via VM33 is configured. Conductive line 412 is configured with respect to, for example, conductive line 406, conductive line 413 and 414 are configured with respect to, for example, conductive line 410, and conductive line 415 is configured with respect to, for example, conductive line 402.

In some embodiments, a portion of the gate 303 over the active region 110 corresponds to the gate of the transistor M3, and another portion of the gate 303 over the active region 140 corresponds to the gate of the transistor M1. The gate 325 corresponds to the gate of the transistor M4. The gate 326 corresponds to the gate of the transistor M2.

In some embodiments, the conductive pattern 235 corresponds to the source/drain of the transistors M1, M3, and M4 and the drain/source of the transistor M2. The conductive pattern 240 corresponds to the drain/source of the transistors M1 and M4. The conductive pattern 241 corresponds to the drain/source of the transistor M3 and the source/drain of the transistor M2.

The conductive patterns 240 and 241 extend in the y direction. The conductive pattern 240 is disposed between the gates 303, 308, 312, and 325. The conductive pattern 241 is disposed between the gate electrodes 303, 319, 320, and 326.

As shown in fig. 11A, the conductive line 403a passes through the conductive patterns 236 and 241 and the gate 303. The conductive line 404a passes through the conductive pattern 241. The conductive line 405a passes through the conductive patterns 235, 237, and 241 and the gate 326. The conductive line 407 passes through the conductive patterns 211 and 240 and the gates 308 and 325. The conductive line 408 passes through the conductive pattern 240. The conductive line 409 passes through the conductive patterns 216, 235, and 240 and the gates 303 and 312.

The conductive lines 412 and 415 extend in the x-direction and are separated from each other in the y-direction. As shown in fig. 11A, conductive line 412 is coupled to conductive patterns 211 and 214 through vias VD10 and VD 13. Conductive line 412 is also coupled to gates 308 and 310 through vias VG8 and VG 10. In some embodiments, the conductive line 412 receives a supply voltage VSS for the conductive patterns 211 and 214 and the gates 308 and 310. The configuration of conductive lines 413-415 is similar to conductive line 412. Therefore, a repetitive description is omitted here. In some embodiments, conductive lines 413-414 output the supply voltage VDD to the integrated circuit 100, and conductive line 415 receives the supply voltage VSS for the integrated circuit 100.

The conductive portion 503 overlaps the conductive pattern 240 and 241 and passes through the conductive lines 403a, 404a, 405a, and 407 and 409.

For illustration purposes, vias VG23-VG24 overlap active regions 130 and 110-120, respectively. Vias VG23 couple gates 325 to conductive lines 407. The vias VM29 couple the conductive lines 407 to the conductive portions 503. Via VM33 couples conductive portion 503 to conductive line 405 a. A via VG25 couples gate 326 to conductive line 405 a. Thus, gate 325 is coupled to gate 326. Further, gate VG24 couples gate 303 to conductive line 403 a.

Via VD39 couples conductive pattern 240 to conductive line 409. Via VD42 couples conductive pattern 241 to conductive line 404 a.

Compared to the configuration in fig. 10A, the embodiment in fig. 11A also preserves the wiring resources of the metal layer in the second layer by not implementing the conductive portion 505.

Reference is now made to fig. 11B. Fig. 11B is a cross-sectional view of integrated circuit 100 corresponding to a portion of fig. 11A along line DD', in accordance with various embodiments. As shown in fig. 11B, the shallow trench isolation region 720 is inserted between the active regions 130 and 140, the shallow trench isolation region 730 is inserted between the active regions 110 and 140, and the shallow trench isolation region 710 is inserted between the active regions 110 and 120. The gate 325 overlaps the active region 130 and the shallow trench isolation region 720. Gate 303 overlaps active regions 110 and 140 and shallow trench isolation regions 710 and 730. Conductive lines 403a, 404a, 405a, 407 and 409 and 412 and 415 are disposed in layers above gates 303, 325 and 326. Conductive line 403a is coupled to gate 303 through via VG 24. Conductive line 405a is coupled to gate 326 through via VG 25. Conductive line 407 is coupled to gate 325 through via VG 23.

The configurations in fig. 11A-11B are for illustration purposes. The various embodiments of fig. 11A-11B are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 407 does not overlap the gate 307-308.

Reference is now made to fig. 12. Fig. 12 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-11B, similar elements in fig. 12 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 12.

Compared with the embodiment in fig. 11A, the integrated circuit 100 further includes the conductive pattern 242-. With respect to, for example, the conductive pattern 240 in fig. 11A, the conductive pattern 242-247 is arranged. With respect to the conductive pattern 409 in fig. 11A, for example, conductive lines 409a-409b are arranged. Regarding the through hole VD42 in FIG. 11A, for example, through holes VD43-VD48 are provided. Regarding, for example, the via VG24 in fig. 11A, the vias VG26-VG28 are arranged. Regarding, for example, the via VM29 in fig. 11A, the vias VM34-VM37 are configured.

In addition, in contrast to the embodiments of fig. 2A-11B, the active region 110 in the embodiment of fig. 12 has n-type conductivity rather than p-type conductivity.

In some embodiments, a portion of the gate 303 over the active region 140 corresponds to the gate of the transistor M1, and another portion of the gate 303 over the active region 140 corresponds to the gate of the transistor M1. A portion of the gate 321 over the active region 140 corresponds to the gate of the transistor M2, and another portion of the gate 321 over the active region 110 corresponds to the gate of the transistor M4.

In some embodiments, the conductive pattern 242 corresponds to a source/drain of the transistor M2. The conductive pattern 244 corresponds to the drain/source of the transistor M1. The conductive pattern 245 corresponds to the drain/source of the transistor M4. The conductive pattern 246 corresponds to the source/drain of the transistors M1, M3, and M4 and the drain/source of the transistor M2. The conductive pattern 247 corresponds to the drain/source of the transistor M3.

The conductive patterns 242 and 247 extend in the y direction. The conductive pattern 242 is disposed between the gates 307, 308, 311, and 321. The conductive pattern 243 is disposed between the gate electrodes 308 and 309. The conductive pattern 244 is disposed between the gates 303, 309 and 310 and 324. The conductive pattern 245 is disposed between the gates 301, 305, 308, and 320. The conductive pattern 246 is disposed between the gate electrodes 303 and 321. The conductive pattern 247 is disposed between the gates 303 and 324.

As shown in fig. 12, a conductive line 403a passes through the conductive patterns 201 and 245 and the gates 301 and 321, and a conductive line 403b passes through the conductive patterns 205 and 247 and the gate 324. The conductive line 404a passes through the conductive pattern 245. The conductive line 405a passes through the conductive patterns 206, 208 and 209, 232 and 245 and the gates 305 and 306, 320 and 326. The conductive line 407 passes through the conductive patterns 210, 214, and 242 and the gate 307 and 310. The conductive line 408 passes through the conductive pattern 244. The conductive line 409a passes through the conductive patterns 215 and 242 and the gate 311. The conductive line 409b passes through the conductive patterns 219 and 244 and the gates 303 and 324. The conductive line 412 passes through the conductive patterns 210, 214, and 242 and the gate 307 and 310. The conductive line 413 passes through the conductive patterns 215, 219, 242, 244, 246 and the gates 303, 311, 321, and 324. The conductive line 414 passes through the conductive patterns 201, 205, 219, and 245 and 247 and the gates 301, 303, 321, and 324. The conductive line 415 passes through the conductive patterns 206, 208, 209, 232, and 245 and the gates 305, 306, 320, and 326.

The conductive portion 502 overlaps the conductive patterns 242 and 245 and passes through the conductive lines 403a, 404a, 405a, 407 and 408 and 409 a. The conductive portion 503 overlaps the conductive patterns 208, 244, and 247 and passes through the conductive lines 403b, 404a, 405a, 407 and 408, and 409 b. The conductive portion 505 overlaps the conductive patterns 232, 243, and 246 and passes through the conductive lines 404a, 405a, and 407 and 408.

A via VG26 is coupled between conductive line 409b and gate 303. A via VG27 is coupled between conductive line 403as and gate 321. In some embodiments, vias VG26 overlap active region 140. Via VG27 overlaps active region 110.

Via VD47 couples conductive pattern 232 to conductive line 415. Via VD48 couples conductive pattern 208 to conductive line 415. In some embodiments, conductive lines 415 output supply voltage VDD or supply voltage VSS to conductive patterns 208 and 232.

With continued reference to fig. 11A, via VD43 couples conductive pattern 244 to conductive line 408. Via VM35 couples conductive line 408 to conductive portion 505. Via VM37 couples conductive portion 505 to conductive line 405 a. Via VD46 couples conductive line 405a to conductive pattern 245. Thus, the conductive pattern 244 is coupled to the conductive pattern 245.

Via VD44 couples conductive pattern 242 to conductive line 409 a. Via VM26 couples conductive line 409a to conductive portion 502. The vias VM34 couple the conductive portions 502 to the conductive lines 407. The vias VM24 couple the conductive lines 407 to the conductive portions 503. Via VM36 couples conductive portion 503 to conductive line 403 b. Via VD45 couples conductive line 403b to conductive pattern 247. Thus, the conductive pattern 242 is coupled to the conductive pattern 247.

The configuration in fig. 12 is for illustrative purposes. The various embodiments in fig. 12 are within the intended scope of the present disclosure. For example, in some embodiments, the embodiment shown in fig. 12 does not include conductive line 404 a.

Reference is now made to fig. 13. Fig. 13 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-12, similar elements in fig. 13 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 13.

In contrast to the embodiment shown in fig. 6, instead of having conductive patterns 203 and 208, conductive portion 504 and corresponding structures for wiring, integrated circuit 100 further includes conductive pattern 248-. With respect to, for example, the conductive pattern 203 in fig. 6, conductive patterns 248-251 are arranged. With respect to, for example, the gate 318 in fig. 6, a gate 327 is disposed. Regarding the through hole VD3 in FIG. 6, for example, through holes VD49-VD51 are provided. Regarding, for example, the via VM14 in fig. 6, the vias VM38-VM40 are configured. Regarding the through-holes VN6 in fig. 6, for example, the through-holes VN7 to VN10 are arranged.

In some embodiments, while a portion of the gate 302 disposed over the active region 120 is referred to as a dummy gate, a portion of the gate 302 disposed over the active region 110 corresponds to a gate of the transistor M1. While a portion of the gate 303 disposed over the active region 120 is referred to as a dummy gate, a portion of the gate 303 disposed over the active region 110 corresponds to the gate of the transistor M2. While a portion of the gate 318 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 318 disposed over the active region 120 corresponds to the gate of the transistor M3. While another portion of the gate 327 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 327 disposed over the active region 120 corresponds to a gate of the transistor M4.

In some embodiments, the conductive pattern 202 corresponds to the drain/source of the transistor M1. The conductive pattern 207 corresponds to the drain/source of the transistor M3. The conductive pattern 226 corresponds to the source/drain of the transistors M3-M4. The conductive pattern 248 corresponds to the source/drain of the transistor M1 and the drain/source of the transistor M2. The conductive pattern 249 corresponds to the drain/source of the transistor M4. The conductive pattern 251 corresponds to the source/drain of the transistor M2.

The conductive patterns 248 and 251 extend in the y direction. The conductive pattern 248 is disposed between the gates 302-303. The conductive pattern 249 is arranged between the gates 301, 305, and 327. The conductive pattern 250 is disposed between the gate electrodes 302-303. The conductive pattern 251 is disposed between the gates 303 and 304 and 306.

The gate 327 extends in the y-direction and is arranged to be interposed between the conductive patterns 225 and 226 and 249.

In contrast to fig. 6, the conductive line 403a also passes through the conductive pattern 249 and the gate 327. The conductive line 403b passes through the conductive patterns 248 and 251 and the gate 303 and 304. The conductive line 404a passes through the conductive pattern 249 and the gates 318 and 327. The conductive line 404b passes through the conductive pattern 251 and the gate electrode 303. Conductive line 404c passes through gates 302 and 318. The conductive line 405a passes through the conductive patterns 226 and 249 and the gates 305, 218, and 327. The conductive line 405b passes through the conductive patterns 207 and 250 and 251 and the gate 302 and 304.

The conductive portion 501 overlaps with the conductive pattern 249 and passes through the conductive lines 403a, 404a, and 405 a. The conductive portion 502 overlaps the conductive pattern 225 and 226 and passes through the conductive lines 403a and 405 a. The conductive portion 503 overlaps the conductive pattern 251 and passes through the conductive lines 403b, 404b, and 405 b. The conductive portion 505 overlaps the conductive patterns 248 and 250 and passes through the conductive lines 403b and 405 b.

While via VG2 couples gate 320 to conductive line 404c, via VG18 couples gate 318 to conductive line 404 c. Thus, gate 318 is coupled to gate 302.

Via VG3 couples gate 303 to conductive line 404 b. Via VM40 couples conductive line 404b to conductive portion 503. The vias VN10 couple the conductive portions 503 to the conductive tracks 602. Vias VN9 couple conductive tracks 602 to conductive portions 501. Via VM38 couples conductive portion 501 to conductive line 404 a. Vias VG29 couple conductive line 404a to gate 327. Thus, gate 303 is coupled to gate 327.

In some embodiments, vias VG2-VG3, VG18, and VG29 are arranged to overlap shallow trench isolation region 710.

With continued reference to fig. 13, vias VD2, VD26, and VD49 couple conductive patterns 202, 225, and 249, respectively, to conductive line 403 a. Thus, the conductive pattern 202 is coupled to the conductive pattern 249.

Vias VD6 and VD51-VD52 couple conductive patterns 249, 251, and 250, respectively, to conductive line 405 b. Thus, the conductive pattern 251 is coupled to the conductive pattern 207.

Via VD50 couples conductive pattern 248 to conductive line 403 b. Via VM39 couples conductive line 403b to conductive portion 505. Vias VN8 couple conductive portions 505 to conductive tracks 601. Vias VN7 couple conductive tracks 601 to conductive portions 502. Via VM1 couples conductive portion 502 to conductive line 405 a. Via VD27 couples conductive line 405a to conductive pattern 226. Thus, conductive pattern 248 is coupled to conductive pattern 226.

The configuration in fig. 13 is for illustrative purposes. The various embodiments in fig. 13 are within the intended scope of the present disclosure. For example, in a lower embodiment, conductive line 410 and/or conductive line 420 are coupled to another cell while abutting the cell shown in the embodiment in fig. 13.

Reference is now made to fig. 14. Fig. 14 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-13, similar elements in fig. 14 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 14.

In contrast to the embodiment shown in fig. 3, integrated circuit 100 includes a structure corresponding to the embodiment shown in fig. 13, rather than having a structure corresponding to the embodiment shown in fig. 2A. In addition, as compared with the embodiment shown in FIG. 13, the integrated circuit 100 further has the structure included in the second cell, the conductive pattern 252-. With respect to, for example, the conductive pattern 211 in fig. 3, the conductive pattern 252 and 256 are arranged. With respect to, for example, gate 307 in FIG. 3, gates 328-331 are configured. Regarding, for example, the via VM1, the vias VM42-VM45 are configured.

The conductive pattern and the correspondence between the gates and the transistors M1-M4 in the embodiment shown in fig. 14 are similar to the embodiment shown in fig. 13. Therefore, a repetitive discussion is omitted here.

As shown in fig. 14, the conductive patterns 252 and 256 extend in the y direction and are separated from each other in both the x direction and the y direction. The conductive pattern 252 passes through the active regions 110-120. The conductive patterns 253 and 254 pass through the active region 130, and the conductive patterns 255 and 256 pass through the active region 140. The conductive pattern 253 is arranged to be interposed between the gates 307 and 328. The conductive pattern 254 is arranged to be interposed between the gates 328 and 329. The conductive pattern 255 is arranged to be interposed between the gate electrodes 311 and 330. The conductive pattern 256 is arranged to be interposed between the gates 330 and 331.

The gates 328-331 extend in the y-direction and are separated from each other in both the x-direction and the y-direction. Gates 328-329 pass through active region 130 and gate 330-331 pass through active region 140. In some embodiments, as shown in fig. 3, gates 328 and 330 are aligned with gate 327 and gates 329 and 331 are aligned with gate 318.

In contrast to the embodiment shown in fig. 3, the conductive line 407 also passes through the conductive pattern 253-254 and the gate 328-329. The conductive line 409 also passes through the conductive pattern 255 and 256 and the gate 330 and 331.

The conductive portion 501 overlaps the conductive patterns 249, 253, and 255 and passes through the conductive lines 401, 403a, 404a, 405a, and 407 and 409. The conductive portion 502 overlaps with the conductive patterns 225, 254, and 256 and passes through the conductive lines 401, 403a, 405a, and 407 and 409. The conductive portion 503 overlaps with the conductive patterns 214, 218, and 251 and passes through the conductive lines 401, 403b, 404b, 405b, and 407 and 409. The conductive portion 505 overlaps the conductive patterns 212, 217, 248, and 250 and passes through the conductive lines 401, 403b, 405b, and 407 and 409. The conductive portion 506 overlaps the conductive pattern 252 and passes through the conductive lines 403a, 404c, and 405 b.

Via VG2 couples gate 302 to conductive line 404c, and via VG18 couples gate 318 to conductive line 404 c. Thus, gate 302 is coupled to gate 318. In some embodiments, via VM41 couples conductive line 404c to conductive portions 506. In such embodiments, conductive portion 506 receives signals for gates 302 and 318.

Via VG3 couples gate 303 to conductive line 404 b. Via VM40 couples conductive line 404b to conductive portion 503. Via VM44 couples conductive portion 503 to conductive line 408. Via VM42 couples conductive line 408 to conductive portion 501. Via VM38 couples conductive portion 501 to conductive line 404 a. Vias VG29 couple conductive line 404a to gate 327. Thus, gate 303 is coupled to gate 327.

Vias VG30-VG31 couple gates 328-329 to conductive line 406. In some embodiments, conductive line 406 also receives a supply voltage VSS for gates 328-329. Vias VG32-33 couple gates 330-331 to conductive line 401. In some embodiments, conductive line 401 also outputs supply voltage VDD to gates 330 and 331.

Vias VD53-VD54 couple conductive patterns 253 and 254 to conductive line 406. In some embodiments, the conductive line 406 also receives a power supply voltage VSS for the conductive patterns 253 and 254. Vias VD55-VD56 couple conductive patterns 255 and 256 to conductive line 401. In some embodiments, the conductive line 401 also outputs the power supply voltage VDD to the conductive patterns 255-256.

As shown in fig. 14, vias VD6 and VD51-VD52 couple conductive patterns 252, 251, and 250, respectively, to conductive line 405 b. Thus, the conductive pattern 251 is coupled to the conductive pattern 252. Meanwhile, vias VD2, VD26, and VD49 couple the conductive patterns 252, 225, and 249 to the conductive line 403b, respectively. Thus, the conductive pattern 252 is coupled to the conductive pattern 249.

Via VD50 couples conductive pattern 248 to conductive line 403 b. Via VM39 couples conductive line 403b to conductive portion 505. Via VM45 couples conductive portion 505 to conductive line 409. The vias VM43 couple the conductive lines 409 to the conductive portions 502. Via VM1 couples conductive portion 502 to conductive line 405 a. Via VD27 couples conductive line 405a to conductive pattern 226. Thus, conductive pattern 248 is coupled to conductive pattern 226.

In contrast to the configuration in fig. 13, the embodiment of fig. 14 also preserves the routing resources of the metal layer in the third layer by not implementing conductive tracks 601 and 602.

The configuration in fig. 14 is for illustrative purposes. The various embodiments in fig. 14 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 401 in FIG. 14 is implemented by the conductive lines 413 and 414 in FIG. 12.

Reference is now made to fig. 15. Fig. 15 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiment of fig. 2A-14, similar elements in fig. 15 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 15.

In contrast to the embodiment shown in FIG. 14, the integrated circuit 100 further includes conductive patterns 252a-252b, gates 332 and 333, and vias VG34-VG36 instead of having gates 313, 327 and 330, conductive lines 404a-404b, conductive portions 501 and 505 and 506, and corresponding structures. With respect to, for example, gate 327 in FIG. 14, gate 322-333 is configured. With respect to, for example, via VG2 in FIG. 3, vias VG34-VG36 are configured.

The conductive pattern 252a corresponds to the source/drain of the transistor M1. The conductive pattern 252b corresponds to the drain/source of the transistor M3. While another portion of the gate 332 disposed over the active regions 110 and 140 is referred to as a dummy gate portion, a portion of the gate 332 disposed over the active region 120 corresponds to the gate of the transistor M4. While another portion of the gate 333 disposed over the active region 140 is referred to as a dummy gate portion, a portion of the gate 333 disposed over the active region 110 corresponds to the gate of the transistor M2. The other conductive patterns and other gate to transistor M1-M4 correspondences in the embodiment shown in fig. 15 are similar to the embodiment shown in fig. 14. Therefore, a repetitive discussion is omitted here.

The gates 332-333 extend in the y-direction and are separated from each other in both the x-direction and the y-direction. Gate 332 passes through active regions 110-120 and gate 333 passes through active regions 110 and 140. In some embodiments, as shown in fig. 3, gate 332 is aligned with gate 328 and gate 333 is aligned with gate 309.

As shown in fig. 15, the conductive line 401 also passes through the gate 332 and 333. The conductive line 403a passes through the conductive patterns 225 and 252a and the gates 301, 318, and 332. The conductive line 403b passes through the conductive pattern 251 and the gates 304 and 333. Conductive line 404c passes through gates 302 and 318. The conductive line 405a passes through the conductive patterns 226 and 249 and the gates 305 and 332. The conductive line 405b passes through the conductive patterns 250 and 251 a and the gates 302 and 303 and 306. Conductive line 409 also passes through gate 332 and 333.

Gates 318 and 302 are coupled to each other through vias VG2, VG18, and conductive line 404 c. Via VG34 couples gate 332 to conductive line 409, and via VG35 couples gate 333 to conductive line 409. Thus, gate 332 is coupled to gate 333.

Vias VG36 couple gates 303 to conductive line 402. In some embodiments, conductive line 402 receives supply voltage VSS for gate 303.

In some embodiments, vias VG34-VG35 overlap active region 140 while vias VG2 and VG18 overlap shallow trench isolation region 710.

Gates 251 and 252a are coupled to each other by vias VD6 and VD51 and conductive line 405 b. Gates 249 and 252b are coupled to each other by vias VD2 and VD49 and conductive line 403 a.

Compared with the configuration in fig. 14, the embodiment shown in fig. 15 also saves the wiring resources of the metal layer in the second layer by not implementing the conductive portions 501 and 505 and 506.

The configuration in fig. 15 is for illustrative purposes. The various embodiments in fig. 15 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 401 in FIG. 15 is implemented by the conductive lines 413 and 414 in FIG. 12.

Reference is now made to fig. 16. Fig. 16 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-15, similar elements in fig. 16 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 16.

In contrast to fig. 13, integrated circuit 100 further comprises a conductive pattern 257 instead of having conductive patterns 202 and 207, conductive portions 502 and 505, conductive tracks 601 and corresponding structures for routing. In some embodiments, the conductive pattern 257 is configured with respect to, for example, the conductive pattern 252 in fig. 15.

In some embodiments, while a portion of the gate 303 disposed over the active region 120 is referred to as a dummy gate, a portion of the gate 303 disposed over the active region 110 corresponds to a gate of the transistor M2. While a portion of the gate 302 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 302 disposed over the active region 120 corresponds to the gate of the transistor M3. While a portion of the gate 302 disposed over the active region 120 is referred to as a dummy gate, a portion of the gate 318 disposed over the active region 110 corresponds to the gate of the transistor M1. While a portion of the gate 327 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 327 disposed over the active region 120 corresponds to a gate of the transistor M4.

In some embodiments, the conductive pattern 225 corresponds to the drain/source of the transistor M1. The conductive pattern 257 corresponds to source/drains of the transistors M1 and M3. The conductive pattern 250 corresponds to the drain/source of the transistor M3. The conductive pattern 248 corresponds to the drain/source of the transistor M2. The conductive pattern 251 corresponds to the source/drain of the transistor M2. The conductive pattern 226 corresponds to the source/drain of the transistor M4. The conductive pattern 249 corresponds to the drain/source of the transistor M4.

As shown in fig. 16, the conductive pattern 257 extends in the y-direction. The conductive pattern 257 is arranged to be interposed between the gates 302 and 318.

The configuration of the metal wiring between the gates 302, 303, 318 and 327 is similar to that of the embodiment shown in fig. 13. Therefore, a repetitive discussion is omitted here.

The conductive patterns 251 and 250 are coupled to each other by vias VD51-VD52 and conductive line 405 b. The conductive patterns 248 and 257 are coupled to each other by vias VD2 and VD50 and conductive line 403 b. The conductive patterns 226 and 257 are coupled to each other by vias VD6 and VD27 and conductive line 405 a. The conductive patterns 225 and 249 are coupled to each other by vias VD26 and VD49 and conductive line 403 a.

Compared to the configuration in fig. 13, the embodiment shown in fig. 16 also conserves routing resources of the metal layers in both the second and third layers by not implementing the conductive portions 502 and 505 and the conductive tracks 601.

The configuration in fig. 16 is for illustrative purposes. The various embodiments in fig. 16 are within the intended scope of the present disclosure. For example, in a lower embodiment, conductive line 410 and/or conductive line 420 are coupled to another cell while abutting the cell shown in the embodiment in fig. 16.

Reference is now made to fig. 17. Fig. 17 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-16, similar elements in fig. 17 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operation of like elements discussed in detail in the above paragraphs is omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 17.

In contrast to the embodiment shown in fig. 15, integrated circuit 100 further includes vias VM46-VM47 and conductive portions 502 and 505. In some embodiments, the vias VM46-VM47 are configured with respect to, for example, via VM 1.

In some embodiments, while a portion of the gate 333 disposed over the active region 140 is referred to as a dummy gate, a portion of the gate 333 disposed over the active region 110 corresponds to a gate of the transistor M2. While a portion of the gate 302 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 302 disposed over the active region 120 corresponds to the gate of the transistor M3. While a portion of the gate 318 disposed over the active region 120 is referred to as a dummy gate, a portion of the gate 318 disposed over the active region 110 corresponds to the gate of the transistor M1. While another portion of the gate 332 disposed over the active regions 110 and 140 is referred to as a dummy gate portion, a portion of the gate 332 disposed over the active region 120 corresponds to the gate of the transistor M4.

In some embodiments, the conductive pattern 225 corresponds to the drain/source of the transistor M1. The conductive pattern 252 corresponds to the source/drain of the transistors M1 and M3. The conductive pattern 250 corresponds to the drain/source of the transistor M3. The conductive pattern 226 corresponds to the source/drain of the transistor M4. The conductive pattern 249 corresponds to the drain/source of the transistor M4. The conductive pattern 248 corresponds to the drain/source of the transistor M2. The conductive pattern 251 corresponds to the source/drain of the transistor M2.

As shown in fig. 17, compared to fig. 15, the conductive line 403a passes through the conductive pattern 225 and the gate 332. The conductive line 403b also passes through the conductive pattern 252 and the gate 302. The conductive line 405b does not pass through the conductive pattern 252a or the gate 302.

To illustrate, via VD2 couples conductive pattern 252 to conductive line 404b, and via VD50 couples conductive pattern 248 to conductive line 403 b. Via VM39 couples conductive line 403b to conductive portion 505. Via VM47 couples conductive portion 505 to conductive line 408. The vias VM46 couple the conductive lines 408 to the conductive portions 502. Via VM1 couples conductive portion 502 to conductive line 405 a. Via VD27 couples conductive line 405a to conductive pattern 226. Thus, conductive patterns 248 and 252 are coupled to conductive pattern 226.

The conductive patterns 250, 251 are coupled to each other by vias VD51-VD52 and conductive line 405 b. The conductive patterns 225 and 249 are coupled to each other by vias VD26 and VD49 and conductive line 403 a.

The configuration in fig. 17 is for illustrative purposes. The various embodiments in fig. 17 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 401 in FIG. 17 is implemented by the conductive lines 413 and 414 in FIG. 12.

Reference is now made to fig. 18. Fig. 18 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-17, similar elements in fig. 18 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 18.

In contrast to the embodiment shown in fig. 17, integrated circuit 100 further includes gates 313 and 330, conductive lines 404a-404b, conductive portions 501 and 503, and vias VG37-VG38, rather than having gate 333, conductive portions 502 and 505, and corresponding structures. With respect to, for example, via VG1 in FIG. 16, vias VG37-VG38 are configured.

While another portion of the gate 303 disposed over the active region 120 is referred to as a dummy gate portion, a portion of the gate 303 disposed over the active region 110 corresponds to the gate of the transistor M1 in some embodiments. While another portion of the gate 302 disposed over the active region 110 is referred to as a dummy gate portion, a portion of the gate 302 disposed over the active region 120 corresponds to the gate of the transistor M3. While another portion of the gate 318 disposed over the active region 120 is referred to as a dummy gate portion, a portion of the gate 318 disposed over the active region 110 corresponds to the gate of the transistor M1. While another portion of the gate 332 disposed over the active region 110 is referred to as a dummy gate portion, a portion of the gate 332 disposed over the active region 120 corresponds to the gate of the transistor M4.

The correspondence between the conductive patterns and the terminals of the transistors M1-M4 in the embodiment shown in fig. 18 is similar to the embodiment shown in fig. 17. Therefore, a repetitive discussion is omitted here.

For illustration, gate 332 is shorted and gate 332 does not overlap active region 140. The gate 303 extends in the y-direction and overlaps the active region 110.

As shown in fig. 18, compared to fig. 17, the conductive line 403a does not pass through the conductive pattern 252 or the gate 318. The conductive line 403b also passes through the conductive pattern 252 and the gate 302. Conductive line 404a passes through gate 332. The conductive line 404c passes through the conductive pattern 251 and the gate electrode 303. The conductive line 405a also passes through the conductive pattern 252 and the gate 318. The conductive line 405b does not pass through the conductive pattern 252 and the gate 302.

The conductive portion 501 overlaps with the conductive patterns 253, 255, and 249 and passes through the conductive lines 401, 403a, 404a, 405a, and 407 and 409. The conductive portion 503 overlaps with the conductive patterns 212, 217, and 251 and passes through the conductive lines 401, 403b, 404b, 405b, and 407 and 409.

Vias VG37-VG38 couple gates 332 and 303, respectively, to conductive line 401, as needed for illustration. In some embodiments, conductive line 401 also outputs supply voltage VDD to gates 332 and 303.

Via VG3 couples gate 303 to conductive line 404 b. Via VM40 couples conductive line 404b to conductive portion 503. Via VM44 couples conductive portion 503 to conductive line 408. Via VM42 couples conductive line 408 to conductive portion 501. Via VM38 couples conductive portion 501 to conductive line 404 b. Vias VG3 couple conductive line 404b to gate 332. Thus, gate 303 is coupled to gate 332.

Vias VD26 and VD49 couple conductive patterns 225 and 249, respectively, to conductive line 403 a. Thus, the conductive pattern 225 is coupled to the conductive pattern 249. Vias VD2 and VD50 couple conductive patterns 248 and 252, respectively, to conductive line 403 b. Thus, the conductive pattern 248 is coupled to the conductive pattern 252. Vias VD27 and VD6 couple conductive patterns 226 and 252, respectively, to conductive line 405 a. Thus, the conductive pattern 226 is coupled to the conductive pattern 252. Vias VD51 and VD52 couple conductive patterns 251 and 250, respectively, to conductive line 405 b. Thus, the conductive pattern 250 is coupled to the conductive pattern 251.

The configuration in fig. 18 is for illustrative purposes. The various embodiments in fig. 18 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 401 in FIG. 18 is implemented by the conductive lines 413 and 414 in FIG. 12.

Reference is now made to fig. 19. Fig. 19 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-18, similar elements in fig. 19 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 19.

In contrast to the embodiment shown in fig. 18, instead of having the conductive patterns 205, 209, 214, 218, 251, the gates 304, 306, 310, 314, the conductive portions 503 and the corresponding structures for wiring, the integrated circuit 100 further comprises conductive patterns 258-. With respect to, for example, the conductive pattern 205 in fig. 14, the conductive pattern 258-. With respect to, for example, gate 302, gate 334-336 is configured. Regarding the through hole VD5 in fig. 16, for example, a through VD57-VD61 is arranged.

While a portion of the gate 302 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 302 disposed over the active region 120 corresponds to a gate of the transistor M3 in some embodiments. While a portion of the gate 318 disposed over the active region 120 is referred to as a dummy gate, a portion of the gate 318 disposed over the active region 110 corresponds to the gate of the transistor M1. While a portion of the gate 332 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 332 disposed over the active region 120 corresponds to a gate of the transistor M4. While another portion of the gate 334 disposed over the active region 130 is referred to as a dummy gate portion, a portion of the gate 334 disposed over the active region 140 corresponds to the gate of the transistor M2.

In some embodiments, the conductive pattern 225 corresponds to the drain/source of the transistor M1. The conductive pattern 252 corresponds to the source/drain of the transistors M1 and M3. The conductive pattern 250 corresponds to the drain/source of the transistor M3. The conductive pattern 226 corresponds to the source/drain of the transistor M4. The conductive pattern 249 corresponds to the drain/source of the transistor M4. The conductive pattern 248 corresponds to the drain/source of the transistor M2. The conductive pattern 216 corresponds to the source/drain of the transistor M2.

For illustration, the conductive pattern 248 extends in the y-direction and overlaps the active regions 110 and 140, compared to fig. 18. The conductive patterns 258 and 261 extend in the y direction. A conductive pattern 258 passes through the active region 110 and is disposed adjacent to the gate 335. A conductive pattern 259 passes through the active region 120 and is disposed adjacent to the gate 336. The conductive pattern 260 passes through the active region 130 and is disposed adjacent to the gate 309. The conductive pattern 261 passes through the active region 140 and is disposed adjacent to the gate 313.

Gate 334-336 extends in the y-direction. The gate 334 passes through the active region 130 and 140 and is disposed to be interposed between the conductive patterns 211 and 216 and 217. In some embodiments, gate 334 is aligned with gate 302 in the y-direction. The gate electrode 335 is disposed adjacent to the conductive pattern 248, and the gate electrode 335 passes through the active region 110. The gate 336 is disposed adjacent to the conductive pattern 250, and the gate 335 passes through the active region 120.

Compared to fig. 18, the conductive line 401 also passes through the conductive pattern 248, and also overlaps with the conductive patterns 258 and 261 and the gate 335. The conductive line 402 also overlaps the conductive pattern 259 and the gate 336. Conductive line 403b passes through conductive patterns 248 and 252 and gates 302 and 336. The conductive line 404b does not pass through any conductive pattern or gate. The conductive line 405b passes through the conductive pattern 250 and the gate 336. Conductive lines 407- ­ 408 also pass through gate 334. The conductive line 409 passes through the conductive pattern 216 and 217 and the gates 313 and 334.

Vias 39 couple gates 334 to conductive lines 408. Via VM42 couples conductive line 408 to conductive portion 501. Via VM38 couples conductive portion 501 to conductive line 404 a. Vias VG29 couple conductive line 404a to gate 332. Thus, gate 334 is coupled to gate 332.

For illustration purposes, vias VG40 couple gates 335 to conductive lines 401. In some embodiments, conductive line 401 also outputs supply voltage VDD to gate 335. Vias VG41 couple gates 336 to conductive line 402. In some embodiments, conductive line 402 also receives supply voltage VSS for gate 336.

Via VD57 couples conductive pattern 260 to conductive line 406. Via VD59 couples conductive pattern 261 to conductive line 401. Via VD60 couples conductive pattern 258 to conductive line 401. Vias VD61 couple conductive pattern 259 to conductive line 402. In some embodiments, conductive line 401 also outputs supply voltage VDD to conductive patterns 258 and 261. The conductive lines 402 and 406 also receive a power supply voltage VSS for the conductive patterns 259-260, respectively.

To illustrate, vias VD58 couple conductive pattern 216 to conductive lines 409. Via VM45 couples conductive line 409 to conductive portion 505. Via VM48 couples conductive portion 505 to conductive line 405 b. Via VD52 couples conductive line 405b to conductive pattern 250. Thus, the conductive pattern 216 is coupled to the conductive pattern 250.

The conductive patterns 225 and 249 are coupled to each other by vias VD26 and VD49 and conductive line 403 a. The conductive patterns 248 and 252 are coupled to each other by vias VD50 and VD2 and conductive line 403 b. The conductive patterns 226 and 252 are coupled to each other by vias VD27 and VD6 and conductive line 405 a.

The embodiment shown in fig. 19 also preserves layout area in integrated circuit 100 by implementing fewer components than the embodiment shown in fig. 18.

The configuration in fig. 19 is for illustrative purposes. The various embodiments in fig. 19 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 401 in FIG. 19 is implemented by the conductive lines 413 and 414 in FIG. 12.

Reference is now made to fig. 20. Fig. 20 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-19, similar elements in fig. 20 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operation of like elements discussed in detail in the above paragraphs is omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 20.

In contrast to the embodiment shown in fig. 20, the integrated circuit 100 further comprises a conductive pattern 262-. With respect to, for example, the conductive pattern 205 in fig. 14, the conductive patterns 262-265 are arranged. With respect to, for example, gate 302, gates 337-339 are configured. Regarding the through hole VD5 in fig. 16, for example, a through VD62-VD65 is arranged. Regarding, for example, the through VM48 in fig. 19, the through VMs 49 to 50 are configured.

While a portion of the gate 302 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 302 disposed over the active region 120 corresponds to a gate of the transistor M3 in some embodiments. While a portion of the gate 318 disposed over the active region 120 is referred to as a dummy gate, a portion of the gate 318 disposed over the active region 110 corresponds to the gate of the transistor M1. While a portion of the gate 334 disposed over the active region 130 is referred to as a dummy gate, a portion of the gate 334 disposed over the active region 140 corresponds to the gate of the transistor M2. While another portion of the gate electrode 337 disposed over the active region 140 is referred to as a dummy gate portion, a portion of the gate electrode 337 disposed over the active region 130 corresponds to the gate electrode of the transistor M4.

In some embodiments, the conductive pattern 225 corresponds to the drain/source of the transistor M1. The conductive pattern 263 corresponds to a source/drain of the transistor M1 and a drain/source of the transistor M2. The conductive pattern 217 corresponds to the source/drain of the transistor M2. The conductive pattern 264 corresponds to the drain/source of the transistor M3. The conductive pattern 265 corresponds to the source/drain of the transistor M3. The conductive pattern 211 corresponds to the drain/source of the transistor M4. The conductive pattern 262 corresponds to the source/drain of the transistor M4.

For illustration, the conductive pattern 262 and 265 extend in the y-direction as compared to fig. 20. The conductive pattern 262 overlaps the active region 130 and 140 and is arranged to be interposed between the gates 307, 311, and 337. The conductive pattern 263 passes through the active regions 110 and 140 and is arranged to be interposed between the gates 302, 318, 334 and 337. The conductive pattern 264 passes through the active region 120 and is arranged to be interposed between the gates 302 and 318. The conductive pattern 265 passes through the active region 110-.

Gate 337 and 339 extend in the y-direction. The gate electrode 337 passes through the active region 130 and 140 and is disposed to be interposed between the conductive patterns 211 and 262 and 263. In some embodiments, gate 337 is aligned in the y-direction with gate 318. The gate electrode 338 is arranged to be interposed between the conductive patterns 217, 258, 261, and 265 and pass through the active regions 110 and 140. The conductive pattern 339 is arranged to be interposed between the conductive patterns 259 and 265 and to pass through the active region 120.

The conductive line 401 also passes through the conductive pattern 263 and the gate 338, and also overlaps with the conductive patterns 217, 262 and 263 and 265 and the gates 318 and 337. The conductive line 402 also overlaps the conductive pattern 264-265 and the gates 318 and 339. The conductive line 403a passes through the conductive patterns 201 and 225 and the gate 301. The conductive line 403b passes through the conductive patterns 263 and 265 and the gates 302 and 338. Conductive line 404a passes through gates 302 and 318. The conductive line 405a passes through the conductive patterns 205, 226, and 264 and 265 and the gates 302, 305, 318, and 339. The conductive line 406 also overlaps the conductive pattern 262-263 and the gate 337. The conductive line 407 also passes through the conductive pattern 263, 263 and the gate 337. Conductive line 408 also passes through gate 334. The conductive line 409a passes through the conductive patterns 215 and 262 and 263 and the gates 311 and 337. The conductive line 409b passes through the conductive patterns 217 and 261 and the gate 338.

The conductive portion 502 overlaps the conductive patterns 225 and 226 and 262 and passes through the conductive lines 401, 403a, 404a, 405a, 407 and 408 and 409 a. The conductive portion 505 overlaps the conductive patterns 212, 217, and 265 and passes through the conductive lines 401, 403b, 405a, 407 and 408, and 409 b.

A via VG41 couples the gate 339 to the conductive line 402. In some embodiments, conductive line 402 also receives a supply voltage VSS for gate 339.

Via VG2 couples gate 302 to conductive line 404a, and via VG18 couples gate 318 to conductive line 404 a. Thus, gate 302 is coupled to gate 318. Via VG3 couples gate 337 to conductive line 408, and via VG39 couples gate 334 to conductive line 408. Thus, gate 337 is coupled to gate 334.

Via VD26 couples conductive pattern 225 to conductive line 403 a. Via VM50 couples conductive line 403a to conductive portion 502. The vias VM49 couple the conductive portions 502 to the conductive lines 407. The via VD63 couples the conductive line 407 to the conductive pattern 211. Thus, the conductive pattern 225 is coupled to the conductive pattern 211.

Vias VD27 and VD6 couple conductive line 405a to conductive portions 226 and 264, respectively. Via VM48 couples conductive line 405a to conductive portion 505. Via VM45 couples conductive portion 505 to conductive line 409 b. Via VD65 couples conductive line 409b to conductive pattern 217. Thus, the conductive patterns 226 and 264 are coupled to the conductive pattern 217.

Vias VD2 and VD50 couple conductive patterns 263 and 265, respectively, to conductive line 403 b. Meanwhile, vias and VD58 and VD62 couple the conductive patterns 263 and 262 to the conductive line 409a, respectively. Accordingly, the conductive patterns 262 and 265 are coupled to each other.

The embodiment shown in fig. 20 also preserves layout area in integrated circuit 100 by implementing fewer components than the embodiment shown in fig. 19.

The configuration in fig. 20 is for illustrative purposes. The various embodiments in fig. 20 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 401 in FIG. 20 is implemented by the conductive lines 413 and 414 in FIG. 12.

Reference is now made to fig. 21. Fig. 21 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiment of fig. 2A-20, similar elements in fig. 21 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 21.

In contrast to the embodiment shown in fig. 21, integrated circuit 100 further comprises conductive lines 408a-408b and conductive portion 507 instead of having conductive lines 403a and 409b and corresponding structures for routing. With respect to, for example, conductive lines 408 of FIG. 21, conductive lines 408a-408b are configured. For example, the conductive portion 507 is disposed in the conductive portion 502.

While a portion of the gate 302 disposed over the active region 110 is referred to as a dummy gate, a portion of the gate 302 disposed over the active region 120 corresponds to a gate of the transistor M3 in some embodiments. While a portion of the gate 318 disposed over the active region 120 is referred to as a dummy gate, a portion of the gate 318 disposed over the active region 110 corresponds to the gate of the transistor M2. While a portion of the gate 334 disposed over the active region 130 is referred to as a dummy gate, a portion of the gate 334 disposed over the active region 140 corresponds to the gate of the transistor M1. While another portion of the gate electrode 337 disposed over the active region 140 is referred to as a dummy gate portion, a portion of the gate electrode 337 disposed over the active region 130 corresponds to the gate electrode of the transistor M4.

In some embodiments, the conductive pattern 225 corresponds to the drain/source of the transistor M2. The conductive pattern 263 corresponds to the drain/source of the transistor 1 and the source/drain of the transistor M2. The conductive pattern 217 corresponds to the source/drain of the transistor M1. The conductive pattern 264 corresponds to the source/drain of the transistor M3. The conductive pattern 265 corresponds to the drain/source of the transistor M3. The conductive pattern 262 corresponds to the drain/source of the transistor M4. The conductive pattern 211 corresponds to the source/drain of the transistor M4.

To illustrate, the conductive portion 507 extends in the y-direction, overlaps the conductive patterns 211 and 263 and 264 and passes through the conductive lines 401, 403b, 405a, 407, and 409 a.

Via VG2 couples gate 302 to conductive line 404 b. Via VM54 couples conductive line 404b to conductive portion 505. Via VM52 couples conductive portion 505 to conductive line 408 b. A via VG39 couples conductive line 408b to gate 334. Thus, gate 302 is coupled to gate 334.

Via VG18 couples gate 318 to conductive line 404 a. Via VM53 couples conductive line 404a to conductive portion 502. Via VM51 couples conductive portion 502 to conductive line 408 a. Via VG3 couples conductive line 408a to gate 337. Thus, gate 318 is coupled to gate 337.

Via VD6 couples conductive pattern 264 to conductive line 405 a. Via VM55 couples conductive line 405a to conductive portion 507. Vias VM56 couple conductive portions 507 to conductive lines 407. The via VD64 couples the conductive line 407 to the conductive pattern 211. Accordingly, the conductive pattern 264 is coupled to the conductive pattern 211.

The conductive patterns 263 and 265 are coupled to each other by vias VD2 and VD50 and conductive line 403 b. The conductive patterns 226 and 264 are coupled to each other by vias VD27 and VD6 and conductive line 405 a. The conductive patterns 262 and 263 are coupled to each other through vias VD62 and VD58 and the conductive line 409 a. The conductive patterns 211 and 212 are coupled to each other through vias VD63-VD64 and conductive line 407.

The configuration in fig. 21 is for illustrative purposes. The various embodiments in fig. 21 are within the intended scope of the present disclosure. For example, in some embodiments, the conductive line 401 in FIG. 21 is implemented by the conductive lines 413 and 414 in FIG. 12.

Reference is now made to fig. 22. Fig. 22 is another layout diagram of a plan view of a portion of integrated circuit 100 corresponding to a portion of fig. 1, in accordance with various embodiments. With respect to the embodiments of fig. 2A-21, similar elements in fig. 22 are assigned the same reference numbers for ease of understanding. For the sake of brevity, specific operations of like elements discussed in detail in the above paragraphs are omitted herein unless needed to introduce a cooperative relationship through the elements shown in fig. 22.

In contrast to the embodiment shown in fig. 2A, the integrated circuit 100 further comprises the conductive pattern 267-. With respect to, for example, the conductive pattern 203, the conductive pattern 267 and 268 are arranged. With respect to, for example, gate 304, gate 340 is configured 343. For example, vias VG42-VG45 are configured for via VG 2. Regarding, for example, the via VM1, the vias VM57-VM60 are configured. Regarding, for example, the through hole VN4, a through hole VN11 is arranged.

The conductive patterns 267 and 268 extend in the y direction and are separated from each other in the x direction. For illustration, a conductive pattern 267 is arranged to be interposed between the gates 304, 306, 341, and 343. The conductive pattern 268 is arranged to be interposed between the gates 301, 305, 340 and 342.

The gates 340-343 extend in the y-direction and are separated from each other in the x-direction. Gate 340-341 passes through active region 110. Gate 342-343 passes through active region 120. The gates 340 and 342 are arranged to be interposed between the conductive patterns 203 and 268. The gates 341 and 343 are arranged to be interposed between the conductive patterns 203 and 267.

The conductive line 403a also passes through the conductive pattern 268 and the gate 340. The conductive line 403b also passes through the conductive pattern 267 and the gate 341. The conductive line 404a passes through the conductive patterns 268 and 267. The conductive line 405a also passes through the conductive pattern 268 and the gate 342. The conductive line 405b also passes through the conductive pattern 267 and the gate 343.

The conductive portion 502 overlaps the conductive pattern 268 and passes through the conductive lines 403a, 404, and 405 a. The conductive portion 503 overlaps the conductive pattern 267 and passes through the conductive lines 403b and 404.

Conductive track 602 overlaps conductive line 404a and passes through conductive lines 203 and 266 and 267.

Vias VG42 and VG44 overlap active region 110 as necessary for illustration. Vias VG43 and VG45 overlap active region 120.

A via VG42 couples gate 340 to conductive line 403 a. Via VM2 couples conductive line 403a to conductive portion 502. The vias VN11 couple the conductive portions 502 to the conductive tracks 602. The vias VN4 couple the conductive tracks 602 to the conductive portions 504. Via VM60 couples conductive portion 504 to conductive line 405 b. A via VG45 couples conductive line 405b to gate 343. Thus, the gate 340 is coupled to the gate 343.

A via VG44 couples gate 341 to conductive line 403 b. Via VM58 couples conductive line 403b to conductive portion 503. Via VM59 couples conductive portion 503 to conductive line 404 a. Via VM57 couples conductive line 404a to conductive portion 501. Via VM1 couples conductive portion 501 to conductive line 405 a. A via VG43 couples conductive line 405a to gate 342. Thus, gate 341 is coupled to gate 342.

In contrast to the embodiment shown in fig. 2A, the embodiment of fig. 22 also preserves the routing resources of the metal layers in the third layer by not implementing conductive tracks 601.

The configuration in fig. 22 is for illustrative purposes. The various embodiments in fig. 22 are within the intended scope of the present disclosure. For example, in a lower embodiment, conductive line 410 and/or conductive line 420 are coupled to another cell while abutting the cell shown in the embodiment in fig. 22.

Reference is now made to fig. 23. Fig. 23 is a flow diagram of a method 2300 of generating a layout design for fabricating the integrated circuit 100, according to some embodiments of the present disclosure. It will be appreciated that additional operations may be provided before, during, and after the process shown in fig. 23, and that some of the operations described below may be replaced or deleted with respect to additional embodiments of the present method 2300. The method 2300 includes operations 2301-2304, and operations 2301-2304 are described below with reference to the integrated circuit 100 shown in FIG. 22.

In operation 2301, gate 340 and gate 341 are disposed through P-type active region 110, and gate 342 and gate 343 are disposed through N-type active region 120.

In operation 2302, conductive lines 403a-403b are arranged through gate 340 and gate 341, respectively, and conductive lines 405a-405b are arranged through gate 342 and gate 343, respectively.

In operation 2303, conductive line 404a is disposed between conductive lines 403a-403b and conductive lines 405a-405b along the y-direction. In some embodiments, gate 340 and gate 341 are located on one side of conductive line 404a, and gate 342 and gate 343 are located on the other side of conductive line 404 a.

In operation 2304, conductive portions 501-504 are disposed through conductive lines 403a-403b, 404a, and 405a-405b, respectively, as shown in FIG. 22.

In some embodiments, gate 341 is coupled to gate 342 by conductive line 403b, conductive portions 501 and 503, conductive line 404a, and conductive line 405 a.

In some embodiments, vias VG42 and VG44 are arranged to be coupled between conductive lines 403a-403b and gates 340-341, and vias VG42 and VG44 overlap active region 110. Vias VG43 and VG45 are arranged to couple between conductive lines 405a-405b and gate 342-343, and vias VG43 and VG45 overlap active region 120.

In some embodiments, the conductive pattern 203 is disposed between the gates 340 and 343. The conductive line 404a passes through the conductive pattern 203. In some embodiments, the conductive pattern 203 corresponds to the sources/drains of the transistors M1 and M3-M4 and the drain/source of the transistor M2. The transistors M1-M4 include gates 340, 341, 343, and 342, respectively.

Reference is now made to fig. 24. Fig. 24 is a flow diagram of a method 2400 of generating a layout design for use in fabricating the integrated circuit 100, according to some embodiments of the present disclosure. It is to be appreciated that additional operations can be provided before, during, and after the process illustrated in fig. 24, and that some of the operations described below can be replaced or deleted with respect to additional embodiments of the present method 2400. The method 2400 includes operations 2401-2405, which are described below with reference to the integrated circuit 100 shown in FIG. 11A as operations 2401-2405.

In operation 2401, as shown in fig. 11A, the active regions 110 and 140 extending in the x direction are formed. In some embodiments, active regions 110 and 120 are included in CELL1 and active regions 130 and 140 are included in CELL 2.

In operation 2402, gates extending in the y-direction are formed, including, for example, gates 303, 306, 308, 310, 319, 320, 324, 326, as shown in FIG. 11A. In some embodiments, conductive patterns extending in the y-direction are formed, including, for example, conductive patterns 240 and 241.

In operation 2403, a via VG23 is formed on the gate 325, a via VG24 is formed on the gate 303, and a via VG25 is formed on the gate 326. Vias VG23-VG25 overlap active regions 130, 110, and 120, respectively, as shown in fig. 11A.

In some embodiments, as shown in fig. 10A, the method 2400 further includes an operation of forming the shallow trench isolation regions 710-730, the shallow trench isolation regions 710-730 extending in the x-direction and being arranged between the active regions 110-140. Method 2400 also includes the operations of forming vias, e.g., forming via VG18 on gate 321 and forming via VG3 on gate 303. Vias VG18 and VG3 overlap shallow trench isolation regions 710 and 720, respectively.

In operation 2404, power rails 414 and 415 are formed that extend in the x-direction. As shown in fig. 11A, power rails 414 and 415 overlap active regions 110 and 120, respectively, and are separated from each other in the y-direction.

In operation 2405, as shown in fig. 11A, conductive lines 403a, 404a, and 405a are formed, the conductive lines 403a, 404a, and 405a extending in the x-direction and being separated from each other in the y-direction. Conductive lines 403a, 404a, and 405a are disposed between conductive lines 414 and 415.

In some embodiments, the method 2400 further includes the operation of forming the power rails 412 and 413, the power rails 412 and 413 extending in the x-direction and being separated from each other in the y-direction. Alternatively, it is stated that the power rails 412 and 415 are separated from each other in the y-direction. Method 2400 also includes an operation of forming conductive lines 407- & 409 disposed between power rails 412 and 413.

In some embodiments, as shown in FIG. 12, for example, method 2400 further includes forming conductive lines 403a-403b without using a mask, the conductive lines 403a-403b being in one metal track and separated from one another. In various embodiments, conductive lines 403a-403b are formed without the use of a shear layer, and forming conductive lines 403a-403b refers to a technique referred to as "metal termination.

Reference is now made to fig. 25. Fig. 25 is a block diagram of an Electronic Design Automation (EDA) system 2500 for designing a layout design of an integrated circuit, in accordance with some embodiments of the present disclosure. The electronic design automation system 2500 is configured to implement one or more operations of the method 2300-2400 disclosed in fig. 23-24, and is further described in conjunction with fig. 1-22. In some embodiments, electronic design automation system 2500 includes an Automatic Place and Route (APR) system.

In some embodiments, electronic design automation system 2500 is a general purpose computing device that includes a hardware processor 2502 and a non-transitory computer readable storage medium 2504. The storage medium 2504 is encoded with, i.e., stores, computer program code (instructions) 2506, i.e., a set of executable instructions, among other uses. Execution of the instructions 2506 by the hardware processor 2502 represents (at least in part) an electronic design automation tool that implements, for example, a portion or all of methods 2300 and 2400.

The processor 2502 is electrically coupled to the computer-readable storage medium 2504 by a bus 2508. Processor 2502 is also electrically coupled to an input/output (I/O) interface 2510 and a preparation tool 2516 via bus 2508. A network interface 2512 is also electrically coupled to the processor 2502 through the bus 2508. The network interface 2512 is connected to a network 2514, thereby enabling the processor 2502 and the computer-readable storage medium 2504 to connect to external elements through the network 2514. Processor 2502 is configured to execute computer program code 2506 encoded in computer-readable storage medium 2504 to make electronic design automation system 2500 available to a portion or all of the processes and/or methods described. In one or more embodiments, the processor 2502 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, Application Specific Integrated Circuit (ASIC), and/or suitable processing unit.

In one or more embodiments, the computer-readable storage medium 2504 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). Computer-readable storage medium 2504 includes, for example, a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium 2504 includes compact disk read-only memory (CD-ROM), read-write compact disk memory (CD-R/W), and/or Digital Video Disks (DVD).

In one or more embodiments, storage medium 2504 storing computer program code 2506 is configured to cause electronic design automation system 2500, where such execution represents (at least in part) an electronic design automation tool, to be available to perform a portion or all of the described processes and/or methods. In one or more embodiments, storage medium 2504 also stores information that assists in performing a portion or all of the described processes and/or methods. In one or more embodiments, the storage medium 2504 stores an integrated circuit layout 2520 of standard cells, including such standard cells disclosed herein, e.g., as included in the integrated circuit 100 discussed above with respect to fig. 1-22.

Electronic design automation system 2500 includes input/output interface 2510. The input/output interface 2510 is coupled to external circuitry. In one or more embodiments, the input/output interface 2510 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for communicating information and commands to the processor 2502.

Electronic design automation system 2500 also includes a network interface 2512 coupled to processor 2502. Network interface 2512 allows electronic design automation system 2500 to communicate with network 2514, which is connected to one or more other computer systems. Network interface 2512 includes a wireless network interface, such as bluetooth, wireless local area network (WIFI), access control (WIMAX), General Packet Radio Service (GPRS), or mobile communications (WCDMA), or a limited network interface, such as ethernet, Universal Serial Bus (USB), or institute of electrical and electronics engineers-2564 (IEEE-2564). In one or more embodiments, some or all of the described processes and/or methods are implemented in two or more systems 2500.

Electronic design automation system 2500 also includes a preparation tool 2516 coupled to processor 2502. Preparation tool 2516 is configured to prepare an integrated circuit, e.g., integrated circuit 100 as shown in fig. 1-22, from the design file processed by processor 2502.

Electronic design automation system 2500 is configured to receive information via input/output interface 2510. Information received via input/output interface 2510 may include one or more instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor 2502. Information is transferred to the processor 2502 via the bus 2508. Electronic design automation system 2500 is configured to receive information related to a User Interface (UI) through input/output interface 2510. This information is stored as design conventions 2522 in the computer readable medium 2504.

In some embodiments, some or all of the described processes and/or methods are executed as a separate software application executed by a processor. In some embodiments, some or all of the described processes and/or methods are performed as software applications of part of an add-on software application. In some embodiments, some or all of the described processes and/or methods are performed as plug-ins to a software application. In some embodiments, some or all of the described processes and/or methods are implemented as software applications of a portion of an electronic design automation tool. In some embodiments, some or all of the described processes and/or methods are implemented as software applications of portion of electronic design automation system 2500. In some embodiments, tools are used, such as may be available from the global electronic design companyOr another suitable layout generation tool, generates a layout diagram that includes standard cells.

In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer readable recording media include, but are not limited to, external/removable and/or internal/built-in storage or memory units, for example, one or more of optical disks such as digital video disks, magnetic disks such as hard disks, semiconductor memories such as read-only memories, random access memories, and memory cards, and the like.

FIG. 26 is a block diagram of an integrated circuit manufacturing system 2600 and an integrated circuit manufacturing flow related thereto according to some embodiments. In some embodiments, integrated circuit manufacturing system 2600 is used to manufacture at least one of: (A) one or more semiconductor masks, or (B) at least one element in a semiconductor integrated circuit layer.

In fig. 26, integrated circuit fabrication system 2600 includes entities, such as design rooms 2620, mask rooms 2630, and integrated circuit fabrication/fabrication plants ("fab") 2650, that interact in design, development, and fabrication cycles and/or services related to the fabrication of integrated circuit device 2660. The entities of the integrated circuit manufacturing system 2600 are connected by a communications network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more other entities. In some embodiments, a single larger company owns two or more of design chamber 2620, mask chamber 2630, and integrated circuit fab/fab 2650. In some embodiments, two or more of design chamber 2620, mask chamber 2630, and integrated circuit fab/fab 2650 coexist in a common facility and use common resources.

Design room (or design team) 2620 generates an integrated circuit design layout 2622. Integrated circuit design layout 2622 includes various geometric patterns, e.g., the integrated circuit layout design shown in fig. 1-22, designed for integrated circuit device 2660, e.g., integrated circuit 100 discussed above with respect to fig. 1-22. The geometric pattern corresponds to the pattern of the metal, oxide, or semiconductor layers that make up the various elements of the integrated circuit device 2660 to be fabricated. The various layers combine to form various integrated circuit components. For example, a portion of integrated circuit design layout 2622 includes various integrated circuit components to be formed on a semiconductor substrate (such as a silicon wafer), such as active regions of inter-layer interconnects, gate electrodes, source and drain, conductive portions or vias, and various metal layers disposed on the semiconductor substrate. Design chamber 2620 performs appropriate design processes to form an integrated circuit design layout 2622. The design process includes one or more of a logical design, a physical design, or a placement and routing. The integrated circuit design layout 2622 resides in one or more data files having information of the geometric pattern. For example, the integrated circuit design layout 2622 may be expressed in a layout data (GDSII) file format or a DFII file format.

Mask chamber 2630 includes data preparation 2632 and mask preparation 2644. Mask chamber 2630 manufactures one or more masks 2645 using integrated circuit design layout 2622 for manufacturing the various layers of integrated circuit device 2660 according to integrated circuit design layout 2622. The mask chamber 2630 performs mask data preparation 2632 in which the integrated circuit design layout 2622 is translated into a representation data file ("RDF"). Mask data preparation 2632 provides mask preparation 2644 with a representative data file. Mask preparation 2644 includes a mask writer. The mask writer converts the representative data file into an image on a substrate, such as a mask (reticle) 2645 or a semiconductor wafer 2653. The integrated circuit design layout 2622 is manipulated by mask data preparation 2632 to comply with the specific performance of the mask writer and/or the requirements of the integrated circuit fab/fab 2650. In fig. 26, data preparation 2632 and mask preparation 2644 are shown as single elements. In some embodiments, data preparation 2632 and mask preparation 2644 can be collectively referred to as mask data preparation.

In some embodiments, data preparation 2632 includes Optical Proximity Correction (OPC) that uses lithographic enhancement techniques to compensate for image distortions such as those caused by diffraction, interference, and other process effects, among others. Optical proximity correction tuning integrated circuit design layout 2622. In some embodiments, data preparation 2632 also includes Resolution Enhancement Techniques (RET), such as off-axis illumination, resolution assist patterns, phase shift masks, and other suitable techniques, and the like or combinations thereof. In some embodiments, Inverse Lithography (ILT) is also used, which treats optical proximity correction as an inverse imaging problem.

In some embodiments, data preparation 2632 includes a Mask Rule Checker (MRC) that checks integrated circuit design layout 2622 with a set of mask creation rules, the integrated circuit design layout 2622 having experienced processes in optical proximity correction, the set of mask creation rules containing certain geometric and/or connectivity constraints to ensure sufficient space, account for variability in semiconductor manufacturing processes, and so forth. In some embodiments, the mask rules checker modifies the integrated circuit design layout 2622 to compensate for limitations of the mask preparation device, which may undo a portion of the modifications performed by the optical proximity correction to satisfy mask creation rules.

In some embodiments, data preparation 2632 includes photolithography process inspection (LPC), which simulates the process to be performed by integrated circuit fab/fab 2650 to fabricate integrated circuit device 2660. The photolithography process check simulates the process based on integrated circuit design layout 2622 to create a simulated fabricated device, such as integrated circuit device 2660. The processing parameters in the lithography process inspection simulation may include parameters associated with various processes of an integrated circuit manufacturing cycle, parameters associated with a tool used to manufacture the integrated circuit, and/or other aspects of the manufacturing process. The photolithography process inspection takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), and other suitable factors, among others or a combination thereof. In some embodiments, after the created simulated fabricated device has been inspected by a lithography process, if the simulated device is not close enough in shape to satisfy the design rules, the optical proximity correction and/or mask rule checker is repeated to further refine the integrated circuit design layout 2622.

It should be appreciated that the foregoing description of data preparation 2632 has been simplified for purposes of brevity. In some embodiments, data preparation 2632 includes additional components, such as Logic Operations (LOPs), to modify integrated circuit design layout 2622 according to manufacturing rules. In addition, the processes applied to integrated circuit design layout 2622 during data preparation 2632 may be performed in a variety of different orders.

After data preparation 2632 and during mask preparation 2644, a mask 2645 or a set of masks 2645 are prepared based on integrated circuit design layout 2622. In some embodiments, mask preparation 2644 includes performing one or more lithographic exposures based on integrated circuit design layout 2622. In some embodiments, an electron beam (e-beam) or multiple electron beam mechanism is used to pattern a mask (photomask or reticle) 2645 based on the modified integrated circuit design layout 2622. Mask 2645 may be formed in various techniques. In some embodiments, mask 2645 is formed using a binarization technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) that has been coated on the wafer is blocked by and transmitted through the opaque regions. In one example, the binary reticle of mask 2645 essentially comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque regions of the binary mask. In another example, mask 2645 is formed using a phase-shift technique. In a Phase Shift Mask (PSM) version of mask 2645, the various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask may be an attenuated phase shift mask or an alternating phase shift mask. Mask preparation 2644 generates one or more masks for use in various processes. Such one or more masks are used, for example, in an ion implantation process to form various doped regions in semiconductor wafer 2653, in an etching process to form various etched regions in semiconductor wafer 2653, and/or in other suitable processes.

The ic fab/fab 2650 includes wafer preparation 2652. Integrated circuit fab/fab 2650 prepares services for integrated circuits that include one or more manufacturing facilities for preparing a variety of different integrated circuit products. In some embodiments, integrated circuit fab/fab 2650 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) preparation of a plurality of integrated circuit products, while a second manufacturing facility may provide back-end-of-line (BEOL) preparation for interconnection and packaging of integrated circuit products, and a third manufacturing facility may provide other services for foundry business.

Integrated circuit fab/fab 2650 uses one or more masks 2645 prepared by mask chamber 2630 to prepare integrated circuit devices 2660. Thus, integrated circuit fab/fab 2650 at least indirectly uses integrated circuit design layout 2622 to fabricate integrated circuit device 2660. In some embodiments, semiconductor wafers 2653 are prepared by an integrated circuit fab/fab 2650 using one or more masks 2654 to form integrated circuit devices 2660. In some embodiments, integrated circuit fabrication includes performing one or more lithographic exposures based at least indirectly on the integrated circuit design layout 2622. Semiconductor wafer 2653 comprises a silicon substrate or other suitable substrate having a plurality of material layers formed thereon. The semiconductor wafer 2653 also includes one or more of various doped regions, dielectric features, and multi-layer interconnects, among others, formed in subsequent fabrication steps.

As described above, the integrated circuit in the present disclosure provides a reduced layout arrangement by including three parallel conductive lines between two power rails, and further includes a reduced layout area compared to some approaches.

In some embodiments, an integrated circuit is disclosed that includes a first pair of power rails extending in a first direction in a first layer and separated from each other in a second direction different from the first direction; a set of conductive lines arranged in the first layer in parallel with the first pair of power rails and arranged in three metal tracks between the first pair of power rails; a first group of active regions extending in a first direction and separated from each other in a second direction; a first gate arranged in a second layer different from the first layer along a second direction while passing through the first group of active regions in a layout view, wherein the first gate is configured to be shared by a first transistor belonging to the first type and a second transistor belonging to the second type; and second and third gates extending parallel to the first gate in the second direction and arranged in the second layer, wherein the second gate is configured as a control terminal of a third transistor and the third gate is configured as a control terminal of a fourth transistor, the control terminal of the fourth transistor being coupled to the control terminal of the third transistor. In some embodiments, the second gate and the third gate are two portions of a continuous gate structure; wherein the integrated circuit further comprises Shallow Trench Isolation (STI) regions extending in the first direction and arranged between the first set of active regions; and a set of gate vias coupled between the first gate, the gate structure, and the set of conductive lines, wherein the set of gate vias overlaps the shallow trench isolation region. In some embodiments, the integrated circuit further comprises shallow trench isolation regions extending in the first direction and arranged between the first set of active regions; and a set of gate vias coupled between the first gate, the second gate, the third gate, and the set of conductive lines, wherein the set of gate vias overlaps the shallow trench isolation region. In some embodiments, the integrated circuit further comprises a second power rail disposed in the first layer between the first pair of power rails; and a second set of active regions extending in the first direction and arranged between the second power rail and one of the first pair of power rails; wherein the second gate and the third gate are two parts of a continuous gate structure and pass through the second set of active regions in a layout view, and the gate structure and the first gate are separated from each other in the second direction; wherein the second power rail overlaps the first gate and the gate structure. In some embodiments, the integrated circuit further comprises a shallow trench isolation region extending in the first direction and arranged between the first set of active regions and the second set of active regions; and a set of gate vias coupled between the first gate, the gate structure, and the set of conductive lines, wherein the set of gate vias overlaps the shallow trench isolation region; wherein the first gate further passes through the second set of active regions and the shallow trench isolation regions, and the gate structure further passes through the first set of active regions and the shallow trench isolation regions. In some embodiments, the integrated circuit further comprises a second power rail disposed in the first layer between the first pair of power rails; wherein the second gate and the third gate are located on opposite sides of the second power rail. In some embodiments, the integrated circuit further includes a set of gate vias coupled between the first gate, the second gate, the third gate, and the set of conductive lines, wherein the set of gate vias overlaps one of the first set of active regions. In some embodiments, the first pair of power rails, the set of conductive lines, and the first set of active regions are included in a first cell. The integrated circuit further includes a second cell having a second set of active regions parallel to the first set of active regions; a second pair of power rails disposed adjacent to one of the first pair of power rails and separated from each other in a second direction; and a further set of conductive lines arranged in three tracks between the second pair of power rails. The second pair of power rails passes through the first gate, the second gate, the third gate, or a combination thereof in the layout view.

Also disclosed is an integrated circuit comprising first to fourth transistors, each of the first to fourth transistors comprising a gate, wherein the gates in the first to fourth transistors extend in a first direction and are separated from each other in a second direction different from the first direction; a plurality of power rails extending in a second direction and separated from each other in a first direction; and a second group of conductive lines extending in the second direction, wherein the second group of conductive lines are arranged between the power rails and are separated from each other in the first direction. The integrated circuit further includes a shallow trench isolation region extending in the second direction and disposed between the power rails, and a plurality of gate vias disposed on the gates of the first through fourth transistors. At least two of the gate vias overlap the shallow trench isolation region. In some embodiments, the integrated circuit further comprises a second set of conductive lines extending in the second direction and separated from each other in the first direction, wherein the set of first conductive lines is arranged in a first area and the second set of conductive lines is arranged in a second area, the second area being located on an opposite side of the first area with respect to the first one of the power rails. In some embodiments, the first set of conductive lines and the second set of conductive lines are arranged in three tracks in the second region. In some embodiments, the gate of the third transistor and the gate of the fourth transistor pass through the first region and the second region. In some embodiments, the gate of the third transistor and the gate of the fourth transistor are coupled together by one of a second set of conductive lines. In some embodiments, at least one of the first to fourth transistors and other of the first to fourth transistors are arranged on opposite sides of a first rail of the power rails; wherein a first rail of the power rails overlaps gates of the first to fourth transistors in a layout view. In some embodiments, two of the first to fourth transistors arranged in the first region are configured as a first pair of complementary transistors, and the other two of the first to fourth transistors arranged in the second region different from the first region are configured as a second pair of complementary transistors; wherein the first and second regions are located on opposite sides of a first one of the power rails. In some embodiments, the integrated circuit further comprises a plurality of active regions included in the first to fourth transistors, wherein at least two of the gate vias overlap one of the active regions.

Also disclosed is a method comprising the operations of: forming a plurality of active regions extending in a first direction; forming a plurality of gates extending in a second direction different from the first direction; forming a second gate through hole group on the gate, wherein the second gate through hole group is overlapped with the active region; forming a first pair of power rails extending in a first direction, overlapping the gate and separated from each other in a second direction; and forming a set of second conductive lines arranged in the three metal tracks between the first pair of power rails. In some embodiments, the method further comprises forming a plurality of shallow trench isolation regions extending in the first direction and arranged between the active regions; and forming a second set of gate vias over the gate, wherein the second set of gate vias overlaps the shallow trench isolation region. In some embodiments, the method further comprises forming a second pair of power rails adjacent to the first pair of power rails; and forming a second set of conductive lines arranged in the three tracks between the second pair of power rails. The first pair of power supplies and the second pair of power rails are included in different cells in the integrated circuit. In some embodiments, forming the second set of conductive lines includes forming two conductive lines separated from each other in one of the three metal tracks without using a mask.

The components of several embodiments are discussed above so that one of ordinary skill in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.