阅读说明：本技术 驱动基板、其制备方法、显示面板组件及电子设备 (Drive substrate, preparation method thereof, display panel assembly and electronic equipment ) 是由 左鸿阳 于 2021-06-25 设计创作，主要内容包括：本申请提供一种驱动基板、其制备方法、显示面板组件及电子设备。所述驱动基板包括：第一薄膜晶体管,所述第一薄膜晶体管包括第一有源层,所述第一有源层包括锌锡氧化物层；以及第二薄膜晶体管,所述第二薄膜晶体管与所述第一薄膜晶体管间隔设置且电连接,所述第二薄膜晶体管包括第二有源层,所述第二有源层包括低温多晶硅层。本申请实施例的驱动基板采用锌锡氧化物替代铟镓锌氧化物作为有源层,成本低且不污染环境。(The application provides a driving substrate, a manufacturing method thereof, a display panel assembly and an electronic device. The driving substrate includes: a first thin film transistor comprising a first active layer comprising a zinc tin oxide layer; and a second thin film transistor disposed at an interval from and electrically connected to the first thin film transistor, the second thin film transistor including a second active layer, the second active layer including a low temperature polysilicon layer. The driving substrate of the embodiment of the application adopts zinc-tin oxide to replace indium-gallium-zinc oxide as an active layer, is low in cost and does not pollute the environment.)

1. A drive substrate, comprising:

a first thin film transistor comprising a first active layer comprising a zinc tin oxide layer; and

and the second thin film transistor is arranged at an interval with the first thin film transistor and is electrically connected with the first thin film transistor, the second thin film transistor comprises a second active layer, and the second active layer comprises a low-temperature polycrystalline silicon layer.

2. The driving substrate of claim 1, wherein the first thin film transistor further comprises a first gate dielectric layer, the first gate dielectric layer is disposed on the surface of the first active layer, and the thickness of the first gate dielectric layer is 130nm to 150 nm.

3. The driving substrate of claim 2, wherein the first thin film transistor is of a bottom-gate structure or a dual-gate structure, and further comprising a first gate electrode disposed on a surface of the first gate dielectric layer away from the first active layer, wherein a roughness of the surface of the first gate dielectric layer close to the first active layer is 0.1nm to 1 nm.

4. The driving substrate as claimed in claim 3, wherein when the first thin film transistor is a dual gate structure, the first thin film transistor further comprises a second gate dielectric layer; the second gate dielectric layer is arranged on the surface, far away from the first gate dielectric layer, of the first active layer, and comprises a first sub-gate dielectric layer and a second sub-gate dielectric layer which are arranged in a stacked mode; the first sub-gate dielectric layer is arranged close to the first active layer compared with the second sub-gate dielectric layer, and the compactness of the first sub-gate dielectric layer is smaller than that of the second sub-gate dielectric layer.

5. The drive substrate of claim 1, wherein the zinc-tin oxide layer comprises zinc oxide and tin oxide in a molar ratio of 1.5: 1to 2.5: 1.

6. The manufacturing method of the driving substrate is characterized in that the driving substrate comprises thin film transistors arranged in an array mode, each thin film transistor comprises a first grid electrode, a first grid dielectric layer and a first active layer, the first grid dielectric layer is arranged on the surface of the first grid electrode, and the first active layer is arranged on the surface, far away from the first grid electrode, of the first grid dielectric layer and corresponds to the first grid electrode; the method comprises the following steps:

preparing a first grid;

depositing a first gate dielectric layer on the surface of the first gate, wherein the deposition speed of the first gate dielectric layer is 0.1nm/s to 0.5 nm/s; and

and depositing a semiconductor layer on the surface of the first grid dielectric layer far away from the first grid electrode, and etching the semiconductor layer to form a first active layer, wherein the first active layer comprises a zinc-tin oxide layer.

7. The method for manufacturing the driving substrate according to claim 6, wherein the first gate dielectric layer is a silicon dioxide layer, and a raw material composition of the first gate dielectric layer comprises SiH₄And N₂O, the SiH₄The flow rate of (1) is 15sccm to 25sccm, the N₂The flow rate of O is 60sccm to 120sccm, and the SiH₄And said N₂The flow ratio of O ranges from 1:4 to 1: 6; the deposition temperature of the first gate dielectric layer is 300-350 ℃.

8. The method for manufacturing the driving substrate according to claim 6, wherein the thin film transistor is of a bottom-gate structure or a dual-gate structure, and after a deposited semiconductor layer is formed on a surface of the first gate dielectric layer away from the first gate electrode, and before the semiconductor layer is etched to form a first active layer, the method further comprises:

carrying out vacuum annealing on the semiconductor layer, wherein the temperature of the vacuum annealing is 300-350 ℃, and the time of the vacuum annealing is 50-70 min;

after the etching is performed on the semiconductor layer to form the first active layer, the method further includes:

and carrying out oxygen annealing at the temperature of 300-350 ℃ for 3-6 h.

9. The method for manufacturing a driving substrate according to claim 7, wherein when the thin film transistor has a dual gate structure, the thin film transistor further comprises a second gate dielectric layer and a second gate electrode; the second gate dielectric layer is arranged on the surface of the first active layer far away from the first gate, the second gate is arranged on the surface of the second gate dielectric layer far away from the first gate and corresponds to the first active layer, and the method further comprises the following steps:

depositing a second gate dielectric layer on the surface of the first active layer far away from the first gate;

forming a second gate layer on the surface of the second gate dielectric layer far away from the first gate, and patterning the second gate layer and the second gate dielectric layer in sequence to form a second gate and expose the area of the first active layer corresponding to the first source and the first drain;

carrying out plasma treatment on the regions of the first active layer corresponding to the first source electrode and the first drain electrode; and

and forming a passivation layer on the surface of the second grid electrode, which is far away from the first grid electrode, and etching the passivation layer.

10. The method of manufacturing a driving substrate according to claim 8 or 9, wherein the thin film transistor further includes a first source electrode and a first drain electrode, the first source electrode and the first drain electrode are disposed in an insulated manner and are electrically connected to the first active layer, respectively, and the method further includes:

and forming a first source electrode and a first drain electrode on one side of the first active layer far away from the first grid electrode.

11. The manufacturing method of the driving substrate is characterized in that the driving substrate comprises thin film transistors which are arranged in an array mode, wherein each thin film transistor comprises a substrate, a second grid electrode, a second grid dielectric layer, a first active layer, a first source electrode and a first drain electrode; the first active layer is arranged on one side of the substrate, the second gate dielectric layer is arranged on the surface, far away from the substrate, of the first active layer, and the second gate electrode is arranged on the surface, far away from the first active layer, of the second gate dielectric layer; the first source electrode and the first drain electrode are arranged at intervals and are respectively and electrically connected with the first active layer; the method comprises the following steps:

forming a semiconductor layer on one side of a substrate, and etching to form a first active layer;

performing plasma treatment on the first active layer;

depositing a second gate dielectric layer on the surface of the first active layer far away from the substrate;

carrying out oxygen annealing treatment;

forming a second gate layer on the surface of the second gate dielectric layer, which is far away from the substrate, and sequentially patterning the second gate layer and the second gate dielectric layer to form a second gate and expose the area of the first active layer, which corresponds to the first source and the first drain;

carrying out plasma treatment on the regions of the first active layer corresponding to the first source electrode and the first drain electrode;

forming a passivation layer on the surface of the second grid electrode, which is far away from the substrate, and etching the passivation layer; and

and forming a first source electrode and a first drain electrode on the surface of the passivation layer far away from the first grid electrode.

12. A display panel assembly, comprising:

the driving substrate of any one of claims 1to 5; and

and the display layer is electrically connected with the driving substrate and is driven by the driving substrate to display contents.

13. An electronic device, comprising:

the shell is provided with an accommodating space;

the display panel assembly of claim 12, for displaying and sealing the receiving space; and

and the circuit board assembly is arranged in the accommodating space, is electrically connected with the display panel assembly and is used for controlling the display panel assembly to display contents.

Technical Field

The application relates to the field of electronics, in particular to a driving substrate, a manufacturing method thereof, a display panel assembly and electronic equipment.

Background

The current indium gallium zinc oxide thin film transistor (IGZO thin film transistor) has less leakage, can ensure stability at a low refresh rate, and has low power consumption, and thus, is commonly used in a driving substrate of a display panel. However, the IGZO thin film transistor needs to be manufactured by using gallium as a raw material, so that the manufactured thin film transistor is expensive, and indium, which is toxic and causes serious environmental pollution, is also used as a raw material.

Disclosure of Invention

In view of the above problems, embodiments of the present application provide a driving substrate that uses zinc tin oxide instead of indium gallium zinc oxide as an active layer, and is low in cost and does not pollute the environment.

The embodiment of the present application provides a driving substrate, which includes: a first thin film transistor comprising a first active layer comprising a zinc tin oxide layer; and a second thin film transistor disposed at an interval from and electrically connected to the first thin film transistor, the second thin film transistor including a second active layer, the second active layer including a low temperature polysilicon layer.

The embodiment of the application also provides a preparation method of the driving substrate, wherein the driving substrate comprises thin film transistors arranged in an array manner, each thin film transistor comprises a first grid electrode, a first grid dielectric layer and a first active layer, the first grid dielectric layer is arranged on the surface of the first grid electrode, and the first active layer is arranged on the surface, far away from the first grid electrode, of the first grid dielectric layer and corresponds to the first grid electrode; the method comprises the following steps:

preparing a first grid;

depositing a first gate dielectric layer on the surface of the first gate, wherein the deposition speed of the first gate dielectric layer is 0.1nm/s to 0.5 nm/s; and

and depositing a semiconductor layer on the surface of the first grid dielectric layer far away from the first grid electrode, and etching the semiconductor layer to form a first active layer, wherein the first active layer comprises a zinc-tin oxide layer.

The embodiment of the application also provides a preparation method of the driving substrate, wherein the driving substrate comprises thin film transistors arranged in an array manner, and the thin film transistors comprise substrates, second grid electrodes, second grid dielectric layers, first active layers, first source electrodes and first drain electrodes; the first active layer is arranged on one side of the substrate, the second gate dielectric layer is arranged on the surface, far away from the substrate, of the first active layer, and the second gate electrode is arranged on the surface, far away from the first active layer, of the second gate dielectric layer; the first source electrode and the first drain electrode are arranged at intervals and are respectively and electrically connected with the first active layer; the method comprises the following steps:

forming a semiconductor layer on one side of a substrate, and etching to form a first active layer;

performing plasma treatment on the first active layer;

depositing a second gate dielectric layer on the surface of the first active layer far away from the substrate;

carrying out oxygen annealing treatment;

forming a second gate layer on the surface of the second gate dielectric layer, which is far away from the substrate, and sequentially patterning the second gate layer and the second gate dielectric layer to form a second gate and expose the area of the first active layer, which corresponds to the first source and the first drain;

carrying out plasma treatment on the regions of the first active layer corresponding to the first source electrode and the first drain electrode;

forming a passivation layer on the surface of the second grid electrode, which is far away from the substrate, and etching the passivation layer; and

and forming a first source electrode and a first drain electrode on the surface of the passivation layer far away from the first grid electrode.

An embodiment of the present application further provides a display panel assembly, which includes:

the driving substrate according to the embodiment of the present application; and

and the display layer is electrically connected with the driving substrate and is driven by the driving substrate to display contents.

An embodiment of the present application provides an electronic device, which includes:

the shell is provided with an accommodating space;

the display panel assembly is used for displaying and sealing the accommodating space; and

and the circuit board assembly is arranged in the accommodating space, is electrically connected with the display panel assembly and is used for controlling the display panel assembly to display contents.

The low-temperature polycrystalline silicon oxide driving substrate does not contain toxic element indium, can reduce pollution to the environment during preparation, does not need to use metal gallium, has lower cost, and simultaneously has stable low refresh rate, lower power consumption and low electric leakage performance.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a driving substrate according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of a first thin film transistor according to an embodiment of the present application.

Fig. 3 is a schematic structural diagram of a first thin film transistor according to yet another embodiment of the present application.

Fig. 4 is a schematic flow chart illustrating a manufacturing process of a driving substrate according to an embodiment of the present disclosure.

Fig. 5 is a schematic flow chart illustrating a process for manufacturing a driving substrate according to another embodiment of the present disclosure.

Fig. 6 is a schematic flow chart illustrating a process for manufacturing a driving substrate according to another embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram of a thin film transistor according to an embodiment of the present application.

Fig. 8 is a schematic flow chart illustrating a process for manufacturing a driving substrate according to another embodiment of the present disclosure.

Fig. 9 is a schematic structural diagram of a display panel assembly according to an embodiment of the present application.

Fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Fig. 11 is a circuit block diagram of an electronic device according to an embodiment of the present application.

Description of reference numerals:

100-drive substrate 31-second active layer

101-substrate 33-third gate

10-first thin film transistor 35-third gate dielectric layer

11-first active layer 37-second source electrode

12-second gate dielectric layer 39-second drain

121-first sub-gate dielectric layer 600-display panel assembly

123-second sub-gate dielectric layer 610-display layer

13-first gate 700-electronics

14-second grid 710-housing

15-first gate dielectric layer 701-accommodating space

17-first source 730-circuit board assembly

19-first drain 731-processor

30-second thin film transistor 733-memory

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

It should be noted that, for convenience of description, like reference numerals denote like parts in the embodiments of the present application, and a detailed description of the like parts is omitted in different embodiments for the sake of brevity.

The low-temperature polycrystalline oxide (LTPO) driving substrate of the related art includes a low-temperature polycrystalline silicon thin film transistor (LTPS thin film transistor for short) and an indium gallium zinc oxide thin film transistor (IGZO thin film transistor for short), however, the indium gallium zinc oxide thin film transistor is expensive, the raw material gallium is a rare metal, the earth storage amount is low, indium is a toxic element, and the environmental pollution is great in the preparation process.

Referring to fig. 1, an embodiment of the present application provides a driving substrate 100, which includes: a first thin film transistor 10, the first thin film transistor 10 including a first active layer 11, the first active layer 11 including a zinc tin oxide layer; and a second thin film transistor 30, the second thin film transistor 30 being disposed at an interval from and electrically connected to the first thin film transistor 10, the second thin film transistor 30 including a second active layer 31, the second active layer 31 including a low temperature polysilicon layer.

Alternatively, the driving substrate 100 may be, but is not limited to, a low temperature poly oxide driving substrate 100 (LTPO driving substrate).

Alternatively, the first thin film transistor 10 may be, but is not limited to, an amorphous metal oxide thin film transistor, such as a zinc-tin oxide thin film transistor (ZTO thin film transistor for short). The first thin film transistor 10 may be, but is not limited to, one or more of a top-gate structure, a bottom-gate structure, or a double-gate structure. The number of the first thin film transistors 10 may be one or more, and the present application is not particularly limited.

Alternatively, the second thin film transistor 30 may be, but is not limited to, a low temperature polysilicon thin film transistor (LTPS thin film transistor for short). The second thin film transistor 30 may be, but is not limited to, one or more of a top-gate structure, a bottom-gate structure, or a double-gate structure. The number of the second thin film transistors 30 may be one or more, and the present application is not particularly limited. When the first thin film transistor 10 and the second thin film transistor 30 are both plural, a part of the first thin film transistor 10 may be electrically connected to the second thin film transistor 30, a part of the first thin film transistor 10 may be electrically connected to the first thin film transistor 10, and a part of the second thin film transistor 30 may be electrically connected to the second thin film transistor 30.

The driving substrate 100 of the embodiment of the present application includes a first thin film transistor 10, the first thin film transistor 10 including a first active layer 11, the first active layer 11 including a zinc-tin oxide layer; and a second thin film transistor 30, the second thin film transistor 30 being disposed at an interval from and electrically connected to the first thin film transistor 10, the second thin film transistor 30 including a second active layer 31, the second active layer 31 including a low temperature polysilicon layer. Therefore, compared with the driving substrate 100 including an IGZO thin film transistor, the low-temperature polycrystalline silicon oxide driving substrate 100 of the embodiment of the present application does not include a toxic element indium, so that environmental pollution during preparation can be reduced, metal gallium does not need to be used, the cost is lower, and meanwhile, the low-temperature polycrystalline silicon oxide driving substrate has a stable low refresh rate, lower power consumption and low leakage performance.

Alternatively, the first active layer 11 may be prepared by using radio frequency magnetron sputtering, and the thickness of the first active layer 11 is 38nm to 42 nm; specifically, it may be, but not limited to, 38nm, 39nm, 40nm, 41nm, 42nm, etc. When the first active layer 11 is too thick, the sub-threshold slope (SS) of the first thin film transistor 10 is caused to increase (the larger the SS, the more disadvantageous), and when the first active layer 11 is too thin, the carrier mobility of the first thin film transistor 10 is caused to decrease.

Optionally, the zinc tin oxide layer comprises zinc oxide and tin oxide in a molar ratio of 1.5: 1to 2.5: 1; specifically, there may be, but are not limited to, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2: 1. 2.1:1, 2.2:1, 2.3:1, 2.4:1, 2.5:1, etc. When the molar ratio of the zinc oxide to the tin oxide is higher than 2.5:1, the carrier mobility of the ZTO thin film transistor is increased, but the ZTO thin film transistor has poor stability, poor switching characteristics, and is prone to electric leakage; when the molar ratio of the zinc oxide to the tin oxide is less than 1.5:1, the carrier mobility of the ZTO thin film transistor is reduced, the switching current becomes small, and the ZTO thin film transistor cannot be turned on. Alternatively, the molar ratio of zinc oxide to tin oxide is 2:1, and when the molar ratio of zinc oxide to tin oxide is within this range, the first active layer 11 is formed to be the most dense, the internal defects are the least, and the performance of the resulting ZTO thin film transistor is the best.

Referring to fig. 2, in some embodiments, the first thin film transistor 10 further includes a substrate 101, a first gate 13, a first gate dielectric layer 15, a first source 17, and a first drain 19; the first gate 13 is arranged on one side of the substrate 101 and used for accessing a gate signal; the first gate dielectric layer 15 is disposed on a surface of the first gate 13, the first active layer 11 is disposed on a surface of the first gate dielectric layer 15 away from the first gate 13 and is disposed corresponding to the first gate 13, the first source 17 and the first drain 19 are disposed on a side of the first active layer 11 away from the substrate 101, the first source 17 and the first drain 19 are disposed at an interval and are electrically connected to the first active layer 11, respectively, the first source 17 or the first drain 19 is electrically connected to the second thin film transistor 30, the first source 17 is used for accessing a low level, and the first drain 19 is used for accessing a high level. The term "corresponding" in this application means that the orthographic projections of two parts on the substrate 101 at least partly overlap, e.g. completely coincide, or partly coincide, or that the orthographic projection of one falls within the orthographic projection of the other.

Optionally, the substrate 101 may include, but is not limited to including, one or more of gallium arsenide, gallium nitride, silicon dioxide, and the like.

Alternatively, the first gate 13 may include, but is not limited to, one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), gold (Au), and the like, which is not particularly limited in the present application. In the embodiment of the present application, the first gate 13 is a molybdenum electrode.

Optionally, the thickness of the first gate 13 is 140nm to 280 nm; specifically, it may be, but not limited to, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 240nm, 260nm, 270nm, 180nm, etc. When the first gate 13 is too thin, gate leakage current increases and breakdown easily occurs, and when the first gate 13 is too thick, carrier mobility decreases and sub-threshold slope stability deteriorates.

Optionally, the first gate dielectric layer 15 may be, but is not limited to, one or more of silicon dioxide, titanium dioxide, and the like, and the application is not particularly limited.

Optionally, the thickness of the first gate dielectric layer 15 is 130nm to 150 nm; specifically, it may be, but not limited to, 130nm, 133nm, 135nm, 138nm, 140nm, 142nm, 145nm, 148nm, 150nm, etc. When the thickness of the first gate dielectric layer 15 is within this range, the conduction band of the first active layer 11 can be sufficiently bent, so that the partial pressure of the first gate dielectric layer 15 on the first gate electrode 13 is reduced, and the reduction of the roughness of the surface of the first gate dielectric layer 15 close to the first active layer 11 is facilitated. When the thickness of the first gate dielectric layer 15 is less than 130nm, the leakage current of the first gate 13 increases, the off-state current of the first thin film transistor 10 increases, and the device is unstable and is more easily broken down; when the thickness of the first gate dielectric layer 15 is greater than 150nm, the bending degree of the energy band near the front channel of the first active layer 11 is reduced, the concentration of excited carriers is reduced, the carrier mobility is reduced, the control capability of the first gate electrode 13 on the carriers in the first active layer 11 is reduced, and the sub-threshold slope is increased.

Optionally, when the first thin film transistor 10 is of a bottom-gate structure or a dual-gate structure, the first gate 13 is located between the first gate dielectric layer 15 and the substrate 101, and the roughness of the surface of the first gate dielectric layer 15 close to the first active layer 11 is 0.1nm to 1 nm; in other words, the roughness of the surface of the first gate dielectric layer 15 away from the first gate 13 is 0.1nm to 1 nm. Specifically, the roughness of the surface of the first gate dielectric layer 15 close to the first active layer 11 may be, but is not limited to, 0.1nm, 0.2nm, 0.4nm, 0.5nm, 0.6nm, 0.8nm, 1nm, and the like. When the roughness of the surface of the first gate dielectric layer 15 close to the first active layer 11 is in this range, the first thin film transistor 10 can have a higher carrier mobility, but the defect state content at the interface between the first gate dielectric layer 15 and the first active layer 11 is lower, so that the carrier trapping in the first active layer 11 is reduced. When the roughness of the surface of the first gate dielectric layer 15 close to the first active layer 11 is less than 0.1nm, the process conditions are more complicated, the cost is higher, but the performance improvement effect on the first thin film transistor 10 is little; when the roughness of the surface of the first gate dielectric layer 15 close to the first active layer 11 is greater than 1nm, scattering is reduced to reduce the mobility of carriers, and in addition, the content of defect states at the interface between the first gate dielectric layer 15 and the first active layer 11 is increased, so that the stability of positive and negative stress is deteriorated, and when the first gate electrode 13 is stressed for a long time, the electrical characteristics and the switching characteristics are irreversibly deteriorated, particularly, the threshold voltage is moved in the positive direction and the negative direction. The positive and negative stress changes cause color cast on the screen, serious low gray scale mura, residual shadow, increase of work number and the like. Roughness in this application is not specifically stated to mean root mean square roughness (RMS roughness).

Alternatively, the first source electrode 17 and the first drain electrode 19 may each include, but are not limited to, one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), gold (Au), and the like. In the embodiment of the present application, the first source electrode 17 and the first drain electrode 19 are both molybdenum electrodes.

Referring to fig. 3, in some embodiments, when the first thin film transistor 10 has a dual-gate structure, the first thin film transistor 10 further includes a second gate dielectric layer 12 and a second gate 14, the second gate dielectric layer 12 is disposed on a surface of the first active layer 11 away from the first gate 13 and is disposed corresponding to the first active layer 11, and the second gate 14 is disposed on a surface of the second gate dielectric layer 12 away from the first active layer 11 and is used for accessing a gate signal.

Alternatively, the second gate 14 may include, but is not limited to, one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), gold (Au), and the like, which is not particularly limited in the present application. In the embodiment of the present application, the second gate 14 is a molybdenum electrode.

Optionally, the second gate dielectric layer 12 may be, but is not limited to, one or more of silicon dioxide, titanium dioxide, and the like, and the application is not particularly limited. Optionally, the thickness of the second gate dielectric layer 12 is 140nm to 200 nm; specifically, it may be, but not limited to, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, etc.

Referring to fig. 3 again, in some embodiments, the second gate dielectric layer 12 includes a first sub-gate dielectric layer 121 and a second sub-gate dielectric layer 123 which are stacked; the first sub-gate dielectric layer 121 is disposed closer to the first active layer 11 than the second sub-gate dielectric layer 123, and the compactness of the first sub-gate dielectric layer 121 is smaller than that of the second sub-gate dielectric layer 123. The first sub-gate dielectric layer 121 grows at a lower temperature and power, and the second sub-gate dielectric layer 123 grows at a higher temperature and power, so that when the first sub-gate dielectric layer 121 is prepared, the bombardment effect on the interface of the first active layer 11 can be reduced, and the second sub-gate dielectric layer has better compactness and can well isolate the first active layer 11 from the second gate electrode 14. Optionally, the thickness of the first sub-gate dielectric layer 121 is 70nm to 100 nm; specifically, it may be, but not limited to, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc. The thickness of the second sub-gate dielectric layer 123 is 70nm to 100 nm; specifically, it may be, but not limited to, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc.

Referring to fig. 1 again, in some embodiments, the second thin film transistor 30 further includes a third gate 33, a third gate dielectric layer 35, a second source 37 and a second drain 39; the third gate 33 is disposed on one side of the substrate 101 and used for accessing a gate signal; the third gate dielectric layer 35 is disposed on a surface of the third gate 33, the second active layer 31 is disposed on a surface of the third gate dielectric layer 35 away from the third gate 33 and is disposed corresponding to the third gate 33, the second source 37 and the second drain 39 are disposed on a side of the second active layer 31 away from the substrate 101, the second source 37 and the second drain 39 are disposed at an interval and are electrically connected to the second active layer 31, respectively, the second source 37 or the second drain 39 is electrically connected to the first source 17 or the first drain 19, the second source 37 is used for accessing a high level, and the second drain 39 is used for accessing a low level. It should be understood that when the second thin film transistor 30 is electrically connected to the first thin film transistor 10, the second source electrode 37 is electrically connected to the first source electrode 17; or the second source electrode 37 is electrically connected to the first drain electrode 19; or the second drain electrode 39 is electrically connected to the first source electrode 17; or the second drain electrode 39 is electrically connected to the first drain electrode 19.

Alternatively, the third gate 33 may include, but is not limited to, one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), gold (Au), and the like, which is not particularly limited in the present application. In the embodiment of the present application, the third gate 33 is a molybdenum electrode. Optionally, the thickness of the third gate 33 is 220nm to 280 nm; specifically, it may be, but not limited to, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, etc.

Optionally, the third gate dielectric layer 35 may be, but is not limited to, one or more of silicon dioxide, titanium dioxide, and the like, and the application is not particularly limited. Optionally, the thickness of the third gate dielectric layer 35 is 110nm to 150 nm; specifically, it may be, but not limited to, 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, 138nm, 140nm, 145nm, 148nm, 150nm, etc.

Alternatively, the second source electrode 37 and the second drain electrode 39 may each include, but are not limited to, one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), gold (Au), and the like. In the embodiment of the present application, the second source electrode 37 and the second drain electrode 39 are both molybdenum electrodes.

The following further describes a method for manufacturing a driving substrate of the present application, and for convenience of description, the first thin film transistor is simply referred to as a thin film transistor or a ZTO thin film transistor.

Referring to fig. 2to 4, an embodiment of the present application further provides a method for manufacturing a driving substrate 100, and the method of the present embodiment may be used for manufacturing the driving substrate 100 of the present embodiment; the driving substrate 100 includes thin film transistors arranged in an array, the thin film transistors include a first gate 13, a first gate dielectric layer 15 and a first active layer 11, the first active layer 11 is disposed on one side of the first gate 13 and is insulated from the first gate 13 by the first gate dielectric layer 15, and the first gate 13 is disposed corresponding to the first active layer 11, and the method includes:

s201, preparing a first grid 13;

alternatively, preparing the first gate 13 includes:

s2011, providing a substrate 101;

specifically, the substrate 101 is cleaned with deionized water until the resistivity of the deionized water is greater than or equal to 7M Ω · cm, and then the substrate 101 is dried. Optionally, the substrate 101 may include, but is not limited to including, one or more of gallium arsenide, gallium nitride, silicon dioxide, and the like. In a specific embodiment, the substrate 101 is a glass substrate 101.

S2012, plating a first gate layer on one side (e.g., surface) of the substrate 101; and

alternatively, the first gate layer is deposited on one side of the substrate 101 in an inert gas atmosphere such as argon by a magnetron sputtering process. The gas pressure of the magnetron sputtering is 0.1Pa to 0.267Pa, and specifically, may be, but is not limited to, 0.1Pa, 0.15Pa, 0.18Pa, 0.2Pa, 0.25Pa, 0.267Pa, and the like.

Optionally, the power of magnetron sputtering is related to the size of the substrate 101, and when the size of the substrate 101 is 8 inches, the sputtering power of magnetron sputtering is 120W to 160W; specifically, it may be, but is not limited to, 120W, 125W, 130W, 135W, 140W, 145W, 150W, 155W, 160W, etc.

In a specific embodiment, the first gate layer is a molybdenum layer, the gas pressure of the magnetron sputtering is 0.36Pa, and the power of the magnetron sputtering is 80W.

Optionally, the thickness of the first gate layer is 140nm to 280 nm; specifically, it may be, but not limited to, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 240nm, 260nm, 270nm, 180nm, etc. When the first gate layer is too thin, the leakage current of the fabricated first gate 13 increases and breakdown easily occurs, and when the first gate layer is too thick, the carrier mobility decreases and the sub-threshold slope stability deteriorates.

S2013, etching the first gate layer to form the first gate 13.

Optionally, the etching of the first gate layer may be performed by a photolithography process, for example: coating photoresist on the surface of the substrate 101, exposing and developing to leave the photoresist on the portion corresponding to the first gate 13, etching, removing the photoresist with acetone, alcohol and the like, and cleaning and drying with deionized water. Optionally, the etching solution is a ketonic acid, and the pattern of the formed first gate 13 is more complete and the step is steeper by etching with the ketonic acid. Alternatively, the first gate electrode 13 may include, but is not limited to, one or more of titanium (Ti), aluminum (Al), molybdenum (Mo), copper (Cu), gold (Au), and the like.

S202, depositing a first gate dielectric layer 15 on the surface of the first gate 13; and

optionally, the first gate dielectric layer 15 is deposited at a Deposition rate of 0.1nm/s to 0.5nm/s at a Deposition temperature of 300 ℃ to 350 ℃ by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, so that the roughness of the surface of the first gate dielectric layer 15 away from the first gate 13 is 0.1nm to 1 nm.

Alternatively, the precipitation temperature may be any value between 300 ℃ and 350 ℃, and specifically, may be, but is not limited to, 300 ℃, 310 ℃, 320 ℃, 330 ℃, 340 ℃, 350 ℃, and the like. When the precipitation temperature is too low, the formed first gate dielectric layer 15 has poor compactness, insufficient reaction, high internal hydrogen content and more defects of the first gate dielectric layer 15 at the interface; with the increase of the deposition temperature, the activity of each reactant on the surface of the substrate 101 gradually increases, the film forming speed of the first gate dielectric layer 15 increases, and the ability of atoms to fill the vacancy in the first gate dielectric layer 15 is improved, so that a more compact first gate dielectric layer 15 is formed, however, the film forming speed is too fast, the gap filling in the first gate dielectric layer 15 is insufficient, the surface roughness of the first gate dielectric layer 15 is high, and the interface state defect between the first gate dielectric layer 15 and the first active layer 11 increases. Therefore, when the deposition temperature is between 300 ℃ and 350 ℃, the first gate dielectric layer 15 can be formed more densely, and the roughness of the surface of the first gate dielectric layer 15 close to the first active layer 11 can be as low as possible.

Alternatively, the precipitation speed may be any value between 0.1nm/s and 0.5nm/s, and specifically, may be, but not limited to, 0.1nm/s, 0.2nm/s, 0.3nm/s, 0.4nm/s, 0.5nm/s, and the like. When the deposition speed is less than 0.1nm/s, the first gate dielectric layer 15 has poor compactness and is easy to break down, when the deposition speed is more than 0.5nm/s, the roughness of the surface of the first gate dielectric layer 15 is increased, the scattering of the first gate dielectric layer 15 is reduced, the mobility of current carriers is further reduced, the hydrogen content in the first gate dielectric layer 15 is high, in addition, the defect state content of an interface between the first gate dielectric layer 15 and the first active layer 11 is increased, the stability of positive and negative stress is deteriorated, when the first gate 13 applies stress for a long time, the electrical characteristics and the switching characteristics are irreversibly deteriorated, and particularly, the threshold voltage is subjected to positive and negative movement. The positive and negative stress changes cause color cast on the screen, serious low gray scale mura, residual shadow, increase of work number and the like.

Optionally, the first gate dielectric layer 15 may be, but is not limited to, one or more of silicon dioxide, titanium dioxide, and the like, and the application is not particularly limited.

When the first gate dielectric layer 15 is a silicon dioxide layer, the raw material component of the first gate dielectric layer 15 is SiH₄And N₂O; the SiH₄And said N₂The flow ratio of O ranges from 1:6 to 1: 4; specifically, it may be, but not limited to, 1:4, 1:4.5, 1:5, 1:5.5, 1:6, etc. When N is present₂When the O content is too low or too high, SiH₄And N₂The reaction speed of O is reduced, and the prepared first gate dielectric layer 15 is not compact and is easy to be broken down electrically; n is a radical of₂When the content of O is excessively low (e.g., SiH)₄And N₂The flow ratio of O is more than 1:4), the content of hydrogen in the formed first gate dielectric layer 15 is excessive, i.e., SiH₄The reaction is insufficient, the content of H inside the first gate dielectric layer 15 increases, the internal hanger defects increase, and hydrogen diffuses to the first active layer 11 in a large amount under a high temperature condition or during annealing, so that a large number of defects exist in the first active layer 11, which affects the characteristics of the thin film transistor.

Alternatively, when the size of the substrate 101 is 8 inches, the SiH is generated when the first gate dielectric layer 15 is deposited₄The flow rate of (1) is 15sccm (milliliters per minute, ml/min) to 25 sccm; specifically, but not limited to, 15sccm, 16sccm, 28sccm, 20sccm, 22sccm, 25sccm, and the like. Said N is₂The flow rate of O is 60sccm to 120 sccm; specifically, but not limited to, 60sccm, 70sccm, 80sccm, 90sccm, 100sccm, 110sccm, 120sccm, etc. SiH₄And N₂When the O flow is too low, the precipitation speed of the first gate dielectric layer 15 is too slow, the reaction speed is reduced, the film layer is not compact, electric breakdown is easy to occur, and long-time plasma bombardment can also generate negative influence on the interface of the first active layer 11, so that the number of absent states is increased, and SiH (hydrogen-oxygen content) is increased₄And N₂When the O flow is too high, the precipitation speed of the first gate dielectric layer 15 is too fast, so that the roughness of the surface of the first gate dielectric layer 15 is increased, the scattering of the first gate dielectric layer 15 is reduced, the mobility of carriers is reduced, and in addition, the defect state content of the interface between the first gate dielectric layer 15 and the first active layer 11 is increased, so that the stability of positive and negative stress is deteriorated; the gate is stressed for a long time, the electrical characteristics and the switching characteristics are irreversibly deteriorated, and particularly, the threshold voltage is shifted in the positive and negative directions. The positive and negative stresses include electrical stress, high temperature electrical stress, and illumination stress. When the size of the substrate 101 is larger than 8 inches, SiH₄And N₂The flow of O may be increased proportionally.

Optionally, the roughness of the surface of the first gate dielectric layer 15 away from the first gate 13 is 0.1nm to 1 nm; specifically, it may be, but not limited to, 0.1nm, 0.2nm, 0.4nm, 0.5nm, 0.6nm, 0.8nm, 1nm, etc. The thickness of the first gate dielectric layer 15 is 130nm to 150 nm; specifically, it may be, but not limited to, 130nm, 133nm, 135nm, 138nm, 140nm, 142nm, 145nm, 148nm, 150nm, etc.

S203, depositing a semiconductor layer on the surface of the first gate dielectric layer 15, which is far away from the first gate 13, and etching the semiconductor layer to form a first active layer 11, wherein the first active layer 11 comprises a zinc-tin oxide layer.

Specifically, a radio frequency magnetron sputtering process is adopted, a ZTO ceramic target is used as a target, a sputtering pressure is 0.0005torr to 0.002torr, a sputtering power is 120W to 160W (taking an 8-inch substrate 101 as an example), a semiconductor layer is deposited on the surface of the first gate dielectric layer 15 far away from the first gate 13 in an argon and oxygen atmosphere, and then the semiconductor layer is etched by a yellow light process to form the first active layers 11 arranged in an array.

Alternatively, the sputtering gas pressure may be, but is not limited to, 0.0005torr, 0.001torr, 0.0015torr, 0.002torr, etc. When the sputtering pressure is too high, the sputtered ion molecules and the like are scattered and enhanced, the density of the first active layer 11 (or the semiconductor layer) is reduced, and the internal defects of the first active layer 11 are increased. If the sputtering pressure is too low, the sputtering conditions may not be initiated or formed, the sputtering rate is slow, the formed first active layer 11 is not dense, the internal defects are high, the sub-threshold slope (SS) of the thin film transistor is deteriorated, the carrier mobility is low, and the stability is poor.

Alternatively, the power of magnetron sputtering is related to the size of the substrate 101, and when the size of the substrate 101 is 8 inches, the sputtering power of magnetron sputtering may be, but is not limited to, 120W, 125W, 130W, 135W, 140W, 145W, 150W, 155W, 160W, and the like. The sputtering power is too low, the density of the formed first active layer 11 is low, the content of internal defects is high, the performance of the thin film transistor is affected, the sputtering power is improved, the density of the formed first active layer 11 can be increased, and the content of internal defects is low, so that the performance of the thin film transistor is improved; however, when the sputtering power exceeds a certain value, the heat is excessive and the ZTO ceramic target will melt, causing the sputtering apparatus to be destroyed. Alternatively, when the power is 140W, the first active layer 11 can be made with a greater density and smaller internal defects, resulting in better performance of the thin film transistor without melting the ZTO ceramic target.

Alternatively, ZnO-SnO in ZTO ceramic targets₂Is 1.5: 1to 2.5: 1. Alternatively, the molar ratio of zinc oxide to tin oxide is 2:1, and when the molar ratio of zinc oxide to tin oxide is within this range, the first active layer 11 is formed to be the most dense, the internal defects are the least, and the performance of the resulting ZTO thin film transistor is the best.

Alternatively, the etching solution is a hydrochloric acid solution, the molar ratio of hydrochloric acid to water in the hydrochloric acid solution is 2: 1to 4:1, for example, 2:1, 3:1, 4:1, etc., the acidity of the hydrochloric acid solution cannot be too low, otherwise, the semiconductor layer is difficult to etch, or a slope exists in the first active layer 11 formed after etching; too strong acidity makes it difficult to achieve rapid volatilization of HCl.

Alternatively, the flow ratio of argon to oxygen (Ar/O) during sputtering₂) From 46: 1to 49:1, and specifically, can be, but is not limited to, 46:4, 47:3, 48:2, 49:1, and the like. During sputtering, the concentration of oxygen vacancies in the formed semiconductor layer (ZTO layer) is reduced along with the increase of the oxygen content, the carrier concentration is reduced, oxygen in the sputtering process is mainly combined with zinc-tin ions, excessive oxygen can form defects, hybridization of 5s orbitals of tin ions is influenced, and the performance of the thin film transistor is influenced, the increase of the oxygen concentration can improve the negative bias voltage of the thin film transistor, but can also deteriorate the positive bias voltage, so that when the flow ratio of argon to oxygen is 48:2, various performances of the formed thin film transistor can be well balanced. Alternatively, when the size of the substrate 101 is 8 inches, the flow rate of the argon gas ranges from 92sccm to 96sccm, and specifically, can be, but is not limited to, 92sccm, 93sccm, 94sccm, 95sccm, and 96 sccm. The flow range of the oxygen is 4sccm to 8 sccm; specifically, but not limited to, 4sccm, 5sccm, 6sccm, 7sccm, 8 sccm. When the size of the substrate 101 is larger or smaller, the flow rates of argon and oxygen may be increased or decreased according to the ratio, but the ratio of the flow rates of argon and oxygen is 46: 1to 49:1, and the formed semiconductor layer has the best performance.

In some embodiments, after forming a deposited semiconductor layer on the surface of the first gate dielectric layer away from the first gate 13 and before etching the semiconductor layer, the method further includes:

s2031, carrying out vacuum annealing on the semiconductor layer.

The semiconductor layer formed by radio frequency magnetron sputtering is usually in a loose and porous structure, vacuum annealing is carried out, the ZTO semiconductor layer can be more densified, the 5s track is fully hybridized due to tight arrangement of tin ions, the mobility of carriers is further improved, and the physical stability and the chemical stability of the ZTO semiconductor layer can be improved. The improvement of the physical stability is beneficial to reducing the damage of the subsequent photoetching development, back channel etching and the growth of a passivation layer to the back channel of the first active layer 11. The improved chemical stability can improve the bearing capacity of back channel etching. In addition, the more "compact" ZTO semiconductor layer can also inhibit defect formation during subsequent oxygen anneal, preventing carrier mobility from excessively attenuating.

Optionally, the temperature of the vacuum annealing is 300 ℃ to 350 ℃; specifically, the temperature may be, but not limited to, 300 ℃, 310 ℃, 320 ℃, 330 ℃, 340 ℃, 350 ℃ and the like. The densification of the ZTO semiconductor layer is limited by the fact that the vacuum annealing temperature is too low, the densification of the ZTO semiconductor layer can be improved by increasing the vacuum annealing temperature, so that the carrier mobility of the thin film transistor is improved, the sub-threshold slope of the thin film transistor is reduced (the smaller the sub-threshold slope is better), however, when the temperature is too high, the semiconductor layer (such as a molybdenum layer) is oxidized, and the formed semiconductor layer is too dense due to the fact that the vacuum annealing temperature is too high, and even strong acid cannot be etched, so that the etching of the subsequent semiconductor layer is influenced.

Optionally, the time of the vacuum annealing is 50min to 70 min; specifically, it may be, but not limited to, 50min, 55min, 60min, 65min, 70min, etc. When the vacuum annealing time is too short, the improvement of the compactness of the ZTO semiconductor layer is limited, and when oxygen annealing is carried out subsequently, a large amount of oxygen can be diffused into the ZTO semiconductor layer, the 5s orbital hybridization of heavy metal ion tin is seriously influenced, the carrier mobility is greatly reduced, defects can be formed after the oxygen is diffused into the ZTO semiconductor layer, and the sub-threshold slope of the thin film transistor is increased. If the vacuum anneal time is too long, the resulting ZTO semiconductor layer is too tight, which can interfere with the subsequent etching of the ZTO semiconductor layer.

For features of the embodiment that are not described in the present embodiment and are the same as those of the other embodiments, please refer to the above embodiments, and detailed descriptions thereof are omitted.

Referring to fig. 2 and fig. 5, an embodiment of the present application further provides a method for manufacturing a driving substrate 100, where the method of the present embodiment may be used for manufacturing the driving substrate 100 of the present embodiment, and the driving substrate 100 includes thin film transistors arranged in an array, where the thin film transistors are bottom gate structures; the thin film transistor comprises a first grid electrode 13, a first grid dielectric layer 15, a first active layer 11, a first source electrode 17 and a first drain electrode 19, wherein the first grid dielectric layer 15 is arranged on the surface of the first grid electrode 13, and the first active layer 11 is arranged on the surface, far away from the first grid electrode 13, of the first grid dielectric layer 15 and corresponds to the first grid electrode 13; the first source electrode 17 and the first drain electrode 19 are disposed at intervals and electrically connected to the first active layer 11, respectively; the method comprises the following steps:

s301, preparing a first grid 13;

s302, depositing a first gate dielectric layer 15 on the surface of the first gate 13;

s303, depositing a semiconductor layer on the surface of the first gate dielectric layer 15 far away from the first gate 13;

s304, carrying out vacuum annealing on the semiconductor layer;

s305, etching the semiconductor layer to form a first active layer 11, wherein the first active layer 11 comprises a zinc-tin oxide layer;

for the features of S301 to S305 that are the same as those of the other embodiments, please refer to the embodiments, which are not described herein again.

S306, forming a first source electrode 17 and a first drain electrode 19 on one side of the first active layer 11 away from the substrate 101;

optionally, a direct current magnetron sputtering process is adopted, a source drain electrode layer is deposited on the surface of the first active layer 11 away from the substrate 101, and the source drain electrode layer is etched by a yellow light process to form a first source electrode 17 and a first drain electrode 19, wherein the first source electrode 17 and the first drain electrode 19 are arranged at intervals and are respectively electrically connected with the first active layer 11.

Alternatively, the etching liquid may be a keto acid. And the ketonic acid is adopted for etching, so that the damage of etching to the active layer can be reduced.

Optionally, the source-drain electrode layer is a molybdenum layer, and the sputtering power is 40W to 80W, and specifically, the sputtering power may be, but is not limited to, 40W, 50W, 60W, 70W, 80W, and the like. The sputtering power is too large, the bombardment effect on the first active layer 11 is too large, the generated defects are too many, and the performance of the thin film transistor is influenced. The power is too low, the formed Mo layer is not compact, the contact is not in place, and the Mo layer is easy to fall off.

Alternatively, the thickness of the source-drain electrode layer is 80nm to 120nm, and specifically, may be, but is not limited to, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm, and the like. When the source-drain electrode layer is too thin, the first source electrode 17 and the first drain electrode 19 formed have poor conductivity and high resistivity; when source drain electrode layer thickness is too thick, be unfavorable for the graphics of source drain electrode layer, the step is too high to be unfavorable for the growth of other retes, increases the sculpture degree of difficulty and causes the step slow excessively, and the sculpture is inhomogeneous, and the sculpture is too thick degree inconsistent, and the sculpture residue appears inadequately.

S307, depositing a passivation layer on the surfaces of the first source electrode 17 and the first drain electrode 19 away from the first gate electrode 13;

specifically, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method is adopted, and the temperature is 120-180 ℃, the power is 40-60W, and SiH₄、NH₃、N₂And depositing a passivation layer on the surface of the first source electrode 17 and the first drain electrode 19 far away from the substrate 101 in the mixed gas atmosphere. Since the donor level HO is formed inside the first active layer 11, carriers can be excited, and the passivation layer can increase the carrier concentration of the thin film transistor.

Specifically, the deposition temperature may be, but is not limited to, 120 ℃, 140 ℃, 150 ℃, 160 ℃, 170 ℃, 180 ℃, and the like. The power may be, but is not limited to, 40W, 50W, 60W, etc. SiH₄The flow rate of (2) is 180sccm to 230 sccm; specifically, but not limited to, 180sccm, 190sccm, 200sccm, 210sccm, 220sccm, 230sccm, etc. NH (NH)₃The flow rate of (2) is 15sccm to 45 sccm; specifically, but not limited to, 15sccm, 18sccm, 20sccm, 22sccm, 25sccm, 28sccm, 30sccm, 32sccm, 35sccm, 38sccm, 40sccm, 45sccm, etc. N is a radical of₂The flow rate of the gas is 350sccm to 450 sccm; specifically, but not limited to, 350sccm, 360sccm, 380sccm, 400sccm, 410sccm, 420sccm, 430sccm, 450sccm, etc.

Alternatively, the passivation layer may be, but is not limited to, one or more of silicon dioxide, titanium dioxide, and the like, and the present application is not particularly limited.

Alternatively, the thickness of the passivation layer is 140nm to 220nm, and specifically, may be, but is not limited to, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, and the like.

S308, etching the passivation layer to expose the first source electrode 17 and the first drain electrode 19; and

alternatively, Reactive Ion Etching (RIE) is used for CF₄And O₂The passivation layer is etched at positions corresponding to the first source electrode 17 and the first drain electrode 19 in the mixed gas to expose the first source electrode 17 and the first drain electrode 19, so that the trace can better contact the first source electrode 17 and the first drain electrode 19.

And S309, performing oxygen annealing treatment.

Optionally, oxygen annealing is performed in an oxygen atmosphere at a normal atmospheric pressure to repair defects between the films obtained in the above steps, particularly the defects of the first active layer 11, so as to improve various electrical properties of the thin film transistor. A large number of oxygen vacancies exist in the first active layer 11, oxygen mainly combines with zinc-tin ions to form a strong metal oxygen bond during sputtering, and it is difficult to fill the oxygen vacancies (because the strong metal oxygen bond needs to be decomposed first if the oxygen vacancies are to be filled, and extremely high energy is needed), so that the oxygen vacancies need to be filled by oxygen annealing, and the oxygen vacancies form defects to reduce the number of the oxygen vacancies, thereby reducing the concentration of carriers and playing a role in adjusting the threshold voltage of the transfer characteristic curve. However, when the defect content is too large, the mobility of carriers is greatly reduced, the subthreshold slope of the thin film transistor is increased, and the performance of the thin film transistor is affected. Therefore, before the oxygen annealing, it is necessary to perform vacuum annealing so that the defects in the first active layer 11 are controlled within a certain concentration range.

Optionally, the temperature of the oxygen annealing is 300 ℃ to 350 ℃; specifically, the temperature may be, but not limited to, 300 ℃, 310 ℃, 320 ℃, 330 ℃, 340 ℃, 350 ℃ and the like. If the oxygen annealing temperature is too low, the sub-threshold slope SS is deteriorated, the carrier mobility is small, the number of internal defects of the first active layer 11 is increased, the stress stability is poor, the leakage current is increased, and the off-state current is increased; when the oxygen annealing temperature is too high, Zinc Tin Oxide (ZTO) is liable to form a polycrystalline structure, the uniformity of a large area is poor, and the temperature affects the properties of other film layers of the thin film transistor, for example, Mo is liable to be oxidized.

Optionally, the oxygen annealing time is 3h to 6 h; specifically, it may be, but is not limited to, 3h, 4h, 5h, 6h, etc. If the oxygen annealing time is too short, the SS subthreshold slope is poor, the carrier mobility is small, the internal defects of the first active layer 11 are increased, the off-state current of the leakage current is increased, and the performance of the thin film transistor is influenced; the oxygen annealing time is too long, so that the performance of the thin film transistor is slightly improved, but the production efficiency is influenced, and the production cost is increased.

For features of the embodiment that are not described in the present embodiment and are the same as those of the other embodiments, please refer to the above embodiments, and detailed descriptions thereof are omitted.

The ZTO thin film transistor manufactured by the method of this embodiment and the IGZO thin film transistor designed in the related art are respectively subjected to electrical property tests, and the test results are shown in the following table:

as can be seen from the above table, the ZTO thin film transistor manufactured in the embodiments of the present application has a saturation mobility, a sub-threshold slope, and a threshold voltage that are equivalent to those of the IGZO thin film transistor designed in the related art, which indicates that the ZTO thin film transistor can replace the IGZO thin film transistor and has no performance inferior to that of the IGZO thin film transistor.

Referring to fig. 3 and fig. 6, an embodiment of the present application further provides a method for manufacturing a driving substrate 100, where the method of the present embodiment may be used for manufacturing the driving substrate 100 of the present embodiment, and the driving substrate 100 includes thin film transistors arranged in an array, where the thin film transistors are in a dual-gate structure; the thin film transistor comprises a first grid electrode 13, a first grid electrode dielectric layer 15, a first active layer 11, a second grid electrode dielectric layer 12, a second grid electrode 14, a first source electrode 17 and a first drain electrode 19, wherein the first grid electrode dielectric layer 15 is arranged on the surface of the first grid electrode 13, and the first active layer 11 is arranged on the surface, far away from the first grid electrode 13, of the first grid electrode dielectric layer 15 and corresponds to the first grid electrode 13; the second gate dielectric layer 12 is arranged on the surface of the first active layer 11 away from the first gate 13, and the second gate 14 is arranged on the surface of the second gate dielectric layer 12 away from the first gate 13 and corresponding to the first active layer 11; the first source electrode 17 and the first drain electrode 19 are disposed at intervals and electrically connected to the first active layer 11, respectively; the method comprises the following steps:

s401, preparing a first grid 13;

s402, depositing a first gate dielectric layer 15 on the surface of the first gate 13;

s403, depositing a semiconductor layer on the surface, far away from the first grid electrode 13, of the first grid dielectric layer 15;

s404, carrying out vacuum annealing on the semiconductor layer;

s405, etching the semiconductor layer to form a first active layer 11, wherein the first active layer 11 comprises a zinc-tin oxide layer;

the features of S401 to S405 are the same as those of the other embodiments described above, please refer to the embodiments described above, and are not described herein again.

S406, depositing a second gate dielectric layer 12 on the surface of the first active layer 11 away from the first gate 13;

optionally, depositing a first sub-gate dielectric layer 121 on the surface of the first active layer 11 away from the first gate 13 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and depositing a second sub-gate dielectric layer 123 on the surface of the first sub-gate dielectric layer 121 away from the first gate 13 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, wherein the second gate dielectric layer 12 includes the first sub-gate dielectric layer 121 and the second sub-gate dielectric layer 123 which are stacked; the first sub-gate dielectric layer 121 is disposed closer to the first active layer 11 than the second sub-gate dielectric layer 123, and the compactness of the first sub-gate dielectric layer 121 is smaller than that of the second sub-gate dielectric layer 123. .

Optionally, the deposition temperature of the first sub-gate dielectric layer 121 is 130 ℃ to 170 ℃; specifically, it may be, but not limited to, 130 ℃, 140 ℃, 150 ℃, 160 ℃, 170 ℃ and the like. The power of the first sub-gate dielectric layer 121 during deposition is 20W to 30W, and specifically, may be, but is not limited to, 20W, 22W, 25W, 28W, 30W, and the like. Optionally, the deposition temperature of the second sub-gate dielectric layer 123 is 270 ℃ to 330 ℃; specifically, it is acceptable. The power of the second sub-gate dielectric layer 123 during deposition is 31W to 40W, and specifically, may be, but is not limited to, 31W, 33W, 35W, 38W, 40W, and the like. The first sub-gate dielectric layer 121 is formed at a lower temperature and a lower power, so that the bombardment effect on the first active layer 11 during the preparation of the first sub-gate dielectric layer 121 can be reduced, but the compactness of the formed first sub-gate dielectric layer is lower, so that a layer of denser second sub-gate dielectric layer 123 is regenerated on the first sub-gate dielectric layer 121 at a higher temperature and a higher power, and at the moment, the bombardment is not directly performed on the first active layer 11, so that the influence on the first active layer 11 is avoided, and meanwhile, the denser second sub-gate dielectric layer 123 can be formed, so that the first active layer 11 and the second gate 14 are better arranged in an insulating manner.

Optionally, both the first sub-gate dielectric layer 121 and the second sub-gate dielectric layer 123 may be silicon dioxide. When the first sub-gate dielectric layer 121 and the second sub-gate dielectric layer 123 are deposited, SiH (reactive gas)₄And N₂The flow ratio of O ranges from 1:6 to 1: 4; specifically, it may be, but not limited to, 1:4, 1:4.5, 1:5, 1:5.5, 1:6, etc.

S407, performing oxygen annealing treatment;

optionally, the defects between the films obtained in the above steps, especially the defects of the first active layer 11, are repaired in an oxygen atmosphere at a normal atmospheric pressure to improve the electrical properties of the thin film transistor.

Optionally, the temperature of the oxygen annealing is 300 ℃ to 350 ℃; specifically, the temperature may be, but not limited to, 300 ℃, 310 ℃, 320 ℃, 330 ℃, 340 ℃, 350 ℃ and the like. If the oxygen annealing temperature is too low, the sub-threshold slope SS is deteriorated, the carrier mobility is small, the number of internal defects of the first active layer 11 is increased, the stress stability is poor, the leakage current is increased, and the off-state current is increased; when the oxygen annealing temperature is too high, Zinc Tin Oxide (ZTO) is liable to form a polycrystalline structure, the uniformity of a large area is poor, and the temperature affects the properties of other film layers of the thin film transistor, for example, Mo is liable to be oxidized.

Optionally, the oxygen annealing time is 1.5h to 3 h; specifically, it may be, but is not limited to, 1.5h, 2h, 2.5h, 3h, etc. If the oxygen annealing time is too short, the SS subthreshold slope is poor, the carrier mobility is small, the internal defects of the first active layer 11 are increased, the off-state current of the leakage current is increased, and the performance of the thin film transistor is influenced; the oxygen annealing time is too long, so that the performance of the thin film transistor is slightly improved, but the production efficiency is influenced, and the production cost is increased.

S408, forming a second gate layer on the surface of the second gate dielectric layer 12 away from the first gate 13, and sequentially patterning the second gate layer and the second gate dielectric layer 12 to form a second gate 14 and expose the first active layer 11 corresponding to the first source 17 and the first drain 19;

optionally, depositing a second gate layer on the surface of the second gate dielectric layer 12 away from the substrate 101 in an inert gas atmosphere such as argon by using a magnetron sputtering process; with 30% by weight of H₂O₂And NH₃·H₂Performing wet etching on the second gate layer to form a second gate 14; and then, Reactive Ion Etching (RIE) is adopted to etch the second gate dielectric layer 12 to expose the regions of the first active layer 11 corresponding to the first source electrode 17 and the first drain electrode 19, so that the first active layer 11 is conveniently electrically connected with the first source electrode 17 and the first drain electrode 19 in the subsequent steps, and the first gate dielectric layer 15 at the position where the first active layer 11 is not arranged is exposed. Optionally, the exposed area of the first active layer 11 corresponding to the first source electrode 17 and the first drain electrode 19 is larger than the area of the first source electrode 17 and the first drain electrode 19 contacting the first active layer 11.

The gas pressure of the magnetron sputtering is 0.3Pa to 0.5Pa, and specifically, may be, but is not limited to, 0.3Pa, 0.33Pa, 0.36Pa, 0.4Pa, 0.45Pa, 0.5Pa, and the like. If the air pressure is too small, the second gate layer formed is easy to pull down if the contact is insufficient; if the air pressure is too high, the bombardment on the second gate dielectric layer 12 is too strong.

Optionally, the sputtering power of the magnetron sputtering is 70W to 100W; specifically, it may be, but not limited to, 70W, 75W, 80W, 85W, 90W, 95W, 100W, etc. When the power is too small, the formed second gate layer is easy to pull down due to insufficient contact; if the air pressure is too high, the bombardment on the second gate dielectric layer 12 is too strong.

In a specific embodiment, the second gate layer is a molybdenum layer, the gas pressure of the magnetron sputtering is 0.36Pa, and the power of the magnetron sputtering is 80W.

Optionally, the thickness of the second gate layer is 140nm to 280 nm; specifically, it may be, but not limited to, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 240nm, 260nm, 270nm, 180nm, etc. When the second gate layer is too thin, the leakage current of the manufactured first gate 13 is increased, and breakdown is easy to occur, when the second gate layer is too thick, patterning is not facilitated, and the step height is not conducive to growth of other film layers.

Optionally, after step S408, the method further includes: and etching the exposed first gate dielectric layer 15 by using Reactive Ion Etching (RIE) to expose the first gate 13 and form a contact hole of the first gate 13, so that the routing can better contact the first gate 13.

S409, performing plasma treatment on the regions of the first active layer 11 corresponding to the first source electrode 17 and the first drain electrode 19;

alternatively, the regions of the first active layer 11 corresponding to the first source electrode 17 and the first drain electrode 19 are treated with Ar plasma to conduct the first source electrode 17 and the first drain electrode 19, and to reduce the contact resistance between the first source electrode 17 and the first active layer 11, and between the first drain electrode 19 and the first active layer 11, and the resistance of the first source electrode 17 and the first drain electrode 19, thereby reducing the load of the display panel assembly.

Optionally, the plasma treatment time is 60s to 120 s; specifically, it may be, but is not limited to, 60s, 70s, 80s, 90s, 100s, 110s, 120 s. If the plasma treatment time is too short, the first source electrode 17 and the first drain electrode 19 are insufficiently conducted, and the contact resistance between the first source electrode 17 and the first active layer 11 and between the first drain electrode 19 and the first active layer 11 cannot be reduced well; the first active layer 11 is easily damaged if the plasma treatment time is too long.

S410, forming a passivation layer on the surface of the second grid electrode 14 far away from the first grid electrode 13, and etching the passivation layer; and

specifically, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method is adopted, and the temperature is 120-180 ℃, the power is 40-60W, and SiH₄、NH₃、N₂And depositing a passivation layer on the surface of the two gates far away from the substrate 101 in the mixed gas atmosphere. And using Reactive Ion Etching (RIE) to CF₄、O₂The passivation layer is etched in the atmosphere to form first source electrode 17 and first drain electrode 19 contact holes.

Specifically, the deposition temperature may be, but is not limited to, 120 ℃, 140 ℃, 150 ℃, 160 ℃, 170 ℃, 180 ℃, and the like. The power may be, but is not limited to, 40W, 50W, 60W, etc. SiH₄The flow rate of (2) is 180sccm to 230 sccm; specifically, but not limited to, 180sccm, 190sccm, 200sccm, 210sccm, 220sccm, 230sccm, etc. NH (NH)₃The flow rate of (2) is 15sccm to 45 sccm; specifically, but not limited to, 15sccm, 18sccm, 20sccm, 22sccm, 25sccm, 28sccm, 30sccm, 32sccm, 35sccm, 38sccm, 40sccm, 45sccm, etc. N is a radical of₂The flow rate of the gas is 350sccm to 450 sccm; specifically, but not limited to, 350sccm, 360sccm, 380sccm, 400sccm, 410sccm, 420sccm, 430sccm, 450sccm, etc. CF (compact flash)₄The flow rate of (2) is 15sccm to 45 sccm; specifically, but not limited to, 15sccm, 18sccm, 20sccm, 22sccm, 25sccm, 28sccm, 30sccm, 32sccm, 35sccm, 38sccm, 40sccm, 45sccm, etc. O is₂The flow rate is 2sccm to 8 sccm; specifically, but not limited to, 2sccm, 3sccm, 4sccm, 5sccm, 6sccm, 7sccm, 8sccm, and the like.

And S411, forming a first source electrode 17 and a first drain electrode 19 on the surface of the passivation layer far away from the first gate electrode 13.

Optionally, a direct current magnetron sputtering process is adopted, a source drain electrode layer is deposited on the surface, away from the substrate 101, of the passivation layer, and the source drain electrode layer is etched by a yellow light process to form a first source electrode 17 and a first drain electrode 19, wherein the first source electrode 17 and the first drain electrode 19 are arranged at intervals and are respectively electrically connected with the first active layer 11.

Alternatively, each of the first source electrode 17 and the first drain electrode 19 may be a molybdenum electrode, and the thickness of the molybdenum electrode may be 750nm to 790nm, and specifically, may be, but is not limited to, 750nm, 760nm, 770nm, 780nm, 790nm, and the like.

For features of the embodiment that are not described in the present embodiment and are the same as those of the other embodiments, please refer to the above embodiments, and detailed descriptions thereof are omitted.

Referring to fig. 7 and fig. 8, an embodiment of the present application further provides a method for manufacturing a driving substrate 100, where the method of the present embodiment may be used for manufacturing the driving substrate 100 of the present embodiment, where the driving substrate 100 includes thin film transistors arranged in an array, and the thin film transistors are in a top gate structure; the thin film transistor comprises a substrate 101, a second grid electrode 14, a second grid dielectric layer 12, a first active layer 11, a first source electrode 17 and a first drain electrode 19; the first active layer 11 is arranged on one side of the substrate 101, the second gate dielectric layer 12 is arranged on the surface of the first active layer 11 away from the substrate 101, and the second gate 14 is arranged on the surface of the second gate dielectric layer 12 away from the first active layer 11; the first source electrode 17 and the first drain electrode 19 are disposed at intervals and electrically connected to the first active layer 11, respectively; the method comprises the following steps:

s501, forming a semiconductor layer on one side of a substrate 101, and etching to form a first active layer 11;

optionally, a radio frequency magnetron sputtering process is adopted, a ZTO ceramic target is used as a target, a sputtering pressure is 0.0005torr (millimeter mercury) to 0.002torr, a sputtering power is 120W to 160W (taking 8 inches of the substrate 101 as an example), a semiconductor layer is deposited on the surface of the substrate 101 in an argon and oxygen atmosphere, and then the semiconductor layer is etched by a yellow light process, so as to form a plurality of first active layers 11 arranged in an array.

S502, performing plasma processing on the first active layer 11;

alternatively, N is used₂The O plasma treats the first active layer 11 to repair the defect at the interface of the first active layer 11, and improve the matching degree between the first active layer 11 and the second gate dielectric layer 12.

Alternatively, the time of the plasma treatment is 120s to 240s, and specifically, may be, but is not limited to, 120s, 140s, 160s, 180s, 200s, 220s, 240s, and the like. N is a radical of₂The O plasma treatment may repair the defect of the first active layer 11. When the plasma processing time is too short, the defects of the first active layer 11 cannot be well repaired, and when the plasma processing time is too long, the bombardment side effect of the plasma with too long time is greater than the repairing effect, which is not beneficial to improving the performance of the thin film transistor.

S503, depositing a second gate dielectric layer 12 on the surface of the first active layer 11 away from the substrate 101;

optionally, depositing a first sub-gate dielectric layer 121 on the surface of the first active layer 11 away from the first gate 13 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and depositing a second sub-gate dielectric layer 123 on the surface of the first sub-gate dielectric layer 121 away from the first gate 13 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, wherein the second gate dielectric layer 12 includes the first sub-gate dielectric layer 121 and the second sub-gate dielectric layer 123 which are stacked; the first sub-gate dielectric layer 121 is disposed closer to the first active layer 11 than the second sub-gate dielectric layer 123. For a detailed description, refer to the description of the corresponding parts of the above embodiments, which are not repeated herein.

S504, carrying out oxygen annealing treatment;

optionally, annealing is performed for 2h to 3h at a temperature of 300 ℃ to 350 ℃ in an oxygen atmosphere to repair defects inside the first active layer 11 and at the interface, thereby improving basic characteristics and stress stability of the thin film transistor.

Optionally, the temperature of the oxygen annealing is 300 ℃ to 350 ℃; specifically, the temperature may be, but not limited to, 300 ℃, 310 ℃, 320 ℃, 330 ℃, 340 ℃, 350 ℃ and the like. If the oxygen annealing temperature is too low, the sub-threshold slope SS is deteriorated, the carrier mobility is small, the number of internal defects of the first active layer 11 is increased, the stress stability is poor, the leakage current is increased, and the off-state current is increased; when the oxygen annealing temperature is too high, Zinc Tin Oxide (ZTO) is liable to form a polycrystalline structure, the uniformity of a large area is poor, and the temperature affects the properties of other film layers of the thin film transistor, for example, Mo is liable to be oxidized.

Optionally, the oxygen annealing time is 2h to 3 h; specifically, it may be, but is not limited to, 2h, 2.5h, 3h, etc. If the oxygen annealing time is too short, the SS subthreshold slope is poor, the carrier mobility is small, the internal defects of the first active layer 11 are increased, the off-state current of the leakage current is increased, and the performance of the thin film transistor is influenced; the oxygen annealing time is too long, so that the performance of the thin film transistor is slightly improved, but the production efficiency is influenced, and the production cost is increased.

S505, forming a second gate layer on the surface of the second gate dielectric layer 12 away from the substrate 101, and sequentially patterning the second gate layer and the second gate dielectric layer 12 to form a second gate 14 and expose the first active layer 11 corresponding to the first source 17 and the first drain 19;

s506, performing plasma treatment on the regions of the first active layer 11 corresponding to the first source electrode 17 and the first drain electrode 19;

s507, forming a passivation layer on the surface of the second gate 14 away from the substrate 101, and etching the passivation layer; and

optionally, Plasma Enhanced Chemical Vapor Deposition (PECVD) is used at a temperature of 120-180 deg.C and a power of 40-60W, SiH₄、NH₃、N₂And depositing a passivation layer on the surface of the two gates far away from the substrate 101 in the mixed gas atmosphere. And using Reactive Ion Etching (RIE) to CF₄、O₂The passivation layer is etched in the atmosphere to form contact holes for the first source electrode 17 and the first drain electrode 19 and expose the second gate electrode 14, so that the trace can better contact the second gate electrode 14.

And S508, forming a first source electrode 17 and a first drain electrode 19 on the surface of the passivation layer away from the first gate electrode 13.

Optionally, a direct current magnetron sputtering process is adopted, a source drain electrode layer is deposited on the surface, away from the substrate 101, of the passivation layer, and the source drain electrode layer is etched by a yellow light process to form a first source electrode 17 and a first drain electrode 19, wherein the first source electrode 17 and the first drain electrode 19 are arranged at intervals and are respectively electrically connected with the first active layer 11.

Alternatively, each of the first source electrode 17 and the first drain electrode 19 may be a molybdenum electrode, and the thickness of the molybdenum electrode may be 750nm to 790nm, and specifically, may be, but is not limited to, 750nm, 760nm, 770nm, 780nm, 790nm, and the like.

For features of the embodiment that are not described in the present embodiment and are the same as those of the other embodiments, please refer to the above embodiments, and detailed descriptions thereof are omitted.

Referring to fig. 9, an embodiment of the present application further provides a display panel assembly 600, where the display panel assembly 600 includes: the driving substrate 100 according to the embodiment of the present application; and a display layer 610, wherein the display layer 610 is electrically connected to the driving substrate 100, and displays content under the driving of the driving substrate 100.

Alternatively, the display layer 610 may be, but is not limited to, one or more of an organic light emitting diode display layer (OLED display layer), a light emitting diode display layer (LED display layer), a micro light emitting diode display layer (micro LED display layer), a mini light emitting diode display layer (MiniLED display layer), a liquid crystal display layer (LCD display layer), and the like.

Optionally, the display panel assembly 600 may be, but is not limited to, one or more of an OLED display panel assembly, an LED display panel assembly, a micro LED display panel assembly, a MiniLED display panel assembly, an LCD display panel assembly, and the like.

For a detailed description of the driving substrate 100, please refer to the description of the corresponding parts of the above embodiments, which is not repeated herein.

Referring to fig. 10, an embodiment of the present application further provides an electronic device 700, which includes: a housing 710, wherein the housing 710 has an accommodating space 701; the display panel assembly 600 according to the embodiment of the present application is configured to display and seal the accommodating space 701; and a circuit board assembly 730, wherein the circuit board assembly 730 is disposed in the accommodating space 701, electrically connected to the display panel assembly 600, and configured to control the display panel assembly 600 to display content.

The electronic device 700 according to the embodiment of the present application may be, but is not limited to, a portable electronic device such as a mobile phone, a tablet, a notebook, a desktop, a smart band, a smart watch, an electronic reader, and a game machine.

Referring also to fig. 11, optionally, the circuit board assembly 730 may include a processor 731 and a memory 733. The processor 731 is electrically connected to the display panel assembly 600 and the memory 733, respectively. The processor 731 is configured to control the display panel assembly 600 to display, and the memory 733 is configured to store a program code required by the processor 731 to operate, a program code required by the processor 731 to control the display panel assembly 600, display contents of the display panel assembly 600, and the like.

Optionally, the processor 731 includes one or more general-purpose processors 731, wherein the general-purpose processors 731 can be any type of device capable of Processing electronic instructions, including a Central Processing Unit (CPU), a microprocessor, a microcontroller, a main processor, a controller, an ASIC, and the like. The processor 731 is configured to execute various types of digitally stored instructions, such as software or firmware programs stored in memory, which enable the computing device to provide a wide variety of services.

Alternatively, the Memory 733 may include a Volatile Memory 733(Volatile Memory), such as a Random Access Memory (RAM); the Memory 733 may also include a Non-volatile Memory (NVM), such as a Read-Only Memory (ROM), a Flash Memory (FM), a Hard Disk Drive (HDD), or a Solid-State Drive (SSD). The memory 733 may also include a combination of the above types of memories.

Reference herein to "an embodiment" or "an implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present application and not for limiting, and although the present application is described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present application without departing from the spirit and scope of the technical solutions of the present application.