Display substrate, preparation method thereof and display device

文档序号：513952 发布日期：2021-05-28 浏览：2次中文

阅读说明：本技术 显示基板及其制备方法、显示装置 (Display substrate, preparation method thereof and display device ) 是由刘文渠姚琪孟德天张锋崔钊董立文宋晓欣侯东飞王利波吕志军于 2021-01-12 设计创作，主要内容包括：本公开提供了一种显示基板及其制备方法、显示装置。显示基板包括基底,设置在所述基底上的有源结构层,设置在所述有源结构层远离所述基底一侧的第一源漏结构层,以及设置在所述第一源漏结构层远离所述基底一侧的第二源漏结构层；所述有源结构层包括第一有源层和第二有源层,所述第一源漏结构层包括第一有源过孔和第一源漏电极,所述第一源漏电极通过所述第一有源过孔与所述第一有源层连接；所述第二源漏结构层包括第二有源过孔和第二源漏电极,所述第二源漏电极通过所述第二有源过孔与所述第二有源层连接。本公开保证了低温多晶硅薄膜晶体管和氧化物薄膜晶体管的阈值电压和开启电流的均一性,提高了良率。(The disclosure provides a display substrate, a preparation method thereof and a display device. The display substrate comprises a substrate, an active structure layer arranged on the substrate, a first source drain structure layer arranged on one side, far away from the substrate, of the active structure layer, and a second source drain structure layer arranged on one side, far away from the substrate, of the first source drain structure layer; the active structure layer comprises a first active layer and a second active layer, the first source drain structure layer comprises a first active via hole and a first source drain electrode, and the first source drain electrode is connected with the first active layer through the first active via hole; the second source-drain structure layer comprises a second active via hole and a second source-drain electrode, and the second source-drain electrode is connected with the second active layer through the second active via hole. The method ensures the uniformity of threshold voltage and starting current of the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor, and improves the yield.)

1. A display substrate is characterized by comprising a substrate, an active structure layer arranged on the substrate, a first source drain structure layer arranged on one side, far away from the substrate, of the active structure layer, and a second source drain structure layer arranged on one side, far away from the substrate, of the first source drain structure layer; the active structure layer comprises a first active layer and a second active layer, the first source drain structure layer comprises a first active via hole and a first source drain electrode, and the first source drain electrode is connected with the first active layer through the first active via hole; the second source-drain structure layer comprises a second active via hole and a second source-drain electrode, and the second source-drain electrode is connected with the second active layer through the second active via hole.

2. The display substrate of claim 1, wherein the active structure layer comprises: the light-emitting diode comprises a first insulating layer arranged on a substrate, a first active layer arranged on one side, far away from the substrate, of the first insulating layer, a second insulating layer covering the first active layer, a first gate electrode arranged on one side, far away from the substrate, of the second insulating layer, a third insulating layer covering the first gate electrode, a light shielding layer arranged on one side, far away from the substrate, of the third insulating layer, a fourth insulating layer covering the light shielding layer, a second active layer arranged on one side, far away from the substrate, of the fourth insulating layer, a fifth insulating layer arranged on one side, far away from the substrate, of the second active layer, and a second gate electrode arranged on one side, far away from the substrate, of the fifth insulating layer.

3. The display substrate of claim 2, wherein the first source drain structure layer comprises: the sixth insulating layer covers the active structure layer, and the first source electrode and the first drain electrode are arranged on one side, far away from the substrate, of the sixth insulating layer; first active via holes are formed in the second insulating layer, the third insulating layer, the fourth insulating layer and the sixth insulating layer, and the first source electrode and the first drain electrode are respectively connected with the first active layer through the first active via holes.

4. The display substrate of claim 2, wherein the second source-drain structure layer comprises: the first source-drain structure layer is arranged on the first flat layer, and the second source electrode and the second drain electrode are arranged on the second flat layer; second active via holes are formed in the sixth insulating layer, the seventh insulating layer and the first flat layer, and the second source electrode and the second drain electrode are respectively connected with the second active layer through the second active via holes.

5. The display substrate of claim 4, wherein the second active via comprises: a via hole formed on the seventh insulating layer through one patterning process, and a via hole formed on the first and sixth insulating layers through another patterning process.

6. The display substrate according to claim 4, wherein the second source/drain structure layer further comprises a connection electrode, the connection electrode is connected to the first source/drain electrode through a via hole, and the connection electrode is disposed on the same layer as the second source electrode and the second drain electrode.

7. The display substrate according to claim 6, further comprising a second planarization layer disposed on the second source-drain structure layer and an anode disposed on the second planarization layer, wherein the anode is connected to the connection electrode through a via hole.

8. The display substrate of any one of claims 1 to 7, wherein the material of the first active layer comprises low temperature polysilicon and the material of the second active layer comprises an oxide; alternatively, the material of the first active layer includes an oxide, and the material of the second active layer includes low temperature polysilicon.

9. A display device comprising the display substrate according to any one of claims 1 to 8.

10. A method for preparing a display substrate comprises the following steps:

forming an active structure layer on a substrate, the active structure layer including a first active layer and a second active layer;

forming a first source-drain structural layer on the active structural layer, wherein the first source-drain structural layer comprises a first active via hole and a first source-drain electrode, and the first source-drain electrode is connected with the first active layer through the first active via hole;

and forming a second source-drain structural layer on the first source-drain structural layer, wherein the second source-drain structural layer comprises a second active via hole and a second source-drain electrode, and the second source-drain electrode is connected with the second active layer through the second active via hole.

11. The method of claim 10, wherein forming an active structure layer on a substrate comprises:

sequentially forming a first insulating layer, a first active layer, a second insulating layer, a first gate electrode, a third insulating layer, a shielding layer, a fourth insulating layer and a second active layer on a substrate;

forming a fifth insulating layer disposed on the second active layer and a second gate electrode disposed on the fifth insulating layer.

12. The method for preparing a semiconductor device according to claim 10, wherein forming a first source-drain structure layer on the active structure layer comprises:

forming a sixth insulating layer covering the active structure layer, wherein first active via holes are formed on the second insulating layer, the third insulating layer, the fourth insulating layer and the sixth insulating layer;

and forming a first source electrode and a first drain electrode on the sixth insulating layer, wherein the first source electrode and the first drain electrode are respectively connected with the first active layer through the first active via hole.

13. The method of claim 12, wherein after forming the first active via, further comprising: and carrying out annealing treatment and/or cleaning treatment on the exposed first active layer in the first active via hole.

14. The method for preparing a semiconductor device according to claim 10, wherein forming a second source-drain structure layer on the first source-drain structure layer comprises:

forming a seventh insulating layer covering the first source drain structure layer, wherein a second through hole is formed in the seventh insulating layer, and an insulating layer covering the second active layer is reserved in the second through hole;

forming a first flat layer on the seventh insulating layer, and etching the insulating layer in the second through hole to form a second active through hole after forming a fourth through hole communicated with the second through hole on the first flat layer;

and forming a second source electrode and a second drain electrode on the seventh insulating layer, wherein the second source electrode and the second drain electrode are respectively connected with the second active layer through the second active via hole.

15. The production method according to claim 14, wherein forming a first flat layer on the seventh insulating layer includes:

coating a flat film on the seventh insulating layer;

forming a first flat layer through a curing annealing process;

forming a fourth via hole communicating with the second via hole through a patterning process;

and etching the insulating layer in the second through hole by using the first flat layer as a mask to form a complete second active through hole exposing the second active layer.

16. The production method according to any one of claims 10 to 15, wherein the material of the first active layer comprises low-temperature polysilicon, and the material of the second active layer comprises an oxide; alternatively, the material of the first active layer includes an oxide, and the material of the second active layer includes low temperature polysilicon.

Technical Field

The present disclosure relates to but not limited to the field of display technologies, and in particular, to a display substrate, a method for manufacturing the same, and a display device.

Background

An Organic Light Emitting Diode (OLED) is an active Light Emitting display device, and has the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, very high response speed, thinness, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED as a light emitting device and performing signal control by a Thin Film Transistor (TFT) has become a mainstream product in the Display field at present.

The research of the inventor of the application finds that the existing OLED display substrate has the problem of poor transistor performance, and directly influences the display effect of the OLED display device.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The technical problem to be solved by the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, so as to solve the problem that the performance of a transistor of an existing display substrate is poor.

The disclosure provides a display substrate, which comprises a substrate, an active structure layer arranged on the substrate, a first source drain structure layer arranged on one side of the active structure layer, which is far away from the substrate, and a second source drain structure layer arranged on one side of the first source drain structure layer, which is far away from the substrate; the active structure layer comprises a first active layer and a second active layer, the first source drain structure layer comprises a first active via hole and a first source drain electrode, and the first source drain electrode is connected with the first active layer through the first active via hole; the second source-drain structure layer comprises a second active via hole and a second source-drain electrode, and the second source-drain electrode is connected with the second active layer through the second active via hole.

In an exemplary embodiment, the active structure layer includes: the light-emitting diode comprises a first insulating layer arranged on a substrate, a first active layer arranged on one side, far away from the substrate, of the first insulating layer, a second insulating layer covering the first active layer, a first gate electrode arranged on one side, far away from the substrate, of the second insulating layer, a third insulating layer covering the first gate electrode, a light shielding layer arranged on one side, far away from the substrate, of the third insulating layer, a fourth insulating layer covering the light shielding layer, a second active layer arranged on one side, far away from the substrate, of the fourth insulating layer, a fifth insulating layer arranged on one side, far away from the substrate, of the second active layer, and a second gate electrode arranged on one side, far away from the substrate, of the fifth insulating layer.

In an exemplary embodiment, the first source-drain structure layer includes: the sixth insulating layer covers the active structure layer, and the first source electrode and the first drain electrode are arranged on one side, far away from the substrate, of the sixth insulating layer; first active via holes are formed in the second insulating layer, the third insulating layer, the fourth insulating layer and the sixth insulating layer, and the first source electrode and the first drain electrode are respectively connected with the first active layer through the first active via holes.

In an exemplary embodiment, the second source-drain structure layer includes: the first source-drain structure layer is arranged on the first flat layer, and the second source electrode and the second drain electrode are arranged on the second flat layer; second active via holes are formed in the sixth insulating layer, the seventh insulating layer and the first flat layer, and the second source electrode and the second drain electrode are respectively connected with the second active layer through the second active via holes.

In an exemplary embodiment, the second active via includes: a via hole formed on the seventh insulating layer through one patterning process, and a via hole formed on the first and sixth insulating layers through another patterning process.

In an exemplary embodiment, the second source-drain structure layer further includes a connection electrode, the connection electrode is connected to the first source-drain electrode through a via hole, and the connection electrode is disposed on the same layer as the second source electrode and the second drain electrode.

In an exemplary embodiment, the display substrate further includes a second planarization layer disposed on the second source-drain structure layer, and an anode disposed on the second planarization layer, and the anode is connected to the connection electrode through a via hole.

In an exemplary embodiment, the material of the first active layer includes low temperature polysilicon, and the material of the second active layer includes oxide; alternatively, the material of the first active layer includes an oxide, and the material of the second active layer includes low temperature polysilicon.

The present disclosure also provides a display device including the display substrate.

The present disclosure also provides a method for manufacturing a display substrate, including:

forming an active structure layer on a substrate, the active structure layer including a first active layer and a second active layer;

In an exemplary embodiment, an active structure layer is formed on a substrate, including:

forming a fifth insulating layer disposed on the second active layer and a second gate electrode disposed on the fifth insulating layer.

In an exemplary embodiment, forming a first source-drain structure layer on the active structure layer includes:

In an exemplary embodiment, after forming the first active via, the method further includes: and carrying out annealing treatment and/or cleaning treatment on the exposed first active layer in the first active via hole.

In an exemplary embodiment, forming a second source-drain structure layer on the first source-drain structure layer includes:

In an exemplary embodiment, forming a first planarization layer on the seventh insulating layer includes:

coating a flat film on the seventh insulating layer;

forming a first flat layer through a curing annealing process;

forming a fourth via hole communicating with the second via hole through a patterning process;

and etching the insulating layer in the second through hole by using the first flat layer as a mask to form a complete second active through hole exposing the second active layer.

The exemplary embodiment of the disclosure discloses a display substrate, a manufacturing method thereof and a display device, wherein a second active via hole is formed after a first drain-source electrode is formed, so that a second active layer is not oxidized by a high-temperature annealing process, the second active layer is not damaged by a cleaning process, the lapping quality of the second drain-source electrode and the second source electrode is ensured, the performance deterioration of a second transistor is avoided, the uniformity of threshold voltage and starting current of a low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor is ensured, the yield is improved, and the display effect is improved.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the example serve to explain the principles of the disclosure and not to limit the disclosure. The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but are merely intended to illustrate the present disclosure.

FIG. 1 is a schematic diagram of a display device;

FIG. 2 is a schematic plan view of a display substrate;

FIG. 3 is a schematic cross-sectional view of a display substrate;

FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 5 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the disclosure;

fig. 6 is a schematic view after a first active layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 7 is a schematic view after a first metal layer pattern is formed in an exemplary embodiment of the present disclosure;

FIG. 8 is a schematic view after patterning a second metal layer according to an exemplary embodiment of the present disclosure;

fig. 9 is a schematic view after a second active layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 10 is a schematic view after a third metal layer pattern is formed in an exemplary embodiment of the present disclosure;

fig. 11 is a schematic view after a first active via pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 12 is a schematic view after a fourth metal layer pattern is formed in an exemplary embodiment of the present disclosure;

fig. 13 is a schematic view after a seventh insulating layer pattern is formed according to an exemplary embodiment of the present disclosure;

fig. 14 is a schematic view after a second active via pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 15 is a schematic view after forming a fifth metal layer pattern according to an exemplary embodiment of the present disclosure;

fig. 16 is a schematic view after a second planarization layer pattern is formed according to an exemplary embodiment of the present disclosure;

FIG. 17 is a schematic view after an anode pattern is formed in accordance with an exemplary embodiment of the present disclosure;

fig. 18 is a schematic view after a pixel defining layer pattern is formed according to an exemplary embodiment of the present disclosure.

Description of reference numerals:

1-a glass carrier plate; 10-a substrate; 11 — a first insulating layer;

12 — a second insulating layer; 13 — a third insulating layer; 14 — a fourth insulating layer;

15-a fifth insulating layer; 16-a sixth insulating layer; 17-a seventh insulating layer;

18 — a first planarization layer; 19 — a second planar layer; 21-a first active layer;

22 — a first gate electrode; 23 — a first source electrode; 24 — a first drain electrode;

31 — a second active layer; 32 — a second gate electrode; 33 — a second source electrode;

34 — a second drain electrode; 41-a first capacitive electrode; 42-a second capacitive electrode;

51-a barrier layer; 52-connecting electrodes; 53-connecting wire;

101-a substrate; 102-a driving circuit layer; 103-a light emitting device;

104-an encapsulation layer; 210 — a drive transistor; 211-storage capacitance;

301-anode; 302-pixel definition layer; 303 — an organic light emitting layer;

304-a cathode; 305-an isolation column; 401 — first encapsulation layer;

402-second encapsulation layer; 403-third encapsulation layer.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments may be implemented in a plurality of different forms. Those skilled in the art can readily appreciate the fact that the forms and details may be varied into a variety of forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments and features of the embodiments in the present disclosure may be arbitrarily combined with each other without conflict.

In the drawings, the size of each component, the thickness of layers, or regions may be exaggerated for clarity. Therefore, one aspect of the present disclosure is not necessarily limited to the dimensions, and the shapes and sizes of the respective components in the drawings do not reflect a true scale. Further, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers such as "first", "second", "third", and the like in the present specification are provided for avoiding confusion among the constituent elements, and are not limited in number.

In this specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating orientations or positional relationships are used to explain positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present disclosure. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, it may be a fixed connection, or a removable connection, or an integral connection; can be a mechanical connection, or an electrical connection; either directly or indirectly through intervening components, or both may be interconnected. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.

In this specification, a transistor refers to an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case of changing the direction of current flow during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". Similarly, the "insulating film" may be replaced with an "insulating layer".

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

FIG. 1 is a display deviceThe structure of the device is shown schematically. As shown in fig. 1, the OLED display device may include a scan signal driver, a data signal driver, a light emitting signal driver, an OLED display substrate, a first power supply unit, a second power supply unit, and an initial power supply unit. In an exemplary embodiment, the OLED display substrate includes at least a plurality of scan signal lines (S)₁To S_N) A plurality of data signal lines (D)₁To D_M) And a plurality of light emitting signal lines (EM)₁To EM_N) The scan signal driver is configured to sequentially supply scan signals to the plurality of scan signal lines (S)₁To S_N) Providing scan signals, the data signal driver being configured to supply a plurality of data signal lines (D)₁To D_M) Providing data signals, the light-emitting signal driver being configured to sequentially supply light-emitting signals to a plurality of light-emitting signal lines (EM)₁To EM_N) A light emission control signal is provided. In an exemplary embodiment, the plurality of scan signal lines and the plurality of light emitting signal lines extend in a horizontal direction. The display device includes a plurality of sub-pixels each including a pixel driving circuit and a light emitting device, and the pixel driving circuit of one sub-pixel may be connected to one scanning signal line, one light emission control line, and one data signal line. The first power supply unit, the second power supply unit, and the initial power supply unit are configured to supply a first power supply voltage, a second power supply voltage, and an initial power supply voltage to the pixel driving circuit through the first power supply line, the second power supply line, and the initial signal line, respectively.

Fig. 2 is a schematic plan view of a display substrate. As shown in fig. 2, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first light emitting unit P1 emitting light of a first color, a second light emitting unit P2 emitting light of a second color, and a third light emitting unit P3 emitting light of a third color, and each of the first light emitting unit P1, the second light emitting unit P2, and the third light emitting unit P3 includes a pixel driving circuit and a light emitting device. The pixel driving circuits in the first, second, and third light emitting units P1, P2, and P3 are connected to the scan signal line, the data signal line, and the light emitting signal line, respectively, and the pixel driving circuits are configured to receive the data voltage transmitted from the data signal line and output corresponding currents to the light emitting devices under the control of the scan signal line and the light emitting signal line. The light emitting devices of the first, second, and third light emitting cells P1, P2, and P3 are respectively connected to the pixel driving circuit of the corresponding light emitting cell, and are configured to emit light with corresponding brightness in response to a current output from the pixel driving circuit of the corresponding light emitting cell.

In an exemplary embodiment, the pixel unit P may include a red light emitting unit, a green light emitting unit, and a blue light emitting unit therein, or may include a red light emitting unit, a green light emitting unit, a blue light emitting unit, and a white light emitting unit therein, which is not limited in this disclosure. In an exemplary embodiment, the shape of the light emitting cell in the pixel unit may be a rectangular shape, a diamond shape, a pentagon shape, or a hexagon shape. When the pixel unit includes three light emitting units, the three light emitting units may be arranged in a horizontal parallel, vertical parallel, or delta-shaped manner, and when the pixel unit includes four light emitting units, the four light emitting units may be arranged in a horizontal parallel, vertical parallel, or Square (Square) manner, which is not limited in this disclosure.

Fig. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in fig. 3, the display substrate may include a driving circuit layer 102 disposed on a base 101, a light emitting device 103 disposed on a side of the driving circuit layer 102 away from the base 101, and an encapsulation layer 104 disposed on a side of the light emitting device 103 away from the base 101, in a plane perpendicular to the display substrate. In some possible implementations, the display substrate may include other film layers, such as spacer pillars, and the like, which are not limited herein.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and fig. 3 illustrates an example in which each sub-pixel includes one driving transistor 210 and one storage capacitor 211. The light emitting device 103 may include an anode 301, a pixel defining layer 302, an organic light emitting layer 303, and a cathode 304, the anode 301 being connected to the drain electrode of the driving transistor 210 through a via hole, the organic light emitting layer 303 being connected to the anode 301, the cathode 304 being connected to the organic light emitting layer 303, the organic light emitting layer 303 emitting light of a corresponding color by being driven by the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 that are stacked, the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, the second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which may ensure that external moisture cannot enter the light emitting device 103.

In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Fig. 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in fig. 4, the pixel driving circuit may include 7 switching transistors (first to seventh transistors T1 to T7), 1 storage capacitor C, and 8 signal lines (DATA signal line DATA, first scan signal line S1, second scan signal line S2, first initial signal line INIT1, second initial signal line INIT2, first power source line VSS, second power source line VDD, and light emitting signal line EM).

In an exemplary embodiment, a control electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor is connected to the second node N2. A control electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3. A control electrode of the third transistor T3 is connected to the second node N2, a first electrode of the third transistor T3 is connected to the first node N1, and a second electrode of the third transistor T3 is connected to the third node N3. A control electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the DATA signal line DATA, and a second electrode of the fourth transistor T4 is connected to the first node N1. A control electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the second power source line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. A control electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. A first terminal of the storage capacitor C is connected to the second power supply line VDD, and a second terminal of the storage capacitor C is connected to the second node N2.

In an exemplary embodiment, the second pole of the light emitting device is connected to a first power line VSS, the first power line VSS is a low level signal, and the second power line VDD is a signal that continuously provides a high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the display line, the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display line, that is, for the nth display line, the first scanning signal line S1 is S (n), the second scanning signal line S2 is S (n-1), the second scanning signal line S2 of the display line and the first scanning signal line S1 in the pixel driving circuit of the previous display line are the same signal line, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may employ a low temperature polysilicon thin film transistor, or may employ an oxide thin film transistor, or may employ both a low temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the Low Temperature polysilicon thin film transistor adopts Low Temperature polysilicon (LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charging and the like, and the oxide thin film transistor has the advantages of low leakage current and the like. In an exemplary embodiment, a Low Temperature polysilicon thin film transistor and an Oxide thin film transistor may be integrated on a display substrate to form a Low Temperature Polysilicon Oxide (LTPO) display substrate, and may use advantages of the two, may implement high resolution (Pixel Per inc, PPI for short), may perform Low frequency driving, may reduce power consumption, and may improve display quality.

Fig. 5 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the disclosure. As shown in fig. 5, the display substrate may include a substrate 10, an active structure layer disposed on the substrate 10, a first source-drain structure layer disposed on the active structure layer, a second source-drain structure layer disposed on the first source-drain structure layer, and a light emitting structure layer disposed on the second source-drain structure layer.

In an exemplary embodiment, the active structure layer may include: a first insulating layer 11 disposed on the substrate 10; a first semiconductor layer disposed on the first insulator 11, the first semiconductor layer including at least a first active layer 21; a second insulating layer 12 covering the first semiconductor layer; a first metal layer provided on the second insulating layer 12, the first metal layer including at least the first gate electrode 22 and the first capacitance electrode 41; a third insulating layer 13 covering the first metal layer; a second metal layer provided on the third insulating layer 13, the second metal layer including at least the second capacitor electrode 42 and the shielding layer 51; a fourth insulating layer 14 covering the second metal layer; a second semiconductor layer disposed on the fourth insulating layer 14, the second semiconductor layer including at least a second active layer 31; a fifth insulating layer 15 disposed on the second active layer 31; a third metal layer disposed on the fifth insulating layer 15, the third metal layer including at least the second gate electrode 32.

In an exemplary embodiment, the first source-drain structure layer may include: a sixth insulating layer 16 covering the third metal layer, and a fourth metal layer disposed on the sixth insulating layer 16, the fourth metal layer including at least a first source electrode 23 and a first drain electrode 24. The second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14 and the sixth insulating layer 16 are provided with two first active via holes, the two first active via holes expose the surface of the first active layer 21 away from the substrate, and the first source electrode 23 and the first drain electrode 24 are respectively connected with the first active layer 21 through the two first active via holes.

In an exemplary embodiment, the second source-drain structure layer may include: a seventh insulating layer 17 covering the fourth metal layer, a first planarization layer 18 covering the seventh insulating layer 17, and a fifth metal layer provided on the first planarization layer 18, the fifth metal layer including at least the second source electrode 33, the second drain electrode 34, and the connection electrode 52. The sixth insulating layer 16, the seventh insulating layer 17 and the first flat layer 18 are provided with two second active via holes, the two second active via holes expose the surface of the second active layer 31 on the side away from the substrate, and the second source electrode 33 and the second drain electrode 34 are respectively connected with the second active layer 31 through the two second active via holes. The seventh insulating layer 17 and the first flat layer 18 are provided with an anode via hole, the anode via hole exposes the surface of the first drain electrode 24 away from the substrate, and the connection electrode 52 is connected with the first drain electrode 24 through the connection electrode via hole.

In an exemplary embodiment, the light emitting structure layer may include: a second planarization layer 19 covering the fifth metal layer, an anode electrode 301 disposed on the second planarization layer 19, a pixel defining layer 302 disposed on the anode electrode 301, an organic light emitting layer (not shown) connected to the anode electrode 301, and a cathode electrode (not shown) connected to the organic light emitting layer. The second planarization layer 19 has an anode via hole exposing the surface of the connection electrode 52 away from the substrate, and the anode 301 is connected to the connection electrode 52 through the anode via hole. The pixel defining layer 302 has a pixel opening, the pixel opening exposes the surface of the anode 301, and the organic light emitting layer is connected to the anode 301 through the pixel opening.

The following is an exemplary description through a process of manufacturing a display substrate. The "patterning process" referred to in the present disclosure includes processes of coating a photoresist, mask exposure, development, etching, stripping a photoresist, and the like, for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposure, development, and the like, for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, and the disclosure is not limited. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, the term "a and B are disposed in the same layer" means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the forward projection of a includes the forward projection of B" or "the forward projection of B is located within the range of the forward projection of a", means that the boundary of the forward projection of B falls within the range of the boundary of the forward projection of a, or the boundary of the forward projection of a overlaps with the boundary of the forward projection of B.

Fig. 6 to 18 are schematic views showing a process of manufacturing the substrate. In an exemplary embodiment, the display substrate may include a display region 100 and a binding region 200 at one side of the display region 100, and the driving structure layer of the display region 100 and the binding structure layer of the binding region 200 are simultaneously prepared. In an exemplary embodiment, the process of preparing the display substrate may include the following operations.

(1) A substrate 10 is prepared on a glass carrier plate 1. In an exemplary embodiment, the substrate 10 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier plate 1. The first and second flexible material layers may be made of Polyimide (PI), polyethylene terephthalate (PET), or a polymer soft film with a surface treatment, the first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called Barrier (Barrier) layers, and the semiconductor layer may be made of amorphous silicon (a-si). In an exemplary embodiment, taking the stacked structure PI1/Barrier1/a-si/PI2/Barrier2 as an example, the preparation process may include: firstly, coating a layer of polyimide on a glass carrier plate 1, and forming a first flexible (PI1) layer after curing and film forming; subsequently depositing a Barrier film on the first flexible layer to form a first Barrier (Barrier1) layer overlying the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and forming a second flexible (PI2) layer after curing and film forming; a Barrier film is then deposited on the second flexible layer to form a second Barrier (Barrier2) layer overlying the second flexible layer, completing the fabrication of the substrate 10.

(2) A first semiconductor layer pattern is formed. In an exemplary embodiment, the forming of the first semiconductor layer pattern may include: a first insulating film and a first semiconductor film are sequentially deposited on the substrate 10, and the first semiconductor film is patterned through a patterning process to form a first insulating layer 11 covering the entire substrate 10 and a first semiconductor layer pattern disposed on the first insulating layer 11, the first semiconductor layer pattern being formed in the display region 100, the first semiconductor layer pattern including at least a first active layer 21, as shown in fig. 6. In an exemplary embodiment, the first insulating layer may prevent substances within the base from diffusing into other film structures in a subsequent process, which may affect the quality of the display substrate.

In an exemplary embodiment, this patterning process is referred to as a first patterning process, and after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, and a first insulating layer 11 disposed on the substrate 10.

In an exemplary embodiment, the patterning of the first semiconductor thin film through the patterning process may include: an amorphous silicon (a-si) thin film is formed on a first insulating thin film, dehydrogenation treatment is performed on the amorphous silicon thin film, and crystallization treatment is performed on the amorphous silicon thin film after the dehydrogenation treatment to form a polycrystalline silicon thin film. Then, the polysilicon thin film is patterned to form a first semiconductor layer pattern. Since a large amount of hydrogen in amorphous silicon causes defects in subsequent processes, a process for removing hydrogen is required after forming an amorphous silicon thin film. The crystallization process is a process for crystallizing amorphous silicon to form polycrystalline silicon (p-si). For example, the crystallization process may be performed by an Excimer Laser Annealing (ELA) process. Since the annealing process for forming the polysilicon may damage the oxide, the preparation of the first active layer of low temperature polysilicon is provided before the preparation of the second active layer of metal oxide.

(3) A first metal layer pattern is formed. In an exemplary embodiment, the forming of the first metal layer pattern may include: on the substrate on which the aforementioned patterns are formed, a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned by a patterning process to form a second insulating layer 12 covering the first semiconductor layer pattern, and a first metal layer pattern disposed on the second insulating layer 12, the first metal layer pattern being formed in the display area 100, the first metal layer pattern including at least the first gate electrode 22 and the first capacitor electrode 41, as shown in fig. 7.

In an exemplary embodiment, this patterning process is referred to as a second patterning process, and after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, a first insulating layer 11 disposed on the substrate 10, and a second insulating layer 12 disposed on the first insulating layer 11.

(4) And forming a second metal layer pattern. In an exemplary embodiment, the forming of the second metal layer pattern may include: on the substrate on which the aforementioned patterns are formed, a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer 13 covering the first metal layer pattern and a second metal layer pattern disposed on the third insulating layer 13, where the second metal layer pattern is formed in the display area 100, and the second metal layer pattern at least includes the second capacitor electrode 42 and the shielding layer 51, as shown in fig. 8. In an exemplary embodiment, the position of the second capacitive electrode 42 corresponds to the position of the first capacitive electrode 41, i.e. the orthographic projection of the second capacitive electrode 42 on the substrate overlaps the orthographic projection of the first capacitive electrode 41 on the substrate.

In an exemplary embodiment, this patterning process is referred to as a third patterning process, after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, and a first insulating layer 11 and a first composite insulating layer sequentially stacked on the substrate 10, where the first composite insulating layer includes a second insulating layer 12 and a third insulating layer 13.

(5) A second active layer pattern is formed. In an exemplary embodiment, the forming of the second active layer pattern may include: on the substrate on which the aforementioned patterns are formed, a fourth insulating film and a second semiconductor film are sequentially deposited, and the second semiconductor film is patterned through a patterning process to form a fourth insulating layer 14 covering the entire substrate 10 and a second semiconductor layer pattern disposed on the fourth insulating layer 14, the second semiconductor layer pattern being formed on the display region 100, the second semiconductor layer pattern including at least a second active layer 31, as shown in fig. 9. In the exemplary embodiment, the position of the second active layer 31 corresponds to the position of the shielding layer 51, i.e., the orthographic projection of the second active layer 31 on the substrate is within the range of the orthographic projection of the shielding layer 51 on the substrate. In an exemplary embodiment, this patterning process is referred to as a fourth patterning process, and after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, and a first insulating layer 11, a first composite insulating layer, and a fourth insulating layer 14 sequentially stacked on the substrate 10.

In an exemplary embodiment, the second semiconductor thin film may employ an oxide, and the oxide may be any one or more of: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor thin film may employ Indium Gallium Zinc Oxide (IGZO) having higher electron mobility than amorphous silicon.

In an exemplary embodiment, the distance between the second active layer 31 and the substrate is greater than the distance between the first active layer 21 and the substrate.

In an exemplary embodiment, the thickness of the fourth insulating layer 14 may be about 2500 to 3500 angstroms, and the thickness of the second active layer 31 may be about 300 to 500 angstroms. In some possible implementations, the thickness of the fourth insulating layer 14 may be about 2800 angstroms to 3200 angstroms, and the thickness of the second active layer 31 may be about 350 angstroms to 450 angstroms.

(6) And forming a third metal layer pattern. In an exemplary embodiment, the forming of the third metal layer pattern may include: on the substrate on which the aforementioned patterns are formed, a fifth insulating film and a third metal film are sequentially deposited, and the third metal film and the fifth insulating film are patterned through a patterning process to form a fifth insulating layer 15 disposed on the second active layer 31 and a third metal layer pattern disposed on the fifth insulating layer 15, where the fifth insulating layer 15 and the third metal layer pattern are formed in the display region 100, and the third metal layer pattern at least includes the second gate electrode 32, as shown in fig. 10. In an exemplary embodiment, an orthographic projection of the second gate electrode 32 on the substrate substantially overlaps with an orthographic projection of the fifth insulating layer 15 on the substrate.

In an exemplary embodiment, this patterning process is referred to as a fifth patterning process, and after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, and a first insulating layer 11, a first composite insulating layer, and a fourth insulating layer 14 sequentially stacked on the substrate 10.

In an exemplary embodiment, the thickness of the third metal layer may be about 2000 to 3000 angstroms. In some possible implementations, the thickness of the third metal layer may be approximately 2300 to 2700 angstroms.

(7) A sixth insulating layer pattern is formed. In an exemplary embodiment, the forming of the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate with the patterns, patterning the sixth insulating film by a patterning process to form a sixth insulating layer 16 pattern covering the third metal layer pattern, wherein the sixth insulating layer 16 is provided with a first via K1 and a first groove Q1, as shown in fig. 11. In the exemplary embodiment, two first vias K1 are formed at the positions of both ends of the first active layer 21 in the display region 100, the sixth insulating layer 16, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the first via K1 are etched away to expose the surfaces of both ends of the second active layer 31, respectively, and the first via K1 serves as the first active via. In an exemplary embodiment, the first groove Q1 is formed at the bonding region 200, and the sixth insulating layer 16, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the first groove Q1 are etched away to expose the surface of the first insulating layer 11.

In an exemplary embodiment, this patterning process is referred to as a sixth patterning process, after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, a first insulating layer 11, a first composite insulating layer, a fourth insulating layer 14, and a sixth insulating layer 16 sequentially stacked on the substrate 10, and a first groove Q1 is formed on the first composite insulating layer, the fourth insulating layer 14, and the sixth insulating layer 16.

In an exemplary embodiment, the thickness of the sixth insulating layer 16 may be about 4500 angstroms to about 6500 angstroms. In some possible implementations, the thickness of the sixth insulating layer 16 may be approximately 5000 angstroms to 6000 angstroms.

In an exemplary embodiment, the bonding region may include a first fan-out region, a bending region, a second fan-out region, a driving chip region, and a bonding pin region, the first fan-out region may be provided with a first power Line, a second power Line, and a plurality of Data transmission lines configured to connect Data lines (Data lines) of the display region in a fan-out (Fanout) routing manner, the first power Line (VDD) is configured to connect a high-level power Line of the display region 100, and the second power Line (VSS) is configured to connect a low-level power Line of the edge region. The second fan-out area can be provided with a plurality of data transmission lines led out in a fan-out routing mode. The driving chip region may be provided with a source driving circuit (Driver IC) configured to be connected with the plurality of data transmission lines of the second fan-out region. The binding pin region may be provided with a plurality of pins configured to be connected to a flexible circuit board (FPC). The first groove Q1 formed in the bonding region 200 is located in the bending region in the bonding region 200 to reduce the thickness of the bending region, so that the bonding region 200 is bent to the back of the display substrate to reduce the bezel. In an exemplary embodiment, the process of forming the first groove Q1 is referred to as a Bending area first MASK (EBA MASK).

(8) And forming a fourth metal layer pattern. In an exemplary embodiment, the forming of the fourth metal layer pattern may include: on the substrate on which the foregoing pattern is formed, a fourth metal film is deposited, and the fourth metal film is patterned through a patterning process, and a fourth metal layer pattern is formed on the sixth insulating layer 16, the fourth metal layer pattern being formed on the display area 100, the fourth metal layer pattern including at least the first source electrode 23 and the first drain electrode 24, the first source electrode 23 and the first drain electrode 24 being connected to the first active layer 21 through the first via hole K1, respectively, as shown in fig. 12. In an exemplary embodiment, the first source electrode 23 and the first drain electrode 24 are referred to as first source/drain electrodes, and the first source electrode 23 and the first drain electrode 24 are respectively overlapped with a surface of the first active layer 21 on a side away from the substrate to form a front Contact (Just Contact) connection manner.

In an exemplary embodiment, after the first via hole is formed and before the first source and drain electrodes are formed, a process of performing high temperature annealing (about 450 ℃) on the first active layer and a process of cleaning the first active layer may be further included to reduce contact resistance and improve connection quality.

According to the preparation process, the first source and drain electrodes are formed after the first via hole is formed, so that the first source and drain electrodes are connected with the first active layer through the first via hole, the second active layer is not provided with the via hole, and the second active layer is completely covered by the sixth insulating layer. The second active layer is completely covered, so that the high-temperature annealing process and the cleaning process of the first active layer cannot influence the second active layer, the high-temperature annealing process cannot enable the second active layer to be deoxidized and conducted, the cleaning process cannot damage the second active layer, and the performance deterioration of the second transistor is effectively avoided.

In an exemplary embodiment, the current patterning process is referred to as a seventh patterning process, and after the current patterning process, the binding structure layer of the binding region 200 has the same structure as that after the sixth patterning process.

In an exemplary embodiment, the thickness of the fourth metal layer may be about 7000 to 9000 angstroms. In some possible implementations, the thickness of the fourth metal layer may be about 7200 angstroms.

(9) Forming a seventh insulating layer pattern. In an exemplary embodiment, the forming of the seventh insulating layer pattern may include: on the substrate on which the aforementioned pattern is formed, a seventh insulating film is deposited, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer 17 pattern covering the fourth metal layer pattern, wherein the seventh insulating layer 17 is provided with a second via hole K2, a third via hole K3, and a second groove Q2, as shown in fig. 13.

In an exemplary embodiment, two second vias K2 are formed in the display region 100 at positions where both ends of the second active layer 31 are located, the seventh insulating layer 17 in the second via K2 is etched away, a portion of the thickness of the sixth insulating layer 16 is etched away, but a portion of the thickness of the sixth insulating layer 16 remains, and a half-hole structure is formed, in which the insulating layer in the second via K2 of the half-hole structure covers the surface of the second active layer 31, that is, the surface of the second active layer 31 is not exposed. That is, the second via K2 is a via that is not fully opened, and is a half-opened via.

In an exemplary embodiment, the third via hole K3 is formed at the position of the first drain electrode 24 in the display region 100, and the seventh insulating layer 17 in the third via hole K3 is etched away to expose the surface of the first drain electrode 24.

In an exemplary embodiment, the second groove Q2 is formed at the position of the first groove Q1 in the strapping region 200, the seventh insulating layer 17, the sixth insulating layer 16, and the fourth insulating layer 14 within the second groove Q2 are etched away to expose the first groove Q1, and the first groove Q1 and the second groove Q2 together constitute a stepped groove structure. In an exemplary embodiment, the orthographic projection of the second groove Q2 on the substrate includes the orthographic projection of the first groove Q1 on the substrate, i.e., the second groove Q2 exposes the first groove Q1, and the first groove Q1 exposes the first insulating layer 11. In an exemplary embodiment, the process of forming the second trench Q2 is referred to as a second MASK (e.g., EBB MASK) of the Bending region.

In an exemplary embodiment, this patterning process is referred to as an eighth patterning process, after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, and a first insulating layer 11, a first composite insulating layer and a second composite insulating layer sequentially stacked on the substrate 10, the first composite insulating layer is formed with a first groove Q1 thereon, the second composite insulating layer is formed with a second groove Q2 thereon, the first composite insulating layer includes a second insulating layer 12 and a third insulating layer 13, and the second composite insulating layer includes a fourth insulating layer 14, a sixth insulating layer 16 and a seventh insulating layer 17.

(10) A first planarization layer pattern is formed. In an exemplary embodiment, forming the first flat layer pattern may include: on the substrate on which the pattern is formed, a first flat film is coated, and the first flat film is patterned through a patterning process to form a pattern of a first flat layer 18, wherein a fourth via hole K4, a fifth via hole K5 and a third groove Q3 are formed on the first flat layer 18, as shown in fig. 14.

In the exemplary embodiment, the first flat layer 18 completely fills the first and second grooves Q1 and Q2 at the binding region 200, the third groove Q3 is formed on the first flat layer 18 of the binding region 200, and the position of the third groove Q3 corresponds to the position of the second groove Q2.

In an exemplary embodiment, a fifth via hole K5 is formed in the display area 100 at the position of the third via hole K3, the first planarization layer 18 within the fifth via hole K5 is removed to communicate with the third via hole K3, and thus the fifth via hole K5 exposes the surface of the first drain electrode 24. In an exemplary embodiment, the fifth via hole K5 is referred to as a connection electrode via hole.

In an exemplary embodiment, two fourth vias K4 are formed in the display region 100 at the positions of the two second vias K2, the first planarization layer 18 in the fourth via K4 is removed to communicate with the second via K2, and the remaining thickness of the sixth insulating layer 16 in the second via K2 of the half-hole structure is etched away by continuing etching, so that the communicating second vias K2 and fourth vias K4 expose the surface of the second active layer 31.

In an exemplary embodiment, after the first planarization film is coated, a cured first planarization layer is formed through a curing annealing (around 230 ℃) process, and then the cured first planarization layer is patterned using a mask. And after a fourth via hole communicated with the second via hole is formed, continuously etching the remaining sixth insulating layer in the second via hole by using the first flat layer as a mask (Hard mask) to form a complete second active via hole exposing the second active layer, wherein the second active via hole comprises a second via hole and a fourth via hole.

According to the above-mentioned preparation process, it can be seen that in the exemplary embodiment of the present disclosure, the second active via hole is formed by using the patterning process twice, and in the eighth patterning process for forming the seventh insulating layer, the second via hole is a half-open hole, only the etching of a part of the depth in the via hole is achieved, and the second active layer is still covered by the insulating layer, so that the second active layer is not subjected to a deoxidation conduction due to the curing and annealing process of the planarization layer, and the performance deterioration of the second transistor is avoided. In the patterning process for forming the first flat layer, the solidified and annealed first flat layer is used as a mask, the formed fourth through hole is communicated with the second through hole, the second through hole is etched in the residual depth, the second active through hole which exposes the second active layer is formed completely, the electrical characteristics of the second active layer cannot be influenced in the process, and the performance deterioration of the second transistor is effectively avoided.

In an exemplary embodiment, this patterning process is referred to as a ninth patterning process, after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, and a first insulating layer 11, a first composite insulating layer, a second composite insulating layer, and a first flat layer 18 sequentially stacked on the substrate 10, wherein a first groove Q1 is formed on the first composite insulating layer, a second groove Q2 is formed on the second composite insulating layer, and a third groove Q3 is formed on the first flat layer 18.

In an exemplary embodiment, the mask used in the ninth patterning process and the mask used in the eighth patterning process may be the same mask, that is, the orthographic projection of the fourth via K4 on the substrate overlaps the orthographic projection of the second via K2 on the substrate, the orthographic projection of the fifth via K5 on the substrate overlaps the orthographic projection of the third via K3 on the substrate, and the orthographic projection of the third groove Q3 on the substrate overlaps the orthographic projection of the second groove Q2 on the substrate, so that the number of masks is reduced, and the production cost is reduced.

(11) Forming a fifth metal layer pattern. In an exemplary embodiment, the forming of the fifth metal layer pattern may include: on the substrate on which the foregoing pattern is formed, a fifth metal thin film is deposited, and the fifth metal thin film is patterned by a patterning process, and a fifth metal layer pattern including at least the second source electrode 33, the second drain electrode 34, the connection electrode 52, and the connection line 53 is formed on the first planarization layer 18, as shown in fig. 15.

In an exemplary embodiment, the second source electrode 33 and the second drain electrode 34 are formed in the display area 100 and connected to the second active layer 31 through the second active via, respectively, and the second source electrode 33 and the second drain electrode 34 overlap with a surface of the second active layer 31 on a side away from the substrate to form a front contact connection.

In the exemplary embodiment, the connection electrode 52 is formed at the display region 100, and is connected to the first drain electrode 24 through the communicated third and fifth vias K3 and K5.

In the exemplary embodiment, the connection line 53 is formed on the bonding region 200, and the connection line 53 is disposed on the first planarization layer 18 within the third groove Q3.

In an exemplary embodiment, this patterning process is referred to as a tenth patterning process, after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, a first insulating layer 11, a first composite insulating layer, a second composite insulating layer, a first flat layer 18 and a connection line 53 sequentially stacked on the substrate 10, the first composite insulating layer is formed with a first groove Q1 thereon, the second composite insulating layer is formed with a second groove Q2 thereon, the first flat layer 18 completely fills the first groove Q1 and the second groove Q2, the first flat layer 18 is formed with a third groove Q3 thereon, and the connection line 53 is disposed in the third groove Q3.

In an exemplary embodiment, the thickness of the fifth metal layer may be about 7000 to 9000 angstroms. In some possible implementations, the thickness of the fifth metal layer may be about 7200 angstroms.

(12) A second flat layer pattern is formed. In an exemplary embodiment, forming the second flat layer pattern may include: a second flat film is coated on the substrate on which the patterns are formed, the second flat film is patterned through a patterning process to form a second flat layer 19 pattern covering the fifth metal layer pattern, a sixth through hole K6 is formed in the second flat layer 19, the sixth through hole K6 is formed in the display area 100 where the connection electrode 52 is located, the second flat layer 19 in the sixth through hole K6 is removed, and the surface of the connection electrode 52 is exposed, as shown in fig. 16. In an exemplary embodiment, the sixth via K6 is referred to as an anode via.

In an exemplary embodiment, this patterning process is referred to as an eleventh patterning process, after this patterning process, the binding structure layer of the binding region 200 includes a substrate 10 disposed on the glass carrier 1, a first insulating layer 11, a first composite insulating layer, a second composite insulating layer, a first planarization layer 18, a connection line 53, and a second planarization layer 19 sequentially stacked on the substrate 10, the first composite insulating layer has a first groove Q1 formed thereon, the second composite insulating layer has a second groove Q2 formed thereon, the first planarization layer 18 completely fills the first groove Q1 and the second groove Q2, the first planarization layer 18 has a third groove Q3 formed thereon, the connection line 53 is disposed in the third groove Q3, and the second planarization layer 19 completely fills the third groove Q3 and covers the connection line 53.

(13) An anode pattern is formed. In an exemplary embodiment, the forming of the anode pattern may include: on the substrate on which the aforementioned pattern is formed, a conductive film is deposited, the conductive film is patterned through a patterning process, and an anode 301 pattern is formed on the second planarization layer 19, the anode 301 is formed in the display area 100, and the anode 301 is connected to the connection electrode 52 through the sixth via hole K6, as shown in fig. 17.

In an exemplary embodiment, the current patterning process is referred to as a twelfth patterning process, and after the current patterning process, the structure of the bonding region 200 is the same as that after the eleventh patterning process.

(14) Forming a pixel definition pattern. In an exemplary embodiment, forming the pixel defining pattern may include: a pixel defining pattern, which is formed on the display region 100 and includes at least a Pixel Defining Layer (PDL)302 and an isolation Pillar (PS)305, is formed by coating a pixel defining film on the substrate on which the aforementioned pattern is formed and patterning the pixel defining film through a patterning process, as shown in fig. 18.

In an exemplary embodiment, a pixel opening is formed on the pixel defining layer 302, the pixel defining thin film in the pixel opening is developed to expose the surface of the anode 301, and the isolation pillar 305 is disposed on the pixel defining layer 302.

In an exemplary embodiment, the pixel defining layer 302 and the isolation pillars 305 may be formed through a single patterning process using a gray-tone mask.

In an exemplary embodiment, the current patterning process is referred to as a thirteenth patterning process, and after the current patterning process, the structure of the binding region 200 is the same as that after the eleventh patterning process.

In an exemplary embodiment, the subsequent preparation process may include: and sequentially forming an organic light-emitting layer, a cathode and an encapsulation layer on the substrate on which the pattern is formed. The organic light emitting layer is connected to the anode through the pixel opening, and the cathode is disposed on and connected to the organic light emitting layer. Since the anode is connected to the connection electrode, which is connected to the first drain electrode, the connection of the organic light emitting layer to the first drain electrode is achieved.

In an exemplary embodiment, the organic light Emitting Layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a light Emitting Layer (EML), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked one on another. In an exemplary embodiment, the hole injection layers of all the sub-pixels may be a common layer connected together, the hole transport layers of all the sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated, and the hole blocking layer may be a common layer connected together.

In an exemplary embodiment, the encapsulation layer may include a stacked structure of a first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer is made of an inorganic material, the second encapsulation layer is made of an organic material, the third encapsulation layer is made of an inorganic material, the stacked structure of the inorganic material/the organic material/the inorganic material is formed, and the organic material layer is disposed between the two inorganic material layers, so that it is ensured that external moisture cannot enter the light emitting structure layer. In an exemplary embodiment, the thickness of the first encapsulation layer may be about 800nm to 1200nm, the thickness of the second encapsulation layer may be about 100000nm to 150000nm, and the thickness of the third encapsulation layer may be about 800nm to 1200 nm.

In an exemplary embodiment, the process of preparing the display substrate may further include: the display substrate is peeled off from the glass carrier by a peeling process, a layer of back film is attached to the back surface (the surface of the substrate 10 away from the film layer) of the display substrate by a roller attaching method, and cutting is performed by using a cutting device, and the like, which is not limited in the disclosure.

In example embodiments, the first, second, third, fourth, fifth, sixth, and seventh insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer is referred to as a Buffer (Buffer) layer for improving the water and oxygen resistance of the substrate, the second, third and fifth insulating layers are referred to as a Gate Insulating (GI) layer, the fourth and sixth insulating layers are referred to as an interlayer Insulating (ILD) layer, and the seventh insulating layer is referred to as a Passivation (PVX) layer. The first metal thin film, the second metal thin film, the third metal thin film, the fourth metal thin film, and the fifth metal thin film may employ a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, or the like. The conductive thin film may be a single layer of a transparent conductive material, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), or may be a composite layer of a metal material and a transparent conductive material, such as Ag/ITO, Ag/IZO, ITO/Ag/ITO, or the like. The pixel defining layer may employ polyimide, acryl, polyethylene terephthalate, or the like. The cathode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

In the display substrate formed by the foregoing process, the first active layer 21, the first gate electrode 22, the first source electrode 23 and the first drain electrode 24 constitute a first transistor, the first transistor is a low temperature polysilicon thin film transistor, the second active layer 31, the second gate electrode 32, the second source electrode 33 and the second drain electrode 34 constitute a second transistor, the second transistor is an oxide thin film transistor, the first capacitor electrode and the second capacitor electrode constitute a storage capacitor, and the storage capacitor can compensate for a threshold voltage of the driving transistor in the pixel driving circuit. In an exemplary embodiment, the first transistor may be a driving transistor in the pixel driving circuit, and the second transistor may be a switching transistor in the pixel driving circuit.

A display substrate with a traditional structure is formed by adopting 14 patterning processes, comprises a first drain-source electrode and a second drain-source electrode which are arranged in the same layer and are formed by the same patterning process. The preparation process of the display substrate comprises the following steps: (1) forming a first insulating layer and an LTPS active layer on a substrate; (2) forming a second insulating layer and a first gate electrode; (3) forming a third insulating layer and a shielding layer; (4) forming a fourth insulating layer and an Oxide active layer; (5) forming a fifth insulating layer and a second gate electrode; (6) forming a sixth insulating layer, and forming a low temperature polysilicon (CNT-L) via hole exposing the LTPS active layer on the sixth insulating layer; (7) forming an Oxide (CNT-O) via hole exposing the Oxide active layer on the sixth insulating layer; (8) forming a first drain-source electrode and a second drain-source electrode; (9) forming a seventh insulating layer, and forming a via hole exposing the first drain electrode on the seventh insulating layer; (10) forming a first flat layer, and forming a through hole exposing the first drain electrode on the first flat layer; (11) forming a connection electrode; (12) forming a second flat layer, and forming a through hole exposing the connection electrode on the second flat layer; (13) forming an anode; (14) and forming a pixel definition layer and an isolation column. In the preparation process, because the depth of the CNT-L through hole of the first source-drain electrode connected with the LTPS active layer is deeper, the depth of the CNT-O through hole of the second source-drain electrode connected with the Oxide active layer is shallower, the depth difference between the CNT-L through hole and the CNT-O through hole is larger, the requirement on a synchronous etching process is very high, and the process difficulty is higher, the CNT-L through hole and the CNT-O through hole are respectively formed by adopting different patterning processes, the number of patterning processes is large, the production cost is high, and the performance of a transistor is poor. For the via holes formed by adopting different patterning processes, both the CNT-L via hole and the CNT-O via hole are formed first and then, and the CNT-O via hole and the CNT-L via hole are formed first and then, the problem of poor transistor performance is caused. For example, after the CNT-L via is formed, in the CNT-O via formation process, the low-temperature polysilicon exposed in the CNT-L via is oxidized, so that a cleaning process needs to be set after the CNT-O via is formed, and a Buffered Oxide Etch solution (BOE for short) is used to clean the low-temperature polysilicon in the CNT-L via, but the Buffered Oxide Etch solution etches the Oxide exposed in the CNT-O via, so that the contact resistance between the second drain-source electrode and the Oxide active layer is increased, which results in the deterioration of the uniformity of the threshold voltage (Vth) and the on-current (Ion) of the two transistors. For another example, after the CNT-O via is formed, in the process of forming the CNT-L via, a high temperature annealing (around 450 ℃) of the low temperature polysilicon active layer may deoxidize the oxide exposed in the CNT-O via, resulting in poor performance of the second transistor, deteriorating uniformity of threshold voltage and on-current of the two transistors.

According to the display substrate provided by the exemplary embodiment of the disclosure, the CNT-O via hole is formed after the first drain-source electrode is formed, so that the second active layer is not subjected to deoxidation and conductor formation by a high-temperature annealing process of the low-temperature polysilicon, the second active layer is not damaged by a cleaning process of the low-temperature polysilicon, the lapping quality of the second drain-source electrode and the second source electrode is ensured, the performance deterioration of the second transistor is avoided, the uniformity of threshold voltages and starting currents of the low-temperature polysilicon thin film transistor and the oxide thin film transistor is ensured, the yield is improved, and the display effect is improved.

According to the display substrate provided by the exemplary embodiment of the disclosure, the CNT-O via hole is formed by adopting two patterning processes, and in the eighth patterning process for forming the seventh insulating layer, partial-depth etching of the CNT-O via hole (i.e., half-open of the CNT-O via hole) is realized, so that the second active layer is not subjected to oxidation conductor removal by a subsequent curing annealing (about 230 ℃) process of the planarization layer, and performance deterioration of the second transistor is avoided. In the ninth patterning process for forming the first flat layer, the first flat layer after curing and annealing is used as a mask (Hard mask) to etch the CNT-O through hole in the residual depth, so that the complete CNT-O through hole exposing the second active layer is formed, the connection between the second drain-source electrode and the second active layer is realized, the performance deterioration of the second transistor is avoided, the uniformity of threshold voltage and starting current of the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor is ensured, and the yield is improved.

The display substrate provided by the exemplary embodiment of the disclosure has the advantages that through a reasonable process flow, the process difficulty is greatly reduced, the process requirements are greatly reduced, the process is simplified, the number of patterning processes is reduced, and the production cost is saved. The preparation process of the display substrate in the exemplary embodiment of the disclosure has the advantages of simple process and good process compatibility, is beneficial to ensuring the uniformity of two transistors, improves the yield and reduces the production cost.

The structure and the manufacturing process thereof shown in the present disclosure are only an exemplary illustration, and in an exemplary embodiment, the corresponding structure may be changed and a patterning process may be added or reduced according to actual needs. For example, the material of the first active layer may include an oxide, and the material of the second active layer may include low temperature polysilicon. As another example, the OLED display substrate may be a top-emitting structure, or may be a bottom-emitting structure, and the transistor may be a top-gate structure, or may be a bottom-gate structure, or may be a single-gate structure, or may be a double-gate structure. For another example, other electrodes or leads may be disposed in the relevant film layer, and the disclosure is not limited thereto.

The present disclosure also provides a method of manufacturing a display substrate, which may include, in an exemplary embodiment:

s1, forming an active structure layer on the substrate, wherein the active structure layer comprises a first active layer and a second active layer;

s2, forming a first source-drain structure layer on the active structure layer, wherein the first source-drain structure layer comprises a first active via hole and a first source-drain electrode, and the first source-drain electrode is connected with the first active layer through the first active via hole;

and S3, forming a second source-drain structure layer on the first source-drain structure layer, wherein the second source-drain structure layer comprises a second active via hole and a second source-drain electrode, and the second source-drain electrode is connected with the second active layer through the second active via hole.

In an exemplary embodiment, step S1 may include:

forming a fifth insulating layer disposed on the second active layer and a second gate electrode disposed on the fifth insulating layer.

In an exemplary embodiment, step S2 may include:

In an exemplary embodiment, step S3 may include:

In an exemplary embodiment, forming a first planarization layer on the seventh insulating layer includes:

coating a flat film on the seventh insulating layer;

forming a first flat layer through a curing annealing process;

forming a fourth via hole communicating with the second via hole through a patterning process;

and etching the insulating layer in the second through hole by using the first flat layer as a mask to form a complete second active through hole exposing the second active layer.

The invention provides a preparation method of a display substrate, wherein a second active via hole is formed after a first drain-source electrode is formed, so that a high-temperature annealing process of low-temperature polycrystalline silicon does not enable a second active layer to be subjected to deoxidation conduction, a cleaning process of the low-temperature polycrystalline silicon does not damage a second active layer, the lapping quality of the second drain-source electrode and the second source electrode is ensured, the performance deterioration of a second transistor is avoided, the uniformity of threshold voltage and starting current of a low-temperature polycrystalline silicon thin film transistor and an oxide thin film transistor is ensured, and the yield is improved. The preparation method of the display substrate of the exemplary embodiment of the disclosure not only greatly reduces the process difficulty and the process requirement, but also simplifies the process, reduces the number of patterning processes and saves the production cost through a reasonable process flow. The preparation process of the display substrate in the exemplary embodiment of the disclosure has the advantages of simple process and good process compatibility, is beneficial to ensuring the uniformity of two transistors, improves the yield and reduces the production cost.

The present disclosure also provides a display device including the display substrate of the foregoing embodiment. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, etc.

Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the present disclosure is to be limited only by the terms of the appended claims.

29页详细技术资料下载

Display substrate, preparation method thereof and display device

相关技术

网友询问留言