阅读说明：本技术 一种tft阵列基板及其制备方法、显示装置 (TFT array substrate, preparation method thereof and display device ) 是由 宋泳锡 刘威 孙宏达 于 2021-01-12 设计创作，主要内容包括：本申请公开了一种TFT阵列基板及其制备方法、显示装置,其中TFT阵列基板,包括源极和漏极,所述源极和漏极之间形成凸起型结构,所述凸起型结构内部设置有第一栅极,所述源极和所述漏极在所述第一栅极平面的投影与所述第一栅极未交叠或接近未交叠。本申请实施例提供的TFT阵列基板,通过在漏极和源极之间形成向上的凸起型结构,将顶栅设置于凸起型结构内,控制顶栅与源漏极之间的覆盖面积,控制寄生电容、寄生电压的产生。此设计可以适用于窄通道或者宽通道的情形；同时,此设计还适用双栅结构,通过适用双栅来增大关态电流或者通过最大限度减小寄生电容或者寄生电压的产生从而增加通态电流。(The application discloses TFT array substrate and preparation method, display device thereof, wherein TFT array substrate, including source electrode and drain electrode, form protruding type structure between source electrode and the drain electrode, protruding type structure inside is provided with first grid, the source electrode with the projection of drain electrode in first grid plane with first grid is not overlapped or is close not overlapped. According to the TFT array substrate provided by the embodiment of the application, the upward convex structure is formed between the drain electrode and the source electrode, the top gate is arranged in the convex structure, the coverage area between the top gate and the source electrode and the drain electrode are controlled, and the generation of parasitic capacitance and parasitic voltage is controlled. This design can be adapted to either narrow or wide channel cases; meanwhile, the design is also applicable to a double-gate structure, and the on-state current is increased by applying the double-gate structure or by reducing the generation of parasitic capacitance or parasitic voltage to the maximum extent.)

1. A TFT array substrate comprises a source electrode and a drain electrode, and is characterized in that a raised structure is formed between the source electrode and the drain electrode, a first grid electrode is arranged in the raised structure, and the projection of the source electrode and the drain electrode on the plane of the first grid electrode is not overlapped or nearly not overlapped with the first grid electrode.

2. The TFT array substrate of claim 1, wherein the source and drain electrodes each have a body, a longitudinal extension and a lateral extension disposed thereon, the longitudinal extension being disposed on opposite sides of the source and drain bodies, the lateral extension being disposed on top of the longitudinal extension.

3. The TFT array substrate of claim 2, wherein the lateral extension on the source electrode is a first lateral extension, the lateral extension on the drain electrode is a second lateral extension, and an inner edge of the first lateral extension and an inner edge of the second lateral extension are aligned or nearly aligned with two side edges of the first gate electrode, respectively.

4. The TFT array substrate of claim 1, further comprising an active layer, wherein the drain electrode and the source electrode are in contact with the active layer through a via disposed on the first interlayer dielectric layer.

5. The TFT array substrate of claim 4, wherein a first gate insulating layer is disposed between the first gate electrode and the active layer, and a second interlayer dielectric layer is filled in the raised structure around the first gate electrode and the first gate insulating layer.

6. The TFT array substrate according to claim 4 or 5, further comprising a substrate on which a light-shielding layer and a first flat layer are disposed, the first flat layer covering the light-shielding layer.

7. The TFT array substrate of claim 6, wherein a first buffer layer is disposed between the first planar layer and the active layer.

8. The TFT array substrate of claim 4 or 5, further comprising a second gate disposed on a substrate, wherein a boss is disposed on the substrate to mate with the second gate.

9. The TFT array substrate of claim 8, wherein the second gate electrode is disposed at a corresponding position below the raised structure, and the width of the second gate electrode is smaller than the width of a channel formed by the source electrode and the gate electrode on the active layer.

10. The TFT array substrate of claim 8, wherein a second buffer layer or a second gate insulating layer is disposed between the second gate electrode and the active layer.

11. The TFT array substrate of claim 10, wherein a second flat layer is disposed between the second buffer layer or the second gate insulating layer and the substrate, and the second flat layer does not cover an upper surface of the second gate.

12. The TFT array substrate of claim 8, wherein the second gate covers a side surface of the mesa and extends on the substrate to an outside of the mesa.

13. A TFT array substrate manufacturing method for manufacturing the TFT array substrate according to any one of claims 1 to 7, the method comprising:

forming a light-shielding layer on a substrate;

coating spin-coating silica glass on the substrate and the shading layer to serve as a first flat layer;

forming a first buffer layer on the first planarization layer;

forming an active layer on the first buffer layer;

forming a first gate insulating layer on the active layer;

manufacturing a metal electrode on the first grid insulation layer to serve as a first grid;

forming an interlayer dielectric layer above the buffer layer or the second gate insulating layer, and forming a via hole in which a drain electrode and a source electrode are in contact with the buffer layer while forming the interlayer dielectric layer, wherein the interlayer dielectric layer covers the first gate and the first gate insulating layer;

and forming a source drain metal layer and patterning the source drain metal layer, wherein the pattern of the source drain metal layer comprises a source electrode and a drain electrode, the source electrode and the drain electrode form a main body through a via hole on the interlayer dielectric layer, a longitudinal extension part positioned on the opposite side of the main body of the source electrode and the drain electrode, and a transverse extension part positioned at the top of the longitudinal extension part.

14. A TFT array substrate manufacturing method for manufacturing the TFT array substrate according to any one of claims 8 to 12, the method comprising:

forming a boss on a substrate;

forming a second gate on the boss;

coating spin-coated silica glass on the substrate to serve as a second flat layer, wherein the second flat layer does not cover the upper surface of the second gate electrode;

forming a second buffer layer or a second gate insulating layer on the upper surface of the second flat layer and the upper surface of the second gate;

forming an active layer on the second buffer layer or the second gate insulating layer;

forming a first gate insulating layer on the active layer, and forming a metal electrode on the first gate insulating layer as a first gate;

forming an interlayer dielectric layer above the buffer layer or the second gate insulating layer, and forming a via hole in which a drain electrode and a source electrode are in contact with the buffer layer while forming the interlayer dielectric layer, wherein the interlayer dielectric layer covers the first gate and the first gate insulating layer;

and forming a source drain metal layer and patterning the source drain metal layer, wherein the pattern of the source drain metal layer comprises a source electrode and a drain electrode, the source electrode and the drain electrode form a main body through a via hole on the interlayer dielectric layer, a longitudinal extension part positioned on the opposite side of the main body of the source electrode and the drain electrode, and a transverse extension part positioned at the top of the longitudinal extension part.

15. The method for manufacturing a TFT array substrate according to claim 14, wherein the substrate is a glass substrate, and the step of forming the projection on the substrate includes:

forming the boss by etching;

or photoetching by using a high-heat-resistance glue material to form the boss.

16. The method for manufacturing a TFT array substrate according to claim 14, wherein the substrate is a plastic substrate, and the step of forming the projection on the substrate includes:

forming the boss by half-tone exposure using a photosensitive PI material;

or using a photomask to carry out dry etching to remove other substrate parts except the lug boss;

or the mesa may be formed using a nanoimprint process.

17. A display device comprising the TFT array substrate according to any one of claims 1 to 12.

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a TFT array substrate, a preparation method thereof and a display device.

Background

Liquid crystal displays (TFT-LCDs) based on Thin Film Transistor (TFT) array substrates have advantages beyond those of any flat panel display and Cathode Ray Tube (CRT), such as thin, light weight, excellent picture quality, low power consumption, long lifetime, digitization, etc. The display screen is widely applied to various products with large, medium and small sizes, gradually replaces the traditional CRT display, quickly enters the daily life of people, and almost covers the main electronic products of the current information society. Such as televisions, monitors, laptops, cell phones, PDAs, GPS, in-vehicle displays, instrumentation, public displays, and medical displays, to name a few.

However, since the liquid crystal display is a passive display device that adjusts the arrangement state of liquid crystal molecules by an electric field to realize light flux modulation, a fine active driving matrix (Array) is required to match the deflection state of liquid crystal in each pixel region.

In the prior art, to improve the conductivity of the conductive channel of the active layer, it is possible to increase the gate area of the TFT or to use a dual-gate thin film transistor. The dual gate thin film transistor is widely used because it does not reduce the aperture ratio of the array substrate, and improves the conductivity of the conductive channel of the active layer.

However, whether the gate area is increased or the dual gate structure is used, parasitic capacitance and parasitic voltage may be generated, for example, parasitic capacitance between the gate and the source and drain, as well as parasitic capacitance between the bottom gate and the active layer in the dual gate structure. For the case of the top gate, the parasitic capacitance and the parasitic voltage between the top gate and the source and drain can be controlled through the self-aligned design of the top gate; however, in the case of the bottom gate, this design is not applicable, and the buffer layer on the bottom gate cannot prevent the generation of parasitic voltage or parasitic capacitance in the coverage area of the bottom gate and the active layer.

Disclosure of Invention

In view of the above-mentioned defects or shortcomings in the prior art, it is desirable to provide a TFT array substrate, a method for manufacturing the same, and a display device, which can effectively reduce parasitic capacitance and parasitic voltage on the thin film transistor array substrate.

Further, a TFT array substrate comprises a source electrode and a drain electrode, and is characterized in that a protrusion type structure is formed between the source electrode and the drain electrode, a first grid electrode is arranged in the protrusion type structure, and the projection of the source electrode and the drain electrode on the plane of the first grid electrode is not overlapped or is close to not overlapped with the first grid electrode.

Further, the source and drain electrodes are each provided with a body, a longitudinal extension disposed on opposite sides of the source and drain body, and a lateral extension disposed on top of the longitudinal extension.

Further, the lateral extension on the source electrode is a first lateral extension, the lateral extension on the drain electrode is a second lateral extension, and an inner edge of the first lateral extension and an inner edge of the second lateral extension are aligned or nearly aligned with two side edges of the first gate electrode, respectively.

Further, the transistor also comprises an active layer, and the drain electrode and the source electrode are in contact with the active layer through a via hole arranged on the first interlayer dielectric layer.

Further, a first gate insulating layer is arranged between the first gate and the active layer, and a second interlayer dielectric layer is filled around the first gate and the first gate insulating layer in the raised structure.

The light-shielding layer is arranged on the substrate, the first flat layer is arranged on the light-shielding layer, and the first flat layer covers the light-shielding layer.

Further, a first buffer layer is arranged between the first flat layer and the active layer.

In a second aspect, the present application provides a TFT array substrate manufacturing method for manufacturing the TFT array substrate as described above, wherein the method includes:

forming a light-shielding layer on a substrate;

coating spin-coating silica glass on the substrate and the shading layer to serve as a first flat layer;

forming a first buffer layer on the first planarization layer;

forming an active layer on the first buffer layer;

forming a first gate insulating layer on the active layer;

manufacturing a metal electrode on the first grid insulation layer to serve as a first grid;

forming an interlayer dielectric layer above the buffer layer or the second gate insulating layer, and forming a via hole in which a drain electrode and a source electrode are in contact with the buffer layer while forming the interlayer dielectric layer, wherein the interlayer dielectric layer covers the first gate and the first gate insulating layer;

and forming a source drain metal layer and patterning the source drain metal layer, wherein the pattern of the source drain metal layer comprises a source electrode and a drain electrode, the source electrode and the drain electrode form a main body through a via hole on the interlayer dielectric layer, a longitudinal extension part positioned on the opposite side of the main body of the source electrode and the drain electrode, and a transverse extension part positioned at the top of the longitudinal extension part.

Optionally, the TFT array substrate further includes a second gate disposed on the substrate, and a boss disposed on the substrate and engaged with the second gate.

Further, the second gate is arranged at a corresponding position below the raised structure, and the width of the second gate is smaller than the width of a channel formed by the source and the gate on the active layer.

Further, a second buffer layer or a second gate insulating layer is disposed between the second gate and the active layer.

Further, a second flat layer is arranged between the second buffer layer or the second gate insulating layer and the substrate, and the second flat layer does not cover the upper surface of the second gate.

Further, the second gate covers a side surface of the boss and extends to an outer side of the boss on the substrate.

In a third aspect, the present application provides a TFT array substrate manufacturing method for manufacturing the TFT array substrate as described above, the method including:

forming a boss on a substrate;

forming a second gate on the boss;

coating spin-coated silica glass on the substrate to serve as a second flat layer, wherein the second flat layer does not cover the upper surface of the second gate electrode;

forming a second buffer layer or a second gate insulating layer on the upper surface of the second flat layer and the upper surface of the second gate;

forming an active layer on the second buffer layer or the second gate insulating layer;

forming a first gate insulating layer on the active layer, and forming a metal electrode on the first gate insulating layer as a first gate;

forming an interlayer dielectric layer above the buffer layer or the second gate insulating layer, and forming a via hole in which a drain electrode and a source electrode are in contact with the buffer layer while forming the interlayer dielectric layer, wherein the interlayer dielectric layer covers the first gate and the first gate insulating layer;

and forming a source drain metal layer and patterning the source drain metal layer, wherein the pattern of the source drain metal layer comprises a source electrode and a drain electrode, the source electrode and the drain electrode form a main body through a via hole on the interlayer dielectric layer, a longitudinal extension part positioned on the opposite side of the main body of the source electrode and the drain electrode, and a transverse extension part positioned at the top of the longitudinal extension part.

Optionally, the substrate is a glass substrate, and the method for forming the boss on the substrate includes:

forming the boss by etching;

or photoetching by using a high-heat-resistance glue material to form the boss.

Optionally, the substrate is a plastic substrate, and the method of forming a boss on the substrate includes:

forming the boss by half-tone exposure using a photosensitive PI material;

or using a photomask to carry out dry etching to remove other substrate parts except the lug boss;

or the mesa may be formed using a nanoimprint process.

In a fourth aspect, the present application provides a display device comprising the TFT array substrate described above.

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

according to the TFT array substrate provided by the embodiment of the application, the upward convex structure is formed between the drain electrode and the source electrode, the top gate is arranged in the convex structure, the coverage area between the top gate and the source electrode and the drain electrode are controlled, and the generation of parasitic capacitance and parasitic voltage is controlled. This design can be adapted to either narrow or wide channel cases; meanwhile, the design is also applicable to a double-gate structure, and the on-state current is increased by applying the double-gate structure or by reducing the generation of parasitic capacitance or parasitic voltage to the maximum extent.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another TFT array substrate according to an embodiment of the present disclosure;

fig. 3 is a schematic view of step SP1 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;

fig. 4 is a schematic view of step SP2 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;

fig. 5 is a schematic view of step SP3 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic view of step SP4 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic view of step SP5 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of steps SP6, 7 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;

fig. 9 is a schematic view of step SP8 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic view of step SP9 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;

fig. 11 is a schematic view of step SP9 of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Referring to fig. 1 in detail, the present application provides a TFT array substrate, which includes a source electrode 2 and a drain electrode 1, a protrusion-type structure is formed between the source electrode 2 and the drain electrode 1, a first gate electrode 4 is disposed inside the protrusion-type structure, and a projection of the source electrode 2 and the drain electrode 1 on a plane of the first gate electrode 4 is not overlapped or nearly not overlapped with the first gate electrode 4.

Wherein a body 101, a longitudinal extension 102 and a lateral extension 103 are disposed on each of the source 2 and the drain 1, the longitudinal extension 102 being disposed on opposite sides of the body 101 of the source 2 and the drain 1, the lateral extension 103 being disposed on top of the longitudinal extension 102.

The inner edges of the first lateral extension 103 on the source 2 and the first lateral extension 103 on the drain 1 are aligned or nearly aligned with the two side edges of the first gate 4.

It should be noted that, in order to improve the conductivity of the thin film transistor, the area of the gate electrode may be increased, but at the same time, an overlap portion may be formed between the source electrode 2S and the drain electrode 1D and the gate electrode G, and parasitic capacitance of the transistor may occur in the overlap portion, thereby causing coupling.

By forming the protrusion-type structure between the source electrode 2 and the drain electrode 1, the overlapping area of the gate electrode and the drain electrode 1 and the source electrode 2 can be controlled, and the occurrence of parasitic capacitance and parasitic voltage between the gate electrode and the source electrode 2 or the drain electrode 1 can be reduced.

What is meant by parasitics is that the capacitance is not designed in that place, but because there is always mutual capacitance between the component wiring patterns, as if it were parasitics between the wirings. When the parasitic capacitance or the parasitic voltage exceeds a certain level, the influence on the element is very large. In the embodiment of the present application, the projection of the source-drain and the top-gate plane is not overlapped with the first gate 4, so that the parasitic capacitance and the parasitic voltage are not generated, and when the projection of the source-drain and the top-gate plane is close to and is not overlapped with the first gate 4, the parasitic capacitance or the parasitic voltage may be generated, but the influence on the transistor is small, and the parasitic capacitance or the parasitic voltage may not be considered. In some embodiments, the "near non-overlapping" may be constrained to be 0-20%, preferably set to 0-10%, of the total area of overlap of the first gate and source drain metals; when applied, the specific setting can be according to the frequency hertz of the element and the like.

Capacitance can be expressed as

Wherein epsilon_rAnd ε_oRespectively, a dielectric constant and an electrical constant, a denotes an overlapping area between two elements (e.g., flat plates) forming the capacitive element, and d denotes a distance between the two elements. As can be appreciated, the variable ε_rAnd ε_oTypically constant depending on the material selected, and increasing d may not be desirable as that would increase the thickness of the LCD panel.

It should be further noted that, in the embodiments of the present application, the consideration of the overlapping area of the source and drain electrodes and the top gate is to improve the conductivity of the array substrate, and in some embodiments, while the TFT array substrate satisfies the conductivity, it may be considered to limit the area of the top gate, so that the area of the first gate 4 is smaller, and the gate is formed below the blank position between the lateral extensions 103 at the opposite positions of the drain electrode 1 and the source electrode 2. No matter how the area of the gate is adjusted, the area is within the scope of the present application without departing from the principle of the present application.

Example one

A TFT array substrate is of a single-gate structure and comprises a substrate 100, wherein a first flat layer 300, a first buffer layer 400, a first interlayer dielectric layer 500 and a third flat layer 600 are sequentially arranged on the substrate 100. A light shielding layer 200 is further disposed between the substrate 100 and the first flat layer 300, and the first flat layer 300 covers the light shielding layer 200; an active layer 3 is further disposed between the first buffer layer 400 and the first interlayer dielectric layer 500; a first gate insulating layer 5 is arranged between the first gate 4 and the active layer 3, and a second interlayer dielectric layer 501 is filled around the first gate 4 and the first gate insulating layer 5 in the raised structure.

It should be noted that the drain electrode 1 and the source electrode 2 are partially in contact with the active layer 3 through a first via hole and a second via hole disposed on the first interlayer dielectric layer 500. The spacing distance between the first via hole and the second via hole defines the channel length. The protruding structure of the embodiment of the application can be suitable for different channel lengths W, different channel lengths W can be adjusted by adjusting the position between the source and drain main bodies 101, the height between the first grid 4 and the active layer 3 can be adjusted by adjusting the height of the longitudinal extension part 102, and the width area of the first grid 4 can be adjusted by adjusting the distance between the transverse extension parts 103.

In the embodiment of the present application, the TFT array substrate further includes an anode 6 disposed on the drain electrode 1 or the source electrode 2, and a cathode 7 disposed on the substrate 100. In the present embodiment, the anode 6 is disposed above the third planarization layer 600, and is connected to the source 2 through the anode 6 via hole disposed on the third planarization layer 600; the cathode 7 is disposed over the third planar layer and is coupled to the substrate 100 through the cathode 7 via disposed on the third planar layer 600, the cathode 7 via on the first interlayer dielectric layer 500, the cathode 7 on the buffer layer.

The substrate 100 is further provided with a projection on which the cathode 7 is provided and extends from the upper surface of the projection to the outside of the projection 8 via the side surface of the projection 8 toward the surface of the substrate 100. The cathode 7 may extend to the source and drain and below the 8-shaped convex structure formed by the source and drain, and in this case, the cathode 7 may be used as the light shielding layer 200. The light-shielding layer 200 can prevent the active layer 3 from generating a photocurrent when receiving external light.

When the anode 6 and/or the cathode 7 are transparent electrodes, the anode 6 and/or the cathode 7 may be made of, for example, ITO, IZO, ZnO or In₂O₃And (4) forming. When the anode electrode 6 and/or the cathode electrode 7 is a reflective electrode, the anode electrode 6 and/or the cathode electrode 7 may include, for example, a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof and a reflective film formed of ITO, IZO, ZnO, or In₂O₃The transparent film is formed. In an exemplary embodiment, the anode 6 and/or the cathode 7 may have a structure of ITO/Ag/ITO.

The application provides a TFT array substrate preparation method, which is used for preparing the TFT array substrate, and is characterized by comprising the following steps:

ST1 depositing a Light Shielding layer 200 (LS) on the substrate 100, and then etching the pattern of the Light Shielding layer 200; the light-shielding layer 200 can prevent the active layer 3 from generating a photocurrent when receiving external light. The light-shielding layer 200 may be made of a metal material or amorphous silicon (a-Si); the amorphous silicon (a-Si) can absorb light rays of the whole wave band, not only can realize the shading effect on the TFT active layer 3, but also has no problems of metal reflection, heating and the like.

ST2 coating spin-on silica glass as a first planarization layer 300 on the substrate 100 and the light-shielding layer 200; curing the SOG layer to form a silicon oxide layer with a flat surface, wherein the SOG (spin on glass Coating or spin on silicate glass) is prepared by uniformly Coating a liquid solvent containing a dielectric material on the surface of the wafer by spin Coating to fill the deposition gapA hole in the electrical layer. Then, heat treatment is carried out to remove the solvent and leave solidified (Curing) silicon dioxide (SiO) on the wafer surface₂) The dielectric material of (1).

ST3 forming a first buffer layer 400 on the first planarization layer 300; the material of the buffer layer includes, but is not limited to, dielectric materials such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), or novel organic insulating materials such as polysiloxane-based materials, acryl-based materials, and polyimide-based materials, or high dielectric constant materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx).

ST4 forming an active layer 3 on the first buffer layer 400; for example, depositing an amorphous silicon layer on the buffer layer; patterning the amorphous silicon layer; and transforming and crystallizing the amorphous silicon layer into a polycrystalline silicon (Poly-Si) layer through an excimer laser annealing process.

The active layer 3 may be a material of a metal oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), or Indium Gallium Zinc Tin Oxide (IGZTO). But may also be an amorphous silicon (a-Si) semiconductor layer, a polycrystalline silicon (p-Si) semiconductor layer, or an organic semiconductor layer.

ST5 forming a first gate insulating layer 5 on the active layer 3; a gate insulating layer is successively deposited on the active layer 3, for example, using a chemical vapor deposition method. The material of the gate insulating layer is usually silicon nitride, and silicon oxide, silicon oxynitride, aluminum oxide, or the like may be used.

ST6 forming a metal electrode on the first gate insulating layer 5 as a first gate 4; the gate metal material used for preparing the gate electrode is usually molybdenum, aluminum neodymium alloy, aluminum nickel alloy, molybdenum tungsten alloy, chromium or copper. In which a gate electrode is formed as a gate pattern on a certain region of a gate insulating layer by, for example, an exposure process and a chemical etching process using a gate electrode mask.

The material of the gate electrode may include at least one metal selected from, for example, molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu). However, the material of the gate electrode is not limited thereto.

The gate is made by using a mask made by a photolithography process, then using metal evaporation or sputtering and other methods, and using a metal lift-off process, or first using metal and then making a mask and then making a gate electrode by using a metal etching technology.

ST7 forming an interlayer dielectric layer over the buffer layer or the second gate insulating layer, and forming via holes in which the drain 1 and the source 2 are in contact with the buffer layer while forming the interlayer dielectric layer, the interlayer dielectric layer covering the first gate 4 and the first gate insulating layer 5; in a specific arrangement, the photo/Dry/STR process can be used to pattern the via pattern therein.

ST8 forms and patterns a source drain metal layer, the pattern of the source drain metal layer includes a source 2 and a drain 1, the source 2 and the drain 1 pass through a main body 101 formed by a via hole on the interlayer dielectric layer, a longitudinal extension 102 located on the opposite side of the main body 101 of the source 2 and the drain 1, and a transverse extension 103 located on the top of the longitudinal extension 102.

The thin film transistor in the TFT-LCD pixel structure controls the working state of the whole pixel, and plays an important role in the pixel structure. The retention rate of the TFT pixel charge is one of the important display parameters of the TFT-LCD. The retention rate of pixel charges has a large relationship with the off-state characteristics of the TFT device, and the larger the off-state resistance of the thin film transistor, i.e., the smaller the off-state current, the longer the retention time of the pixel charges.

Calculation formula of off-state current Ioff:

q、n、p、μ_e、μ_p、d_s: the electron charge amount, the electron density, the hole density, the electron mobility, the hole mobility, and the active layer 3 thickness, respectively.

As can be seen from the above, the off-state current Ioff is related to the width-to-length ratio W/L of the thin film transistor and the thickness ds of the active layer 3 in view of the device structure. Reducing the ratio of the width-to-length ratio W/L and the active layer 3 thickness ds is an effective way to reduce the off-state current, without taking into account other factors.

The effective channel length remains unchanged and therefore does not result in device shorting or increased leakage current. Under the condition of keeping the width of the source and the drain unchanged and not influencing the effective channel length, the depth of the source and the drain is increased, so that the resistance of the source and the drain is reduced, and the parasitic resistance of the source and the drain is greatly reduced.

Example two

A TFT array substrate has a double-gate structure, and further comprises a second grid electrode 10 arranged on a substrate 100, wherein a boss 8 matched with the second grid electrode 10 is arranged on the substrate 100. The second gate 10 is disposed at a corresponding position below the raised structure, and the width of the second gate 10 is smaller than the width of a channel formed by the source 2 and the gate on the active layer 3. The second gate 10 covers the side surface of the boss 8 and extends on the substrate 100 to the outside of the boss 8.

The structure comprises a substrate 100, wherein a second flat layer 301, a second buffer layer 401 or a second gate insulating layer, a first interlayer dielectric layer 500 and a third flat layer 600 are sequentially arranged on the substrate 100. The second planarization layer 301 does not cover the upper surface of the second gate 10; the second buffer layer 401 or the second gate insulating layer is disposed between the second gate electrode 10 and the active layer 3.

In the embodiment of the present application, the TFT array substrate further includes an anode 6 disposed on the drain electrode 1 or the source electrode 2, and a cathode 7 disposed on the substrate 100. In the present embodiment, the anode 6 is disposed above the third planarization layer 600, and is connected to the source 2 through the anode 6 via hole disposed on the third planarization layer 600; the cathode 7 is disposed over the third planar layer and is coupled to the substrate 100 through a cathode 7 via disposed on the third planar layer 600, a cathode 7 via on the first interlayer dielectric layer 500, the second buffer layer 401, or the cathode 7 on the second gate insulating layer.

The substrate 100 is further provided with a projection on which the cathode 7 is provided and extends from the upper surface of the projection to the outside of the projection 8 via the side surface of the projection 8 toward the surface of the substrate 100. The cathode 7 extends over the substrate 100 but does not contact the second gate 10. In this case, the cathode 7 may be used as the light shielding layer 200. The light-shielding layer 200 can prevent the active layer 3 from generating a photocurrent when receiving external light.

When the anode 6 and/or the cathode 7 are transparent electrodes, the anode 6 and/or the cathode 7 may be made of, for example, ITO, IZO, ZnO or In₂O₃And (4) forming. When the anode electrode 6 and/or the cathode electrode 7 is a reflective electrode, the anode electrode 6 and/or the cathode electrode 7 may include, for example, a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof and a reflective film formed of ITO, IZO, ZnO, or In₂O₃The transparent film is formed. In an exemplary embodiment, the anode 6 and/or the cathode 7 may have a structure of ITO/Ag/ITO.

The application provides a TFT array substrate preparation method, which is used for preparing the TFT array substrate, and is characterized by comprising the following steps:

SP1 as shown in fig. 3, a boss 8 is formed on a substrate 100; the substrate 100 may be a glass substrate or a plastic substrate, and the boss 8 may be formed by a different method for different types of substrates 100.

SP001 the substrate 100 is a glass substrate, and the method of forming the mesa 8 on the substrate 100 includes:

forming the boss 8 by etching;

or photoetching is carried out by utilizing a high-heat-resistance glue material to form the boss 8.

SP002 the substrate 100 is a plastic substrate, and the method of forming the projection 8 on the substrate 100 includes:

forming the boss 8 by half-tone exposure using a photosensitive PI material;

or dry etching is carried out by using a photomask to remove the other substrate 100 parts except the lug boss 8;

or the boss 8 is formed using a nanoimprint method.

SP2 as shown in fig. 4, a second gate electrode 10 and a cathode electrode 7 are formed on a substrate 100; the gate metal material used for preparing the gate electrode is usually molybdenum, aluminum neodymium alloy, aluminum nickel alloy, molybdenum tungsten alloy, chromium or copper. In which a gate electrode is formed as a gate pattern on a certain area of the substrate 100 through, for example, an exposure process and a chemical etching process using a gate electrode mask.

The second gate electrode 10 and the cathode electrode 7 can also exert a light-shielding effect, achieving a light-shielding effect on the TFT active layer 3.

SP3 as shown in fig. 5, coating spin-on silicon glass as a second flat layer 301 on the substrate 100, wherein the second flat layer 301 does not cover the upper surface of the second gate 10; the SOG layer is changed into a silicon oxide layer with a flat surface by curing the SOG layer, wherein SOG (spin on glass Coating or spin on silicate glass) is formed by uniformly Coating a liquid solvent containing a dielectric material on the surface of a wafer in a spin Coating manner so as to fill the holes of the recesses of the deposited dielectric layer. Thereafter, the solvent is removed by a heat treatment, leaving a cured (Curing) dielectric material on the wafer surface that approximates silicon dioxide (SiO 2).

SP4 as shown in fig. 6, a second buffer layer 401 or a second gate insulating layer is formed on the upper surface of the second planarization layer 301 and the upper surface of the second gate electrode 10; the materials of the insulating layer and the buffer layer include, but are not limited to, dielectric materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), novel organic insulating materials such as polysiloxane-based materials, acrylic-based materials, or polyimide-based materials, or high dielectric constant materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx).

SP5 as shown in fig. 7, an active layer 3 is formed on the second buffer layer 401 or the second gate insulating layer; for example, depositing an amorphous silicon layer on the buffer layer; patterning the amorphous silicon layer; and transforming and crystallizing the amorphous silicon layer into a polycrystalline silicon (Poly-Si) layer through an excimer laser annealing process.

The active layer 3 may be a material of a metal oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), or Indium Gallium Zinc Tin Oxide (IGZTO). But may also be an amorphous silicon (a-Si) semiconductor layer, a polycrystalline silicon (p-Si) semiconductor layer, or an organic semiconductor layer.

SP6 as shown in fig. 8, a first gate insulating layer 5 is formed on the active layer 3; a gate insulating layer is successively deposited on the active layer 3, for example, using a chemical vapor deposition method. The material of the gate insulating layer is usually silicon nitride, and silicon oxide, silicon oxynitride, aluminum oxide, or the like may be used.

SP7 as shown in fig. 8, a metal electrode is formed on the first gate insulating layer 5 as a first gate 4; the gate metal material used for preparing the gate electrode is usually molybdenum, aluminum neodymium alloy, aluminum nickel alloy, molybdenum tungsten alloy, chromium or copper. In which a gate electrode is formed as a gate pattern on a certain region of a gate insulating layer by, for example, an exposure process and a chemical etching process using a gate electrode mask.

The material of the gate electrode may include at least one metal selected from, for example, molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu). However, the material of the gate electrode is not limited thereto.

The gate is made by using a mask made by a photolithography process, then using metal evaporation or sputtering and other methods, and using a metal lift-off process, or first using metal and then making a mask and then making a gate electrode by using a metal etching technology.

SP8 as shown in fig. 9, forming an interlayer dielectric layer over the buffer layer or the second gate insulating layer, and forming via holes for the drain 1 and the source 2 to contact with the buffer layer simultaneously with the formation of the interlayer dielectric layer, the interlayer dielectric layer covering the first gate 4 and the first gate insulating layer 5; in a specific arrangement, the photo/Dry/SPR process can be used to pattern the via holes therein.

SP9 as shown in fig. 10 and 11, forming and patterning a source drain metal layer, where the pattern of the source drain metal layer includes a source 2 and a drain 1, the source 2 and the drain 1 pass through a body 101 formed by a via hole on the interlayer dielectric layer, a longitudinal extension 102 located on the opposite side of the body 101 of the source 2 and the drain 1, and a lateral extension 103 located on the top of the longitudinal extension 102.

In the field of display technology, the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, ink-jetting, etc.; the photolithography process refers to a process of forming a pattern by using a photoresist, a mask plate, an exposure machine, and the like, including processes of film formation, exposure, development, and the like. The corresponding patterning process may be selected according to the structure formed in the present invention.

The dual gate structure is mainly applied to maintain stable Vth uniformity and increase Ion in the TFT. A boss 8 of a glass or plastic substrate is formed on the substrate, a bottom gate is covered above the boss 8, the distance between the bottom gate and an active layer 3 is minimized, and therefore, the driving voltage is reduced to the maximum extent, and meanwhile, in a protrusion type structure area between the bottom gate and an upper source drain electrode, a bottom gate metal is placed below the area during design, and the generation of parasitic voltage (Cp, Cgs) is reduced or restrained to the maximum extent. In particular, when the distance between the active layer 3 and the bottom gate metal reaches 1.7um or more, no parasitic capacitance occurs.

The double-Gate TFT can be applied to a display area to improve an aperture ratio, and can also be applied to a Gate On Array (GOA) area to reduce the size of the GOA area, thereby reducing the edge size of the display device and facilitating the realization of a narrow frame of the display device.

The double-gate TFT can also be applied to an Electro-Static Discharge (ESD) circuit, and the size of the ESD circuit and the time required by Discharge are reduced. The ESD circuit is a conductive loop made of TFTs to prevent static electricity from damaging the screen of the display device during the manufacturing and subsequent use of the product, and if an instantaneous high voltage occurs on a certain trace on the array substrate, the current is averaged over the entire array substrate by the ESD circuit.

On the other hand, the application also provides a display device which comprises the single-gate TFT array substrate and the double-gate TFT array substrate.

In some regions where twice w (channel width) is needed, Ion can be increased by using a double gate to increase Ioff or minimize Cp, Cgs. In some pixel structures with large W difference, the pixel structure can be applied to OLED requiring small W or LED (uLED, QNED, etc.) requiring large W in a modified manner, and also can be applied to Hybrid LED display using large W TFT in which one or two of R G B sub-pixels use small W to deposit organic EL and the remaining sub-pixels deposit inorganic EL (LED, etc.).

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be construed as limiting the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Terms such as "disposed" and the like, as used herein, may refer to one element being directly attached to another element or one element being attached to another element through intervening elements. Features described herein in one embodiment may be applied to another embodiment, either alone or in combination with other features, unless the feature is otherwise inapplicable or otherwise stated in the other embodiment.

The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the scope of the described embodiments. It will be appreciated by those skilled in the art that many variations and modifications may be made to the teachings of the invention, which fall within the scope of the invention as claimed.