阅读说明：本技术 使用环境参数来进行编程脉冲控制 (Programming pulse control using environmental parameters ) 是由 C·J·比布 P·卡莱 于 2020-10-29 设计创作，主要内容包括：本申请案涉及使用环境参数来进行编程脉冲控制。一种方法包括：在存储器子系统处从主机系统接收与所述存储器子系统的使用相关联的配置参数；监视所述存储器子系统的环境参数,其中所述环境参数包括所述存储器子系统的特性和所述存储器子系统的环境,以及基于所述配置参数和环境参数为所述存储器子系统的编程脉冲特性选择值,所述编程脉冲特性至少包括编程脉冲电压。(The present application relates to using environmental parameters for program pulse control. One method comprises the following steps: receiving, at a memory subsystem, configuration parameters associated with use of the memory subsystem from a host system; monitoring an environmental parameter of the memory subsystem, wherein the environmental parameter includes a characteristic of the memory subsystem and an environment of the memory subsystem, and selecting a value for a programming pulse characteristic of the memory subsystem based on the configuration parameter and the environmental parameter, the programming pulse characteristic including at least a programming pulse voltage.)

1. A method, comprising:

receiving, at a memory subsystem, configuration parameters associated with use of the memory subsystem from a host system;

monitoring environmental parameters of the memory subsystem, wherein the environmental parameters include characteristics of the memory subsystem and an environment of the memory subsystem; and

selecting values for a programming pulse characteristic of the memory subsystem based on the configuration parameters and environmental parameters, the programming pulse characteristic including at least a programming pulse voltage.

2. The method of claim 1, wherein the configuration parameters comprise at least one of:

an expected environment in which the memory subsystem is used;

an expected location in which the memory subsystem is used; or

The expected type of use of the memory subsystem.

3. The method of claim 1, wherein the programming pulse characteristics further comprise at least one of a width of the programming pulse or a current of the programming pulse.

4. The method of claim 1, wherein the environmental parameters comprise:

a programming temperature, wherein the programming temperature is indicative of a temperature at which a portion of the memory subsystem is programmed;

a read temperature, wherein the read temperature is indicative of a temperature at which data is read from the memory subsystem;

a bit error rate of the memory subsystem, wherein the bit error rate indicates a number of bits that have been identified as incorrect during a time interval; and

a frequency of data refresh events, wherein the frequency of data refresh events indicates how frequently the memory subsystem has been refreshed.

5. The method of claim 1, wherein selecting the value for the programming pulse characteristic of the memory subsystem based on the environmental parameter comprises:

determining a bit error rate of the memory subsystem using a previous value of the programming pulse characteristic; and

adjusting the previous value of the programming pulse characteristic to reduce the bit error rate.

6. The method of claim 1, further comprising:

when selecting values for programming pulse characteristics of the memory subsystem, reducing weighting of previous statistics of an environmental parameter in view of the configuration parameter as the memory subsystem ages, wherein if the configuration parameter indicates that a first condition is satisfied, the weighting of the previous statistics is reduced at a faster rate than if the configuration parameter indicates that the first condition is not satisfied.

7. The method of claim 6, wherein the first condition is satisfied when the configuration parameter indicates an expected environment of the memory subsystem changes by more than a threshold amount within a defined time period.

8. A system, comprising:

a memory subsystem; and

a processing device operatively coupled with the memory subsystem to:

receiving, at the memory subsystem, configuration parameters associated with an expected usage environment of the memory subsystem from a host system;

selecting a value of a programming pulse voltage based on the configuration parameter;

monitoring environmental parameters of the memory subsystem, wherein the environmental parameters include characteristics of the memory subsystem and an environment surrounding the memory subsystem; and

adjusting the programming pulse voltage of the memory subsystem based on the environmental parameter and the configuration parameter.

9. The system of claim 8, wherein the environmental parameter comprises at least one of:

data associated with a temperature of the environment in which the memory subsystem is used; or

Data associated with use of the memory subsystem.

10. The system of claim 8, wherein the configuration parameter indicates an expected temperature change for the expected usage environment, and wherein a high expected temperature change indicates that previous statistics of environmental factors will be weighted less as the memory subsystem ages.

11. The system of claim 8, wherein to adjust the programming pulse voltage, the processing device is to:

determining that a bit error rate of the memory subsystem using the programming pulse voltage exceeds a threshold bit error rate; and

adjusting the programming pulse voltage to reduce the bit error rate of the memory subsystem.

12. The system of claim 8, wherein to select the value of the programming pulse voltage, the processing device is further to:

the value of the programming pulse voltage is selected in view of the intended use environment to provide data in the memory subsystem that is stable for a specified period of time.

13. The system of claim 12, wherein the processing device is further to:

increasing the programming pulse voltage in response to the environmental parameter indicating that stability of the data will decrease during the specified time period.

14. The system of claim 8, wherein the processing device is further to:

program pulse widths are adjusted in view of the configuration parameters and environmental parameters.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

receiving, at a memory subsystem, configuration parameters associated with an expected usage of the memory subsystem from a host system, wherein the expected usage comprises at least one of: an expected environment in which the memory subsystem is used, an expected location in which the memory subsystem is used, or an expected type of use of the memory subsystem;

monitoring environmental parameters of the memory subsystem, wherein the environmental parameters include a usage characteristic of the memory subsystem, an error rate of the memory subsystem, and a temperature of the memory subsystem; and

selecting values for programming pulse characteristics of the memory subsystem based on the configuration parameters and environmental parameters, the programming pulse characteristics including at least a programming pulse voltage and a programming pulse duration, wherein weights of previously recorded environmental parameter data decrease over time.

16. The non-transitory computer-readable storage medium of claim 15, wherein the configuration parameters comprise:

the intended environment in which the memory subsystem is used;

the expected location in which the memory subsystem is used; and

the expected usage type of the memory subsystem, wherein the expected usage type comprises an application for which the memory subsystem is used.

17. The non-transitory computer-readable storage medium of claim 15, wherein the programming pulse characteristics further comprise at least one of a width of the programming pulse or a current of the programming pulse.

18. The non-transitory computer-readable storage medium of claim 15, wherein the environmental parameters comprise:

a programming temperature, wherein the programming temperature is indicative of a temperature at which a portion of the memory subsystem is programmed;

a read temperature, wherein the read temperature is indicative of a temperature at which data is read from the memory subsystem;

a bit error rate of the memory subsystem, wherein the bit error rate indicates a number of bits that have been identified as incorrect during a time interval; and

a frequency of data refresh events, wherein the frequency of data refresh events indicates how frequently the memory subsystem has been refreshed.

19. The non-transitory computer-readable storage medium of claim 15, wherein selecting the value for the programming pulse characteristic of the memory subsystem based on the environmental parameter comprises:

determining a bit error rate of the memory subsystem using a previous value of the programming pulse characteristic; and

adjusting the previous value of the programming pulse characteristic to reduce the bit error rate.

20. The non-transitory computer-readable storage medium of claim 15, further comprising:

when selecting values for programming pulse characteristics of the memory subsystem, reducing weighting of previous statistics of an environmental parameter in view of the configuration parameter as the memory subsystem ages, wherein if the configuration parameter indicates that a first condition is satisfied, the weighting of the previous statistics is reduced at a faster rate than if the configuration parameter indicates that the first condition is not satisfied.

Technical Field

Embodiments of the present disclosure relate generally to memory subsystems and, more particularly, to using environmental parameters for program pulse control.

Background

The memory subsystem may be a storage device, a memory module, and a mix of storage devices and memory modules. The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, a host system may utilize a memory subsystem to store data at and retrieve data from memory components.

Disclosure of Invention

In one aspect, the present disclosure is directed to a method comprising: receiving, at a memory subsystem, configuration parameters associated with use of the memory subsystem from a host system; monitoring environmental parameters of the memory subsystem, wherein the environmental parameters include characteristics of the memory subsystem and an environment of the memory subsystem; and selecting values for a programming pulse characteristic of the memory subsystem based on the configuration parameters and environmental parameters, the programming pulse characteristic including at least a programming pulse voltage.

In another aspect, the present disclosure is directed to a system comprising: a memory subsystem; and a processing device operatively coupled with the memory subsystem to: receiving, at the memory subsystem, configuration parameters associated with an expected usage environment of the memory subsystem from a host system; selecting a value of a programming pulse voltage based on the configuration parameter; monitoring environmental parameters of the memory subsystem, wherein the environmental parameters include characteristics of the memory subsystem and an environment surrounding the memory subsystem; and adjusting the programming pulse voltage of the memory subsystem based on the environmental parameter and the configuration parameter.

In another aspect, the disclosure is directed to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving, at a memory subsystem, configuration parameters associated with an expected usage of the memory subsystem from a host system, wherein the expected usage comprises at least one of: an expected environment in which the memory subsystem is used, an expected location in which the memory subsystem is used, or an expected type of use of the memory subsystem; monitoring environmental parameters of the memory subsystem, wherein the environmental parameters include a usage characteristic of the memory subsystem, an error rate of the memory subsystem, and a temperature of the memory subsystem; and selecting values for programming pulse characteristics of the memory subsystem based on the configuration parameters and environmental parameters, the programming pulse characteristics including at least a programming pulse voltage and a programming pulse duration, wherein a weight of previously recorded environmental parameter data decreases over time.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention.

FIG. 1 illustrates an example computing environment including a memory subsystem in accordance with some embodiments of the present disclosure.

FIG. 2 is a flow diagram of an example method of controlling programming pulse characteristics in view of environmental parameters, in accordance with some embodiments of the present disclosure.

FIG. 3 is a flow diagram of an example method of adjusting program pulse characteristics in view of usage and environmental factors, in accordance with some embodiments of the present disclosure.

FIG. 4 illustrates an example program pulse control component in accordance with some embodiments of the present disclosure.

FIG. 5 is a flow diagram of an example method of controlling programming pulse characteristics based on environmental parameters, in accordance with some embodiments of the present disclosure.

FIG. 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure are directed to controlling and adjusting programming pulse characteristics in view of usage parameters and environmental parameters. The memory subsystem may be a storage device, a memory module, or a mix of storage devices and memory modules. Examples of memory devices and memory modules are described below in connection with FIG. 1. In general, host systems may utilize a memory subsystem that includes one or more memory components (also referred to below as "memory devices"). The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

To program data to the memory subsystem, the memory controller can apply a voltage on the gate of the NAND device to trap charge (e.g., electrons) in the floating gate of the NAND. The memory controller may apply the voltage in pulses (referred to as programming pulses). The amount of voltage and the width of the pulse may determine the amount of charge to be stored at the NAND device, and in turn program the state of the NAND. In some examples, the memory controller may apply a programming pulse, verify the state of the NAND, and then apply another programming pulse if desired. This pulse-verify-pulse sequence can ensure that the NAND is programmed correctly without applying larger voltages that could result in more damage to the NAND.

As the memory subsystem ages, the voltage (Vt) distribution of the NAND states of the memory cells tends to widen, and thus towards the end of the life of the memory subsystem, higher programming pulses may be required to ensure that the data can be read properly. Thus, memory controllers in conventional memory systems use programming pulses that take into account end-of-life conditions (i.e., start with a larger programming pulse voltage and/or width). However, using larger programming pulses at the beginning of the life of the memory subsystem may reduce the life of the memory components, as larger programming pulses may unnecessarily cause more damage to the NAND components than if lower programming pulses were used instead.

In addition, some memory subsystems used in embedded systems that tend to experience extreme temperatures, large shifts in temperature, or other environmental factors that cause data degradation may require large programming pulses to ensure that data is not lost in a worst case scenario. Conventionally, a larger programming pulse is used throughout the life of the memory subsystem. However, the memory subsystem may not always be used in a worst case scenario, and therefore uses large programming pulses, if not necessary. Thus, the lifetime of the memory subsystem may be significantly reduced due to the unnecessary use of larger programming pulses.

Aspects of the present disclosure address the above and other deficiencies by providing the ability to control programming pulse characteristics using environmental parameters. The memory subsystem may receive configuration parameters from a user that identify an intended use of the memory devices in the memory subsystem. Based on the intended use, a memory controller in a memory subsystem may determine an initial programming pulse, as well as weights associated with environmental parameters/statistics identified early in the life of the memory device. The memory controller may monitor environmental parameters from the sensors that identify conditions (e.g., temperature) of the environment surrounding the memory subsystem. Thus, the memory controller can monitor actual conditions, with the memory subsystem being placed in real time, and determine the appropriate programming pulses to reduce the amount of wear on the device, but still ensure that data is not lost due to changing conditions.

Thus, the ability to control the programming pulse characteristics based on usage and environment can substantially increase the lifetime of the memory subsystem. The advantages are particularly useful in embedded memory systems where replacement of the memory subsystem may be difficult or impossible.

FIG. 1 illustrates an example computing environment 100 including a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

Memory subsystem 110 may be a storage device, a memory module, or a mix of storage devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage device (UFS) drives, and Hard Disk Drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, host system 120 is coupled to different types of memory subsystems 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory subsystem 110. Host system 120 writes data to memory subsystem 110 and reads data from memory subsystem 110 using, for example, memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components that may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such a computing device that includes memory and a processing device. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, fibre channel, Serial Attached SCSI (Serial Attached SCSI), SAS), and the like. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled with the host system 120 over a PCIe interface, the host system 120 may further utilize an NVM express (NVMe) interface to access memory components, such as the memory device 130. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120.

The memory devices may include any combination of different types of non-volatile memory devices and/or volatile memory devices. Volatile memory devices (e.g., storage device 140) may be, but are not limited to, Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM).

Examples of non-volatile memory devices, such as memory device 130, include NAND (NAND) type flash memory. Each of the memory devices 130 may include one or more arrays of memory cells, such as Single Level Cells (SLC) or multi-level cells (MLC) (e.g., Three Level Cells (TLC) or four level cells (QLC)). In some embodiments, a particular memory component may include an SLC portion, as well as an MLC portion, a TLC portion, or a QLC portion of a memory cell. Each of the memory cells may store one or more bits of data for use by the host system 120. Further, the memory cells of memory device 130 may be grouped into memory pages or memory blocks, which may refer to units of memory components used to store data.

Although non-volatile memory components such as NAND type flash memory are described, memory device 130 may be based on any other type of non-volatile memory, such as Read Only Memory (ROM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), NOR (NOR) flash memory, Electrically Erasable Programmable Read Only Memory (EEPROM), and cross-point arrays of non-volatile memory cells. A cross-point array of non-volatile memory may perform bit storage based on changes in body resistance in conjunction with a stackable cross-meshed data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform a write-in-place operation in which non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells.

Memory subsystem controller 115 may communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130, among other such operations. Memory subsystem controller 115 may include hardware, such as one or more integrated circuits and/or discrete components, buffer memory, or a combination thereof. Memory subsystem controller 115 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor.

Memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

In some embodiments, local memory 119 may include memory registers that store memory pointers, acquired data, and so forth. Local memory 119 may also include Read Only Memory (ROM) for storing microcode. Although the example memory subsystem 110 in fig. 1 has been illustrated as including memory subsystem controller 115, in another embodiment of the present disclosure, memory subsystem 110 may not include memory subsystem controller 115, and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

In general, memory subsystem controller 115 may receive commands or operations from host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve a desired access to memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical and physical block addresses associated with the memory device 130. Memory subsystem controller 115 may further include host interface circuitry to communicate with host system 120 via a physical host interface. Host interface circuitry may convert commands received from the host system into command instructions to access memory device 130 and convert responses associated with memory device 130 into information to host system 120.

Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory devices 130.

In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory units of memory device 130.

Memory subsystem 110 includes a programming pulse control component 113 that can be used to control programming pulse characteristics based on environmental parameters. In some embodiments, memory subsystem controller 115 includes at least a portion of programming pulse control component 113. For example, memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, program pulse control component 113 is part of host system 110, an application program, or an operating system.

Program pulse control component 113 can select a program pulse characteristic based on an environmental parameter. Program pulse control component 113 may monitor the environment of memory subsystem 110 and memory device 130 to determine the program pulse characteristics to select. The program pulse control component 113 may receive configuration parameters from the host system 120. Program pulse control component 113 can use these configuration parameters to establish a baseline for program pulse characteristics and apply weights to environmental factors. Program pulse control component 113 can use the weights to further determine the program pulse characteristics to select. Further details regarding the operation of programming pulse control component 113 are described below.

FIG. 2 is a flow diagram of an example method 200 of controlling programming pulse characteristics based on environmental parameters, in accordance with some embodiments of the present disclosure. Method 200 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 200 is performed by program pulse control component 113 of FIG. 1. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

At operation 210, processing logic of the memory subsystem receives configuration parameters associated with an intended use of the memory subsystem from the host system. The configuration parameters may be provided automatically by the host system or by a user of the host system. The parameters may include the expected environment and location to which the memory subsystem will be exposed and used. Additionally, the configuration parameters may include the expected type of use of the memory subsystem. For example, the host may indicate that the memory subsystem is located in an automobile, a cellular device, a laptop computer, or any other embedded system. Thus, using the configuration parameters, processing logic may determine expected environmental and usage characteristics for the memory subsystem. From the intended environment and use, processing logic may determine an initial value for a programming pulse to write data to a memory device of a memory subsystem.

At operation 220, processing logic monitors environmental parameters, including characteristics of the memory subsystem and the environment surrounding the memory subsystem. The environmental parameter may be temperature fluctuations, usage statistics, age of the device, and any other internal or external parameter that may affect data stability in the memory devices of the memory subsystem (i.e., how long after the data is programmed the data remains valid). For example, large temperature fluctuations between a program operation and a read operation can increase the bit error rate when reading the data. The Vt distributions of the memory cells of the memory device may shift due to temperature fluctuations that result in a large error rate. Additionally, processing logic may monitor usage statistics of the memory subsystem and store the usage statistics at the memory subsystem. For example, a large number of program and erase (P/E) cycles may mean a large bit error rate when reading data, because as the number of P/E cycles increases, the Vt distributions tend to widen and overlap. Also, if the usage indicates that the memory subsystem is off for a longer period of time, it is possible that the bit error rate may increase due to charge loss from the memory cells during power down. Extreme temperatures may also indicate that there will be more bit errors. In addition to usage statistics, processing logic may monitor the actual bit error rate and refresh rate of the memory devices of the memory subsystem.

At operation 230, processing logic selects values for a programming pulse characteristic of the memory subsystem based on the configuration parameters and the environmental parameters, wherein the programming pulse characteristic includes at least a programming pulse voltage. Each of the characteristics of the programming pulses may be adjusted. Characteristics of a programming pulse may include voltage, width of the pulse (i.e., how long the pulse is applied), and current of the pulse. Applying a larger voltage can program the memory cell faster, but can result in more wear. Lower voltages and wider (longer) pulses may result in less loss, but may increase program latency. Thus, which characteristic is adjusted and how much may depend on the needs of the user.

As described above with respect to operation 220, environmental factors may result in higher bit error rates and/or refresh rates. Thus, monitoring of the bit error rate and the refresh rate can be used to adjust the programming pulse voltage, and adjust the Vt distribution accordingly. Processing logic may increase the programming pulse voltage if environmental factors are detected that typically result in a higher bit error rate, such as greater temperature fluctuations. Additionally, if the bit error rate increases, or the refresh rate increases, processing logic may increase the programming voltage to adjust the Vt distribution and decrease the bit error rate. A high refresh rate may indicate that the bit error rate increases faster than it should, e.g., due to environmental parameters.

FIG. 3 is a flow diagram of an example method 300 of controlling programming pulse characteristics based on environmental parameters, in accordance with some embodiments of the present disclosure. The method 300 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed by program pulse control component 113 of FIG. 1. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

At operation 310, the processing logic of the memory component receives configuration parameters associated with the expected usage of the memory subsystem from the host system. The intended use of the memory subsystem may include the geographic location where the memory subsystem will be used, the type of use, the environment in which the memory subsystem will be disposed, and so forth. For example, the expected usage may indicate whether the memory subsystem is to be used indoors or outdoors, whether it is to be stationary or mobile, and so on. The expected usage may indicate an expected worst case condition for the memory subsystem.

At operation 320, processing logic selects a value of a program pulse voltage based on the configuration parameters. Expected usage identified from the configuration parameters may be used to determine an expected worst case condition for the memory subsystem. For example, the configuration parameters may indicate what the average temperature will be, what temperature fluctuations in the environment will be, and so forth. Based on the configuration parameters and the expected usage of the memory subsystem, processing logic may select values for the programming pulse voltages so that the stored data may be stable enough to meet the performance specifications of the memory subsystem under those conditions (e.g., data may last for 6 months under the identified conditions).

At operation 330, processing logic monitors environmental parameters of the memory subsystem, wherein the environmental parameters include characteristics of the memory subsystem and an immediate environment surrounding the memory subsystem. The environmental parameters may be temperature fluctuations, usage statistics, age of the device, and any other internal or external parameter that may affect data stability/validity. For example, large temperature fluctuations between a program operation and a read operation can increase the bit error rate when reading the data. The Vt distributions of the memory cells of the memory components of the memory subsystem may shift due to temperature fluctuations that result in a large error rate. In addition, processing logic may monitor usage statistics of the memory subsystem, which may also be stored by the memory subsystem. For example, a large number of P/E cycles can result in a large bit error rate when reading data due to the widening of the Vt distribution as wear on the device occurs from the P/E cycles. In addition, if the indicating device is used to turn off for a longer period of time, it is possible that the bit error rate will increase due to charge loss from the memory cell during power down. Extreme temperatures may also indicate that there will be more bit errors. Processing logic may also monitor the bit error rate and refresh rate of the memory subsystem.

At operation 340, processing logic adjusts a programming pulse voltage of the memory component based on the environmental parameter and the configuration parameter. Processing logic may adjust each of the characteristics of the programming pulses. Characteristics of a programming pulse may include voltage, length of the pulse (i.e., how long the pulse is applied), and current of the pulse. Applying a larger voltage may program the memory cell faster, but may result in more wear, while a lower voltage may result in less wear, but may increase the time required to program the memory cell. Thus, which adjustment to program pulses is made may depend on the needs of the user.

Further, as the memory subsystem ages, statistics associated with environmental parameters that have been previously collected may be reduced in weight according to configuration parameters received from the host system. When the environment in which the memory subsystem is used is very steady, the environment statistic is more likely to change less. When the environment is highly unstable, then the early statistics may be substantially different from the more current environment statistics. Thus, processing logic may change the weight that processing logic places on the previous (early life) environmental parameter based on the expected environment and usage identified by the configuration parameter. For example, if the configuration parameters indicate that a condition is satisfied (i.e., the environment/usage changes by more than a threshold amount within a specified time period), the weight of previously collected statistics may be reduced when determining the programming pulse voltage to select. On the other hand, if the condition is not met (i.e., the context/usage does not change by more than a threshold amount within a specified time period), then the weighting placed on the earlier collected context statistics may be kept flat or may be reduced by less than the amount if the condition is met.

As described above with respect to operation 330, environmental factors may result in a higher bit error rate, and thus monitoring of those factors may be used by processing logic to adjust the programming pulse voltage and thus the Vt distribution accordingly. If environmental factors are detected that typically result in a higher bit error rate (e.g., greater temperature fluctuations), the programming pulse voltage may be increased. Additionally, if the bit error rate is increased, or the refresh rate is increased, the programming voltage can be increased to adjust the Vt distribution and reduce the bit error rate. A high refresh rate may indicate that the bit error rate increases faster than it should, e.g., due to environmental parameters.

Fig. 4 depicts a program pulse control component 113 according to some embodiments of the present disclosure. Programming pulse control component 113 may initially receive configuration parameters 425 from a host system. The program pulse control component 113 may use the configuration parameters 425 to identify an initial program pulse 430 for a programming operation. The configuration parameters 425 may identify the environment and intended use for which the memory component is intended. Thus, program pulse control component 113 can select program pulse 430 to ensure that data stored in the memory component remains valid for a minimum period of time in view of expected environment and usage. If the configuration parameters indicate that the environment and usage are to be relatively stable, program pulse control component 113 can select a relatively lower program pulse 430 voltage or width to reduce wear on the memory components due to the programming operation. Programming pulse control component 113 may also receive one or more environmental parameters and/or usage statistics of the memory component from sensors or other components.

In one example, program pulse control component 113 can receive a program temperature 402, a read temperature 404, a bit error rate 406, a refresh rate 408, and a number of P/E cycles 410. The programming temperature 402 may be the temperature recorded when data is written to the memory component. The programming temperature 402 may be stored in association with data or a portion of the memory in which data is stored. Similarly, the read temperature 404 can be the temperature of the memory component when previously written data is read from the memory component. Thus, using the programming temperature 402 and the read temperature 404, not only the average temperature of the memory components can be determined, but also the temperature range over which data is read or written. Because large variations in temperature can cause data degradation (e.g., data is written at low temperatures, but read at high temperatures) and increase the bit error rate, the programming pulse 430 can be adjusted to a higher voltage or larger width (i.e., longer pulse). The larger programming pulse 430 can help ensure that data can remain valid and accessible despite large changes in temperature compared to what was originally expected from the configuration parameters 425.

The bit error rate 406 and the refresh rate 408 can also be used to adjust the programming pulses 430. For example, if the bit error rate 406 becomes greater over a period of time, the program pulse control component 113 may increase the voltage or width of the program pulse 430 to increase the difference between the Vt states and decrease the bit error rate 406. A high refresh rate 408 may indicate that the bit error rate 406 is increasing consistently and that the data is relatively unstable under the current conditions. Thus, if the refresh rate 408 is higher, the program pulse control component 113 can increase the voltage or width of the program pulse. The more P/E cycles 410 present relative to a program/erase (P/E) cycle 410, the more dispersed the Vt states become in general, and thus can cause increased read errors. Thus, as the P/E cycle 410 increases, the program pulse control component 113 may increase the voltage or width of the program pulse 430. Additionally, if any of the environmental parameters indicate that the environment is more stable than expected (e.g., low temperature change, low bit error rate, low refresh rate, etc.), program pulse control component 113 may reduce the voltage and/or width of program pulse 430. It should also be noted that program pulse control component 113 can adjust program pulse 430 using any number of environmental parameters and/or usage statistics.

FIG. 5 is a flow diagram of an example method 500 of controlling programming pulse characteristics based on environmental parameters, in accordance with some embodiments of the present disclosure. Method 500 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by program pulse control component 113 of fig. 1. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

At operation 510, processing logic receives configuration data from a host system. The configuration data may indicate the environment in which the memory subsystem is expected to be used. At operation 520, processing logic determines a value of a programming pulse characteristic based on configuration data received from a host system. The programming pulse characteristics may include the voltage, current, and width of the programming pulse. Processing logic may select values for the program pulse characteristics based on configuration data received from the host system. In one example, the configuration data indicates an expected environment of the memory subsystem. Processing logic may select the programming pulse voltage to be high if the environment is expected to be unstable or extreme, and may select the programming pulse voltage to be low if the environment is stable and moderate. Thus, the baseline programming pulse may be selected based on the configuration data.

At operation 530, processing logic monitors environmental factors that may affect the validity and stability of data written in the memory subsystem. Environmental factors may include the temperature, bit error rate, frequency of refresh events, and number of P/E cycles associated with programming and reading of data in the subsystem. Processing logic may also monitor any other environmental factors, usage statistics, or other parameters. Processing logic may monitor environmental factors using internal or external sensors of the host system and/or memory subsystem. The factors may be continuously monitored throughout the following operations 540, 550, and 560.

At operation 540, if the environmental factors indicate that the environment is less stable than expected, then processing logic increases the programming pulse voltage. If environmental factors indicate that the environment is more stable than expected, processing logic may reduce the programming pulse voltage, current, or width. At operation 550, if the frequency of the refresh events is increased from the previously recorded frequency of refresh events, then processing logic increases the program pulse voltage. Alternatively, if the frequency of refresh events is reduced or very low, processing logic may reduce the programming pulse voltage. At operation 560, as the number of P/E cycles increases, processing logic increases the program pulse voltage.

At operation 570, processing logic reduces the weight of previous statistics of the environmental factors based on the configuration parameters when adjusting the programming pulse voltage. When the configuration parameters indicate that the environment or use of the memory subsystem is to be very stable, the environment statistics are more likely to change less. Similarly, if the configuration parameters indicate that the environment or use of the memory subsystem is highly unstable, the early statistics may be substantially different from the more current environment statistics. Thus, the weight placed by processing logic on previous (early life) environmental parameters may change based on the expected environment and usage identified by the configuration parameters. For example, if the configuration parameters indicate that a condition is satisfied (i.e., the environment/usage is unstable), then processing logic may reduce the weight of previously collected statistics at a higher rate when determining the programming pulse voltage to select than if the condition was not satisfied. On the other hand, if the condition is not met (i.e., the environment is stable), then processing logic may keep the weights placed on the earlier collected environment statistics stable or reduce the weights at a slower rate than if the condition is met.

After completion of operation 560, processing logic returns to operation 530 to continue monitoring for environmental factors. Although depicted as performing operations 540, 550, 560, and 570 prior to returning to operation 530, it should be noted that processing logic may return to operation 530 after performance of any of the operations. Operation 530 may also continue throughout the execution of operations 540, 550, 560, and 570. In addition, processing logic may adjust the programming pulses using any other number of operations and parameters. The above description relates to adjusting the programming pulse voltage of the memory subsystem, however, it should be noted that any programming pulse characteristic may be similarly adjusted.

Fig. 6 illustrates an example machine of a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., host system 120 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory subsystem 110 of fig. 1) or may be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to program pulse control component 113 of fig. 1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or decentralized) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Example computer system 600 includes a processing device 602, a main memory 604 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM), such as synchronous DRAM (sdram) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

The processing device 602 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate over a network 620.

The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and/or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. Machine-readable storage medium 624, data storage system 618, and/or main memory 604 may correspond to memory subsystem 110 of fig. 1.

In one embodiment, instructions 626 include instructions to implement functionality corresponding to a program pulse control component (e.g., program pulse control component 113 of fig. 1). While the machine-readable storage medium 624 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical control of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, and so forth.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.