阅读说明：本技术 一种多层绝缘体上硅锗衬底结构及其制备方法和用途 (Multilayer silicon germanium substrate structure on insulator and preparation method and application thereof ) 是由 亨利·H·阿达姆松 王桂磊 罗雪 林鸿霄 于 2021-05-18 设计创作，主要内容包括：本发明涉及一种多层绝缘体上硅锗衬底结构,其包括由下至上依次堆叠的背衬硅层、第一绝缘层、第一硅锗层以及交替垂直堆叠在所述第一硅锗层上的n层第二绝缘层和n层第二硅锗层,并且靠近所述第一硅锗层的是所述第二绝缘层；所述第一硅锗层的硅锗材料的化学式为Si-(1-)-yGe-y；所述第二硅锗层的硅锗材料的化学式为Si-(1-z)Ge-z,0＜z≤0.5；其中,n为1以上的正整数；所述第二绝缘层存在贯穿所述第二绝缘层的凹槽；并且所述凹槽中充满与所述第二硅锗层的硅锗材料相同的硅锗材料。本发明还涉及一种多层绝缘体上硅锗衬底结构的制备方法。该衬底结构有利于减小器件的短沟道效应,同时有利于提升器件的开态电流,在小尺寸半导体器件的制备中有望得到应用。(The invention relates to a multilayer silicon-germanium-on-insulator substrate structure which comprises a backing silicon layer, a first insulating layer, a first silicon-germanium layer, an n-layer second insulating layer and an n-layer second silicon-germanium layer, wherein the backing silicon layer, the first insulating layer, the first silicon-germanium layer and the n-layer second insulating layer and the n-layer second silicon-germanium layer are stacked in sequence from bottom to top; the chemical formula of the silicon-germanium material of the first silicon-germanium layer is Si 1‑ y Ge y (ii) a The chemical formula of the silicon-germanium material of the second silicon-germanium layer is Si 1‑z Ge z Z is more than 0 and less than or equal to 0.5; wherein n is a positive integer of 1 or more; the second insulating layer is provided with a groove penetrating through the second insulating layer; and the recess is filled with a silicon germanium material that is the same as the silicon germanium material of the second silicon germanium layer. The invention also relates to a preparation method of the multilayer silicon germanium substrate structure on the insulator. The substrate structure is beneficial to reducing the short channel effect of the device and is beneficial to reducing the short channel effect of the deviceThe on-state current of the device is improved, and the method is expected to be applied to the preparation of small-size semiconductor devices.)

1. A multilayer silicon-germanium-on-insulator substrate structure is characterized by comprising a backing silicon layer, a first insulating layer, a first silicon-germanium layer, an n-layer second insulating layer and an n-layer second silicon-germanium layer, wherein the n-layer second insulating layer and the n-layer second silicon-germanium layer are stacked from bottom to top in sequence, and the second insulating layer is close to the first silicon-germanium layer; the first silicon germanium layer is Si_1-yGe; the second silicon germanium layer is Si_1-zGe_z，0＜z≤0.5；

Wherein n is a positive integer of 1 or more;

the second insulating layer is provided with a groove penetrating through the second insulating layer; and is

The groove is filled with the same material as the silicon germanium material of the second silicon germanium layer.

2. The multi-layer sige-on-insulator substrate structure of claim 1, wherein the first insulating layer and the first sige layer are each 100nm or less thick.

3. The multi-layer sige-on-insulator substrate structure of claim 1, wherein the thickness of each of the second insulating layer and the second sige layer is 100nm or less.

4. The multi-layer sige-on-insulator substrate structure of claim 1, wherein the first insulating layer and the second insulating layer are both silicon oxide.

5. The method of forming a multi-layer sige-on-insulator substrate structure as claimed in any one of claims 1 to 4, comprising:

step a: providing a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate comprises a back lining silicon layer, a first insulating layer and a silicon top layer which are sequentially stacked from bottom to top;

step b: forming an initial silicon germanium layer on the top silicon layer, the initial silicon germanium layer being Si_1-xGe_xX is more than 0 and less than or equal to 0.5; and forming an insulating protection layer on the initial silicon germanium layer;

step c: performing an annealing treatment to perform interlayer diffusion on the top silicon layer and the initial silicon germanium layer so as to form a first silicon germanium layer; then removing the insulating protection layer;

step d: forming a second insulating layer;

step e: etching a groove penetrating through the second insulating layer on the second insulating layer;

step f: filling the groove and forming a second silicon-germanium layer, wherein the second silicon-germanium layer is Si_1-zGe_zZ is more than 0 and less than or equal to 0.5, and then surface smoothing treatment is optionally carried out;

step g: repeating the processes from the step d to the step f for n-1 times, wherein n is a positive integer more than 1.

6. The multi-layer sige-on-insulator substrate structure of claim 5, wherein the thickness of the top layer of silicon is reduced to less than 100nm before step b.

7. The multi-layer sige-on-insulator substrate structure of claim 5, wherein the second sige layer is formed by a selective epitaxial growth process.

8. The structure of claim 5, wherein step f further comprises thinning the thickness of the second SiGe layer to less than 100nm, optionally followed by surface smoothing.

9. The multi-layer sige-on-insulator substrate structure of claim 5, wherein the first insulating layer and the second insulating layer are both made of silicon oxide.

10. The multi-layer sige-on-insulator substrate structure of any one of claims 1 to 4 or the multi-layer sige-on-insulator substrate structure prepared by the method of any one of claims 5 to 9 is used to fabricate a vertically stacked fully depleted transistor.

Technical Field

The invention belongs to the field of semiconductor manufacturing, and particularly relates to a multi-layer silicon germanium substrate structure on an insulator, and a preparation method and application thereof.

Background

With the continuous development of semiconductor technology, the feature size of semiconductor devices is continuously reduced, and the research and development nodes of the current process technology reach 3nm and below. Under the condition of small size, the short channel effect of the device and the like seriously affect the performance of the device, and under the condition, new materials, new device structures, new integration technologies and packaging technologies are continuously proposed.

The existing substrate on the insulating layer is mainly single-layer, and in practical application, the electrostatic property is improved, but the performance improvement is limited.

Therefore, there is a strong need to develop a substrate-on-insulator structure that overcomes the drawbacks of the prior art.

Disclosure of Invention

The invention aims to provide a multi-layer silicon germanium substrate structure on an insulator. The substrate structure can be used for a vertical stacked fully depleted transistor, is beneficial to reducing the short channel effect of a device, is beneficial to improving the on-state current of the device, and is expected to be applied to the preparation of small-size semiconductor devices.

Another objective of the present invention is to provide a method for fabricating a multi-layer sige-on-insulator substrate structure.

The purpose of the invention can be realized by the following technical scheme.

A multilayer silicon-germanium-on-insulator substrate structure comprises a backing silicon layer, a first insulating layer, a first silicon-germanium layer, an n-layer second insulating layer and an n-layer second silicon-germanium layer, wherein the backing silicon layer, the first insulating layer, the first silicon-germanium layer and the n-layer second insulating layer and the n-layer second silicon-germanium layer are stacked in sequence from bottom to top, the n-layer second insulating layer and the n-layer second silicon-germanium layer are stacked on the first silicon-germanium layer alternately and vertically, and the second insulating layer is close to the first silicon-germanium layer; the first silicon germanium layer is Si_1-yGe_y(ii) a The second silicon germanium layer is Si_1-zGe_z，0＜z≤0.5；

Wherein n is a positive integer of 1 or more;

the second insulating layer is provided with a groove penetrating through the second insulating layer; and is

The groove is filled with the same material as the silicon germanium material of the second silicon germanium layer.

A method for preparing a multi-layer silicon germanium-on-insulator substrate structure comprises the following steps:

step a: providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises a back lining silicon layer, a first insulating layer and a silicon top layer which are sequentially stacked from bottom to top;

step b: forming an initial silicon germanium layer on the top silicon layer, the initial silicon germanium layer being Si_1-xGe_xX is more than 0 and less than or equal to 0.5; and forming an insulating protection layer on the initial silicon germanium layer;

step c: performing an annealing treatment to perform interlayer diffusion on the top silicon layer and the initial silicon germanium layer so as to form a first silicon germanium layer; then removing the insulating protection layer;

step d: forming a second insulating layer;

step e: etching a groove penetrating through the second insulating layer on the second insulating layer;

step f: filling the groove and forming a second silicon-germanium layer, wherein the second silicon-germanium layer is Si_1-zGe_zZ is more than 0 and less than or equal to 0.5, and then surface smoothing treatment is optionally carried out;

step g: repeating the processes from the step d to the step f for n-1 times, wherein n is a positive integer more than 1.

The multilayer silicon germanium on insulator substrate structure or the multilayer silicon germanium on insulator substrate structure prepared by the method is used for vertically stacking the fully depleted transistor.

Compared with the prior art, the invention achieves the following technical effects:

the substrate structure is provided with a multi-layer channel structure when the substrate structure is used for vertically stacking fully depleted transistors, so that the short channel effect of the device can be reduced, meanwhile, the multi-layer channel structure is beneficial to improving the on-state current of the device, and the substrate structure is expected to be applied to the preparation of small-size semiconductor devices.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a flow chart of a method for forming a multi-layer sige-on-insulator substrate structure according to the present invention.

Fig. 2-8 are schematic structural diagrams obtained at each step in the substrate preparation method according to the embodiment of the present invention, in which 1 is a backing silicon layer, 2 is a first insulating layer, 3 is a first silicon germanium layer, 4 is a second insulating layer, 5 is a second silicon germanium layer, 6 is a groove, 31 is a silicon top layer, 32 is an initial silicon germanium layer, and 33 is an insulating protective layer.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

Because the existing transistor with a fully depleted substrate is limited in optimizing short channel effect and insufficient in on-state current for smaller-size applications, the invention provides an improved substrate which has the following structure.

A multilayer silicon-germanium-on-insulator substrate structure comprises a backing silicon layer, a first insulating layer, a first silicon-germanium layer, an n-layer second insulating layer and an n-layer second silicon-germanium layer, wherein the backing silicon layer, the first insulating layer, the first silicon-germanium layer and the n-layer second insulating layer and the n-layer second silicon-germanium layer are stacked in sequence from bottom to top, the n-layer second insulating layer and the n-layer second silicon-germanium layer are stacked on the first silicon-germanium layer alternately and vertically, and the second insulating layer is close to the first silicon-germanium layer; the first silicon germanium layer is Si_1-yGe_y(ii) a The second silicon germanium layer is Si_1-zGe_z，0＜z≤0.5；

Wherein n is a positive integer of 1 or more;

the second insulating layer is provided with a groove penetrating through the second insulating layer; and is

The groove is filled with the same material as the silicon germanium material of the second silicon germanium layer.

The substrate structure is characterized in that: the silicon germanium film has a stacked structure and is formed by alternately stacking insulating layers and silicon germanium layers, wherein the silicon germanium layers are electrically connected or contacted through grooves.

Such a substrate structure has significant advantages when used for vertically stacked fully depleted transistors: the multi-layer channel structure can be formed, the short channel effect of the device can be reduced, meanwhile, the on-state current of the device can be improved, and the multi-layer channel structure is expected to be applied to preparation of small-size semiconductor devices.

The constituent materials of the first insulating layer and the second insulating layer are not particularly limited in the present invention. The first and second insulating layers may be silicon oxide or other commonly used dielectric materials, and may be the same or different.

In order to improve the electrical properties of the substrate structure, the thickness of the first insulating layer, the first silicon germanium layer, the second insulating layer and the second silicon germanium layer is suitably kept below 100 nm.

The present invention is not particularly limited with respect to the outer wall profile of the grooves and the spacing between the grooves. The outline of the outer wall of the grooves can be round or rectangular, and the like, and the intervals among the grooves can be the same or different.

The number n of the second insulating layer, the second silicon germanium layer comprised by the substrate structure of the invention is arbitrary, e.g. 1-6 or 3-6 etc.

The substrate structure of the present invention can be prepared as follows.

The first step is as follows: providing a silicon-on-insulator Substrate (SOI) which comprises a back lining silicon layer, a first insulating layer and a silicon top layer which are sequentially stacked from bottom to top.

The first insulating layer is a conventional buried oxide layer, and in some preferred embodiments, the thickness of the first insulating layer is required to be less than 100 nm; the silicon top layer is top layer silicon in the traditional SOI, the thickness of the silicon top layer is required to be below 100nm in some preferred embodiments, if the silicon top layer is too thick, the silicon top layer can be thinned in advance, the thinning is not limited, and wet etching, dry etching, combination of wet etching and dry etching or Chemical Mechanical Polishing (CMP) and the like can be adopted. The SOI used in this step can be purchased directly from the market or prepared by itself.

The second step is that: forming an initial silicon germanium layer on the top silicon layer, the initial silicon germanium layer being Si_1-xGe_xX is more than 0 and less than or equal to 0.5; and forming an insulating protective layer on the initial silicon germanium layer.

Some preferred embodiments require that the initial sige layer and the insulating protective layer have a thickness of 100nm or less; the initial sige layer and the insulating protective layer may be formed directly to the desired thickness or may be deposited in excess and then thinned. The initial sige layer formation method is preferably performed using an epitaxial growth process, such as Reduced Pressure Chemical Vapor Deposition (RPCVD). The method for forming the insulating protective layer in the present invention is not particularly limited, and a chemical vapor deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), Ultra High Vacuum Chemical Vapor Deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), or the like can be used. The present invention is not particularly limited with respect to the thinning method. The thinning may be performed by wet etching, dry etching, a combination of wet etching and dry etching, or Chemical Mechanical Polishing (CMP), or the like.

The third step: performing an annealing treatment to perform interlayer diffusion on the top silicon layer and the initial silicon germanium layer so as to form a first silicon germanium layer; the insulating protective layer is then removed.

The annealing method is not particularly limited in the present invention. The temperature of the annealing treatment can be 800-1300 ℃. Some preferred embodiments require that the thickness of the annealed first sige layer is below 100 nm.

The method for removing the insulating protective layer according to the present invention is not particularly limited. The removal may be performed by wet etching, dry etching, a combination thereof, or the like.

The fourth step: and forming a second insulating layer on the first silicon-germanium layer.

Some preferred embodiments require that the thickness of the second insulating layer be 100nm or less; the second insulating layer can be formed directly to the desired thickness or over-deposited and then thinned. The method for forming the second insulating layer is not particularly limited. A second insulating layer may be formed on the first silicon germanium layer using Chemical Vapor Deposition (CVD). The present invention is not particularly limited with respect to the thinning method. Preferably, the thinning is performed by wet etching, dry etching, a combination of wet etching and dry etching, or Chemical Mechanical Polishing (CMP), or the like.

The fifth step: and etching a groove penetrating through the second insulating layer on the second insulating layer.

The main purpose of the recess is to achieve contact between the sige layers, and the etching means is not limited, such as wet etching, dry etching or a combination thereof. The specific structure and arrangement of the grooves are arbitrary, the outline of the outer wall of each groove can be circular or rectangular, and the like, and the intervals among the grooves can be the same or different.

And a sixth step: filling the recess and forming a second silicon germanium layer of silicon germanium material of the formula Si_{1- z}Ge_zAnd z is more than 0 and less than or equal to 0.5, and then surface smoothing treatment is optionally carried out.

Some preferred embodiments require that the thickness of the second sige layer is 100nm or less; the second sige layer may be formed directly to the desired thickness or may be deposited in excess and then thinned. The present invention is not particularly limited to the method of filling the recess and forming the second silicon germanium layer. The steps of filling the recess and forming the second silicon germanium layer may be performed simultaneously. The recess is preferably filled and the second silicon germanium layer is formed by a selective epitaxial growth process. The present invention is not particularly limited with respect to the thinning method. Preferably, the thinning is performed by wet etching, dry etching, a combination of wet etching and dry etching, or Chemical Mechanical Polishing (CMP), or the like.

The method of surface smoothing treatment in the present invention is not particularly limited. The surface smoothing may be performed by ion beam polishing, plasma-assisted chemical polishing, liquid jet polishing, magnetorheological polishing, Chemical Mechanical Polishing (CMP), or elastic emission machining.

The seventh step: repeating the process from the fourth step to the sixth step for n-1 times, wherein n is a positive integer more than 1.

The process conditions for the repetition are as above.

The present invention will be further described with reference to the following specific examples.

Example 1

An SOI substrate as shown in fig. 2 is provided, which comprises a backing silicon layer 1, a first insulating layer 2 and a silicon top layer 31 stacked in this order from bottom to top. The thickness of the first insulating layer 2 is 100nm or less.

The top layer of silicon 31 is thinned and the thickness is controlled below 100 nm.

An initial silicon germanium layer 32 is then formed on top silicon layer 31, initial silicon germanium layer 32 being Si_1-xGe_xX is more than 0 and less than or equal to 0.5; and an insulating protective layer 33 is formed on the initial silicon germanium layer 32, the initial silicon germanium layer 32 and the insulating protective layer 33 having a thickness of 100nm or less, resulting in the structure shown in fig. 3.

Subjecting the structure shown in fig. 3 to an annealing process to inter-layer diffuse the top silicon layer 31 and the initial sige layer 32 to form a first sige layer 3, the first sige layer 3 having a thickness of 100nm or less; the insulating protective layer 33 is then removed, resulting in the structure shown in fig. 4.

A second insulating layer 4 is then formed on the first sige layer 3, and the resulting second insulating layer 4 is then thinned to a thickness of 100nm or less, resulting in the structure shown in fig. 5.

Next, a groove 6 is etched in the second insulating layer 4, which penetrates the second insulating layer 4, resulting in the structure shown in fig. 6.

Then filling the recess 6 by a selective epitaxial growth process and forming a second silicon germanium layer 5, the second silicon germanium layer 5 being Si_1-zGe_zAnd z is more than 0 and less than or equal to 0.5, and then the obtained second silicon-germanium layer 5 is thinned, and the thickness is controlled to be less than 100nm, so that the structure shown in the figure 7 is obtained. Followed by optional surface smoothing.

Example 2

An SOI substrate as shown in fig. 2 is provided, which comprises a backing silicon layer 1, a first insulating layer 2 and a silicon top layer 31 stacked in this order from bottom to top. The first insulating layer 2 and the top layer of silicon 31 are both below 100 nm.

An initial silicon germanium layer 32 is then formed on top silicon layer 31, initial silicon germanium layer 32 being Si_1-xGe_xX is more than 0 and less than or equal to 0.5; and an insulating protective layer 33 is formed on the initial silicon germanium layer 32, the initial silicon germanium layer 32 and the insulating protective layer 33 having a thickness of 100nm or less, resulting in the structure shown in fig. 3.

Subjecting the structure shown in fig. 3 to an annealing process to inter-layer diffuse the top silicon layer 31 and the initial sige layer 32 to form a first sige layer 3, the first sige layer 3 having a thickness of 100nm or less; the insulating protective layer 33 is then removed, resulting in the structure shown in fig. 4.

A second insulating layer 4 is then formed on the first sige layer 3, the resulting second insulating layer 4 having a thickness of 100nm or less, resulting in the structure shown in fig. 5.

Next, a groove 6 is etched in the second insulating layer 4, which penetrates the second insulating layer 4, resulting in the structure shown in fig. 6.

Then filling the recess 6 by a selective epitaxial growth process and forming a second silicon germanium layer 5, the second silicon germanium layer 5 being Si_1-zGe_zZ is more than 0 and less than or equal to 0.5, the thickness of the second silicon-germanium layer 5 is less than or equal to 100nm,a structure as shown in fig. 7 is obtained. Followed by optional surface smoothing.

Example 3

An SOI substrate as shown in fig. 2 is provided, which comprises a backing silicon layer 1, a first insulating layer 2 and a silicon top layer 31 stacked in this order from bottom to top. The first insulating layer 2 and the top layer of silicon 31 are both below 100 nm.

An initial silicon germanium layer 32 is then formed on top silicon layer 31, initial silicon germanium layer 32 being Si_1-xGe_xX is more than 0 and less than or equal to 0.5; and an insulating protective layer 33 is formed on the initial silicon germanium layer 32, the initial silicon germanium layer 32 and the insulating protective layer 33 having a thickness of 100nm or less, resulting in the structure shown in fig. 3.

Subjecting the structure shown in fig. 3 to an annealing process to inter-layer diffuse the top silicon layer 31 and the initial sige layer 32 to form a first sige layer 3, the first sige layer 3 having a thickness of 100nm or less; the insulating protective layer 33 is then removed, resulting in the structure shown in fig. 4.

A second insulating layer 4 is then formed on the first sige layer 3, the resulting second insulating layer 4 having a thickness of 100nm or less, resulting in the structure shown in fig. 5.

Next, a groove 6 is etched in the second insulating layer 4, which penetrates the second insulating layer 4, resulting in the structure shown in fig. 6.

Then filling the recess 6 by a selective epitaxial growth process and forming a second silicon germanium layer 5, the second silicon germanium layer 5 being Si_1-zGe_zAnd z is more than 0 and less than or equal to 0.5, and the thickness of the second SiGe layer 5 is less than or equal to 100nm, so that the structure shown in FIG. 7 is obtained.

The above process of forming the second insulating layer 4, the recess 6 and the second sige layer 5 is repeated 1 time to obtain the structure shown in fig. 8. Followed by optional surface smoothing.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.