阅读说明：本技术 用于对存储器单元进行编程的技术 (Techniques for programming memory cells ) 是由 H·A·卡斯特罗 I·托尔托雷利 A·皮罗瓦诺 F·佩里兹 于 2019-08-09 设计创作，主要内容包括：本发明提供用于对存储第一逻辑状态的自选择存储器单元进行编程的技术。为对所述存储器单元进行编程,可将具有第一极性的脉冲施加到所述单元,此可导致所述存储器单元具有降低的阈值电压。在其中可降低所述存储器单元的所述阈值电压的持续时间期间(例如,在选择时间期间),可将具有第二极性(例如,不同极性)的第二脉冲施加到所述存储器单元。将所述第二脉冲施加到所述存储器单元可导致所述存储器单元存储不同于所述第一逻辑状态的第二逻辑状态。(Techniques for programming a self-selected memory cell storing a first logic state are provided. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be lowered (e.g., during a select time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may cause the memory cell to store a second logic state different from the first logic state.)

1. A method, comprising:

applying a first pulse having a first polarity to a memory cell storing a first logic state during a write operation;

detecting a snapback event at the memory cell in response to applying the first pulse;

applying a second pulse having a second polarity different from the first polarity to the memory cell in response to detecting the snapback event; and

storing a second logic state different from the first logic state in the memory cell based at least in part on applying the second pulse to the memory cell.

2. The method of claim 1, further comprising:

applying a first voltage to a first access line coupled with the memory cell; and

applying a second voltage to a second access line coupled with the memory cell, wherein applying the first pulse is based at least in part on applying the first voltage and the second voltage.

3. The method of claim 2, further comprising:

applying the second voltage to the first access line; and

applying the first voltage to the second access line, wherein applying the second pulse is based at least in part on applying the first voltage to the second access line and applying the second voltage to the first access line.

4. The method of claim 1, further comprising:

detecting a decrease in a magnitude of a voltage across the memory cell, wherein detecting the snapback event is based at least in part on detecting the decrease in the magnitude of the voltage.

5. The method of claim 1, wherein the snapback event is based at least in part on a value of the first logic state being different from a value of the second logic state to be stored to the memory cell.

6. The method of claim 1, further comprising:

a voltage magnitude of the first pulse is selected based at least in part on a value of the second logic state to be stored to the memory cell.

7. The method of claim 1, wherein a threshold voltage of the memory cell is lowered based at least in part on applying the first pulse.

8. The method of claim 7, wherein the lowered threshold voltage of the memory cell is based at least in part on the first logic state.

9. The method of claim 7, wherein the magnitude of the threshold voltage of the memory cell is reduced for a duration in response to an occurrence of the snapback event.

10. The method of claim 9, wherein the second pulse is applied to the memory cell during the duration when the threshold voltage is lowered.

11. The method of claim 9, further comprising:

performing a read operation or other operation during the duration, wherein the second pulse is applied after the duration.

12. The method of claim 9, further comprising:

detecting a second snapback event at the memory cell in response to applying the second pulse to the memory cell after the duration.

13. The method of claim 9, wherein the lowered threshold voltage of the memory cell is based at least in part on the first logic state.

14. The method of claim 1, wherein the memory cell comprises a self-selecting memory cell.

15. A method, comprising:

applying a first pulse having a first polarity to a memory cell storing a first logic state during a write operation;

detecting the first logic state stored by the memory cell in response to applying the first pulse to the memory cell; and

storing a second logic state in the memory cell by applying a second pulse having a second polarity in response to detecting the first logic state during the write operation, wherein the second logic state is different from the first logic state.

16. The method of claim 15, further comprising:

applying a first voltage to a first access line coupled with the memory cell; and

applying a second voltage to a second access line coupled with the memory cell, wherein applying the first pulse is based at least in part on applying the first voltage and the second voltage.

17. The method of claim 16, wherein applying the first voltage to the first access line lowers a threshold voltage of the memory cell.

18. The method of claim 17, wherein the second voltage is greater than the lowered threshold voltage of the memory cell.

19. The method of claim 15, wherein detecting the first logic state is based at least in part on a threshold voltage of the memory cell being less than a magnitude of the first pulse.

20. The method of claim 15, wherein storing the second logic state to the memory cell is based at least in part on a threshold voltage of the memory cell being lowered for a duration of time.

21. The method of claim 15, wherein the first polarity is opposite the second polarity.

22. The method of claim 15, wherein the first logic state is detected during a duration of time after applying the first pulse, and wherein the second logic state is written to the memory cell during the duration of time.

23. A method, comprising:

reducing a threshold voltage of a memory cell for a duration of time during a write operation by applying a first pulse having a first polarity to the memory cell, the memory cell comprising a first logic value;

applying a second pulse to the memory cell during the duration during the write operation, the second pulse having a second polarity different from the first polarity; and

storing a second logic value in the memory cell after applying the second pulse.

24. The method of claim 23, further comprising:

determining the first logical value of the memory cell based at least in part on lowering the threshold voltage of the memory cell during the write operation.

25. The method of claim 23, further comprising:

decreasing the threshold voltage of the memory cell after the duration by applying the first pulse having the first polarity to the memory cell during the write operation, the memory cell including the second logical value.

26. The method of claim 23, wherein a magnitude of the second pulse applied to the memory cell is less than a magnitude of the first pulse.

27. The method of claim 23, wherein the first pulse applies a voltage across the memory cell in a first direction and the second pulse applies a voltage across the memory cell in a second direction.

28. An apparatus, comprising:

a first access line coupled with a memory cell storing a first logic state;

a second access line coupled with the memory cell; and

a memory controller coupled with the first access line and the second access line, the memory controller configured to:

applying a first pulse having a first polarity to the memory cell during a write operation;

detecting a snapback event at the memory cell in response to applying the first pulse;

applying a second pulse having a second polarity different from the first polarity to the memory cell in response to detecting the snapback event; and

storing a second logic state different from the first logic state in the memory cell based at least in part on applying the second pulse to the memory cell.

29. The apparatus of claim 28, wherein the memory controller is configured to detect the snapback event at the memory cell during a duration after applying the first pulse.

30. The apparatus of claim 29, wherein the memory cell comprises a reduced threshold voltage during the duration.

31. The apparatus of claim 30, wherein applying the second pulse having the second polarity comprises applying a voltage to the second access line that is greater than the reduced threshold voltage.

32. An apparatus, comprising:

a first access line coupled with a memory cell storing a first logic state;

a second access line coupled with the memory cell; and

a memory controller coupled with the first access line and the second access line, the memory controller configured to:

applying a first pulse having a first polarity to the memory cell during a write operation;

detecting the first logic state stored by the memory cell in response to applying the first pulse to the memory cell; and

storing a second logic state in the memory cell by applying a second pulse having a second polarity during the write operation based at least in part on detecting the first logic state, wherein the second logic state is different from the first logic state.

33. The apparatus of claim 32, wherein the memory controller is operable to apply the first pulse having the first polarity to the memory cell during a duration of time.

34. The apparatus of claim 33, wherein the first logic state is detected during the duration and the second logic state is written to the memory cell during the duration.

35. The apparatus of claim 32, wherein:

applying the first pulse having the first polarity comprises applying a first voltage to the first access line; and is

Applying the second pulse having the second polarity comprises applying a second voltage to the second access line, wherein writing the second logic state to the memory cell is based at least in part on a magnitude of the second voltage exceeding a threshold voltage of the memory cell.

36. The apparatus of claim 32, wherein the memory controller is operable to select the first pulse from a plurality of pulses based at least in part on a value of the second logic state to be written to the memory cell.

Background

The following generally relates to operating a memory array and more particularly to programming a self-selecting memory device.

Memory devices are widely used to store information in various electronic devices, such as computers, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, components of the electronic device may read or sense a stored state in the memory device. To store information, components of the electronic device may write or program states in the memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memory (RAM), Read Only Memory (ROM), dynamic RAM (dram), synchronous dynamic RAM (sdram), ferroelectric RAM (feram), magnetic RAM (mram), resistive RAM (rram), flash memory, Phase Change Memory (PCM), and others. The memory devices may be volatile or non-volatile. A non-volatile memory cell can maintain its stored logic state for an extended period of time even in the absence of an external power source. Volatile memory cells may lose their stored state over time unless they are periodically refreshed by an external power supply.

Improving memory devices may generally include increasing memory cell density, increasing read/write speed, increasing reliability, increasing data retention, reducing power consumption or reducing manufacturing costs, and the like. It may be desirable to program memory cells with a reduced write voltage to reduce stress on the memory cells and to reduce the overall power usage of the memory array.

Drawings

FIG. 1 illustrates an example memory device according to an example of the present disclosure.

FIG. 2 illustrates an example of a memory array supporting techniques for programming self-selecting memory devices, in accordance with aspects of the present disclosure.

FIG. 3 illustrates an example of a diagram showing distributions of threshold voltages of self-selected memory cells in support of techniques for programming self-selected memory devices, in accordance with aspects of the present disclosure.

FIG. 4 illustrates an example of a timing diagram associated with distributions of threshold voltages of self-selected memory cells in support of techniques for programming self-selected memory devices, in accordance with aspects of the present disclosure.

FIG. 5 shows a block diagram of a device supporting techniques for programming self-selecting memory devices, in accordance with aspects of the present disclosure.

Fig. 6-8 illustrate flow diagrams of methods of supporting techniques for programming self-selecting memory devices, in accordance with aspects of the present disclosure.

Detailed Description

Self-selected memory cells including chalcogenide alloys can be programmed to store one or more bits of data by using various programming pulses. Thus, a single self-selecting memory cell may be configured to store more than one bit of digital data. In some cases, a self-selected memory cell can be selected by applying a particular bias between a word line and a digit line. The logic state stored in a self-selected memory cell may be based on the polarity of the programming pulse applied to the self-selected memory cell. For example, the self-selecting memory may store a logic '0' after application of a programming pulse having a first polarity and the self-selecting memory may store a logic '1' after application of a programming pulse having a second, different polarity. Further, the threshold voltage representing the logical state (e.g., logical "0") detected by the sense component may change based on the polarity of the read pulse applied during the read operation. For example, due to the asymmetric distribution of ions in programmed self-selected memory cells, the threshold voltages may appear different when read pulses of different polarities are applied.

Techniques are provided for programming a self-selected memory cell (which may comprise a chalcogenide material, for example) by detecting the occurrence of a snap-back event. To program (e.g., write) a self-selecting memory storing a first logic state (e.g., logic "1"), a programming pulse sequence including two pulses may be used. A first pulse of the sequence of programming pulses may have a first polarity and a second pulse of the sequence of programming pulses may have a second polarity different from the first polarity. Depending on the logic state stored in the self-selected memory cell, the self-selected memory cell may experience a snapback event due to the first pulse applied to the cell. The snapback event may be characterized by an increase (e.g., a sudden increase) in the conductivity of the memory cell. After a duration, the memory cell may return to its original conductivity. After the memory cell returns to its original conductivity, the memory cell may experience a temporary decrease in its threshold voltage.

After detecting the snapback event, a second pulse may be applied to program a second logic state (e.g., a logic "0") of the memory cell. Because the threshold voltage of the memory cell can be temporarily lowered, the second pulse can include a smaller magnitude to program the second logic state. In other words, when the threshold voltage of the memory cell is lowered, a lower voltage is required to write the second logic state to the memory cell (e.g., relative to the threshold voltage of the memory cell not being lowered). Thus, by applying the second voltage to the self-selected memory cell during a snapback event (e.g., during a duration of time that the threshold voltage of the memory cell is reduced), a logic state may be written to the memory cell using the reduced voltage, which may reduce stress of the memory cell and reduce overall power consumption of the memory array. In some cases, the duration of the snapback event may be less than 1 nanosecond. If no snapback event is detected, the self-selected memory cell may have stored the value that was attempted to be written to the self-selected memory cell by the write operation, and the second pulse may not be applied to the memory cell.

In some examples, a first pulse may be applied to a memory cell storing a first logic state. As described above, application of the first pulse may result in a snapback event associated with the memory cell. The snapback event may then be detected (e.g., by a memory controller), and a second pulse may be applied to the memory cell based on or in response to the detected snapback event. In some examples, the second pulse may have a second polarity (e.g., opposite polarity) different from the first polarity. Based on the application of the second pulse, a second logic state (e.g., a different logic state) may be stored in the memory cell.

In another example, a first pulse may be applied to the memory cell during a write operation. In some examples, the memory cell may store a first logic state. The first logic state (e.g., logic "1") may be detected (e.g., by a memory controller) in response to applying a first pulse to a memory cell. After detecting the first logic state, a second pulse may be applied to the memory cell. In some examples, the second pulse may have a second polarity (e.g., opposite polarity) different from the first polarity. Based on the application of the second pulse, a second logic state (e.g., a different logic state) may be stored in the memory cell.

In some examples, the threshold voltage of a memory cell may be lowered for a duration of time during a write operation. In some examples, the threshold voltage may be lowered based on a first pulse applied to the memory cell. For example, the first pulse may have a first polarity and the memory cell may store a first logic value. The second pulse may be applied to the memory cell during a duration in which a threshold voltage of the memory cell is reduced. In some examples, the second pulse may have a different polarity than the first pulse. Based on the application of the second pulse, a second logic state (e.g., a different logic state) may be stored in the memory cell.

The features of the present disclosure introduced above are further described below in the context of a memory array. Specific examples for operating a memory array related to techniques of programming self-selecting memory devices are then described in some examples. These and other features of the invention are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flow charts related to techniques for programming self-selecting memory devices.

FIG. 1 illustrates an example memory device 100 according to an example of the invention. Memory device 100 may also be referred to as an electronic memory device. FIG. 1 is an illustrative representation of various components and features of a memory device 100. As such, it should be understood that the components and features of the memory device 100 are shown to illustrate functional interrelationships, rather than their actual physical location within the memory device 100. In the illustrative example of FIG. 1, memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some examples, each memory cell 105 can be programmed to store two states, represented as a logic 0 and a logic 1. In some examples, memory cell 105 may be configured to store more than two logic states. In some examples, memory cells 105 may include self-selecting memory cells. Although some elements included in fig. 1 are labeled with numerical indicators and other corresponding elements are not labeled, they are the same or will be understood to be similar in an attempt to increase the visibility and clarity of the depicted features.

The 3D memory array 102 may include two or more two-dimensional (2D) memory arrays 103 formed on top of each other. This may increase the number of memory cells that can be placed or created on a single die or substrate, which in turn may reduce production costs or increase performance of the memory device, or both, as compared to 2D arrays. Memory array 102 may include two levels of memory cells 105 and thus may be considered a 3D memory array; however, the number of levels may not be limited to two. Each level may be aligned or positioned such that memory cells 105 may be aligned (completely, overlapping, or approximately) with each other across each level, forming a memory cell stack 145. In some cases, memory cell stack 145 may include a plurality of self-selecting memory cells laid on top of each other while both share an access line, as explained below. In some cases, the self-selecting memory cells may be multi-level self-selecting memory cells configured to store more than one bit of data using multi-level storage techniques.

In some examples, each row of memory cells 105 is connected to an access line 110, and each column of memory cells 105 is connected to a bit line 115. The access lines 110 and bit lines 115 can be substantially perpendicular to each other and can create an array of memory cells. As shown in fig. 1, two memory cells 105 in a memory cell stack 145 may share a common conductive line (e.g., bitline 115). That is, bit line 115 may be in electronic communication with a bottom electrode of upper memory cell 105 and a top electrode of lower memory cell 105. Other configurations are possible, for example, the third tier may share access lines 110 with the lower tier. In general, one memory cell 105 may be located at the intersection of two conductive lines (e.g., access line 110 and bit line 115). This intersection may be referred to as the address of the memory cell. Target memory cell 105 may be memory cell 105 located at the intersection of powered access line 110 and bitline 115; that is, access lines 110 and bit lines 115 may be energized in order to read or write memory cells 105 at their intersection. Other memory cells 105 in electronic communication with (e.g., connected to) the same access line 110 or bitline 115 may be referred to as untargeted memory cells 105.

As discussed herein, electrodes may be coupled to memory cells 105 and access lines 110 or bit lines 115. The term electrode may refer to an electrical conductor, and in some cases, may serve as an electrical contact to memory cell 105. The electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide a conductive path between elements or components of the memory device 100. In some examples, memory cell 105 may include a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode may be coupled to an access line 110 and the other side of the first electrode is coupled to the chalcogenide material. Additionally, one side of the second electrode may be coupled to a bit line 115 and the other side of the second electrode is coupled to a chalcogenide material. The first and second electrodes may be the same material (e.g., carbon) or different materials.

Operations (e.g., reads and writes) may be performed on memory cell 105 by activating or selecting access line 110 and bitline 115. In some examples, the access lines 110 may also be referred to as word lines 110, and the bit lines 115 may also be referred to as digit lines 115. References to access lines, word lines, and bit lines, or the like, may be interchanged without loss of understanding or operation. Activating or selecting a word line 110 or bit line 115 may include applying a voltage to the respective line. The word line 110 and the bit line 115 may be made of a conductive material, such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, a conductively-doped semiconductor, or other conductive materials, alloys, compounds, or the like.

Access to the memory cells 105 may be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, a column decoder 130 may receive a column address from a memory controller 140 and activate the appropriate bit lines 115. For example, the memory array 102 may include a plurality of word lines 110 labeled WL _1 to WL _ M and a plurality of digit lines 115 labeled DL _1 to DL _ N, where M and N depend on the array size. Thus, by activating word line 110 and bit line 115 (e.g., WL _2 and DL _3), memory cell 105 at its intersection can be accessed.

After the access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, a voltage may be applied to memory cell 105 (using the corresponding word line 110 and bit line 115) and the presence of the resulting current may depend on the applied voltage and threshold voltage of memory cell 105. In some cases, more than one voltage may be applied. Further, if the applied voltage does not cause a current to flow, other voltages can be applied until a current is detected by the sensing component 125. By evaluating the voltage that causes the current to flow, the stored logic state of memory cell 105 can be determined. In some cases, the voltage may be ramped in magnitude until current flow is detected. In other cases, the predetermined voltages may be applied sequentially until current is detected. Likewise, a current may be applied to memory cell 105 and the magnitude of the voltage that generates the current may depend on the resistance or threshold voltage of memory cell 105.

In some examples, memory cells, which may include memory storage elements, may be programmed by providing electrical pulses to the cells. The pulse may be provided via a first access line (e.g., word line 110) or a second access line (e.g., bit line 115), or a combination thereof. In some cases, ions may migrate within the memory storage element after providing the pulse depending on the polarity of the memory cell 105. Thus, the concentration of ions relative to the first side or the second side of the memory storage element may be based at least in part on the polarity of the voltage between the first access line and the second access line. In some cases, asymmetrically shaped memory storage elements may cause ions to be more concentrated at portions of the element having more area. Certain portions of the memory storage elements may have higher resistivity and thus may generate higher threshold voltages than other portions of the memory storage elements. This description of ion migration represents an example of a mechanism for self-selecting memory cells to achieve the results described herein. This example of a mechanism should not be considered limiting. Other examples of mechanisms for self-selecting memory cells to achieve the results described herein are also included.

The sensing component 125 may include various transistors or amplifiers in order to detect and amplify differences in signals, which may be referred to as latching. The detected logic state of memory cell 105 may then be output as output 135 through column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 can be connected to column decoder 130 or row decoder 120 or in electronic communication with column decoder 130 or row decoder 120. Those skilled in the art will appreciate that the sensing component may be associated with a column decoder or a row decoder without losing its functional purpose.

Memory cell 105 may be set or written by similarly activating the associated word line 110 and bit line 115 and at least one logical value may be stored in memory cell 105. Column decoder 130 or row decoder 120 can accept data (e.g., input/output 135) to be written to memory cells 105. In the case of a self-selecting memory cell comprising a chalcogenide material, memory cell 105 may be written to store data by applying a programming sequence comprising a first pulse having a first polarity and a second pulse having a second polarity. The programming pulses can have various shapes. This process is discussed in more detail below with reference to fig. 3 and 4.

The memory controller 140 may control the operation (e.g., read, write, rewrite, refresh, discharge) of the memory cells 105 through various components (e.g., row decoder 120, column decoder 130, and sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals in order to activate the desired word line 110 and bit line 115. Memory controller 140 may also generate and control various voltages or currents used during operation of memory device 100.

The memory controller 140 may be configured to perform a write operation that can program a self-selected memory cell. For example, memory controller 140 may be configured to apply a first pulse having a first polarity to memory cells 105 during a write operation. In some examples, applying the first pulse having the first polarity may include applying a first voltage to a first access line (e.g., to word line 110) and applying a second voltage to a second access line (e.g., bit line 115). Applying the second pulse having the second polarity may include applying a third voltage to the first access line (e.g., to the bit line 115) and applying a fourth voltage to the second access line (e.g., the bit line 115). Memory controller 140 may be configured to detect a snapback event at memory cell 105 in response to applying the first pulse. For example, the snap-back event may result in a lowered threshold voltage of memory cell 105.

In some examples, memory controller 140 may apply a second pulse having a second polarity different from the first polarity to memory cell 105 in response to detecting the snapback event, and may then store a second logic state different from the first logic state in memory cell 105 based at least in part on applying the second pulse to the memory cell. In other words, the threshold voltage of memory cell 105 may be lowered after applying the first pulse (e.g., during a snapback event) and applying the second pulse while the threshold voltage is lowered may store (e.g., write) the second logic state to memory cell 105.

In some examples, memory controller 140 may be configured to apply a first pulse having a first polarity to memory cell 105 during a write operation. In some examples, memory controller 140 may detect a first logic state stored by a memory cell in response to applying the first pulse to the memory cell. As described above, the first logic state may be detected during a snapback event. In some examples, the memory controller 140 may then store a second logic state in the memory cells 105 by applying a second pulse having a second polarity based at least in part on detecting the first logic state during the write operation. The second logic state may be different from the first logic state.

FIG. 2 illustrates an example of a 3D memory array 200 that supports techniques for programming self-selecting memory devices, according to aspects of the present disclosure. The memory array 200 may be an example of a portion of the memory array 102 described with reference to FIG. 1. The memory array 200 may include a first array or deck 205 of memory cells positioned above a substrate 204 and a second array or deck 210 of memory cells positioned on top of the first array or deck 205. The memory array 200 may also include word lines 110-a and 110-b and bit lines 115-a, which may be examples of word lines 110 and bit lines 115 as described with reference to FIG. 1. The memory cells of the first and second decks 205, 210 may each have one or more self-selected memory cells (e.g., self-selected memory cell 220-a and self-selected memory cell 220-b, respectively). Although some elements included in fig. 2 are labeled with numerical indicators and other corresponding elements are not labeled, they are the same or will be understood to be similar in an attempt to increase the visibility and clarity of the depicted features.

The self-selecting memory cells of first deck 205 may include a first electrode 215-a, a chalcogenide material 220-a and a second electrode 225-a. Additionally, the self-selecting memory cells of the second deck 210 may include a first electrode 215-b, a chalcogenide material 220-b, and a second electrode 225-b. In some examples, the self-selected memory cells of the first and second levels 205 and 210 may have a common conductive line such that corresponding self-selected memory cells of each level 205 and 210 may share a bit line 115 or word line 110 as described with reference to fig. 1. For example, the first electrode 215-b of the second deck 210 and the second electrode 225-a of the first deck 205 may be coupled to the bit line 115-a such that the bit line 115-a is shared by vertically adjacent self-selected memory cells.

The architecture of the memory array 200 may be referred to in some cases as a cross-point architecture, in which memory cells are formed at topological cross-points between word lines and bit lines, as illustrated in fig. 2. The cross-point architecture provides relatively high density data storage at a lower manufacturing cost than other memory architectures. For example, the cross-point architecture may have memory cells with reduced area and thus increased memory cell density compared to other architectures. For example, the architecture may have a 4F2 memory cell area, where F is the minimum feature size, as compared to other architectures having a 6F2 memory cell area (e.g., architectures having a three-terminal select device). For example, a DRAM may use a transistor (which is a three terminal device) as the select component for each memory cell and may have a larger memory cell area compared to a cross-point architecture.

Although the example of FIG. 2 shows two memory levels, other configurations are possible. In some examples, a single memory level of self-selecting memory cells (which may be referred to as a two-dimensional memory) may be constructed over the substrate 204. In some examples, three or four memory levels of memory cells may be configured in a manner similar to that in one three-dimensional cross-point architecture.

In some examples, one or more of the memory levels may include a self-selecting memory cell 220 comprising a chalcogenide material. For example, the self-selecting memory cell 220 may include a chalcogenide glass, such As an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si), for example. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to As an SAG alloy. In some examples, the SAG alloy may include silicon (Si) and this chalcogenide material may be referred to as a SiSAG alloy. In some examples, chalcogenide glasses may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

In some examples, a self-selected memory cell 220 including a chalcogenide material may be programmed to a logic state by applying a first pulse having a first polarity. By way of example, when a particular self-selecting memory cell 220 is programmed, elements within the cell separate, causing ion migration. Depending on the polarity of the pulse applied to the memory cell, ions may migrate toward a particular electrode. For example, in the self-selecting memory cell 220, ions may migrate toward the negative electrode. The memory cell can then be read by applying a voltage for sensing across the cell. The threshold voltage seen during a read operation may be based on the ion distribution in the memory cell and the polarity of the read pulse. For example, if the memory cell has a given ion distribution, the threshold voltage detected during the read operation may be different for a first read pulse having a first polarity than for a second read pulse having a second polarity. Depending on the polarity of the memory cell, this concentration of mobile ions may represent a logic "1" or logic "0" state. This description of ion migration represents an example of a mechanism for self-selecting memory cells to achieve the results described herein. This example of a mechanism should not be considered limiting. The present disclosure also includes other examples of mechanisms for self-selecting memory cells to achieve the results described herein.

Prior to programming, the self-selecting memory cell 220 may have stored a first logic state (e.g., a logic "1"). A first pulse may be applied to, for example, word line 110-b. After applying the first pulse, a snapback event at the self-selected memory cell 220 may be detected in response to applying the first pulse. As described above, the snapback event may be characterized by selecting a reduced threshold voltage of memory cell 220. For example, as part of a snapback event, the memory cell may experience an increase (e.g., a sudden increase) in the conductivity of the memory cell. After a duration, the memory cell may return to its original conductivity. After the memory cell returns to its original conductivity, the memory cell may then experience a temporary decrease in its threshold voltage. This threshold decrease can be detected using a pulse having a positive or negative polarity. Thus, applying the first pulse may lower the threshold voltage (e.g., for a duration) of the self-selected memory cell 220. In some examples, the snapback event may be detected by a memory controller (e.g., by memory controller 140 as described above with reference to fig. 1). After detecting the snapback event, a second pulse having a second polarity different from the first polarity may be applied to the self-selecting memory cell 220. In some examples, the second pulse may be applied to bit line 115-b. Once a second pulse having a second polarity (e.g., a different polarity) is applied, a second logic state (e.g., a logic "0") may be stored in the self-selected memory cell 220.

FIG. 3 illustrates an example of a diagram 300 showing a distribution of threshold voltages of self-selecting memory cells, according to an example of the present disclosure. A self-selecting memory cell may be configured to store a particular logic state based on one or more pulses applied to the cell. The voltage distribution depicts the logic state that can be stored in the self-selecting memory cell.

The self-selected memory cell may include a chalcogenide material as described with reference to fig. 1 and 2. The threshold voltage distribution can represent a programming scheme for writing a logic state to the cell. The x-axes 305 and 305-a may represent voltage values for threshold voltage distributions of memory cells (e.g., memory cell 105 as described with reference to FIG. 1). The y-axis 310 may represent the likelihood that a threshold voltage may occur in a memory cell. Additionally or alternatively, fig. 3 may include a threshold voltage distribution 315 representing a first logic state and a threshold voltage distribution 320 representing a second (e.g., different) logic state. In some examples, fig. 3 can include a threshold voltage distribution 325 representing a first logic state and a threshold voltage distribution representing a second (e.g., different) logic state. In some examples, fig. 3 may include voltage levels 335, 340, 345, and 350, which may represent various voltage levels needed to access (e.g., write or read) a particular logic state of a memory cell.

In some examples, write operation 360 may be illustrated. In a first write operation 360, a self-selected memory cell can be written using a programming pulse having a first polarity and a first magnitude. The programming pulse may be configured to store a particular logic state (e.g., a logic "0") in the memory cell. For example, when a logic "0" is stored in a memory cell, the programming pulse may have a voltage level 345. After applying the voltage 350, the memory component of the memory cell may have an asymmetric distribution of material (e.g., ions) configured to store a logic state. Due to the asymmetric distribution, the threshold voltage observed by the sense component for a particular logic state can differ based on the polarity of the read pulse applied to the memory cell. For example, if a first read pulse having a first polarity is applied to the memory cells, the memory cells may exhibit the threshold voltage distribution indicated by group 365. In another example, if a second read pulse having a second polarity is applied to the memory cells, the memory cells may exhibit the threshold voltage distribution indicated by group 370.

For example, before the write operation 360 occurs, the memory cell may store a logic state (e.g., a logic "1"). Due to the write operation 360, a logic state (e.g., a logic "0") may be written to the memory cell. The memory cells may include a threshold voltage distribution for each logic state (e.g., threshold voltage distribution 320 or 330 for a logic "1"). To write a desired logic state to a memory cell, a particular voltage may be applied to the memory cell to overcome the threshold voltage of the memory cell. As shown in FIG. 3, voltage 350 may be used to write a logic "1" to the memory cell in some write operations. Thus, voltage 350 (e.g., VWRT1) may be applied to the memory cell to store a logic "1" in the memory cell for a duration of time. Because voltage 350 is a higher voltage (e.g., relative to voltage 340), the memory cells may eventually experience higher stress and the memory array associated with the memory cells (e.g., memory array 102 as described with reference to fig. 1) may consume less power.

In some examples, a write operation 355 may be illustrated. The write operation 355 may reduce stress on the memory cell and may cause a memory array associated with the memory cell to consume less power (e.g., relative to the write operation 360). In a write operation 355, the desired logic state may be written to the memory cell that has stored the current logic state. For example, the current logic state of the memory cell may be a logic "1" as represented by threshold voltage distribution 320 or 330, and the desired logic state may be a logic "0" as represented by threshold voltage distribution 315 or 325. To write a desired logic state (e.g., a logic "0") to the memory cell, a first pulse (e.g., voltage 340) having a first polarity and a first magnitude may be applied to the memory cell. As described above, a memory cell may include a particular threshold voltage distribution. By applying the first pulse to the memory cell, a snapback event may occur. The snapback event may be characterized by a reduction in a threshold voltage distribution associated with a logic state. In other words, by applying the first pulse to the memory cell, the threshold voltage distribution associated with the logic state may be shifted (e.g., toward 0V). When a snapshot event occurs, the distribution 315, 320, 325, or 330 may shift closer to the y-axis 310 for a duration of time. After abruptly moving into the y-axis 310, the distributions 315, 320, 325, and 330 can relax back to their original positions. The write operation 355 may be configured to write the opposite polarity cells before at least one of the distributions 315, 320, 325, and 330 fully recovers to its original location.

The occurrence of snapback caused by the applied voltage 340 may indicate that a logic "1" as represented by the threshold voltage distribution 320 is stored in the memory cell. The memory controller may reverse the polarity of the programming pulses (e.g., the memory controller may apply programming pulses having a polarity opposite to the pulse associated with the state stored on the memory cell) rather than applying programming pulses having a larger magnitude to write a logical "0". Thereby taking advantage of the asymmetric nature of programming self-selecting memory cells. Such features may reduce power consumed during the write operation 355 as compared to the write operation 360.

Because the snapback event results in a reduced voltage distribution of the memory cells, a lower voltage may be used to write the logic state to the memory cells (e.g., relative to the write operation 360). Thus, in some examples, a voltage greater than the threshold distribution of the memory cell can be applied to write a logic state to the memory cell. Using lower voltages may ultimately reduce stress on the memory cells and reduce power consumption of a memory array associated with the memory cells (e.g., memory array 102 as described with reference to fig. 1).

In some examples, an alternative write operation 355 may be illustrated. The write operation 355 may reduce stress on the memory cell and may cause a memory array associated with the memory cell to consume less power (e.g., relative to the write operation 360). In an alternate write operation 355, the desired logic state may be written to the memory cell that has stored the current logic state. For example, the current logic state of the memory cell may be a logic "0" as represented by threshold voltage distribution 315 or 325, and the desired logic state may be a logic "1" as represented by threshold voltage distribution 320 or 330.

To write a desired logic state (e.g., a logic "1") to the memory cell, a first pulse (e.g., voltage 335) having a first polarity and a first magnitude may be applied to the memory cell. As described above, a memory cell may include a particular threshold voltage distribution. By applying the first pulse to the memory cell, a snapback event may occur. The snapback event may be characterized by a reduction in a threshold voltage distribution associated with a logic state. In other words, by applying the first pulse to the memory cell, the threshold voltage distribution associated with the logic state may be shifted (e.g., toward 0V).

The occurrence of a snapback caused by applying voltage 335 may indicate that a logic "0" as represented by threshold voltage distribution 315 is stored in the memory cell. The memory controller may reverse the polarity of the programming pulses (e.g., the memory controller may apply programming pulses having a polarity opposite to the pulse associated with the state stored on the memory cell) rather than applying programming pulses having a larger magnitude to write a logic "1". Thereby taking advantage of the asymmetric nature of programming self-selecting memory cells. Such features may reduce power consumed during the write operation 355 as compared to the write operation 360.

Because the snapback event results in a reduced voltage distribution of the memory cells, a lower voltage may be used to write the logic state to the memory cells (e.g., relative to the write operation 360). Thus, in some examples, a voltage greater than the threshold distribution of the memory cell can be applied to write a logic state to the memory cell. Using lower voltages may ultimately reduce stress on the memory cells and reduce power consumption of a memory array associated with the memory cells (e.g., memory array 102 as described with reference to fig. 1).

FIG. 4 illustrates an example of a timing diagram 400 associated with a distribution of threshold voltages from selected memory cells, according to an example of the invention. A self-selecting memory cell may be configured to store a particular logic state based on one or more pulses applied to the cell. The voltage distribution depicts the logic state that can be stored in the self-selecting memory cell.

The self-selected memory cell may include a chalcogenide material as described with reference to fig. 1 and 2. The threshold voltage distributions can represent various logic states of the memory cells during a write operation. In the example of fig. 4, timing diagram 405 may represent writing a second logic state (e.g., a logic "1") to a memory cell storing a first logic state (e.g., a logic "0"). Timing diagram 410 may represent a write operation in which a memory cell stores the same logic state (e.g., logic "1") as is desired for the write operation (e.g., logic "1"). Timing diagram 415 may represent a write operation in which a memory cell stores the same logic state (e.g., logic "0") as is desired for the write operation (e.g., logic "0"). Timing diagram 420 may represent writing a second logic state (e.g., logic "0") to a memory cell storing a first logic state (e.g., logic "1").

Timing diagram 405 may depict a write operation (e.g., from a selected memory cell) of a memory cell. Timing diagram 405 may show a voltage 435, which may be referred to as a first pulse 435, and a voltage 440 (e.g., VHOLD), which may be referred to as a second pulse 440. In some cases, first pulse 435 may be an example of voltage 335 as described with reference to fig. 3, and second pulse 440 may be an example of voltage 340 as described with reference to fig. 3. Timing diagram 405 may also depict voltages 425 of an access line (e.g., word line 110 as described with reference to FIG. 1) and voltages 430 of an access line (e.g., bit line 115 as described with reference to FIG. 1). Thus, to write a memory cell, a first pulse 435 can be applied to the access line and subsequently a second pulse 440 can be applied to the second access line.

The memory cell associated with timing diagram 405 may store a first logic state (e.g., a logic "0"). To write a second logic state (e.g., a logic "1") to the memory cell, the first pulse 435 may be applied to the memory cell, as described above with reference to fig. 3. The first pulse 435 may be configured such that a snapback event occurs if the memory cell stores a first logic state but not if the memory cell stores a second logic state different from the first logic state. Thus, a first pulse 435 having a first polarity may be applied to the cell.

After applying the first pulse 435, a snapback event may occur that may be characterized by a decrease in the threshold voltage distribution of the memory cell. In some examples, the snapback event may be determined by a memory controller (e.g., memory controller 140 as described with reference to fig. 1). The snapback event may cause a threshold voltage associated with the memory cell to decrease. In some cases, the snapback event may cause the magnitude of the first pulse to decrease, as shown by first pulse 435-a.

The snapback event may occur for a fixed duration, and may then be followed by a period of time (e.g., duration 447) in which the memory cell is maintained in the higher conductivity state. This high conductivity state may be referred to as the select time. Thus, to write a second logic value (e.g., a logic "1") to the memory cell, a second pulse 440 may be applied. In some cases, the second pulse 440 may be similar to the first pulse 435-a, but with an inverted polarity. To reverse polarity, the voltages applied to the word lines and bit lines may be switched. As described with reference to fig. 3, a second pulse 440 having a second polarity (e.g., a different polarity) can be applied to the memory cell. In other words, the second pulse 440 may be applied to a respective access line. By applying the second pulse 440 during the select time (e.g., during duration 447), a second logic state (e.g., a logic "1") may be written to the memory cell using a reduced voltage compared to some write operations. As described above, the lower voltage may ultimately reduce stress on the memory cells and reduce power consumption of a memory array associated with the memory cells (e.g., memory array 102 as described with reference to fig. 1).

In some examples, second pulse 440 may not be applied during a select time (e.g., duration 447). Thus, the threshold voltage of the memory cell may increase to its original level. For example, in the context of timing diagram 405, if second pulse 440 is not applied during duration 447, the threshold voltage of the memory cell may increase to the voltage value depicted before duration 447. If second pulse 440 is applied after duration 447, for example, the magnitude of the pulse may be greater to achieve the same result of writing a logic state to the memory cell. In some examples, a memory cell may be selected after duration 447 by applying a voltage that is lower than the memory cell's original threshold voltage. For example, a threshold refresh operation may occur by selecting memory cells in either polarity after a duration 447 in the event that a write operation is not completed. Because the threshold recovery time of the memory cell may be greater after the duration 447 (e.g., relative to the duration 447), the memory cell may be deselected (e.g., by applying the same voltages to the word line and digit line of the memory cell). When deselected, additional snapback events or other array operations may be performed on other portions of the memory array before the write operation depicted by timing diagram 405 is completed. This may enable more efficient writing by efficiently combining multiple cells together for some stages of a write operation.

Timing diagram 410 may depict a portion of a write operation (e.g., from a selected memory cell) of a memory cell. Timing diagram 410 may show a first pulse 435-b applied to the memory cell. The first pulse 435-a may be an example of the voltage 335 as described with reference to fig. 3. Timing diagram 410 may also depict voltage 425-a of an access line (e.g., word line 110 as described with reference to FIG. 1), and voltage 430-a of an access line (e.g., bit line 115 as described with reference to FIG. 1).

The memory cells associated with timing diagram 410 may store a logic state (e.g., a logic "1"). To write a logic state (e.g., a logic "1") to the memory cell, a first pulse 435-a may be applied to the memory cell, as described above with reference to FIG. 3. Thus, a first pulse 435-a having a first polarity may be applied to the cell.

As described above, when a memory cell stores a first logic state (e.g., a logic "0"), a snapback event may occur when a second logic state (e.g., a logic "1") is written to the memory cell. However, when the same logical state as the memory cell is currently storing is written (e.g., attempted to be written) to the memory cell, a snapback event may not occur. In other words, a snapback event may not occur when a memory cell stores a logic "1" and attempts to write a logic "1" to the same cell. Thus, as illustrated in timing diagram 410, a snapback event does not occur and a write operation (e.g., an attempted write operation) may complete. The absence of the snapback event may be detected by not seeing a decrease in the magnitude of the first pulse 435-b. If no snapback is detected, the polarity of the programming pulses is not reversed as shown in timing diagram 405.

Timing diagram 415 may depict a portion of a write operation (e.g., from a selected memory cell) of a memory cell. Timing diagram 415 can show a first pulse 445 applied to the memory cell. First pulse 445 may be an example of voltage 340 as described with reference to fig. 3. Timing diagram 415 may also depict voltages 430-b of an access line (e.g., word line 110 as described with reference to FIG. 1) and voltages 425-b of a second access line (e.g., bit line 115 as described with reference to FIG. 1).

The memory cells associated with timing diagram 415 can store a logic state (e.g., a logic "0"). To write a logic state (e.g., a logic "0") to the memory cell, a first pulse 445 may be applied to the memory cell, as described above with reference to fig. 3. Thus, a first pulse 445 having a first polarity may be applied to the cell. As described above, when a memory cell stores a first logic state (e.g., a logic "1"), a snapback event may occur when a second logic state (e.g., a logic "0") is written to the memory cell.

However, when the same logical state as the memory cell is currently storing is written (e.g., attempted to be written) to the memory cell, a snapback event may not occur. In other words, a snapback event may not occur when a memory cell stores a logic "0" and attempts to write a logic "0" to the same cell. Thus, as illustrated in timing diagram 415, a snapback event does not occur and the write operation (e.g., the attempted write operation) may complete. The absence of the snapback event may be detected by not seeing a decrease in the magnitude of the first pulse 445. If no snapback is detected, the polarity of the programming pulses is not reversed as shown in timing diagram 405.

Timing diagram 420 may depict a write operation (e.g., from a selected memory cell) of a memory cell. Timing diagram 420 may show a voltage 445 that may be referred to as a first pulse 445 and a voltage 450 (e.g., VHOLD) that may be referred to as a second pulse 450. In some cases, first pulse 445 may be an example of voltage 335 as described with reference to fig. 3 and second pulse 450 may be an example of voltage 340 as described with reference to fig. 3. Timing diagram 420 may also depict voltages 430-c of an access (e.g., word line 110 as described with reference to FIG. 1), and voltages 425-c of a second access line (e.g., bit line 115 as described with reference to FIG. 1). Thus, to write a memory cell, a first pulse 445-a may be applied to an access line and subsequently a second pulse 450 may be applied to a second access line.

The memory cells associated with timing diagram 420 may store a first logic state (e.g., logic "1"). To write a second logic state (e.g., a logic "0") to the memory cell, a first pulse 445-a may be applied to the memory cell, as described above with reference to fig. 3. The first pulse 445-a may be configured such that a snapback event occurs if the memory cell stores a first logic state but not if the memory cell stores a second logic state different from the first logic state. Thus, a first pulse 445-a having a first polarity may be applied to the cell.

After applying the first pulse, a snapback event may occur that may be characterized by a decrease in the threshold voltage distribution of the memory cell. In some examples, the snapback event may be determined by a memory controller (e.g., memory controller 140 as described with reference to fig. 1). The snapback event may cause a threshold voltage associated with the memory cell to decrease. In some cases, the snapback event may cause the magnitude of the first pulse to decrease, as shown by the second pulse 450.

The snapback event may occur for a fixed duration, and may then be followed by a period of time (e.g., duration 447-a) in which the memory cell is maintained in the higher conductivity state. This high conductivity state may be referred to as the select time. Thus, to write a second logic value (e.g., a logic "1") to the memory cell, a second pulse 440-a may be applied. In some cases, the second pulse 450 may be similar to the first pulse 445-a, but with an inverted polarity. To reverse polarity, the voltages applied to the word lines and bit lines may be switched. As described with reference to fig. 3, a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. In other words, the second pulse 450 may be applied to the second access line. By applying the second pulse 450 during the select time (e.g., during duration 447-a), a second logic state (e.g., a logic "1") may be written to the memory cell using a reduced voltage compared to some write operations. As described above, the lower voltage may ultimately reduce stress on the memory cells and reduce power consumption of a memory array associated with the memory cells (e.g., memory array 102 as described with reference to fig. 1).

In some examples, second pulse 450 may not be applied during a select time (e.g., duration 447-a). Thus, the threshold voltage of the memory cell may increase to its original level. For example, in the context of timing diagram 420, if second pulse 450 is not applied during duration 447-a, the threshold voltage of the memory cell may increase to the voltage value depicted before duration 447-a. If second pulse 450 is applied after duration 447-a, for example, the magnitude of the pulse may be greater to achieve the same result of writing a logic state to the memory cell.

FIG. 5 shows a block diagram 500 of a snapback event detector 505 that supports techniques for programming memory cells, according to an example of the invention. The snapback event detector 505 may be an example of an aspect of a memory controller (e.g., the memory controller 140 as described with reference to fig. 1). Snapback event detector 505 may include an apply component 510, a detect component 515, a store component 520, a select component 525, a reduce component 530, a determine component 535, a bias component 540, and a timing component 545. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

The applying component 510 may apply a first pulse having a first polarity to a memory cell storing a first logic state during a write operation. In some examples, applying component 510 may apply a second pulse having a second polarity different from the first polarity to the memory cell in response to detecting a snapback event. In some examples, applying component 510 may apply a first voltage to a first access line coupled with a memory cell. In some examples, applying component 510 may apply a second voltage to a second access line coupled with the memory cell, wherein applying the first pulse is based at least in part on applying the first voltage and the second voltage.

In some examples, applying component 510 may apply a second voltage to the first access line. In some examples, applying component 510 may apply the first voltage to the second access line, wherein applying the second pulse is based at least in part on applying the first voltage to the second access line and applying the second voltage to the first access line. In some examples, applying component 510 may apply the second pulse to the memory cell during a duration when the threshold voltage is lowered. In some examples, applying component 510 may apply a first pulse having a first polarity to a memory cell storing a first logic state during a write operation. In some examples, applying component 510 may apply a first voltage to a first access line coupled with the memory cell. In some examples, applying component 510 may apply a second voltage to a second access line coupled with the memory cell, wherein applying the first pulse is based at least in part on applying the first voltage and the second voltage.

In some examples, during a write operation, applying component 510 may apply a second pulse to the memory cell during the duration, the second pulse having a second polarity different from the first polarity. In some examples, applying component 510 may apply a first pulse having a voltage across the memory cell in a first direction and a second pulse having a voltage across the memory cell in a second direction. In some examples, applying component 510 may apply a first pulse having a first polarity to the memory cell during a write operation. In some examples, applying component 510 may apply a second pulse having a second polarity different from the first polarity to the memory cell in response to detecting a snapback event.

In some examples, applying component 510 may apply a second pulse having a second polarity by applying a voltage to a second access line, the voltage being greater than the reduced threshold voltage. In some examples, applying component 510 may apply a first pulse having a first polarity to the memory cell during a duration. In some examples, applying component 510 may apply a first pulse having a first polarity by applying a first voltage to a first access line. In some examples, applying component 510 may apply a second pulse having a second polarity in which to write a second logic state to the memory cell by applying a second voltage to a second access line is based at least in part on a magnitude of the second voltage exceeding a threshold voltage of the memory cell.

The detection component 515 can detect a snapback event at the memory cell in response to applying the first pulse. The detection component 515 can detect a decrease in a magnitude of a voltage across a memory cell, wherein detecting the snapback event is based at least in part on detecting the decrease in the magnitude of the voltage. The detection component 515 can detect a snapback event based at least in part on a value of the first logic state being different from a value of a second logic state to be stored to the memory cell. The detection component 515 may detect a second snapback event at the memory cell in response to applying a second pulse to the memory cell after the duration.

The detection component 515 can detect a first logic state stored by the memory cell in response to applying a first pulse to the memory cell. Detection component 515 can detect the first logic state based at least in part on the threshold voltage of the memory cell being less than the magnitude of the first pulse. The detection component 515 can detect the first logic state during a duration after applying the first pulse, and wherein the second logic state is written to the memory cell during the duration. In some examples, detection component 515 may detect a snapback event at the memory cell during a duration after applying the first pulse. The detection component 515 can detect the first logic state during the duration and write the second logic state to the memory cell during the duration.

Storage component 520 may store a second logic state different from the first logic state in the memory cell based at least in part on applying the second pulse to the memory cell. In some examples, storage component 520 may store a second logic state in the memory cell by applying a second pulse having a second polarity in response to detecting the first logic state during a write operation, wherein the second logic state is different from the first logic state. Storage component 520 may store a second logic state to the memory cell based at least in part on the threshold voltage of the memory cell decreasing for a duration of time. In some examples, storage component 520 may store the second logical value in the memory cell after applying the second pulse.

The selection component 525 may select a voltage magnitude of the first pulse based at least in part on a value of a second logic state to be stored to the memory cell. In some examples, selection component 525 may select the first pulse from a plurality of pulses based at least in part on a value of a second logic state to be written to the memory cell.

The reducing component 530 may reduce the threshold voltage of the memory cell during a write operation by applying a first pulse having a first polarity to the memory cell for a duration of time, the memory cell comprising a first logic value. In some examples, reducing component 530 may reduce the threshold voltage of a memory cell after the duration by applying the first pulse having the first polarity to a memory cell during the write operation, the memory cell comprising a second logic value.

Determining component 535 can determine a first logical value of the memory cell based at least in part on lowering a threshold voltage of the memory cell during the write operation.

FIG. 6 shows a flow diagram illustrating a method 600 of supporting techniques for programming memory cells, in accordance with an aspect of the present invention. The operations of method 600 may be implemented by a memory controller or components thereof as described herein. For example, the operations of method 600 may be performed by a snapback event detector as described with reference to fig. 5. In some examples, a memory controller may execute a set of instructions to control the functional elements of the snapback event detector to perform the functions described below. Additionally or alternatively, the memory controller may perform aspects of the functions described below using dedicated hardware.

At 605, the memory controller may apply a first pulse having a first polarity to a memory cell storing a first logic state during a write operation. 605 may be performed according to the methods described herein. In some examples, aspects of the operations of 605 may be performed by an apply component as described with reference to fig. 5.

At 610, the memory controller may detect a snapback event at the memory cell in response to applying the first pulse. 610 may be performed according to the methods described herein. In some examples, aspects of the operations of 610 may be performed by a detection component as described with reference to fig. 5.

At 615, the memory controller may apply a second pulse having a second polarity different from the first polarity to the memory cell in response to detecting the snapback event. 615 may be performed in accordance with the methods described herein. In some examples, aspects of the operations of 615 may be performed by an apply component as described with reference to fig. 5.

At 620, the memory controller may store a second logic state different from the first logic state in the memory cell based on applying the second pulse to the memory cell. The operations of 620 may be performed according to the methods described herein. In some examples, aspects of the operations of 620 may be performed by a storage component as described with reference to fig. 5.

FIG. 7 shows a flow diagram illustrating a method 700 of supporting techniques for programming memory cells, in accordance with an aspect of the present invention. The operations of method 700 may be implemented by a memory controller or components thereof as described herein. For example, the operations of method 700 may be performed by a snapback event detector as described with reference to fig. 5. In some examples, a memory controller may execute a set of instructions to control the functional elements of the snapback event detector to perform the functions described below. Additionally or alternatively, the memory controller may perform aspects of the functions described below using dedicated hardware.

At 705, the memory controller may apply a first pulse having a first polarity to a memory cell storing a first logic state during a write operation. The operations of 705 may be performed in accordance with the methods described herein. In some examples, aspects of the operations of 705 may be performed by an apply component as described with reference to fig. 5.

At 710, the memory controller may detect a first logic state stored by the memory cell in response to applying a first pulse to the memory cell. 710 may be performed according to the methods described herein. In some examples, aspects of the operations of 710 may be performed by a detection component as described with reference to fig. 5.

At 715, the memory controller may store a second logic state in the memory cell by applying a second pulse having a second polarity in response to detecting the first logic state during the write operation, wherein the second logic state is different from the first logic state. 715 may be performed according to the methods described herein. In some examples, aspects of the operations of 715 may be performed by a storage component as described with reference to fig. 5.

FIG. 8 shows a flow diagram illustrating a method 800 of supporting techniques for programming memory cells, in accordance with an aspect of the present invention. The operations of method 800 may be implemented by a memory controller or components thereof as described herein. For example, the operations of method 800 may be performed by a snapback event detector as described with reference to fig. 5. In some examples, a memory controller may execute a set of instructions to control the functional elements of the snapback event detector to perform the functions described below. Additionally or alternatively, the memory controller may perform aspects of the functions described below using dedicated hardware.

At 805, the memory controller may reduce a threshold voltage of a memory cell during a write operation by applying a first pulse having a first polarity to the memory cell for a duration, the memory cell including a first logic value. 805 may be performed according to the methods described herein. In some examples, aspects of the operations of 805 may be performed by a lower component as described with reference to fig. 5.

At 810, during a write operation, the memory controller may apply a second pulse to the memory cell during the duration, the second pulse having a second polarity different from the first polarity. 810 may be performed according to the methods described herein. In some examples, aspects of the operations of 810 may be performed by an apply component as described with reference to fig. 5.

At 815, the memory controller may store a second logic value in the memory cell after applying the second pulse. 815 may be performed according to the methods described herein. In some examples, aspects of the operation of 815 may be performed by a storage component as described with reference to fig. 5.

A method is described. In some examples, the method may include applying a first pulse having a first polarity to a memory cell storing a first logic state during a write operation. In some examples, the method may include detecting a snapback event at the memory cell in response to applying the first pulse. The method may include applying a second pulse having a second polarity different from the first polarity to the memory cell in response to detecting the snapback event. The method may include storing a second logic state different from the first logic state in the memory cell based at least in part on applying the second pulse to the memory cell. In some examples, a method may include applying a first voltage to a first access line coupled with the memory cell. The method can include applying a second voltage to a second access line coupled with the memory cell, wherein applying the first pulse is based at least in part on applying the first voltage and the second voltage.

The method may include applying the second voltage to the first access line. The method may include applying the first voltage to the second access line, wherein applying the second pulse is based at least in part on applying the first voltage to the second access line and applying the second voltage to the first access line. In some examples, a method may include detecting a decrease in a magnitude of a voltage across the memory cell, wherein detecting the snapback event is based at least in part on detecting the decrease in the magnitude of the voltage. In some examples, the snapback event is based at least in part on a value of the first logic state being different from a value of the second logic state to be stored to the memory cell. In some examples, a method may include selecting a voltage magnitude of the first pulse based at least in part on a value of the second logic state to be stored to the memory cell.

In some examples, a threshold voltage of the memory cell is lowered based at least in part on applying the first pulse. In some examples, the reduced threshold voltage of the memory cell is based at least in part on the first logic state. In some examples, the magnitude of the threshold voltage of the memory cell is reduced for a duration in response to the occurrence of the snapback event. In some examples, the second pulse is applied to the memory cell during the duration when the threshold voltage is lowered. In some examples, the method may include performing a read operation or an additional write operation on the memory cell during the duration. In some examples, the second pulse may be applied after the duration. In some examples, operations other than a write operation may occur between the first pulse and the second pulse. In some examples, the method may include detecting a second snapback event at the memory cell in response to applying the second pulse to the memory cell after the duration. In some examples, the reduced threshold voltage of the memory cell is based at least in part on the first logic state. In some examples, the memory cell comprises a self-selecting memory cell.

In some examples, a threshold refresh operation may occur by selecting the memory cell in either polarity after the duration if the write operation is not completed. In some examples, when the memory cell is deselected, additional snapback events or other array operations may be performed on other portions of the memory array before the write operation is completed.

An apparatus is described. In some examples, the apparatus may support applying a first pulse having a first polarity to a means of storing a memory cell of a first logic state during a write operation. The apparatus may support means for detecting a snapback event at the memory cell in response to applying the first pulse. The apparatus may support means for applying a second pulse having a second polarity different from the first polarity to the memory cell in response to detecting the snapback event. The apparatus may support means for storing a second logic state different from the first logic state in the memory cell based at least in part on applying the second pulse to the memory cell. The apparatus may support means for applying a first voltage to a first access line coupled with the memory cell. The apparatus may support means for applying a second voltage to a second access line coupled with the memory cell, wherein applying the first pulse is based at least in part on applying the first voltage and the second voltage.

The apparatus may support means for applying the second voltage to the first access line. The apparatus may support means for applying the first voltage to the second access line, wherein applying the second pulse is based at least in part on applying the first voltage to the second access line and applying the second voltage to the first access line. The apparatus may support means for detecting a decrease in a magnitude of a voltage across the memory cell, wherein detecting the snapback event is based at least in part on detecting the decrease in the magnitude of the voltage. The apparatus may support means for selecting a voltage magnitude of the first pulse based at least in part on a value of the second logic state to be stored to the memory cell. The apparatus may support means for detecting a second snapback event at the memory cell in response to applying the second pulse to the memory cell after the duration.

A method is described. In some examples, the method may include applying a first pulse having a first polarity to a memory cell storing a first logic state during a write operation. The method may include detecting the first logic state stored by the memory cell in response to applying the first pulse to the memory cell. The method may include storing a second logic state in the memory cell by applying a second pulse having a second polarity in response to detecting the first logic state during the write operation, wherein the second logic state is different from the first logic state. The method can include applying a first voltage to a first access line coupled with the memory cell. The method can include applying a second voltage to a second access line coupled with the memory cell, wherein applying the first pulse is based at least in part on applying the first voltage and the second voltage.

In some examples, a threshold refresh operation may occur by selecting the memory cell in either polarity after the duration if the write operation is not completed. In some examples, when the memory cell is deselected, additional snapback events or other array operations may be performed on other portions of the memory array before the write operation is completed.

In some examples, applying the first voltage to the first access line lowers a threshold voltage of the memory cell. In some examples, the second voltage is greater than the lowered threshold voltage of the memory cell. In some examples, detecting the first logic state is based at least in part on a threshold voltage of the memory cell being less than a magnitude of the first pulse. In some examples, storing the second logic state to the memory cell is based at least in part on a threshold voltage of the memory cell being lowered for a duration of time. In some examples, the first polarity is opposite the second polarity. In some examples, the first logic state is detected during a duration after the first pulse is applied, and wherein the second logic state is written to the memory cell during the duration. In some cases, operations other than a write operation may be performed during the duration and/or before writing the second logic state to the memory cell.

An apparatus is described. In some examples, the apparatus may support applying a first pulse having a first polarity to a means of storing a memory cell of a first logic state during a write operation. The apparatus may support means for detecting the first logic state stored by the memory cell in response to applying the first pulse to the memory cell. The apparatus may support means for storing a second logic state in the memory cell by applying a second pulse having a second polarity in response to detecting the first logic state during the write operation, wherein the second logic state is different from the first logic state. The apparatus may support means for applying a first voltage to a first access line coupled with the memory cell. The apparatus may support means for applying a second voltage to a second access line coupled with the memory cell, wherein applying the first pulse is based at least in part on applying the first voltage and the second voltage.

A method is described. In some examples, the method may include reducing a threshold voltage of a memory cell for a duration of time during a write operation by applying a first pulse having a first polarity to the memory cell, the memory cell comprising a first logic value. The method can include applying a second pulse to the memory cell during the duration during the write operation, the second pulse having a second polarity different from the first polarity. The method may include storing a second logic value in the memory cell after applying the second pulse. The method may include determining the first logical value of the memory cell based at least in part on lowering the threshold voltage of the memory cell during the write operation. In some cases, the first logical value of the memory may be determined prior to completion of the write operation.

The method may include decreasing the threshold voltage of the memory cell after the duration by applying the first pulse having the first polarity to the memory cell during the write operation, the memory cell including the second logical value. In some examples, the magnitude of the second pulse applied to the memory cell is less than the magnitude of the first pulse. In some examples, the first pulse applies a voltage across the memory cell in a first direction and the second pulse applies a voltage across the memory cell in a second direction.

An apparatus is described. In some examples, the apparatus may support means for reducing a threshold voltage of a memory cell for a duration of time during a write operation by applying a first pulse having a first polarity to the memory cell, the memory cell comprising a first logic value. The apparatus may support applying a second pulse to the means of the memory cell during the duration during the write operation, the second pulse having a second polarity different from the first polarity. The apparatus may support means for storing a second logical value in the memory cell after applying the second pulse. The apparatus may support means for determining the first logical value of the memory cell based at least in part on lowering the threshold voltage of the memory cell during the write operation. The apparatus may support means for decreasing the threshold voltage of the memory cell after the duration by applying the first pulse having the first polarity to the memory cell during the write operation, the memory cell including the second logical value.

An apparatus is described. In some examples, the apparatus may include: a first access line coupled with a memory cell storing a first logic state; a second access line coupled with the memory cell; and a memory controller coupled with the first access line and the second access line. In some examples, the memory controller may be configured to: applying a first pulse having a first polarity to the memory cell during a write operation; detecting a snapback event at the memory cell in response to applying the first pulse; applying a second pulse having a second polarity different from the first polarity to the memory cell in response to detecting the snapback event; and storing a second logic state different from the first logic state in the memory cell based at least in part on applying the second pulse to the memory cell.

In some examples, the memory controller is configured to detect the snapback event at the memory cell during a duration after applying the first pulse. In some examples, the memory cell includes a reduced threshold voltage during the duration. In some examples, applying the second pulse having the second polarity includes applying a voltage to the second access line that is greater than the reduced threshold voltage.

An apparatus is described. In some examples, the apparatus may include: a first access line coupled with a memory cell storing a first logic state; a second access line coupled with the memory cell; and a memory controller coupled with the first access line and the second access line. In some examples, the memory controller may be configured to: applying a first pulse having a first polarity to the memory cell during a write operation; detecting the first logic state stored by the memory cell in response to applying the first pulse to the memory cell; and storing a second logic state in the memory cell by applying a second pulse having a second polarity based at least in part on detecting the first logic state during the write operation, wherein the second logic state is different from the first logic state.

In some examples, the memory controller is operable to apply the first pulse having the first polarity to the memory cell during a duration of time. In some examples, the first logic state is detected during the duration and the second logic state is written to the memory cell during the duration. In some examples, applying the first pulse having the first polarity comprises applying a first voltage to the first access line and applying the second pulse having the second polarity comprises applying a second voltage to the second access line, wherein writing the second logic state to the memory cell is based at least in part on a magnitude of the second voltage exceeding a threshold voltage of the memory cell. In some examples, the memory controller is operable to select the first pulse from a plurality of pulses based at least in part on a value of the second logic state to be written to the memory cell.

It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Further, aspects from two or more of the methods may be combined.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, those skilled in the art will appreciate that the signals may represent a signal bus, where the bus may have various bit widths.

The terms "electronic communication" and "coupling" refer to the relationship between components that support electronic flow between the components. This may include direct connections between the components or may include intermediate components. Components that are in electronic communication or coupled with each other may or may not actively exchange electrons or signals (e.g., in a powered-on circuit), but may be configured and operable to exchange electrons or signals upon powering-on to a circuit. By way of example, two components physically connected via a switch (e.g., a transistor) are in electronic communication or can be coupled regardless of the state (i.e., open or closed) of the switch.

As used herein, the term "substantially" means that a modifying property (e.g., a verb or adjective substantially modified by the term) need not be absolute, but sufficiently close to achieve the benefit of the property.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. The electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide conductive paths between memory array 102 elements or components.

The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorous, boron or arsenic. The doping may be performed during initial formation or growth of the substrate by ion implantation or by any other doping method.

The description set forth herein, in connection with the appended drawings, describes example configurations and is not intended to represent all examples that may be implemented or may be within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "superior to other instances. The detailed description contains specific details for the purpose of providing an understanding of the described technology. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. When only the first reference label is used in the specification, the description may apply to any one of the similar components having the same first reference label, regardless of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or program code on a computer-readable medium. Other examples and implementations are within the scope of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement a function may also be physically located at various positions, including portions that are distributed such that the function is implemented at different physical locations. Also, as used herein, including in the claims, an "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one" or "one or more") indicates that the list is included, such that, for example, a list of at least one of A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, exemplary steps described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

Computer-readable media includes both non-transitory computer storage media and communication media, including any medium that facilitates transfer of a computer program from one location to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, a non-transitory computer-readable medium may comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), Compact Disc (CD) ROM or other magneto-optical memory, magnetic disk memory or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.