阅读说明：本技术 非易失性存储器及其数据写入方法 (Nonvolatile memory and data writing method thereof ) 是由 何文乔 于 2019-10-08 设计创作，主要内容包括：本发明提供一种非易失性存储器及其数据写入方法。非易失性存储器包括存储器阵列以及存储器控制器。存储器阵列具有多个存储单元。存储器控制器用以对多个选中存储单元进行数据写入操作。在数据写入操作中,存储器控制器记录提供的数据写入脉冲的总次数,通过比较数据写入脉冲的总次数与预设的临界值以获得指示值,并依据指示值调整数据写入脉冲的电压绝对值。(The invention provides a nonvolatile memory and a data writing method thereof. The non-volatile memory includes a memory array and a memory controller. The memory array has a plurality of memory cells. The memory controller is used for carrying out data writing operation on a plurality of selected memory units. In the data writing operation, the memory controller records the total times of the data writing pulses, obtains an indication value by comparing the total times of the data writing pulses with a preset critical value, and adjusts the voltage absolute value of the data writing pulses according to the indication value.)

1. A data writing method of a nonvolatile memory, comprising:

performing data writing operation on a plurality of selected storage units;

recording a total number of data write pulses supplied in the data write operation;

comparing the total times of the data writing pulses with a preset critical value to obtain an indicated value; and

and adjusting the voltage absolute value of the data writing pulse according to the indicated value.

2. The data writing method according to claim 1, wherein the step of comparing the total number of data writing pulses with the preset critical value to obtain the indication value comprises:

adjusting the indication value when the total number of data write pulses is greater than the critical value; and

and increasing the voltage absolute value of the data writing pulse according to the indicated value.

3. The data writing method of claim 2, wherein the step of adjusting the indication value when the total number of data writing pulses is greater than the critical value comprises:

increasing the indication value by an offset value.

4. The data writing method according to claim 1, wherein when the data writing operation is an erase operation, the data writing method further comprises:

recording the total number of erase pulses provided;

comparing the total times of the erasing pulses with a preset erasing critical value to obtain an erasing indication value;

and adjusting the voltage absolute value of the erasing pulse according to the erasing indication value.

5. The data writing method according to claim 4, wherein the step of comparing the total number of erase pulses with the preset erase threshold to obtain the erase indication value comprises:

adjusting the erase indication value when the total number of erase pulses is greater than the erase threshold; and

and increasing the voltage absolute value of the erasing pulse according to the erasing indication value.

6. The data writing method of claim 5, wherein the step of adjusting the erasure indication value when the total number of the erase pulses is greater than the erasure threshold comprises:

the erasure indication value is incremented by an offset value.

7. The data writing method according to claim 1, wherein when the data writing operation is a program operation, the data writing method further comprises:

recording the total number of programming pulses provided;

comparing the total times of the programming pulses with a preset programming critical value to obtain a programming indication value; and

and adjusting the voltage absolute value of the programming pulse according to the programming indication value.

8. The method of claim 7, wherein comparing the total number of programming pulses with a predetermined threshold value to obtain a programmed indicator value comprises:

adjusting the program indicator value when the total number of the program pulses is greater than the program threshold value; and

and increasing the voltage absolute value of the programming pulse according to the programming indication value.

9. The method of claim 8, wherein the step of adjusting the program indicator when the total number of program pulses is greater than the program threshold comprises:

increasing the programmed indication value by an offset value.

10. The data writing method according to claim 1, wherein the step of performing the data writing operation on the plurality of selected memory cells includes:

and selecting the selected storage units according to the address information.

Technical Field

The present invention relates to a memory device and a data writing method thereof, and more particularly, to a nonvolatile memory device and a data writing method thereof capable of increasing a lifetime.

Background

For non-volatile memories (e.g., flash memories), the flash memory usually needs to be completed by a plurality of pulsed cycling operations when performing erase (erase) operations and program (program) operations. For example, in an erase operation of a flash memory, one or more erase pulses may be applied to selected memory cells and measured for variations in threshold voltage (threshold voltage) of the selected memory cells. Similarly, in a programming operation of the flash memory, one or more programming pulses may be applied to a selected memory cell and the variation in threshold voltage of the selected memory cell is measured.

However, after the flash memory undergoes multiple erase operations and program operations, the memory cells in the flash memory may be degraded, and the threshold voltage may not be changed as expected. In this case, when a data read operation is performed on the flash memory, a read margin (read margin) may be insufficient, which may cause a read data read error.

Disclosure of Invention

The invention provides a nonvolatile memory and a data writing method thereof, which can prolong the service life of the memory and improve the correctness of reading data.

The non-volatile memory of the present invention includes a memory array and a memory controller. The memory array has a plurality of memory cells. The memory controller is coupled to the memory array. The memory controller is used for carrying out data writing operation on a plurality of selected memory units. In the data writing operation, the memory controller records the total times of the data writing pulses, obtains an indication value by comparing the total times of the data writing pulses with a preset critical value, and adjusts the voltage absolute value of the data writing pulses according to the indication value.

The data writing method of the nonvolatile memory comprises the following steps: performing data writing operation on a plurality of selected storage units; recording a total number of data write pulses supplied in a data write operation; comparing the total number of data write pulses with a preset critical value to obtain an indication value; the absolute value of the voltage of the data write pulse is adjusted in accordance with the instruction value.

In view of the above, the nonvolatile memory according to the present invention can perform the adjustment operation of the indication value according to the total number of data write pulses applied during the data write operation and the change state of the threshold voltage of the corresponding selected memory cell. The nonvolatile memory adjusts the absolute value of the voltage of the data write pulse according to the indication value, and can select the proper voltage of the data write pulse according to the deterioration state of the selected memory cell, so as to maintain the read boundary provided by the nonvolatile memory, thereby prolonging the service life of the whole nonvolatile memory and improving the accuracy of the read data.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a non-volatile memory according to an embodiment of the invention;

FIG. 2 is a flowchart illustrating an erase operation and a program operation according to the present invention;

fig. 3A to fig. 3E are schematic waveforms illustrating steps of fig. 2 according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an erase pulse and a program pulse according to an embodiment of the present invention;

fig. 5 is a flowchart of a data writing method of a nonvolatile memory according to an embodiment of the present invention.

Description of reference numerals:

100: nonvolatile memory

110: memory array

120: memory controller

130: voltage generator

140. 140': storage device

DWPE, V0, V1: voltage of

EP: erase pulse

EIND: erase indicator

EV: level of erase voltage

IND: indication value

PP: programmed pulse

PIND: programmed indicator

PV: level of programming voltage

RD: read voltage

S21, S22, S23a to S26a, S23b to S26b, and S51 to S54: step (ii) of

VL1, VL 2: voltage level

Vt: critical voltage

WP: data write pulse

Detailed Description

FIG. 1 is a diagram of a non-volatile memory 100 according to an embodiment of the invention. Referring to fig. 1, in the present embodiment, a nonvolatile memory 100 includes a memory array 110, a memory controller 120, a voltage generator 130, and a storage device 140. The memory array 110 has a plurality of memory cells. The memory controller 120 is coupled to the memory array 110 for performing a data write operation on a selected one of the memory cells of the memory array 110.

On the other hand, the voltage generator 130 is coupled to the memory controller 120. The voltage generator 130 is used for generating the voltage DWPE of the data write pulse WP according to the indication value IND. Memory device 140 is coupled to memory controller 120. The storage device 140 is used to record the indication value IND, wherein the storage device 140 may be a non-volatile memory, but the invention is not limited thereto.

Specifically, in the present embodiment, the indication value IND may be preset to an initial value. When the memory controller 120 performs a data writing operation on the selected memory cells, the memory controller 120 may select one or more selected memory cells according to an address information, and apply a data writing pulse WP to the selected memory cells, wherein an absolute value of the voltage DWPE of the data writing pulse WP may be set according to the indication value IND. After the data write pulse WP is applied, the memory controller 120 can measure the threshold voltage of the selected memory cell and compare the threshold voltage of the selected memory cell with a write verify voltage to verify whether the data write operation is completed.

Continuing with the above description, if the memory controller 120 determines that the data write operation is not complete, the memory controller 120 can provide another data write pulse WP to be applied to the selected memory cell, measure the threshold voltage of the selected memory cell again, and compare the threshold voltage of the selected memory cell with the write verify voltage to verify whether the data write operation is complete. The application of the data write pulse WP and the verification of the completion of the data write operation each time form a data write verification cycle. It should be noted that the memory controller 120 can record the number of times of execution of the data write verification cycle (i.e., the total number WT1 of the data write pulses WP).

The memory controller 120 may compare the total count WT1 with a predetermined threshold N to obtain the indication value IND. To elaborate, if the total count WT1 is not greater than the predetermined threshold N, the memory controller 120 may maintain the value of the indication value IND, and if the total count WT1 is greater than the predetermined threshold N, the memory controller 120 adjusts the value of the indication value IND.

In the embodiment of the invention, when the total number WT1 is greater than the predetermined threshold N, it indicates that the selected memory cell has a certain degree of degradation. Accordingly, the memory controller 120 may adjust, for example, increase the value of the indication value IND according to the value of the indication value IND. It should be noted that the absolute value of the voltage DWPE of the data write pulse WP is set according to the indication value IND, so that after the value of the indication value IND is increased, the absolute value of the voltage DWPE of the data write pulse WP subsequently applied to the selected memory cell can be correspondingly increased, thereby maintaining the data accuracy of the selected memory cell.

In particular, in the embodiment of the present invention, when the nonvolatile memory 100 operates in a programming operation in a data writing operation, the data writing pulse WP applied to the selected memory cell by the memory controller 120 may be a programming pulse PP, and the indication value IND may be a programming indication value PIND. When the nonvolatile memory 100 operates in an erase operation of the data write operation, the data write pulse WP applied to the selected memory cell by the memory controller 120 may be an erase pulse EP, and the indication value IND may be an erase indication value EIND.

It is noted that the memory device 140 of the present embodiment can be disposed outside the memory array 110, or disposed inside the memory array 110 (as shown in the memory device 140' of fig. 1). In the embodiment, the memory device 140 disposed outside the memory array 110 is used as an example for explanation.

As can be understood from the above description of the embodiment of fig. 1, the nonvolatile memory 100 of the present embodiment can adjust the indication value IND stored in the memory device 140 according to the total number WT1 of the applied data write pulses WP and the variation state of the threshold voltage of the corresponding selected memory cell by the memory controller 120. When the selected memory cell is determined to be in a degraded state (e.g., the total number WT1 is greater than the predetermined threshold N), the voltage generator 130 increases the absolute value of the voltage DWPE of the data write pulse WP according to the adjusted indication value IND. In this way, in the subsequent data writing operation, the memory controller 120 can apply the data writing pulse WP with the increased voltage DWPE to the selected memory cell, so as to maintain the read margin provided by the nonvolatile memory 100, thereby prolonging the overall service life of the nonvolatile memory 100 and improving the accuracy of the read data.

FIG. 2 is a flowchart illustrating an operation of an erase operation and a program operation according to the present invention, and FIGS. 3A to 3E are waveforms corresponding to the steps shown in FIG. 2 according to an embodiment of the present invention. The data writing operation of the present embodiment may include an erase operation and a program operation.

Referring to fig. 1, fig. 2 and fig. 3A, in step S21, the memory controller 120 selects one or more selected memory cells from the memory array 110 according to the address information to obtain information of the erase voltage level EV and the program voltage level PV corresponding to the selected memory cells. That is, in step S21, the memory controller 120 can obtain information about the erase voltage level EV of the selected memory cell being preset to the voltage V0 and the program voltage level PV of the selected memory cell being preset to the voltage V0 from the memory array 110.

Next, referring to fig. 1, fig. 2 and fig. 3B, in step S22, the memory controller 120 initializes the erase voltage level EV and the program voltage level PV corresponding to the selected memory cell. For example, the memory controller 120 may initialize the voltage value corresponding to the level EV of the erase voltage to 3V, the voltage value corresponding to the level PV of the program voltage to 5V, and the voltage value corresponding to the read voltage RD of the nonvolatile memory 100 to 4V. The above-mentioned voltage values are merely examples, and the embodiments of the present invention are not limited to the above-mentioned examples.

Next, referring to fig. 1, fig. 2, fig. 3C and fig. 4, in step S23a, the memory controller 120 may perform a programming operation on the selected memory cell. In detail, in a programming operation, the memory controller 120 may apply a programming pulse PP to a selected memory cell, wherein an absolute value of the voltage DWPE of the programming pulse PP may be set according to the programming indication value PIND.

For example, as shown in FIG. 4, the memory controller 120 may generate the voltage DWPE having the first voltage level VL1 through the voltage generator 130, so that the memory controller 120 may apply the program pulse PP having the first voltage level VL1 to the selected memory cell. After the program pulse PP is applied, the memory controller 120 may measure a threshold Vt of the selected memory cell and verify whether the program operation is completed by comparing the threshold Vt of the selected memory cell with a program verify voltage.

Referring to fig. 3C, in the operation of measuring the threshold voltage Vt of the selected memory cell, when the nonvolatile memory 100 performs a program operation, the memory controller 120 may program the selected memory cell having the relatively low threshold voltage Vt into a memory cell having a relatively high threshold voltage Vt. Here, the selected memory cell may be regarded as a memory cell storing data of logic 0.

Specifically, in step S23a, if the memory controller 120 determines that the program operation is not completed, the memory controller 120 may provide another program pulse PP to be applied to the selected memory cell, measure the threshold voltage Vt of the selected memory cell again, and compare the threshold voltage Vt of the selected memory cell with the program verification voltage to verify whether the program operation is completed.

It should be noted that each of the above-mentioned applying of the program pulse PP and verifying whether the program operation is completed may form a program verification loop. The memory controller 120 may record the number of execution cycles of the program-verify loop (i.e. the total number WT2 of the program pulses PP) in the memory device 140.

Next, referring to fig. 1 and fig. 2, in step S24a, the memory controller 120 can determine whether the total number WT2 of the provided programming pulses PP is greater than a predetermined programming threshold NP. Specifically, the memory controller 120 may compare the total count WT2 with the predetermined programmed threshold NP to obtain the programmed indicator PIND. When the memory controller 120 determines that the total count WT2 is not greater than the predetermined programmed threshold NP, the memory controller 120 may execute step S26a to end the operation of step S24a and maintain the value of the programmed indicator PIND. In contrast, when the memory controller 120 determines that the total count WT2 is greater than the predetermined programmed threshold NP, the memory controller 120 may execute step S25a to adjust the value of the programmed indication PIND.

It should be noted that in the programming operation of the embodiment of the present invention, when the total number WT2 is greater than the predetermined programming threshold NP, it indicates that a certain degradation phenomenon has occurred in the selected memory cell.

Based on the above degradation of the nonvolatile memory 100, the memory controller 120 may continue to perform the operation of step S25a after step S24 a. Referring to fig. 1, fig. 2, fig. 3E and fig. 4, in step S25a, the memory controller 120 may adjust the magnitude of the program indication value PIND to adjust the level PV of the program voltage. For example, the memory controller 120 may increase the magnitude of the programmed indication value PIND by an offset value according to the determination result of step S24 a. Further, the memory controller 120 may store the adjusted programmed indication value PIND in the storage device 140 to update the preset initial value. Then, the memory controller 120 may increase the level PV of the programming voltage from the original voltage V0 to the voltage V1 according to the programming indication PIND increased by an offset value.

In addition, since the absolute value of the voltage DWPE of the programming pulse PP is set according to the programming indication value PIND, after the programming indication value PIND increases by an offset value, as shown in FIG. 4, the memory controller 120 can increase the voltage DWPE to the second voltage level VL2 through the voltage generator 130 according to the adjusted programming indication value PIND, so that the memory controller 120 can apply the programming pulse PP having the second voltage level VL2 to the selected memory cell, thereby maintaining the data accuracy of the selected memory cell.

It should be noted that, in other embodiments of the present invention, the memory controller 120 may also increase the magnitude of the programmed indication value PIND by two or more offset values according to the determination result of step S24 a. Thus, the memory controller 120 can further increase the absolute value of the voltage DWPE of the programming pulse PP by increasing the magnitude of the programming indication value PIND.

In this way, when the selected memory cell is degraded during the programming operation, the memory controller 120 of the embodiment can increase the magnitude of the programming indication value PIND according to the total number WT2 of the applied programming pulses PP and the variation state of the threshold voltage Vt of the corresponding selected memory cell, and thereby increase the absolute value of the voltage DWPE of the programming pulses PP, so as to effectively maintain the read margin provided by the nonvolatile memory 100, thereby prolonging the overall lifetime of the nonvolatile memory 100 and improving the accuracy of the read data.

On the other hand, referring to fig. 1, fig. 2, fig. 3D and fig. 4, in step S23b, the memory controller 120 may perform an erase operation on the selected memory cell. In detail, in the erase operation, the memory controller 120 may apply an erase pulse EP to the selected memory cell, wherein an absolute value of the voltage DWPE of the erase pulse EP may be set according to the erase indication value EIND.

For example, as shown in FIG. 4, memory controller 120 may generate voltage DWPE having first voltage level VL1 by voltage generator 130, such that memory controller 120 may apply an erase pulse EP having first voltage level VL1 to the selected memory cell. Also, after the application of the erase pulse EP is completed, the memory controller 120 may measure a threshold Vt of the selected memory cell and verify whether the program operation is completed by comparing the threshold Vt of the selected memory cell with an erase verify voltage.

Referring to fig. 3D, in the operation of measuring the threshold Vt of the selected memory cell, when the nonvolatile memory 100 performs an erase operation, the memory controller 120 can erase the selected memory cell having the relatively high threshold voltage Vt into a memory cell having a relatively low threshold voltage Vt. Here, the selected memory cell may be regarded as a memory cell storing data of logic 1.

Specifically, in step S23b, if the memory controller 120 determines that the erase operation is not complete, the memory controller 120 may provide another erase pulse EP to be applied to the selected memory cell, measure the threshold voltage Vt of the selected memory cell again, and compare the threshold voltage Vt of the selected memory cell with the erase verify voltage to verify whether the erase operation is complete.

It should be noted that the applying of the erase pulse EP and verifying whether the erase operation is completed each time can form an erase verification cycle. The memory controller 120 records the number of times of performing the erase verification cycle (i.e., the total number of times of the erase pulse EP WT3) in the memory device 140.

Next, referring to fig. 1 and fig. 2, in step S24b, the memory controller 120 can determine whether the total number WT3 of the erase pulses EP provided is greater than a predetermined erase threshold NE. Specifically, the memory controller 120 may compare the total count WT3 with the predetermined erase threshold NE to obtain an erase indication value EIND. Moreover, when the memory controller 120 determines that the total count WT3 is not greater than the predetermined erase threshold NE, the memory controller 120 may execute step S26b to end the operation of step S24b and maintain the value of the erase indication value EIND. In contrast, when the memory controller 120 determines that the total count WT3 is greater than the predetermined erase threshold NE, the memory controller 120 may execute step S25b to adjust the value of the erase indication value EIND.

It should be noted that, in the erasing operation of the embodiment of the present invention, when the total number WT3 is greater than the predetermined erasing threshold NE, it indicates that a certain degradation phenomenon has occurred in the selected memory cell.

Based on the above degradation of the nonvolatile memory 100, the memory controller 120 may continue to perform the operation of step S25b after step S24 b. Referring to fig. 1, fig. 2, fig. 3E and fig. 4, in step S25b, the memory controller 120 adjusts the value of the erase indication value PIND to adjust the level EV of the erase voltage. For example, the memory controller 120 may increase the value of the erasure indication value EIND by an offset value according to the determination result of step S24 b. Further, the memory controller 120 may store the adjusted erase indication value EIND to the storage device 140 to update the predetermined initial value. Then, the memory controller 120 may increase the erase voltage level EV from the original voltage V0 to the voltage V1 according to the erase indication EIND with an offset value.

In addition, since the absolute value of the voltage DWPE of the erase pulse EP is set according to the erase indication value EIND, as shown in FIG. 4, after the erase indication value EIND is increased by an offset value, the memory controller 120 can increase the voltage DWPE to the second voltage level VL2 through the voltage generator 130 according to the adjusted erase indication value EIND, so that the memory controller 120 can apply the erase pulse EP with the second voltage level VL2 to the selected memory cells, thereby maintaining the data accuracy of the selected memory cells.

It should be noted that, in other embodiments of the present invention, the memory controller 120 may also increase the value of the erasure indication value EIND by two or more offset values according to the determination result of step S24 b. Thus, the memory controller 120 can further increase the absolute value of the voltage DWPE of the erase pulse EP by increasing the value of the erase indication value EIND.

In this way, when the selected memory cell is degraded during the erase operation, the memory controller 120 of the present embodiment can increase the magnitude of the erase indication value EIND according to the total number WT3 of the applied erase pulse EP and the variation state of the threshold voltage Vt of the corresponding selected memory cell, and thereby increase the absolute value of the voltage DWPE of the erase pulse EP, so as to effectively maintain the read margin provided by the nonvolatile memory 100, thereby prolonging the overall lifetime of the nonvolatile memory 100 and improving the accuracy of the read data.

It should be noted that the threshold values N, NP, NE and the total times WT1, WT2, WT3 in the above embodiments can be adjusted according to the design requirements of the nonvolatile memory 100, and the invention is not limited to specific values. The predetermined thresholds N, NP, NE may be set according to the values of the offset values added by the indication value IND, the program indication value PIND, and the erase indication value EIND, respectively.

Fig. 5 is a flowchart of a data writing method of the nonvolatile memory 100 according to an embodiment of the invention. Referring to fig. 1 and 5, in step S51, the memory controller 120 may perform a data write operation on a plurality of selected memory cells. In step S52, in the data write operation, the memory controller 120 may record the total number of times of the data write pulses WP supplied. In step S53, the memory controller 120 may compare the total number of data write pulses WP with a preset threshold value N to obtain an indication value IND. In step S54, the memory controller 120 may adjust the absolute value of the voltage DWPE of the data write pulse WP according to the indication value IND.

The details of the steps are described in the foregoing embodiments and implementations, and are not repeated herein.

In summary, the nonvolatile memory of the present invention can perform the adjustment operation of the program indication value (or the erase indication value) according to the total number of program pulses (or erase pulses) applied during the program operation (or the erase operation) and the variation state of the threshold voltage of the corresponding selected memory cell. The non-volatile memory adjusts the absolute value of the voltage of the programming pulse (or the erasing pulse) according to the programming indication value (or the erasing indication value), can select the proper voltage of the programming pulse (or the erasing pulse) according to the deterioration state of the selected memory cell, maintains the reading boundary provided by the non-volatile memory, and prolongs the service life of the whole non-volatile memory and improves the accuracy of reading data.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.