阅读说明：本技术 集成晶体管器件及形成其的方法 (Integrated transistor device and method of forming the same ) 是由 关文豪 姚福伟 蔡俊琳 余俊磊 张庭辅 于 2019-12-24 设计创作，主要内容包括：在一些实施例中,本公开涉及一种集成晶体管器件及形成其的方法,所述集成晶体管器件包含布置在衬底上方的第一势垒层。另外,未掺杂层可以布置在第一势垒层上方且具有横向紧接p沟道器件区的n沟道器件区。未掺杂层的n沟道器件区具有最顶部表面,所述最顶部表面高于未掺杂层的p沟道器件区的最顶部表面。集成晶体管器件可更包括未掺杂层的n沟道器件区上方的第二势垒层。第一栅极电极布置在第二势垒层上方,且第二栅极电极布置在未掺杂层的p沟道器件区上方。本公开提供了防止形成寄生沟道,进而产生可靠的集成晶体管器件。(In some embodiments, the present disclosure relates to an integrated transistor device including a first barrier layer disposed over a substrate and a method of forming the same. Additionally, an undoped layer may be disposed over the first barrier layer and have an n-channel device region laterally proximate the p-channel device region. The undoped layer has an n-channel device region with a topmost surface that is higher than a topmost surface of the undoped layer's p-channel device region. The integrated transistor device may further include a second barrier layer over the undoped layer n-channel device region. A first gate electrode is disposed over the second barrier layer and a second gate electrode is disposed over the undoped layer p-channel device region. The present disclosure provides for preventing the formation of parasitic channels, thereby resulting in a reliable integrated transistor device.)

1. An integrated transistor device, comprising:

a first barrier layer disposed over a substrate;

an undoped layer disposed over the first barrier layer, wherein the undoped layer has an n-channel device region laterally immediately adjacent to a p-channel device region, wherein the n-channel device region of the undoped layer has a topmost surface that is higher than a topmost surface of the p-channel device region of the undoped layer;

a second barrier layer over the n-channel device region of the undoped layer;

a first gate electrode disposed over the second barrier layer; and

a second gate electrode disposed over the p-channel device region of the undoped layer.

2. The integrated transistor device of claim 1, wherein the second barrier layer is thinner than the first barrier layer.

3. The integrated transistor device of claim 1, further comprising:

a first doped layer and a second doped layer disposed above and in direct contact with the p-channel device region of the undoped layer, wherein the second gate electrode is between the first doped layer and the second doped layer.

4. The integrated transistor device of claim 1, further comprising:

a third doped layer disposed over the second barrier layer and below the first gate electrode; and

a first contact and a second contact disposed over the second barrier layer, wherein the third doped layer is between the first contact and the second contact.

5. The integrated transistor device of claim 1, further comprising:

a third gate electrode disposed over the second barrier layer and the n-channel device region of the undoped layer, wherein an additional isolation region is between the third gate electrode and the first gate electrode.

6. An integrated transistor device, comprising:

a first III/V semiconductor layer disposed over a substrate;

an undoped binary III/V semiconductor layer disposed over the first III/V semiconductor layer, wherein the undoped binary III/V semiconductor layer has an n-channel device region laterally flanking a p-channel device region, wherein the n-channel device region has a greater thickness than the p-channel device region;

a second III/V semiconductor layer disposed over the n-channel device region of the undoped binary III/V semiconductor layer;

a doped binary III/V source region and a doped binary III/V drain region disposed above the p-channel device region of the undoped binary III/V semiconductor layer;

a first gate electrode disposed over the second III/V semiconductor layer; and

a second gate electrode disposed over the undoped binary III/V semiconductor layer and between the doped binary III/V source region and the doped binary III/V drain region.

7. The integrated transistor device of claim 6, wherein a top surface of the first gate electrode is higher than a top surface of the second gate electrode.

8. A method of forming an integrated transistor device, comprising:

depositing a first barrier layer over a substrate, wherein the substrate comprises an n-channel device region immediately laterally adjacent to and continuously connected to a p-channel device region;

depositing an undoped layer over the first barrier layer;

depositing a second barrier layer over the undoped layer;

performing a first etch process on the p-channel device region of the substrate to remove the second barrier layer on the p-channel device region of the substrate and to remove an upper portion of the undoped layer on the p-channel device region of the substrate, wherein a lower portion of the undoped layer on the p-channel device region of the substrate has an upper surface that is lower than an uppermost surface of the undoped layer on the n-channel device region of the substrate;

selectively forming a doped layer over the lower portion of the undoped layer on the p-channel device region of the substrate;

forming a first gate electrode disposed over the second barrier layer; and

forming a second gate electrode disposed over the lower portion of the undoped layer.

9. The method of forming an integrated transistor device of claim 8, further comprising:

a plurality of buffer layers are formed over the substrate and under the first barrier layer, wherein the plurality of buffer layers and the first barrier layer comprise the same quaternary III/V semiconductor material.

10. The method of forming an integrated transistor device of claim 8, further comprising:

a first set of contacts formed over the second barrier layer and laterally spaced apart from the first gate electrode; and

forming a second set of contacts over the doped layer on the p-channel device region of the substrate, wherein the second gate electrode is between the second set of contacts.

Technical Field

Embodiments of the present disclosure relate to integrated transistor devices and methods of forming integrated transistor devices.

Background

Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Integrated Chips (ICs) may use many different types of transistor devices depending on the application of the IC. In recent years, the increased market for cellular and Radio Frequency (RF) devices has led to a significant increase in the use of high voltage transistor devices. Therefore, High Electron Mobility Transistor (HEMT) devices have received increased attention due to higher electron mobility and wide band gap compared to silicon-based semiconductor devices. Such high electron mobility and wide bandgap allow improved performance (e.g., fast switching speed, low noise) and high temperature applications.

Disclosure of Invention

An integrated transistor device of an embodiment of the present disclosure includes: a first barrier layer disposed over a substrate; an undoped layer disposed over the first barrier layer, wherein the undoped layer has an n-channel device region laterally immediately adjacent to a p-channel device region, wherein the n-channel device region of the undoped layer has a topmost surface that is higher than a topmost surface of the p-channel device region of the undoped layer; a second barrier layer, a first gate electrode over the n-channel device region of the undoped layer, disposed over the second barrier layer; and a second gate electrode disposed over the p-channel device region of the undoped layer.

An integrated transistor device of an embodiment of the present disclosure includes: a first III/V semiconductor layer disposed over a substrate; an undoped binary III/V semiconductor layer disposed over the first III/V semiconductor layer, wherein the undoped binary III/V semiconductor layer has an n-channel device region laterally flanking a p-channel device region, wherein the n-channel device region has a greater thickness than the p-channel device region; a second III/V semiconductor layer disposed over the n-channel device region of the undoped binary III/V semiconductor layer; a doped binary III/V source region and a doped binary III/V drain region disposed above the p-channel device region of the undoped binary III/V semiconductor layer; a first gate electrode disposed over the second III/V semiconductor layer; and a second gate electrode disposed over the undoped binary III/V semiconductor layer and between the doped binary III/V source region and the doped binary III/V drain region.

A method of forming an integrated transistor device of an embodiment of the present disclosure includes: depositing a first barrier layer over a substrate, wherein the substrate comprises an n-channel device region immediately laterally adjacent to and continuously connected to a p-channel device region; depositing an undoped layer over the first barrier layer; depositing a second barrier layer over the undoped layer; performing a first etch process on the p-channel device region of the substrate to remove the second barrier layer on the p-channel device region of the substrate and to remove an upper portion of the undoped layer on the p-channel device region of the substrate, wherein a lower portion of the undoped layer on the p-channel device region of the substrate has an upper surface that is lower than an uppermost surface of the undoped layer on the n-channel device region of the substrate; selectively forming a doped layer over the lower portion of the undoped layer on the p-channel device region of the substrate; forming a first gate electrode disposed over the second barrier layer; and forming a second gate electrode disposed over the lower portion of the undoped layer.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated High Electron Mobility Transistor (HEMT) device having an n-channel device and a p-channel device on the same substrate.

Fig. 2 shows a cross-sectional view of some additional embodiments of an integrated HEMT device having an n-channel device and a p-channel device on the same substrate.

Fig. 3 illustrates a cross-sectional view of some embodiments of an integrated HEMT device having a high-voltage power device, an n-channel device, and a p-channel device on the same substrate.

Fig. 4-20 show cross-sectional views of some embodiments of methods of forming an integrated HEMT device having an n-channel device and a p-channel device on the same substrate.

Fig. 21 shows a flow diagram corresponding to some embodiments of the method of fig. 4 to 20.

[ description of reference numerals ]

100. 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000: a cross-sectional view;

102: a substrate;

102 a: an n-channel device region;

102 b: a p-channel device region;

104: a first barrier layer;

106: a first undoped layer;

106 a: a sheet;

106 i: an intermediate upper surface;

106 t: a topmost surface;

108: a second barrier layer;

110: an n-channel device;

112: a p-channel device;

114: a dielectric structure;

116 a: a first contact member;

116 b: a second contact member;

118: a first gate electrode;

120: a first doped layer;

121: a second doped layer;

122 a: a third contact member;

122 b: a fourth contact member;

123: a third doped layer;

124: a second gate electrode;

126: an isolation region;

130: a first heterojunction;

132: a second heterojunction;

202: a contact hole;

302: a high voltage power device;

316 a: a fifth contact member;

316 b: a sixth contact member;

318: a third gate electrode;

320: buffer stacking;

322: a second buffer layer;

324: a first buffer layer;

330: a fourth doped layer;

340: a third idiosyncratic nodule;

406: a first undoped material;

408: a second barrier material;

420: doping a material;

502: a first mask layer;

602: a first etching process;

620: patterning the doped layer;

702: a second mask layer;

704: an opening;

802: selectively doping the layer;

804: an epitaxial growth process;

902: a third mask layer;

1002: a second etching process;

1102: an isolation implant process;

1104: a fourth mask layer;

1106: a first opening;

1202: a dielectric layer;

1204: a contact opening;

1302: a conductive layer;

1402: a fifth mask layer;

1602: an additional dielectric layer;

1702: a first gate opening;

1704: a second gate opening;

1706: a dielectric layer;

1802: a gate layer;

2100: a method;

2102. 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, 2122: an action;

d₁: a first distance;

t₁: a first thickness;

t₂: a second thickness;

t₃: a third thickness;

w₁: a first width;

w₂: a second width;

w₃: a third width.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms, such as "below …," "below," "lower," "above," "upper," and similar terms, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A High Electron Mobility Transistor (HEMT) device includes a heterojunction located at an interface between two materials having different band gaps and serving as a channel region of the HEMT device. In an enhancement-mode device (e.g., an enhancement-mode field effect transistor (E-FET)), the HEMT device uses a gate-to-source voltage to switch the HEMT device "on" (e.g., to "turn on" the current between the source and drain). In a depletion-mode device (e.g., a depletion-mode field effect transistor (D-FET)), the HEMT device uses the gate-to-source voltage to switch the device "off" (e.g., "turn off" the current between the source and drain).

For example, in the enhancement mode of an n-channel HEMT device, the conduction band at the heterojunction has a sharp valley that falls below and intersects the Fermi level, thereby forming a two-dimensional electron gas (2DEG) at the heterojunction when a gate-to-source voltage is applied. For example, in the enhancement mode of a p-channel HEMT device, the valence band at the heterojunction exhibits a peak above and intersecting the fermi level, thereby forming a two-dimensional hole gas (2DHG) at the heterojunction when a gate-to-source voltage is applied. In some applications, the p-channel HEMT device and the n-channel HEMT device are integrated onto the same substrate. However, parasitic 2DEG and 2DHG may form, interfering with the desired 2DEG and 2DHG and degrading device performance.

In some embodiments of an integrated HEMT device, a first undoped III-V layer may be disposed over a substrate and a barrier layer may be disposed over the first undoped III-V layer. An n-channel device can be disposed on the n-channel device region of the substrate, including in part disposing a second undoped III-V layer over the barrier layer. In enhancement mode, the desired 2DEG in an n-channel device can be formed between the barrier layer and the first undoped III-V layer. However, undesired parasitic 2DHG may also be formed between the second undoped III-V layer and the barrier layer. The parasitic 2DHG may interact with the desired 2DEG, assisting electron-hole recombination, and thus reducing the carrier density of the desired 2 DEG. In addition, parasitic 2 DHGs may cause a reduction in the sheet resistance of the 2DEG and may also cause leakage when the device is "off, thereby reducing device performance.

A p-channel device can be disposed on the p-channel device region laterally lateral to the n-channel device region of the substrate, including in part disposing a third undoped III-V layer over the barrier layer. In enhancement mode, the desired 2DHG in a p-channel device can be formed between the third undoped III-V layer and the barrier layer. However, an undesired parasitic 2DEG may also be formed between the barrier layer and the first undoped III-V layer. The parasitic 2DEG may interact with the desired 2DHG, assisting in electron-hole recombination, and thus reducing the carrier density of the desired 2 DHG. In addition, parasitic 2DEG may cause the sheet resistance of the 2DHG to decrease and may also cause leakage when the device is "off," thereby degrading device performance.

Various embodiments of the present disclosure provide a method and corresponding structure of an integrated HEMT device that eliminates unwanted parasitic channels to produce a reliable integrated HEMT device. In some embodiments, a first barrier layer is formed over a substrate, a first undoped layer is formed over the first barrier layer, a second barrier layer is formed over the first undoped layer and a first doped layer is formed over the second barrier layer. A selective etch is performed to remove the first doped layer, the second barrier layer, and an upper portion of the first undoped layer over the p-channel device region of the substrate. A second doped layer is grown on a lower portion of the first undoped layer on the p-channel device region of the substrate by an epitaxial growth process. Forming a remaining contact, a gate electrode, and an isolation structure, such n-channel device on an n-channel device region of the substrate, and a p-channel device on a p-channel device region of the substrate.

In such embodiments, because the second barrier layer is thin (e.g., less than 30 nanometers), the parasitic 2DHG channel is prevented or prevented from forming in the n-channel device, thereby preventing or preventing the valence band from intersecting the fermi level at the interface between the first doped layer and the second barrier layer. Since the first barrier layer is above and directly contacts the substrate (rather than the undoped layer), the parasitic 2DEG channel is prevented or prevented from being formed in the p-channel device, and thus no heterojunction is formed. Thus, the disclosed methods of forming integrated HEMT devices prevent or prevent the formation of parasitic channels, thereby resulting in reliable integrated HEMT devices without compromising, for example, carrier density, sheet resistance or on/off gate control.

Fig. 1 shows a cross-sectional view 100 of some embodiments of an integrated HEMT device including an n-channel device and a p-channel device.

In some embodiments, the integrated HEMT device in cross-section 100 includes a first barrier layer 104 disposed over a substrate 102. In some embodiments, first barrier layer 104 may comprise a III-V semiconductor material, such as, for example, indium aluminum gallium nitride (e.g., In)_xAl_yGa_1-x-yN, wherein x + y ═ 1, and wherein x can range from 0 to 1). In some embodiments, the substrate 102 may comprise, for example, silicon carbide, or sapphire. A first undoped layer 106 may be disposed over the first barrier layer 104. In some embodiments, the first undoped layer 106 may comprise a binary III-V semiconductor material, such as, for example, aluminum nitride, gallium nitride, or indium nitride. In some embodiments, the first undoped layer 106 has a topmost 104 surface 106t above the n-channel device region 102a of the substrate 102 that is higher than an intermediate upper surface 106i of the first undoped layer 106 above the p-channel device region 102b of the substrate 102. In some embodiments, the topmost surface 106t of the first undoped layer 106 may be at a first distance d above the middle upper surface 106i of the first undoped layer 106₁At the location of (a). For example, in some embodiments, the first distance d₁Can range between about 290 nanometers and about 990 nanometersInside the enclosure. In some embodiments, the first undoped layer 106 may have a different thickness due to the use of a thinner first undoped layer 106 for the p-channel device region 102b as compared to the n-channel device region 102a of the substrate 102. In some embodiments, the first undoped layer 106 has a bottom-most surface that is substantially coplanar.

In some embodiments, the n-channel device 110 may be disposed on the n-channel device region 102a of the substrate 102. The n-channel device 110 may include a second barrier layer 108 over a topmost surface 106t of the first undoped layer 106. In some embodiments, second barrier layer 108 may comprise a quaternary III-V semiconductor material, such as, for example, indium aluminum gallium nitride (e.g., In)_mAl_nGa_1-m-nN, wherein m + N ═ 1, and wherein m may range from 0 to 1). Thus, in some embodiments, first barrier layer 104 may comprise the same material with the same concentration of each element (e.g., x ≠ m and y ≠ n) as second barrier layer 108, while in other embodiments first barrier layer 104 may comprise a different concentration of each element (e.g., x ≠ m and y ≠ n) as second barrier layer 108. Thus, in some embodiments, the substrate 102 may comprise silicon, the first barrier layer 104 may comprise indium aluminum gallium nitride, the first undoped layer 106 may comprise indium nitride, and the second barrier layer 108 may comprise indium aluminum gallium nitride. In some embodiments, a first contact 116a and a second contact 116b may be disposed over the second barrier layer 108 and spaced apart from each other by the first doped layer 120. In some embodiments, the first doped layer 120 may comprise the same material as the first undoped layer 106; however, the first doping layer 120 also has a doping concentration. Accordingly, in some embodiments, the first doped layer 120 may comprise doped indium nitride. In some embodiments, the first doped layer 120 may correspond to a doped binary III/V gate region. A first gate electrode 118 may be arranged above the first doped layer 120, between the first contact 116a and the second contact 116b and surrounded by the dielectric structure 114.

In the enhancement mode, a two-dimensional electron gas (2DEG) may follow a first difference at the interface between first undoped layer 106 and second barrier layer 108 due to the difference in band gap between first undoped layer 106 and second barrier layer 108A mass junction 130 is formed. In some embodiments, parasitic two-dimensional hole gas (2DHG) is not formed at the interface between second barrier layer 108 and first doped layer 120 because second barrier layer 108 is sufficiently thin. For example, in some embodiments, the second barrier layer 108 may have a first thickness t less than about 20 nanometers₁. In other embodiments, the second barrier layer 108 may have a first thickness t less than about 30 nanometers₁. In some embodiments, first thickness t of second barrier layer 108 to efficiently prevent parasitic 2DHG formation₁May depend on the concentration of each element in second barrier layer 108. Additionally, in some embodiments, the parasitic 2DHG may not be formed on the n-channel device region 102a of the substrate 102 because the first doped layer 120 may be sufficiently thin and/or have a sufficiently low p-type dopant concentration. For example, in some embodiments, the first doped layer 120 may have a second thickness t less than 30 nanometers₂And/or may comprise about 10¹⁸A dopant concentration of p-type dopant per cubic centimeter. Thus, in some embodiments, the first thickness t of the second barrier layer 108₁Concentration of each element in the second barrier layer 108, second thickness t of the first doped layer 120₂And/or the dopant concentration of first doped layer 120 may be designed such that the conduction band is below the fermi level at the interface between second barrier layer 108 and first undoped layer 106 to form a 2DEG without forming a 2 DHG. Thus, the n-channel device 110 can utilize a 2DEG along the first heterojunction 130 without interference from a parasitic 2 DHG.

In some embodiments, the p-channel device 112 may be disposed on the p-channel device region 102b of the substrate 102. The p-channel device 112 may include a second doped layer 121 disposed above the intermediate upper surface 106i of the first undoped layer 106. The third doped layer 123 may also be disposed above the intermediate upper surface 106i of the first undoped layer 106 and spaced apart from the second doped layer 121 by the second gate electrode 124. In some embodiments, the second and third doped layers 123 may correspond to doped binary III/V source and drain regions, respectively, such that the second gate electrode 124 is disposed between the doped binary III/V source region (e.g., the second doped region 121) and the doped binary III/V drain region (e.g., the third doped region 123). In some embodiments, the second gate electrode 124 is spaced apart from the intermediate upper surface 106i of the first undoped layer 106 by the dielectric structure 114. In some embodiments, the third and fourth contacts 122a and 122b may be disposed over the second and third doped layers 121 and 123, respectively.

In the enhancement mode, a two-dimensional hole gas (2DHG) may form along the second heterojunction 132 at the interface between the first undoped layer 106 and the first barrier layer 104. In some embodiments, the 2DHG is formed, in part, due to the first undoped layer 106 on the p-channel device region 102b of the substrate 102 having a thickness in a range between, for example, about 10 nanometers and about 30 nanometers, thereby causing the valence band at the second heterojunction 132 to exhibit a peak above and intersecting the fermi level. In some embodiments, if the first undoped layer 106 on the p-channel device region 102b of the substrate 102 has a thickness greater than 30 nanometers, the 2DHG may not be formed at the second heterojunction 132 in the enhancement mode. Additionally, in some embodiments, the 2DHG may be formed along the second heterojunction 132 due in part to the elemental concentration of the first barrier layer 104. The parasitic 2DEG is not formed in the p-channel device 112 because the first barrier layer 104 does not overlie the undoped layer on the p-channel device region 102b of the substrate 102. In contrast, first undoped layer 106 is above first barrier layer 104, thereby forming a 2DHG instead of a 2 DEG. Thus, the p-channel device can utilize the 2DHG along the second heterojunction 132 without interference from the parasitic 2 DEG.

Thus, in some embodiments, the p-channel device 112 and the n-channel device 110 may be integrated on the same substrate 102 without forming parasitic 2 DHGs and 2 DHGs. Additionally, an isolation region 126 may surround the p-channel device 112 such that the p-channel device 112 is isolated from the n-channel device 110. In some embodiments, the isolation region 126 may extend through the first undoped layer 106 and into at least a portion of the first barrier layer 104 such that the isolation region 126 intersects the second heterojunction 132. Thus, in the enhancement mode, the isolation region 126 prevents the 2DEG along the first heterojunction 130 in the n-channel device 110 from interfering with the 2DHG along the second heterojunction 132 in the p-channel device 112.

Fig. 2 shows a cross-sectional view 200 of some other embodiments of an integrated HEMT device including an n-channel device and a p-channel device.

The integrated HEMT device in cross-section 200 includes a contact hole 202 embedded within the dielectric structure 114. Each of the first contact 116a, the first gate electrode 118, the second contact 116b, the second gate electrode 124, the third contact 122a, and the fourth contact 122b may be coupled to one of the contact holes 202. The contact holes 202 may be coupled to a voltage source to control the operation (e.g., "on", "off") of the n-channel device 110 and the p-channel device 112. In some embodiments, up to 20 volts may be applied across the n-channel device 110 and the p-channel device 112 through the contact holes 202. In other embodiments, the voltage bias applied to the n-channel device 110 and the p-channel device 112 may be in a range between about 1 volt and about 12 volts, for example. Additionally, unlike the cross-sectional view 100 in fig. 1, in some embodiments, the first doped layer (the first doped layer 120 of fig. 1) may be omitted such that the first gate electrode 118 directly contacts the dielectric structure 114, wherein the dielectric structure 114 separates the first gate electrode 118 from the second barrier layer 108. In such embodiments without the first doped layer (first doped layer 120 of fig. 1) under the first gate electrode 118, the n-channel device 110 may be a depletion mode device, wherein an applied voltage bias to the first gate electrode 118 causes the n-channel device 110 to become "off.

Fig. 3 shows a cross-sectional view 300 of some embodiments of an integrated HEMT device including an n-channel device, a p-channel device, and a high-voltage power device.

The integrated HEMT device in cross-section 300 includes an n-channel device 110 and a p-channel device 112 integrated over the same substrate 102. Additionally, in some embodiments, the high voltage power device 302 may be disposed above the substrate 102 and laterally proximate to the n-channel device 110 and the p-channel device 112. In some embodiments, the high voltage power device 302 may operate using a voltage greater than 100 volts. For example, in some embodiments, the high voltage power device 302 may operate using a voltage in a range between about 100 volts and about 1000 volts. Thus, in some embodiments, the high voltage power device 302 may operate using a voltage between 100 and 1000 times greater than the voltage applied to the n-channel device 110 and/or the p-channel device 112.

In cross-sectional view 300, high voltage power device 302 may be an n-channel enhancement mode device. Thus, the high voltage power device 302 may include a fifth contact 316a and a sixth contact 316b disposed over the second barrier layer 108, and in some embodiments, a fourth doped layer 330 separates the fifth contact 316a from the sixth contact 316 b. Fourth doped layer 330 may directly contact second barrier layer 108. In some embodiments, third gate electrode 318 is disposed above fourth doped layer 330.

In some embodiments, to accommodate operating voltages greater than 100 volts, sixth contact 316b may be spaced from fourth doped layer 330 and/or third gate electrode 318 by a second width w₂The second width is larger than the first width w between the fifth contact 316a and the fourth doped layer 330 and/or the third gate electrode 318₁. The fifth contact 316a may correspond to a source region of the high voltage power device 302 and the sixth contact 316b may correspond to a drain region of the high voltage power device 302. Similarly, the first contact 116a of the n-channel device 110 may correspond to a source region of the n-channel device 110, and the second contact 116b of the n-channel device 110 may correspond to a drain region of the n-channel device 110. The second contact 116b of the n-channel device 110 may be spaced apart from the first doped layer 120 and/or the first gate electrode 118 by a third width w₃. In some embodiments, the second width w₂May be greater than the third width w₃This is because the high voltage power device 302 utilizes a higher operating voltage than the n-channel device 110.

Similar to the n-channel device 110, in the high voltage power device 302, upon application of a sufficient voltage bias to the third gate electrode 318, a 2DEG may be formed at the interface between the second barrier layer 108 and the first undoped layer 106 or the third hetero-junction 340. The isolation region 126 may separate the third heterojunction 340 from the first heterojunction 130 in order to isolate the high-voltage power device 302 from the n-channel device 110. In other embodiments, the high voltage power device 302 may be immediately adjacent to the p-channel device 112, and thus, the isolation region 126 may separate the third heterojunction 340 from the second heterojunction 132.

In some embodiments, a buffer stack 320 may be disposed between the substrate 102 and the first barrier layer 104. The buffer stack 320 may include a second buffer layer 322 over the first buffer layer 324. The first buffer layer 324 and the second buffer layer 322 may each include indium aluminum gallium arsenide. In some embodiments, the first buffer layer 324 and the second buffer layer 322 may include the same concentration of each element, different concentrations of each element, or a combination thereof. The buffer stack 320 may reduce vertical electric field effects caused by the high voltage power device 302. The total number of layers in the buffer stack 320 may depend on the operating voltage used to operate the high voltage power device 302. For example, in some embodiments, a first number of layers may be used in the buffer stack 320 if the operating voltage of the high voltage power device 302 is 500 volts, whereas a second number of layers, less than the first number of layers, may be used in the buffer stack 320 if the operating voltage of the high voltage power device 302 is 100 volts. Nonetheless, the buffer stack 320 allows the high voltage power device 302 to withstand and maintain its high voltage without interfering with the first heterojunction 130 of the n-channel device 110 and the second heterojunction 132 of the p-channel device 112, respectively.

Fig. 4-20 illustrate cross-sectional views 400-2000 of some embodiments of methods of forming an integrated HEMT device comprising an n-channel device and a p-channel device on the same substrate. Although fig. 4-20 are described with respect to a method, it should be understood that the structure disclosed in fig. 4-20 is not limited to such a method, but instead may stand alone as a method independent structure.

As depicted in the cross-sectional view 400 of fig. 4, a substrate 102 is provided. In some embodiments, substrate 102 comprises silicon, sapphire, or silicon carbide. In some embodiments, the substrate 102 may comprise p-type silicon, which is a widely available substrate and thus reduces the cost of HEMT devices. A first barrier layer 104 may be deposited over the substrate 102. In some embodiments, the first barrier layer 104 may include a quaternary III-V semiconductor material, such as, for example, indium aluminum gallium arsenide. The first barrier layer 104 may have a thickness in a range between approximately 20 nanometers and approximately 50 nanometers. A first undoped material 406 may be deposited over and directly contacting the first barrier layer 104A barrier layer 104. The first undoped material 406 may comprise a III-V semiconductor material or a III-N semiconductor material, such as, for example, aluminum nitride, indium nitride, gallium nitride, or the like. In some embodiments, the first undoped material 406 may have a thickness in a range between about 0.3 microns and about 1 micron. A second barrier material 408 may be deposited over the first undoped material 406. In some embodiments, the second barrier material 408 may comprise a quaternary III-V semiconductor material, such as, for example, indium aluminum gallium arsenide. In some embodiments, the second barrier material 408 may include a different concentration of each element of indium aluminum gallium arsenide than the first barrier layer 104, while in other embodiments, the second barrier material 408 may include the same concentration of each element of indium aluminum gallium arsenide as the first barrier layer 104. In some embodiments, the second barrier material 408 may have a first thickness t in a range between about 10 nanometers and about 30 nanometers₁. Thus, in some embodiments, the second barrier material 408 may be thinner than the first barrier layer 104. A first thickness t₁May be less than 30 nanometers to prevent parasitic channels from forming in the n-channel device to be formed over the substrate 102 (see n-channel device 110 of fig. 1).

In some embodiments, a doping material 420 may be deposited over the second barrier material 408. The doped material 420 may comprise the same material as the first undoped material 406, but with a doping concentration. For example, in some embodiments, the doped material 420 may comprise a p-type III-V semiconductor material, such as, for example, aluminum nitride, indium nitride, gallium nitride, or the like. In some embodiments, the doped material 420 is lightly doped (e.g., less than 10)¹⁸One dopant per cubic centimeter) to prevent a parasitic channel from forming in an n-channel device to be formed over the substrate 102 (see, n-channel device 110 of fig. 1). Similarly, in some embodiments, the doped material 420 may have a second thickness t less than 30 nanometers₂To prevent a parasitic channel from forming in the n-channel device to be formed over the substrate 102 (see n-channel device 110 of fig. 1). In other embodiments, it will be appreciated that the dopant material 420 may be omitted, such as in devices including n-channel devices (shown in the figure)2 n-channel device 110), the n-channel device is a depletion mode device, as in fig. 2.

In some embodiments, the first barrier layer 104, the first undoped material 406, the second barrier material 408, and/or the doped material 420 may be deposited by an epitaxial process and/or another form of deposition process (e.g., Chemical Vapor Deposition (CVD), metal organic chemical vapor deposition (MO-CVD), plasma enhanced chemical vapor deposition (PE-CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), sputtering, electron beam/thermal evaporation, etc.).

As depicted in the cross-sectional view 500 of fig. 5, a first mask layer 502 may be formed over the n-channel device region 102a of the substrate 102, while the p-channel device region 102b of the substrate 102 may remain uncovered. Since the n-channel device region 102a and the p-channel device region 102b are part of the same substrate 102, the n-channel device region 102a of the substrate 102 may be laterally lateral to the p-channel device region 102b of the substrate 102 and continuously connected to the p-channel device region 102b of the substrate 102. In some embodiments, first masking layer 502 may comprise a photosensitive material (e.g., photoresist) formed over doping material 420 by a spin-on process. In such embodiments, the layer of photosensitive material is selectively exposed to electromagnetic radiation according to a photomask. The electromagnetic radiation may modify the solubility of the exposed regions within the photosensitive material to define soluble regions. The photosensitive material can then be subsequently developed to define openings within the photosensitive material by removing the soluble regions. In other embodiments, the first mask layer 502 may comprise a hard mask layer (e.g., a silicon nitride layer, a silicon carbide layer, or the like).

As illustrated in the cross-sectional view 600 of fig. 6, a first etch process 602 may be performed to remove the doped material (the doped material 420 of fig. 5) on the p-channel device region 102b of the substrate 102 and to remove an upper portion of the first undoped material (the first undoped material 406 of fig. 5) on the p-channel device region 102b of the substrate 102. In some embodiments, the first etch process 602 may be a wet etch or a dry etch. In the first placeAfter an etch process 602, a patterned doped layer 620 is disposed over the second barrier layer 108, the second barrier layer 108 is disposed over the first undoped layer 106, and the first undoped layer 106 is disposed over the first barrier layer 104 on the n-channel device region 102a of the substrate 102. A sheet 106a of first undoped layer 106 is disposed over the first barrier layer 104 on the p-channel device region 102b of the substrate 102. In some embodiments, sheet 106a of first undoped layer 106 may have a third thickness t in a range between about 10 nanometers and about 30 nanometers₃。

Thus, in some embodiments, the first etch process 602 may be controlled to remove the first distance d of the first undoped material (the first undoped material 406 of fig. 5) on the p-channel device region 102b of the substrate 102₁. In some embodiments, the first distance d₁May be in a range between about 270 nanometers and about 990 nanometers, for example. In some embodiments, since the sheet 106a is disposed over the p-channel device region 102b of the substrate 102, which laterally surrounds a portion of the first undoped layer 106 disposed over the n-channel device region 102a of the substrate 102 (e.g., the n-channel device region of the first undoped layer 106), the sheet 106a may correspond to the p-channel device region of the first undoped layer 106.

Third thickness t of the sheet 106a₃The p-channel device region 102b of the substrate 102 may be allowed to form a 2DHG during operation in the enhancement mode. In some embodiments, if the third thickness t₃Too large (e.g., greater than 30 nanometers), then the 2DHG may not be formed on the p-channel device region 102b of the substrate 102, and thus the p-channel device region 102b of the substrate 102 will be unreliable. In some embodiments, the first undoped layer 106 is thicker on the n-channel device region 102a of the substrate 102 than the sheet 106a because the n-channel device region 102a of the substrate 102 relies on the thicker (e.g., greater than 30 nanometers) first undoped layer 106 to form a 2DEG during operation in the enhancement mode.

As depicted in the cross-sectional view 700 of fig. 7, in some embodiments, the first mask layer (the first mask layer 502 of fig. 5) may be removed and a second mask layer 702 may be formed over the patterned doped layer 620 and the first undoped layer 106. The second mask layer 702 also covers the sidewalls of the patterned doped layer 620, the second barrier layer 108, and the first undoped layer 106. The opening 704 in the second mask layer 702 exposes the first undoped layer 106 on the p-channel device region 102b of the substrate 102. In some embodiments, second masking layer 702 can be deposited and patterned using similar lithographic techniques as used to form the first masking layer (first masking layer 502 of FIG. 5). In some embodiments, the second mask layer 702 may be a hard mask and may be an amorphous material.

As depicted in the cross-sectional view 800 of fig. 8, a selective epitaxial growth process 804 may be performed to selectively deposit a selectively doped layer 802 within the opening of the second mask layer 702 (the opening 704 of fig. 7) over the p-channel device region 102b of the substrate 102. The selective epitaxial growth process 804 may be an epitaxial process or another form of deposition process (e.g., Chemical Vapor Deposition (CVD), metal organic chemical vapor deposition (MO-CVD), plasma enhanced chemical vapor deposition (PE-CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), sputtering, e-beam/thermal evaporation, etc.). The selective epitaxial growth process 804 may be selective to the first undoped layer 106 such that the selectively doped layer 802 directly contacts the first undoped layer 106 because the first undoped layer 106 may be a crystalline material. The selective epitaxial growth process 804 may prevent the formation of the selective doping layer 802 on the second mask layer 702 because the second mask layer 702 is an amorphous material.

In some embodiments, selectively doped layer 802 comprises a p-type binary III-V semiconductor material, such as, for example, aluminum nitride, indium nitride, gallium nitride, or the like. In some embodiments, the selectively doped layer 802 may comprise the same material as the patterned doped layer 620, while in other embodiments, the selectively doped layer 802 may comprise a different material than the patterned doped layer 620. In some embodiments, selectively doped layer 802 may be formed to a thickness of less than, for example, about 30 nanometers. In some embodiments, selectively doped layer 802 is lower than patterned doped layer 620.

As depicted in cross-sectional view 900 of fig. 9, a third mask layer 902 may be formed over portions of patterned doped layer 620 and selective doped layer 802, while other portions of patterned doped layer 620 and selective doped layer 802 remain uncovered. The third mask layer 902 may be deposited and patterned using similar lithographic techniques as used to form the first mask layer (first mask layer 502 of fig. 5).

As illustrated in the cross-sectional view 1000 of fig. 10, a second etch process 1002 may be performed in accordance with the third mask layer 902. In some embodiments, the second etch process 1002 may be a dry etch or a wet etch and may be selective to the selectively doped layer (the selectively doped layer 802 of fig. 9) and the patterned doped layer (the patterned doped layer 620 of fig. 9). Thus, after the second etch process 1002, portions of the selectively doped layer (selectively doped layer 802 of fig. 9) and the patterned doped layer (patterned doped layer 620 of fig. 9) are removed, thereby forming the first doped layer 120 over the second barrier layer 108 and the second doped layer 121 and the third doped layer 123 over the first undoped layer 106.

As illustrated in the cross-sectional view 1100 of fig. 11, a fourth mask layer 1104 may be formed over the first doped layer 120, the second doped layer 121, and the third doped layer 123. The fourth mask layer 1104 may include a first opening 1106. In some embodiments, the first opening 1106 may be a continuous ring shape surrounding the second doping layer 121 and the third doping layer 123 from a top view. The isolation implant process 1102 may be performed above the fourth mask layer 1104 such that the isolation region 126 is formed within the first opening 1106 in the fourth mask layer 1104. The fourth mask layer 1104 may prevent the isolation implant process 1102 from affecting other features of the cross-sectional view 1100. In some embodiments, the isolation implant process 1102 may include implanting iron, chlorine, fluorine, or the like into the first undoped layer 106 not covered by the fourth mask layer 1104. In other embodiments, the isolation implant process 1102 may involve forming a Shallow Trench Isolation (STI) structure such that the isolation region 126 comprises silicon dioxide.

In some embodiments, isolation region 126 may also be a continuous ring shape that surrounds second doped layer 121 and third doped layer 123. In some embodiments, the isolation region 126 may extend from a top surface of the first undoped layer 106 on the p-channel device region 102b of the substrate 102 to the first barrier layer 104. In some embodiments, the isolation region 126 extends through the second heterojunction 132 at the interface between the first undoped layer 106 and the second and third doped layers 121 and 123 and into the first barrier layer 104. Accordingly, the isolation region 126 may separate the second heterojunction 132 from the first heterojunction 130 along the interface between the first barrier layer 104 and the first undoped layer 106 to prevent cross-interference and/or parasitic channels between the first device on the n-channel device region 102a of the substrate 102 and the second device on the p-channel device region 102b of the substrate 102.

As depicted in the cross-sectional view 1200 of fig. 12, a dielectric layer 1202 may be formed that defines a contact opening 1204. The contact opening 1204 may be patterned such that the contact opening 1204 overlies the second barrier layer 108 on either side of the first doped layer 120 and overlies the second doped layer 121 and the third doped layer 123. The dielectric layer 1202 defining the contact opening 1204 may be formed by deposition and photolithography processes. In some embodiments, the dielectric layer 1202 may comprise, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., carbon-doped oxide, SiCOH), or the like.

As depicted in cross-sectional view 1300 of fig. 13, a conductive layer 1302 can be formed over the dielectric layer 1202 and within the contact opening 1204. In some embodiments, conductive layer 1302 may comprise a material, such as, for example, titanium or aluminum, that creates an Ohmic contact (Ohmic contact) with second barrier layer 108 and second and third doped layers 121 and 123. In other embodiments, the conductive layer 1302 can comprise, for example, copper, tungsten, or the like. The conductive layer 1302 can be formed by a deposition process (e.g., Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), etc.).

As depicted in the cross-sectional view 1400 of fig. 14, a fifth mask layer 1402 can be formed over the conductive layer 1302. In some embodiments, a fifth mask layer 1402 may have been formed by deposition and photolithography processes overlying the contact openings (contact openings 1204 of fig. 12).

As depicted in the cross-sectional view 1500 of fig. 15, a third etch process (selective to the conductive layer (1302 of fig. 14)) can be performed to remove the conductive layer (1302 of fig. 14) not protected by the fifth mask layer 1402. In some embodiments, the third etch process may include a wet etchant or a dry etchant. After the third etching process, the remaining conductive layer (conductive layer 1302 of fig. 14) defines the first contact 116a, the second contact 116b, the third contact 122a, and the fourth contact 122 b. Thus, in some embodiments, the first contact 116a, the second contact 116b, the third contact 122a, and the fourth contact 122b may comprise the same material.

As depicted in the cross-sectional view 1600 of fig. 16, the fifth mask layer (the fifth mask layer 1402 of fig. 15) is removed (e.g., stripped), and an additional dielectric layer 1602 is deposited over the dielectric layer 1202. The additional dielectric layer 1602 may be formed in the same manner as the dielectric layer 1202 and also includes the same materials as the dielectric layer 1202.

As illustrated in the cross-sectional view 1700 of fig. 17, a first gate opening 1702 and a second gate opening 1704 may be formed in the plurality of dielectric layers 1706. The plurality of dielectric layers 1706 includes a dielectric layer (dielectric layer 1202 of fig. 16) and an additional dielectric layer (additional dielectric layer 1602 of fig. 16). In some embodiments, a masking layer (not shown) and subsequent etching may be used to remove portions of the plurality of dielectric layers 1706 to define the first gate opening 1702 and the second gate opening 1704. In some embodiments, the first gate opening 1702 may expose the first doped layer 120 on the n-channel device region 102a of the substrate, and the second gate opening 1704 may be disposed between the second doped layer 121 and the third doped layer 123. However, in some embodiments, the second gate opening 1704 may not extend completely through the plurality of dielectric layers 1706. Thus, in some embodiments, the second gate opening 1704 may have a bottom surface defined by the plurality of dielectric layers 1706.

As depicted in the cross-sectional view 1800 of fig. 18, a gate layer 1802 can be deposited over the plurality of dielectric layers 1706 and fill the first gate opening (the first gate opening 1702 of fig. 17) and the second gate opening (the second gate opening 1704 of fig. 17). In some embodiments, the gate layer 1802 can include a conductive material, such as, for example, titanium nitride, nickel, tungsten, titanium, or platinum. In some embodiments, the gate layer 1802 may form a Schottky contact (Schottky contact) with the first doped layer 120 and/or the plurality of dielectric layers 1706. However, in other embodiments, the gate layer 1802 is not limited to a material that forms a schottky contact. The gate layer 1802 can be formed by a deposition process (e.g., Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), etc.).

As depicted in the cross-sectional view 1900 of fig. 19, the gate layer (gate layer 1802 of fig. 18) may be patterned to form the first gate electrode 118 over the first doped layer 120 and the second gate electrode 124 over the plurality of dielectric layers 1706 and between the second doped layer 121 and the third doped layer 123. In some embodiments, the gate layer (gate layer 1802 of fig. 18) may be patterned using photolithography and etching processes. In some embodiments, the first gate electrode 118 and the second gate electrode 124 may have upper portions that are wider than lower portions.

As illustrated in the cross-sectional view 2000 of fig. 20, additional dielectric material may be deposited over the plurality of dielectric layers (the dielectric layer 1706 of fig. 19) to form the dielectric structure 114 over the substrate 102. Accordingly, the dielectric structure 114 may cover the first gate electrode 118 and the second gate electrode 124, thereby isolating the n-channel device 110 disposed over the n-channel device region 102a of the substrate 102 from the p-channel device 112 disposed over the p-channel device region 102b of the substrate 102. In addition, because the second barrier layer 108 is thin (e.g., less than 30 nanometers), during operation, a 2DEG is formed on the n-channel device 110 along the first heterojunction 130, and the 2DHG parasitic channel is not formed on the n-channel device region 102a of the substrate 102. Similarly, because the first barrier layer 104 directly contacts the substrate 102, during operation, the 2DHG is formed on the p-channel device along the second heterojunction 132, and the 2DEG parasitic channel is not formed on the p-channel device region 102b of the substrate 102. The integrated HEMT device in the cross-sectional view 2000 of fig. 20 is a reliable device with optimal sheet resistance and minimal current leakage along the first and second heterojunctions 130 and 132 by isolating the p-channel device 112 from the n-channel device 110 and by preventing parasitic channels from forming in the p-channel device 112 and the n-channel device.

Fig. 21 shows a flow diagram of some embodiments of a method 2100 of forming an integrated HEMT device comprising an n-channel device and a p-channel device on the same substrate.

While the method 2100 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Additionally, one or more of the acts depicted herein may be performed in one or more separate acts and/or phases.

At act 2102, a first barrier layer is deposited over a substrate.

At act 2104, a first undoped layer is deposited over the first barrier layer.

At act 2106, a second barrier layer is deposited over the first undoped layer. Fig. 4 illustrates a cross-sectional view 400 of some embodiments corresponding to act 2102, act 2104, and act 2106.

At act 2108, a first etch process is performed on the p-channel device region of the substrate to remove the second barrier layer and an upper portion of the first undoped layer, wherein a lower portion of the undoped layer remains on the p-channel device region of the substrate. Figure 6 illustrates a cross-sectional view 600 of some embodiments corresponding to act 2108.

At act 2110, a doped layer is selectively grown on a lower portion of the first undoped layer. Fig. 8 illustrates a cross-sectional view 800 of some embodiments corresponding to act 2110.

At act 2112, a second etch process is performed to remove a central portion of the doped layer. Figure 10 illustrates a cross-sectional view 1000 of some embodiments corresponding to act 2112.

At act 2114, an isolation region is formed within the first undoped layer and between the n-channel device region and the p-channel device region of the substrate. Figure 11 illustrates a cross-sectional view 1100 of some embodiments corresponding to act 2114.

At act 2116, a first set of contacts is formed over the peripheral portion of the doped layer.

At act 2118, a second set of contacts is formed on the second barrier layer. Fig. 12-15 illustrate cross-sectional views 1200-1500 of some embodiments corresponding to acts 2116 and 2118.

At act 2120, a first gate is formed on an n-channel device region of a substrate and over a second barrier layer.

At act 2122, a second gate is formed between peripheral portions of the doped layers and over the first undoped layer on the p-channel device region of the substrate. Figures 16-19 illustrate cross-sectional views 1600-1900 of some embodiments corresponding to acts 2120 and 2122.

Accordingly, the present disclosure relates to a new method of fabricating an integrated HEMT device without forming a parasitic channel in order to produce a reliable integrated HEMT device comprising an n-channel device and a p-channel device on the same substrate.

Accordingly, in some embodiments, the present disclosure relates to an integrated transistor device comprising: a first barrier layer disposed over a substrate; an undoped layer disposed over the first barrier layer, wherein the undoped layer has an n-channel device region laterally proximate to the p-channel device region, wherein the n-channel device region of the undoped layer has a topmost surface that is higher than a topmost surface of the p-channel device region of the undoped layer; a second barrier layer over the undoped layer n-channel device region; a first gate electrode arranged over the second barrier; and a second gate electrode disposed over the undoped layer p-channel device region.

In some embodiments, an isolation region is within the undoped layer and between the first gate electrode and the second gate electrode. In some embodiments, the second barrier layer is thinner than the first barrier layer. In some embodiments, the first barrier layer directly contacts the substrate. In some embodiments, a first doped layer and a second doped layer disposed above and in direct contact with the p-channel device region of the undoped layer, wherein the second gate electrode is between the first doped layer and the second doped layer. In some embodiments, a third doped layer disposed above the second barrier layer and below the first gate electrode; and a first contact and a second contact disposed over the second barrier layer, wherein the third doped layer is between the first contact and the second contact. In some embodiments, the second barrier layer has a thickness of less than about 30 nanometers. In some embodiments, a buffer layer is disposed between the first barrier layer and the substrate, wherein the buffer layer comprises the same elements as the first barrier layer. In some embodiments, a third gate electrode is disposed over the second barrier layer and the n-channel device region of the undoped layer, with an additional isolation region between the third gate electrode and the first gate electrode.

In other embodiments, the present disclosure relates to an integrated transistor device comprising: a first III/V semiconductor layer disposed over a substrate; an undoped binary III/V semiconductor layer disposed above the first III/V semiconductor layer, wherein the undoped binary III/V semiconductor layer has an n-channel device region laterally flanking the p-channel device region, wherein the n-channel device region has a greater thickness than the p-channel device region; a second III/V semiconductor layer disposed over the n-channel device region of the undoped binary III/V semiconductor layer; a doped binary III/V source region and a doped binary III/V drain region disposed above the p-channel device region of the undoped binary III/V semiconductor layer; a first gate electrode disposed over the second III/V semiconductor layer; and a second gate electrode disposed over the undoped binary III/V semiconductor layer and between the doped binary III/V source region and the doped binary III/V drain region.

In some embodiments, a top surface of the first gate electrode is higher than a top surface of the second gate electrode. In some embodiments, an isolation region is disposed between the first gate electrode and the second gate electrodeBetween poles and extending from a top surface of the p-channel device region of the undoped binary III/V semiconductor layer to the first III/V semiconductor layer. In some embodiments, a doped binary III/V gate region is disposed between the second III/V semiconductor layer and the first gate electrode. In some embodiments, the doped binary III/V gate region has less than about 10¹⁸A doping concentration of p-type dopant per cubic centimeter.

In yet other embodiments, the present disclosure relates to a method of forming an integrated transistor device, comprising: depositing a first barrier layer over the substrate, wherein the substrate comprises an n-channel device region laterally proximate to and continuously connected to the p-channel device region; depositing an undoped layer over the first barrier layer; depositing a second barrier layer over the undoped layer; performing a first etch process on the p-channel device region of the substrate to remove the second barrier layer on the p-channel device region of the substrate and to remove an upper portion of the undoped layer on the p-channel device region of the substrate, wherein a lower portion of the undoped layer on the p-channel device region of the substrate has an upper surface that is lower than an uppermost surface of the undoped layer on the n-channel device region of the substrate; selectively forming a doped layer over a lower portion of the undoped layer on a p-channel device region of the substrate; forming a first gate electrode disposed over the second barrier layer; and forming a second gate electrode disposed over a lower portion of the undoped layer.

In some embodiments, an isolation process is performed to form an isolation region through the undoped layer and between the first gate electrode and the second gate electrode. In some embodiments, a doped gate region is formed over the second barrier layer on the n-channel device region of the substrate, wherein the doped gate region is between the first gate electrode and the second barrier layer. In some embodiments, the doped gate region has a thickness of less than about 30 nanometers. In some embodiments, a plurality of buffer layers are formed over the substrate and under the first barrier layer, wherein the plurality of buffer layers and the first barrier layer comprise the same quaternary III/V semiconductor material. In some embodiments, a first set of contacts formed over the second barrier layer and laterally spaced apart from the first gate electrode; and forming a second set of contacts over the doped layer on the p-channel device region of the substrate, wherein the second gate electrode is between the second set of contacts.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.