阅读说明：本技术 显示面板及其制作方法、拼接显示面板 (Display panel, manufacturing method thereof and spliced display panel ) 是由 卢马才 于 2020-12-10 设计创作，主要内容包括：本发明提供一种显示面板及其制作方法、拼接显示面板。显示面板包括阵列基板、发光部以及驱动芯片,发光部电连接于阵列基板的一侧,驱动芯片电连接于阵列基板的另一侧。阵列基板包括衬底基板、显示电路及扇出电路,显示电路设置于衬底基板的第一侧上,显示电路包括TFT层、存储电容器以及信号走线,扇出电路设置于衬底基板的第二侧上,扇出走线的一端电连接于驱动芯片,扇出走线的另一端电连接于信号走线,TFT层的遮光层与源极层同层设置,半导体层与遮光层及源极层连接,像素电极层与半导体层连接。本发明能够简化显示面板的电路结构,减小显示面板所需的黄光制程的道数,从而有利于制作成本降低及良率提升。(The invention provides a display panel, a manufacturing method thereof and a spliced display panel. The display panel comprises an array substrate, a light emitting part and a driving chip, wherein the light emitting part is electrically connected to one side of the array substrate, and the driving chip is electrically connected to the other side of the array substrate. The array substrate comprises a substrate, a display circuit and a fan-out circuit, the display circuit is arranged on a first side of the substrate, the display circuit comprises a TFT layer, a storage capacitor and a signal wiring line, the fan-out circuit is arranged on a second side of the substrate, one end of the fan-out wiring line is electrically connected to a driving chip, the other end of the fan-out wiring line is electrically connected to the signal wiring line, a light shielding layer and a source electrode layer of the TFT layer are arranged on the same layer, a semiconductor layer is connected with the light shielding layer and the source electrode layer. The invention can simplify the circuit structure of the display panel and reduce the number of yellow light processing procedures required by the display panel, thereby being beneficial to reducing the manufacturing cost and improving the yield.)

1. A display panel is characterized by comprising an array substrate, a light emitting part and a driving chip, wherein the light emitting part is electrically connected to one side of the array substrate, and the driving chip is electrically connected to the other side of the array substrate;

the array substrate includes:

a substrate base plate having a first side and a second side opposite the first side;

the display circuit is arranged on the first side of the substrate base plate and comprises a TFT layer, a storage capacitor and a signal wire, wherein the TFT layer comprises a light shielding layer, a source layer, a semiconductor layer, a grid electrode insulating layer and a grid electrode layer; and

the fan-out circuit is arranged on the second side of the substrate base plate, one end of the fan-out wiring is electrically connected to the driving chip, and the other end of the fan-out wiring is electrically connected to the signal wiring;

the light shielding layer and the source electrode layer are arranged on the same layer, the semiconductor layer is connected with the light shielding layer and the source electrode layer, and the pixel electrode layer is connected with the semiconductor layer.

2. The display panel according to claim 1, wherein the array substrate comprises a first metal layer and a second metal layer stacked on each other, the first metal layer comprises the light shielding layer and the source layer, the second metal layer comprises the gate layer, the gate insulating layer is located between the first metal layer and the second metal layer, and the semiconductor layer is located between the first metal layer and the gate insulating layer.

3. The display panel according to claim 2, wherein an interlayer dielectric layer is disposed between the first metal layer and the gate insulating layer, the interlayer dielectric layer includes a first via hole and a second via hole, the semiconductor layer is located in the first via hole and the second via hole, the semiconductor layer is connected to the light shielding layer through the first via hole, and the semiconductor layer is connected to the gate layer through the second via hole.

4. The display panel according to claim 3, wherein the storage capacitor includes a first metal electrode, a second metal electrode, and a pixel electrode which are provided in an insulating manner, wherein the first metal layer includes the first metal electrode, wherein the second metal layer includes the second metal electrode, and wherein the pixel electrode is connected to the semiconductor layer;

an opening is formed in the position, corresponding to the storage capacitor, of the interlayer dielectric layer, and the orthographic projection of the opening on the substrate covers the orthographic projection of the first metal electrode and the orthographic projection of the second metal electrode on the substrate.

5. The display panel of claim 1, wherein the display circuit further comprises a first passivation layer disposed on the TFT layer, the storage capacitor and the signal trace, wherein the pixel electrode layer is disposed on the first passivation layer, the first passivation layer includes a third via, and the pixel electrode layer and the semiconductor layer are connected through the third via.

6. The display panel according to claim 5, wherein a second passivation layer and a black matrix layer are sequentially stacked at a position where the first passivation layer corresponds to the TFT layer, the second passivation layer and the black matrix layer are aligned, and a thickness of the second passivation layer is smaller than a thickness of the first passivation layer.

7. A manufacturing method of a display panel is characterized by comprising the following steps:

s10: a fan-out circuit forming step of providing a substrate base plate having a first side and a second side opposite to the first side, and forming the fan-out circuit on the second side of the substrate base plate;

s20: a display circuit forming step of forming a TFT layer, a storage capacitor, and a signal trace on the first side of the substrate, the TFT layer including a light-shielding layer, a source layer, a semiconductor layer, a gate insulating layer, and a gate layer, the light-shielding layer and the source layer being disposed on the same layer, the semiconductor layer being connected to the light-shielding layer and the source layer;

s30: a fan-out circuit connecting procedure, wherein one end of the fan-out wiring is electrically connected to the driving chip, and the other end of the fan-out wiring is electrically connected to the signal wiring; and

s40: the method comprises a light emitting part and a drive chip binding process, wherein the light emitting part is bound on one side of an array substrate, the light emitting part is electrically connected to the array substrate, the drive chip is bound on the other side of the array substrate, and the other end of a fan-out circuit is electrically connected with the drive chip.

8. The method according to claim 7, wherein the display circuit forming step includes a step of forming an interlayer dielectric layer between the first metal layer and the gate insulating layer.

9. The method according to claim 8, wherein the display circuit forming step includes a step of forming an opening in the interlayer dielectric layer at a position corresponding to the storage capacitor.

10. A tiled display panel comprising a plurality of display panels according to any of claims 1 to 6, wherein the plurality of display panels are tiled to form the tiled display panel.

Technical Field

The invention relates to the technical field of display, in particular to a display panel, a manufacturing method of the display panel and a spliced display panel.

Background

In the display field, a borderless or narrow-bezel display is becoming mainstream. For displays such as Liquid Crystal Displays (LCDs), organic light-emitting displays (OLEDs), and light-emitting diode (LED) displays, the larger the screen size is, the higher the manufacturing difficulty and the manufacturing cost per unit area are. Therefore, large displays are usually formed by splicing a plurality of small and medium-sized displays. The existence of the frame of the small and medium-sized display can cause the display area of the spliced display panel to have a strip-shaped splicing seam, and the display quality is reduced.

The mode of arranging the fan-out circuit on the back of the display panel to form a double-sided circuit structure is an idea of avoiding splicing seams, but the circuit structure of the display panel is complex and the manufacturing steps are complex.

In summary, it is desirable to provide a new display panel, a method for manufacturing the same, and a tiled display panel, so as to solve the above technical problems.

Disclosure of Invention

The display panel, the manufacturing method thereof and the spliced display panel solve the technical problems that a fan-out circuit is arranged on the back of the display panel of the existing display panel, and a formed double-sided circuit is complex in structure and complicated in manufacturing steps.

In order to solve the above problems, the technical scheme provided by the invention is as follows:

the embodiment of the invention provides a display panel, which comprises an array substrate, a light-emitting part and a driving chip, wherein the light-emitting part is electrically connected to one side of the array substrate, and the driving chip is electrically connected to the other side of the array substrate;

the array substrate includes:

a substrate base plate having a first side and a second side opposite the first side;

the display circuit is arranged on the first side of the substrate base plate and comprises a TFT layer, a storage capacitor and a signal wire, wherein the TFT layer comprises a light shielding layer, a source layer, a semiconductor layer, a grid electrode insulating layer and a grid electrode layer; and

the fan-out circuit is arranged on the second side of the substrate base plate, one end of the fan-out wiring is electrically connected to the driving chip, and the other end of the fan-out wiring is electrically connected to the signal wiring;

the light shielding layer and the source electrode layer are arranged on the same layer, the semiconductor layer is connected with the light shielding layer and the source electrode layer, and the pixel electrode layer is connected with the semiconductor layer.

According to the display panel provided by the embodiment of the invention, the array substrate includes a first metal layer and a second metal layer which are stacked, the first metal layer includes the light shielding layer and the source layer, the second metal layer includes the gate layer, the gate insulating layer is located between the first metal layer and the second metal layer, and the semiconductor layer is located between the first metal layer and the gate insulating layer.

According to the display panel provided by the embodiment of the invention, an interlayer dielectric layer is arranged between the first metal layer and the gate insulating layer, the interlayer dielectric layer comprises a first via hole and a second via hole, the semiconductor layer is positioned in the first via hole and the second via hole, the semiconductor layer is connected with the shading layer through the first via hole, and the semiconductor layer is connected with the gate layer through the second via hole.

According to the display panel provided by the embodiment of the invention, the storage capacitor comprises a first metal electrode, a second metal electrode and a pixel electrode which are arranged in an insulating manner, the first metal layer comprises the first metal electrode, the second metal layer comprises the second metal electrode, and the pixel electrode is connected with the semiconductor layer;

an opening is formed in the position, corresponding to the storage capacitor, of the interlayer dielectric layer, and the orthographic projection of the opening on the substrate covers the orthographic projection of the first metal electrode and the orthographic projection of the second metal electrode on the substrate.

According to the display panel provided by the embodiment of the invention, the display circuit further includes a first passivation layer disposed on the TFT layer, the storage capacitor and the signal trace, the pixel electrode layer is disposed on the first passivation layer, the first passivation layer includes a third via hole, and the pixel electrode layer is connected to the semiconductor layer through the third via hole.

According to the display panel provided by the embodiment of the invention, the first passivation layer and the position corresponding to the TFT layer are sequentially stacked with the second passivation layer and the black matrix layer, the second passivation layer and the black matrix layer are arranged in an aligned manner, and the thickness of the second passivation layer is smaller than that of the first passivation layer.

The embodiment of the invention provides a manufacturing method of a display panel, which comprises the following steps:

s10: a fan-out circuit forming step of providing a substrate base plate having a first side and a second side opposite to the first side, and forming the fan-out circuit on the second side of the substrate base plate;

s20: a display circuit forming step of forming a TFT layer, a storage capacitor, and a signal trace on the first side of the substrate, the TFT layer including a light-shielding layer, a source layer, a semiconductor layer, a gate insulating layer, and a gate layer, the light-shielding layer and the source layer being disposed on the same layer, the semiconductor layer being connected to the light-shielding layer and the source layer;

s30: a fan-out circuit connecting procedure, wherein one end of the fan-out wiring is electrically connected to the driving chip, and the other end of the fan-out wiring is electrically connected to the signal wiring; and

s40: the method comprises a light emitting part and a drive chip binding process, wherein the light emitting part is bound on one side of an array substrate, the light emitting part is electrically connected to the array substrate, the drive chip is bound on the other side of the array substrate, and the other end of a fan-out circuit is electrically connected with the drive chip.

According to the manufacturing method of the display panel provided by the embodiment of the invention, the display circuit forming process comprises the step of forming an interlayer dielectric layer between the first metal layer and the gate insulating layer.

According to the manufacturing method of the display panel provided by the embodiment of the invention, the display circuit forming process comprises the step of forming an opening at the position of the interlayer dielectric layer corresponding to the storage capacitor.

The embodiment of the invention provides a spliced display panel, which comprises a plurality of display panels, wherein the spliced display panel is formed by splicing the display panels.

The invention has the beneficial effects that: according to the display panel and the manufacturing method thereof and the spliced display panel provided by the embodiment of the invention, the display circuit of the display panel is arranged on the front side of the array substrate, and the fan-out circuit and the driving chip are arranged on the back side of the array substrate, so that a frameless or narrow frame effect can be obtained.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention;

fig. 2A to fig. 2C are schematic diagrams illustrating a flow structure of a fan-out circuit forming process of a display panel according to an embodiment of the present invention;

fig. 3A to fig. 3F are schematic structural flow diagrams illustrating a display circuit forming process of a display panel according to an embodiment of the invention;

fig. 4A to fig. 4C are schematic diagrams illustrating a flow structure of a fan-out circuit connection process of a display panel according to an embodiment of the present invention;

fig. 5A to 5B are schematic diagrams illustrating a flow structure of a bonding process between a light emitting portion and a driver chip of a display panel according to an embodiment of the present invention;

fig. 6 is a schematic plan view of a tiled display panel according to an embodiment of the present invention.

Detailed Description

The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.

In the display panel, the manufacturing method thereof and the spliced display panel in the prior art, the fan-out line is arranged on the back of the display panel, and the double-sided circuit structure is complex and the manufacturing steps are complicated. The present embodiment can solve this drawback.

As shown in fig. 1, the display panel 100 according to the embodiment of the invention includes an array substrate 10, a plurality of light emitting portions 20 and a driving chip 30, wherein the plurality of light emitting portions 20 are electrically connected to one side of the array substrate 10 in a matrix shape, and the driving chip 30 is electrically connected to the other side of the array substrate 10. Specifically, the light emitting part 20 is electrically connected to the display side of the array substrate 10, and the driving chip 30 is electrically connected to the non-display side of the array substrate 10, the display side and the non-display side being disposed opposite to each other.

The array substrate 10 includes a substrate 11, a display circuit 12, and a fan-out circuit 13, where the substrate 11 has a first side 11a and a second side 11b opposite to the first side 11a, the first side 11a is a side of the substrate 11 close to the display side, and the second side 11b is a side of the substrate 11 close to the non-display side. The display circuit 12 is disposed on a first side 11a of the substrate base 11, and the fan-out circuit 13 is disposed on a second side 11b of the substrate base 11. The display circuit 12 includes a Thin Film Transistor (TFT) 12a, a storage capacitor 12b, and a signal wiring 12 c. The TFT layer 12a includes a light-shielding layer 121, a source layer 121S, a semiconductor layer 122, and a gate layer 121G. One end of the fan-out circuit 13 is electrically connected to the driving chip 30, and the other end of the fan-out circuit 13 is electrically connected to the signal trace 12 c. The electrical connection between the fan-out circuit 13 and the signal trace 12c can be realized through a connection trace 14 disposed at a side edge of the array substrate 10. The signal traces 12c may include traces for transmitting signals, such as scan lines, data lines, common electrode lines, and power voltage lines, and in the embodiment of the present invention, the fan-out circuit 12c is electrically connected to the scan lines and the data lines, and is configured to transmit signals of the driving chip 30 to the display circuit 12, so as to implement image display.

In the present application, the light-shielding layer 121 and the source layer 121S are disposed on the same layer, and the semiconductor layer 122 is connected to the light-shielding layer 121 and the source layer 121S. It should be noted that the light-shielding layer 121 and the source layer 121S share a metal layer, both are prepared by a photolithography process, and the light-shielding layer 121 is made of an opaque metal material.

Specifically, the substrate base plate 11 may be a plastic base plate or a glass base plate. In the embodiment of the present invention, the substrate 11 may be a flexible substrate, such as a polyimide substrate.

The light-shielding layer 121 and the source layer 121S are disposed on the first side 11a of the substrate 11 and on the surface of the substrate 11, and the light-shielding layer 121 and the source layer 121S may be metal film layers having a light-shielding effect, such as a stack of molybdenum (Mo), silver (Ag), aluminum (Al), molybdenum-copper (MoCu), molybdenum (Mo) and aluminum (Al), a stack of copper and Indium Tin Oxide (ITO), a stack of nickel (Ni) and copper, a stack of copper (Cu) and molybdenum-titanium (MoTi), a stack of copper (Cu) and titanium (Ti), a stack of aluminum (Al) and molybdenum (Mo), and a copper-niobium (CuNb) alloy.

The semiconductor layer 122 is located on the light-shielding layer 121 and the source layer 121S, and the semiconductor layer 122 may be an oxide semiconductor or another type of semiconductor, such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Tin Oxide (IGTO), gallium indium oxide (IGO), Indium Zinc Oxide (IZO), and Aluminum Indium Zinc Oxide (AIZO).

The gate insulating layer 123 is disposed on the semiconductor layer 122, and the gate insulating layer 123 may be a stack of SiNx, SiOx, AlOx, SiNx, and SiOx, or a stack of SiOx and SiOx.

The gate electrode layer 121G is disposed on the gate insulating layer 123, and the gate electrode 121G may be made of molybdenum (Mo), copper niobium (CuNb) alloy, or the like, or may be made of, for example, a stack of copper (Cu) and molybdenum (Mo), a stack of copper (Cu) and nickel (Ni), a stack of molybdenum (Mo) -copper (Cu) -Indium Zinc Oxide (IZO), a stack of copper (Cu) and Indium Zinc Oxide (IZO), a stack of molybdenum (Mo) -copper (Cu) -Indium Tin Oxide (ITO), a stack of copper (Cu) and molybdenum titanium nickel (MoTiNi) alloy, a stack of copper (Cu) and nickel cadmium (NiCr) alloy, or the like.

The array substrate 10 includes a first metal layer 101 and a second metal layer 102 stacked and insulated from each other, the first metal layer 101 includes a light-shielding layer 121 and a source layer 121S, the second metal layer 102 includes a gate layer 121G, a gate insulating layer 123 is located between the first metal layer 101 and the second metal layer 102, and a semiconductor layer 122 is located between the first metal layer 101 and the gate insulating layer 123. In the embodiment of the invention, the TFT layer 12a adopts a top gate structure, the material of the first metal layer 101 is the same as the material of the light-shielding layer 121 and the source layer 121S, and the material of the second metal layer 102 is the same as the material of the gate layer 121G, which is not described herein again.

Further, an interlayer dielectric layer 124 is disposed between the first metal layer 101 and the gate insulating layer 123, the interlayer dielectric layer 124 includes a first via 1241 and a second via 1242, the semiconductor layer 122 is located in the first via 1241 and the second via 1242, the semiconductor layer 122 is connected to the light-shielding layer 121 through the first via 1241, and the semiconductor layer 122 is connected to the gate layer 121 through the second via 1242. Because the gate insulating layer 123 and the interlayer dielectric layer 124 are arranged between the first metal layer 101 and the second metal layer 102 at intervals, the thickness of the film layer is larger, and compared with the traditional structure, the structure has the advantage that one more interlayer dielectric layer 124 is arranged, so that the parasitic capacitance is favorably reduced, and the delay of a signal circuit is reduced.

In addition, the interlayer dielectric layer 124 and the gate insulating layer 123 are arranged between the signal traces 12c of the first metal layer 101 and the second metal layer 102 at intervals, so that the probability of short circuit between the two layers can be reduced, and the yield is improved.

The storage capacitor 12b includes a first metal electrode 125a, a second metal electrode 125b, and a pixel electrode layer 126, the first metal layer 101 includes the first metal electrode 125a, and the second metal layer includes the second metal electrode 125 b. The pixel electrode 126 is connected to the semiconductor layer 122. A gate insulating layer 123 is disposed between the first metal electrode 125a and the second metal electrode 125b, and a sub-storage capacitor is formed between the first metal electrode 125a and the second metal electrode 125 b. The pixel electrode layer 126 is connected to one of the drain electrode 121D and the source electrode 121S through the semiconductor layer 122. The display circuit 12 further includes a first passivation layer 127 disposed on the TFT layer 12a, the storage capacitor 12b and the signal trace 12c, the pixel electrode layer 126 is disposed on the first passivation layer 127, so that a sub-storage capacitor is formed between the pixel electrode layer 126 and the second metal electrode 125b, the first passivation layer 127 includes a third via 1271, and the pixel electrode layer 126 and the semiconductor layer 122 are connected through the third via 1271, so that the pixel electrode layer 126 is electrically connected to the light-shielding layer 121.

It can be understood that the storage capacitor 12b is a stacked structure formed by the pixel electrode layer 126, the first passivation layer 127, the second metal electrode 125b, the gate insulating layer 123 and the first metal electrode 125a, and the two sub-storage capacitors are in a parallel structure, that is, the storage capacitor 12b in this application forms two parallel capacitor structures by stacking three metal layers, and the total capacitance of the two sub-storage capacitors is the sum of the capacitances of the two sub-storage capacitors, and such an arrangement increases the capacitance of the storage capacitor 12 b. Therefore, under the condition that the total amount of the storage capacitors required by the single pixel unit is not changed, the area of the storage capacitor 12b can be reduced through the structure, and the area occupation ratio of the single pixel unit in the array substrate 10 is further reduced. Accordingly, in the case of obtaining a smaller area ratio of the pixel unit, the number of the pixel units that the array substrate 10 can accommodate is increased, so that the pixel density (PPI) of the array substrate 10 can be increased.

Further, an opening 1243 is disposed at a position of the interlayer dielectric layer 124 corresponding to the storage capacitor 12b, and an orthographic projection of the opening 1243 on the substrate 11 covers an orthographic projection of the first metal electrode 12a and the second metal electrode 12b on the substrate 11. That is, the interlayer dielectric layer 124 is removed between the first metal electrode 12a and the second metal electrode 12b, and the thickness of the interlayer dielectric layer 124 is 400nm or more, which is thicker than the thickness of the gate insulating layer 123 and the first passivation layer 127. The thickness of the gate insulating layer 123 is 50nm to 300nm, and preferably, the thickness of the gate insulating layer 123 is 140 nm. The thickness of the first passivation layer 127 is 200nm to 400 nm. The capacitance of the sub-storage capacitor formed between the first metal electrode 12a and the second metal electrode 12b and the capacitance of the sub-storage capacitor formed between the pixel electrode layer 126 and the first metal electrode 12a can be further increased as compared to the conventional structure.

A second passivation layer 128 and a black matrix layer 129 are sequentially stacked at a position of the first passivation layer 127 corresponding to the TFT layer 12a, and the second passivation layer 128 and the black matrix layer 129 are aligned. The stack of the second passivation layer 128 and the black matrix layer 129 may serve to shield the top of the TFT layer 12a from light and external water and oxygen. The thickness of the second passivation layer 128 is less than that of the first passivation layer 127, and preferably, the thickness of the first passivation layer 127 is 200nm to 400nm, and the thickness of the second passivation layer 128 is 30nm to 400 nm. Materials of the first passivation layer 127 and the second passivation layer 128 may be SiOx, SiNx, SiNOx, or the like.

Specifically, the fan-out circuit 13 includes a metal circuit layer 131, a transparent circuit layer 133, and a circuit insulating film 132 between the metal circuit layer 131 and the transparent circuit layer 133, which are laminated. The material of the metal circuit layer 131 may be a stack of Mo (molybdenum) and Cu (copper), a stack of molybdenum-titanium alloy (MoTi) and Cu (copper). The transparent circuit layer 133 is made of ITO or IZO.

Specifically, the display panel 100 is a Micro light emitting diode (Micro LED) type display panel 100. The light emitting section 20 is a micro light emitting diode light emitting body, and includes a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 are connected to the pixel electrode layer 126 and the common electrode layer, respectively. According to the structure of the micro light emitting diode, the micro light emitting diode can be divided into a vertical micro light emitting diode and a horizontal micro light emitting diode, a first electrode 21 and a second electrode 22 of the vertical micro light emitting diode are respectively positioned at the upper side and the lower side of the micro light emitting diode, and the first electrode 21 and the second electrode 22 of the horizontal micro light emitting diode are both positioned at the lower side of the micro light emitting diode. In this embodiment, the micro light emitting diode has a horizontal structure.

Specifically, the driving chip 30 may be in the form of a chip on film, i.e. the driving chip 30 is disposed on the film and connected to the fan-out circuit 13.

As shown in fig. 2A to 2C, fig. 3A to 3F, fig. 4A to 4C, and fig. 5A to 5B, a method for manufacturing a display panel 100 according to an embodiment of the present invention includes the following steps:

s10: a fan-out circuit 13 forming step of providing a substrate base plate 11, the substrate base plate 11 having a first side 11a and a second side 11b opposite to the first side 11a, and forming the fan-out circuit 13 on the second side 11b of the substrate base plate 11.

S20: and a display circuit 12 forming step of forming a TFT layer 12a, a storage capacitor 12b, and signal traces 12c on the first side 11a of the base substrate 11, wherein the TFT layer 12a includes a light-shielding layer 121, a source layer 121S, a semiconductor layer 122, and a gate layer 121G, the light-shielding layer 121 and the source layer 121S are formed in the same layer, and the semiconductor layer 122 is connected to the light-shielding layer 121 and the source layer 121S.

S30: and a fan-out circuit connecting process, wherein one end of the fan-out circuit 13 is electrically connected to the driving chip 30, and the other end is electrically connected to the signal wiring 12 c.

S40: and a light emitting part 20 and a driving chip 30 binding process, wherein the light emitting part 20 is bound on one side of the array substrate 10, the light emitting part 20 is electrically connected to the array substrate 10, the driving chip 30 is bound on the other side of the array substrate 10, and the other end of the fan-out circuit 13 is electrically connected with the driving chip 30.

Specifically, as shown in fig. 2A to 2C, the fan-out circuit 13 forming process includes the steps of:

s101: providing a substrate 11, and depositing and patterning a metal circuit layer 131 on the second side 11b of the substrate 11;

s102: depositing and patterning a circuit insulating film 132 on the metal circuit layer 131;

s103: depositing a hard protective layer 15 on the circuit insulating film; and

s104: the substrate base 11 is inverted.

The circuit insulating film 132 may be formed using silicon nitride, silicon oxide, or the like; the hard protective layer 15 covers the metal circuit layer 131 to protect the metal circuit layer 131, and the material of the hard protective layer 15 may be silicon nitride, silicon oxide, or the like. After the hard protective layer 15 is deposited on the metal circuit layer 131, the substrate 11 is inverted with the first side of the substrate 11 facing upward to facilitate the subsequent preparation of the display circuit 12.

Specifically, as shown in fig. 3A to 3F, the display circuit 12 forming process includes a step of forming an interlayer dielectric layer 124 between the first metal layer 101 and the gate insulating layer 123, and the display circuit 12 forming process specifically includes the following steps:

s201: depositing and patterning a first metal layer 101 on the first side 11a of the substrate 11, wherein the first metal layer 101 includes a light-shielding layer 121, a source layer 121S, a first metal electrode 125a, and a signal trace 12 c;

s202: depositing an interlayer dielectric layer 124 on the first metal layer 101, and patterning to form a first via 1241 corresponding to the light-shielding layer 121, a second via 1242 corresponding to the source layer 121S, and an opening 1243 corresponding to the storage capacitor 12 b;

s203: depositing and patterning a semiconductor layer 122 on the interlayer dielectric layer 124;

s204: depositing and patterning a gate insulating layer 123 on the interlayer dielectric layer 124 and the semiconductor layer 122;

s205: depositing and patterning a second metal layer 125a on the gate insulating layer 123;

s206: forming a first passivation layer 127 on the second metal layer 125a, and forming a third via 1271 penetrating the first passivation layer 127;

s207: sequentially depositing and patterning a pixel electrode layer 126, a common electrode layer and a second passivation layer 128 on the first passivation layer 127; and

s208: a black matrix layer 129 is deposited and patterned on the second passivation layer 128.

In step S208, the second passivation layer 128 may be subjected to a self-aligned patterning process using the black matrix layer 129 as a Hard Mask (Hard Mask), so that the second passivation layer 128 and the black matrix layer 129 are aligned.

Specifically, as shown in fig. 4A to 4C, the fan-out circuit 13 connection process includes the steps of:

s301: coating and forming a first soft protection layer 161 on the display circuit 12;

s302: the hard protective layer 15 is removed, and a second soft protective layer 162 is formed on the fan-out circuit 13 by coating:

s303: forming a connecting trace 14 on a side portion of the array substrate 10, wherein one end of the fan-out circuit 13 is electrically connected to the driving chip 30, and the other end of the fan-out circuit 13 is electrically connected to the signal trace 12 c; and

s304: the first and second soft protective layers 161 and 162 are removed.

Specifically, as shown in fig. 5A to 5B, the light emitting part 20 and the driving chip 30 binding process includes the steps of:

s401: forming a transparent circuit layer 133 on the metal circuit layer 131, and binding the driving chip 30 on the metal circuit layer 131 through the transparent circuit layer 133; and

s402: the first electrode 21 of the light emitting section 20 is electrically connected to the pixel electrode layer 126, and the second electrode 22 of the light emitting section 20 is electrically connected to the common electrode layer.

Therefore, the display panel 100 in the embodiment of the present invention is obtained, and the manufacturing method of the display panel 100 in the embodiment of the present invention can simplify the circuit structure of the display panel 100 by disposing the light shielding layer 121 and the source layer 121S on the same layer of the TFT layer 12a of the display panel 100.

As shown in fig. 6, an embodiment of the present invention further provides a tiled display panel 100, where the tiled display panel 100 includes a plurality of display panels 100 closely arranged in a matrix. The tiled display panel 100 can reduce the tiled seams to the size of one pixel unit by using the display panel 100 without a frame or with a narrow frame in the above embodiment, so that the user is difficult to visually perceive the existence of the tiled seams, and the effect of eliminating or reducing the tiled seams is achieved. In addition, the structure of the tiled display panel 100 can be simplified, the manufacturing process can be saved, and the yield can be improved.

The beneficial effects are that: according to the display panel and the manufacturing method thereof and the spliced display panel provided by the embodiment of the invention, the display circuit of the display panel is arranged on the front side of the array substrate, and the fan-out circuit and the driving chip are arranged on the back side of the array substrate, so that a frameless or narrow frame effect can be obtained.

In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.