阅读说明：本技术 显示基板及其制备方法 (Display substrate and preparation method thereof ) 是由 卢马才 于 2020-12-11 设计创作，主要内容包括：本发明公开一种显示基板及其制备方法。显示基板包括一衬底基板；驱动电路层,形成于衬底基板的底面,其包含多个电路单元,其中至少一个电路单元由低温多晶硅薄膜晶体管组成；显示阵列层,形成于衬底基板的顶面,包含多个阵列分布的像素单元,每一像素单元包含至少一氧化物薄膜晶体管；侧面导线,形成于衬底基板的侧壁；电路单元通过侧面导线电连接显示阵列层。本发明可以实现无边框显示。(The invention discloses a display substrate and a preparation method thereof. The display substrate comprises a substrate; the driving circuit layer is formed on the bottom surface of the substrate and comprises a plurality of circuit units, wherein at least one circuit unit consists of a low-temperature polycrystalline silicon thin film transistor; the display array layer is formed on the top surface of the substrate and comprises a plurality of pixel units distributed in an array mode, and each pixel unit comprises at least one oxide thin film transistor; a side surface wire formed on a side wall of the substrate base plate; the circuit unit is electrically connected with the display array layer through the side conducting wire. The invention can realize frameless display.)

1. A display substrate, comprising:

a substrate base plate, which is provided with a top surface and a bottom surface which are opposite and a side wall connecting the top surface and the bottom surface;

the driving circuit layer is formed on the bottom surface of the substrate base plate and comprises a plurality of circuit units, wherein at least one circuit unit consists of a low-temperature polycrystalline silicon thin film transistor;

the display array layer is formed on the top surface of the substrate and comprises a plurality of pixel units distributed in an array mode, and each pixel unit comprises at least one oxide thin film transistor; and

the side surface conducting wire is formed on the side wall of the substrate base plate;

and the circuit units of the driving circuit layer are electrically connected with the display array layer through the side conducting wires.

2. The display substrate of claim 1, wherein the circuit units comprise a gate driver circuit, a demultiplexer circuit and a fan-out circuit, all formed on a bottom surface of the substrate.

3. The display substrate of claim 1, wherein each pixel unit further comprises a light emitting device disposed on the top surface of the substrate and connected to the oxide thin film transistor;

the display substrate further includes:

the driving chip is connected to at least one binding pad of the driving circuit layer; and

and the printed circuit board is connected to the driving chip.

4. The display substrate according to claim 3, wherein the driving chip is disposed on the flexible circuit board by a chip-on-film method, and is connected to the at least one bonding pad of the driving circuit layer through the flexible circuit board; the printed circuit board is connected to the flexible circuit board; or

The driving chip is directly bound to at least one binding pad of the driving circuit layer in a chip-on-glass mode and is connected to the flexible circuit board; the printed circuit board is connected to the flexible wiring board.

5. The display substrate of claim 3, wherein the light emitting device is a micro light emitting diode or an organic light emitting diode.

6. A preparation method of a display substrate is characterized by comprising the following steps:

step A, providing a substrate base plate, wherein the substrate base plate is provided with a top surface, a bottom surface and a side wall which is connected with the top surface and the bottom surface;

step B, preparing a driving circuit layer on the bottom surface of the substrate, wherein the driving circuit layer comprises a plurality of circuit units, and at least one circuit unit consists of a low-temperature polycrystalline silicon thin film transistor;

step C, preparing a display array layer on the top surface of the substrate base plate, wherein the display array layer comprises a plurality of pixel units distributed in an array mode, and each pixel unit comprises at least one oxide thin film transistor;

and D, preparing a side lead on the side wall of the substrate base plate, so that the circuit unit of the driving circuit layer is electrically connected with the display array layer through the side lead.

7. The method of claim 6, wherein in step B, the circuit units including gate driving circuits, demultiplexer circuits and fan-out circuits are formed on a bottom surface of the substrate.

8. The manufacturing method according to claim 6, wherein in the step C, each pixel unit further comprises a light emitting device disposed on the top surface of the substrate base plate and connected to the oxide thin film transistor;

the display substrate further comprises the following steps:

step E, connecting a driving chip to at least one binding pad of the driving circuit layer; and

and F, connecting the printed circuit board to the driving chip.

9. The manufacturing method according to claim 8, wherein in the step E, the driving chip is disposed on the flexible circuit board by a chip-on-film method, and is connected to the at least one bonding pad of the driving circuit layer through the flexible circuit board; the printed circuit board is connected to the flexible circuit board; or

The driving chip is directly bound to at least one binding pad of the driving circuit layer in a chip-on-glass mode and is connected to the flexible circuit board; the printed circuit board is connected to the flexible wiring board.

10. The method according to claim 8, wherein the light-emitting device is a micro light-emitting diode or an organic light-emitting diode.

Technical Field

The invention relates to the technical field of display, in particular to a display substrate and a preparation method thereof.

Background

In the display field, such as LCD, OLED, LED screens, the larger the single screen is, the higher the manufacturing cost is, so that a common oversized screen is usually formed by splicing several small screens together, so as to reduce the cost per unit area. Since a general screen has a frame, the display area of the tiled screen has a plurality of non-display dark areas, which reduces the display quality. In addition, for mobile display devices, such as mobile phones or watches, having a higher screen duty ratio is also one of the pursuit targets for high quality display screens. Therefore, the size of the splicing seam of the spliced screen is reduced, the frameless display is realized, and the spliced screen becomes a popular research object in the industry.

Disclosure of Invention

In order to solve the problems of reducing the size of a splicing seam of a spliced screen and realizing frameless display, the embodiment of the invention provides a display substrate and a preparation method thereof.

In a first aspect, an embodiment of the present invention provides a display substrate, which includes:

a substrate base plate, which is provided with a top surface and a bottom surface which are opposite and a side wall connecting the top surface and the bottom surface;

the driving circuit layer is formed on the bottom surface of the substrate base plate and comprises a plurality of circuit units, wherein at least one circuit unit consists of a low-temperature polycrystalline silicon thin film transistor;

the display array layer is formed on the top surface of the substrate and comprises a plurality of pixel units distributed in an array mode, and each pixel unit comprises at least one oxide thin film transistor; and

the side surface conducting wire is formed on the side wall of the substrate base plate;

and the circuit units of the driving circuit layer are electrically connected with the display array layer through the side conducting wires.

Furthermore, the circuit unit comprises a gate driving circuit, a demultiplexer circuit and a fan-out circuit which are all formed on the bottom surface of the substrate base plate.

Furthermore, each pixel unit also comprises a light-emitting device which is arranged on the top surface of the substrate base plate and is connected with the oxide thin film transistor; and

the display substrate further includes:

the driving chip is connected to at least one binding pad of the driving circuit layer; and

and the printed circuit board is connected to the driving chip.

Furthermore, the driving chip is arranged on the flexible circuit board in a chip-on-film mode and is connected to the at least one binding pad of the driving circuit layer through the flexible circuit board; the printed circuit board is connected to the flexible circuit board; or

The driving chip is directly bound to at least one binding pad of the driving circuit layer in a chip-on-glass mode and is connected to the flexible circuit board; the printed circuit board is connected to the flexible wiring board.

Further, the light emitting device is a micro light emitting diode or an organic light emitting diode.

Further, the low temperature polysilicon thin film transistor includes:

a light-shielding layer formed on a bottom surface of the base substrate;

a first buffer insulating layer covering the light-shielding layer and the bottom surface of the substrate;

a first semiconductor layer formed on the first buffer insulating layer;

a first gate insulating layer covering the first semiconductor layer and the first buffer insulating layer;

the first metal film layer is formed on the first grid electrode insulating layer and at least forms a first grid electrode;

a first dielectric layer covering the first metal film layer and the first gate insulating layer;

the second metal film layer is formed on the first dielectric layer and at least forms a first source electrode, a first drain electrode, a first binding pad and a second source electrode; and

a first passivation layer covering the second metal film layer and the first dielectric layer;

wherein: one end of the first source electrode is connected with the shading layer, and the other end of the first source electrode is connected with the first semiconductor layer; the first drain electrode is connected with the first semiconductor layer; the second source electrode is arranged at the edge of the substrate base plate, is close to one side of the side face conducting wire and is connected with the side face conducting wire.

Further, the oxide thin film transistor includes:

a second buffer insulating layer covering the top surface of the substrate base plate;

a second semiconductor layer formed over the second buffer insulating layer;

a gate insulating film layer formed on the second semiconductor layer and the second buffer insulating layer, and at least a second gate insulating layer formed on the second semiconductor layer;

a third metal film layer formed on the gate insulating film layer and at least formed with a third gate electrode positioned on the second gate insulating layer;

a second dielectric layer covering the second buffer insulating layer, the second semiconductor layer, the gate insulating film layer and the third metal film layer;

a fourth metal film layer formed on the second dielectric layer and at least formed with a third source, a second drain, a second bonding pad or a common cathode, and a fourth source;

a second passivation layer covering the fourth metal film layer and the second dielectric layer;

wherein: the drain electrode is connected with the second semiconductor layer; the third source electrode is connected with the second semiconductor layer; the fourth source electrode is arranged at the edge of the substrate base plate, is close to one side of the side face conducting wire and is connected with the side face conducting wire.

In a second aspect, the present invention further provides a method for manufacturing a display substrate, which includes the following steps:

step A, providing a substrate base plate, wherein the substrate base plate is provided with a top surface, a bottom surface and a side wall which is connected with the top surface and the bottom surface;

step B, preparing a driving circuit layer on the bottom surface of the substrate, wherein the driving circuit layer comprises a plurality of circuit units, and at least one circuit unit consists of a low-temperature polycrystalline silicon thin film transistor;

step C, preparing a display array layer on the top surface of the substrate base plate, wherein the display array layer comprises a plurality of pixel units distributed in an array mode, and each pixel unit comprises at least one oxide thin film transistor;

and D, preparing a side lead on the side wall of the substrate base plate, so that the circuit unit of the driving circuit layer is electrically connected with the display array layer through the side lead.

Further, in the step B, the circuit unit includes a gate driving circuit, a demultiplexer circuit and a fan-out circuit, all formed on the bottom surface of the substrate.

Further, in the step C, each pixel unit further includes a light emitting device disposed on the top surface of the substrate and connected to the oxide thin film transistor;

the display substrate further comprises the following steps:

step E, connecting a driving chip to at least one binding pad of the driving circuit layer; and

and F, connecting the printed circuit board to the driving chip.

Furthermore, in the step E, the driving chip is disposed on the flexible circuit board in a chip-on-film manner, and is connected to the at least one bonding pad of the driving circuit layer through the flexible circuit board; the printed circuit board is connected to the flexible circuit board; or

The driving chip is directly bound to at least one binding pad of the driving circuit layer in a chip-on-glass mode and is connected to the flexible circuit board; the printed circuit board is connected to the flexible wiring board.

Further, the light emitting device is a micro light emitting diode or an organic light emitting diode.

Further, the preparation method of the low-temperature polycrystalline silicon thin film transistor comprises the following steps:

a1, forming a light shielding layer on the bottom surface of the substrate;

a2, forming a first buffer insulating layer to cover the light-shielding layer and the substrate;

a3, forming a first semiconductor layer on the first buffer insulating layer;

a4, forming a first gate insulating layer on the first semiconductor layer and the first buffer insulating layer;

a5, forming a first metal film layer on the first gate insulating layer, and forming at least a first gate on the first metal film layer; doping the first semiconductor layer;

a6, forming a first dielectric layer covering the first metal film layer and the first gate insulating layer;

a7, forming a second metal film layer on the first dielectric layer, and forming at least a first source electrode, a first drain electrode, a first bonding pad and a second source electrode on the second metal film layer; wherein: connecting one end of the first source electrode with the shading layer, and connecting the other end of the first source electrode with the first semiconductor layer; connecting the first drain electrode with the first semiconductor layer; enabling the second source electrode to be arranged at the edge of the substrate base plate and close to one side of the side face conducting wire, and enabling the second source electrode to be connected with the side face conducting wire; and

a8, forming a first passivation layer covering the second metal film layer and the first dielectric layer.

Further, the preparation method of the oxide thin film transistor comprises the following steps:

b1, forming a second buffer insulating layer to cover the top surface of the substrate base plate;

b2, forming a second semiconductor layer on the second buffer insulating layer;

b3, forming a gate insulating film layer on the second semiconductor layer and the second buffer insulating layer, and at least forming a second gate insulating layer on the second semiconductor layer;

b4, forming a third metal film layer on the gate insulation film layer, and at least forming a third gate on the second gate insulation layer;

b5, forming a second dielectric layer covering the second buffer insulating layer, the second semiconductor layer, the gate insulating film and the third metal film;

b6, forming a fourth metal film layer on the second dielectric layer, and forming at least a third source, a second drain, a second bonding pad or a common cathode, and a fourth source on the fourth metal film layer; wherein: connecting the drain to the second semiconductor layer; connecting the third source to the second semiconductor layer; enabling the fourth source electrode to be arranged at the edge of the substrate base plate and close to one side of the side face conducting wire, and enabling the fourth source electrode to be connected with the side face conducting wire; and

b7, forming a second passivation layer covering the fourth metal film layer and the second dielectric layer.

The invention has the beneficial effects that:

the display array layer is formed on the top surface of the substrate base plate, the drive circuit layer is formed on the bottom surface of the substrate base plate, and the gate drive circuit, the demultiplexer circuit, the fan-out circuit and other circuit units are connected through the side lead. In addition, the driving circuit layer adopts a low-temperature polycrystalline silicon thin film transistor, the display array layer adopts an oxide thin film transistor, and the low leakage current of the oxide thin film transistor and the high current passing capacity of the low-temperature polycrystalline silicon thin film transistor can be utilized to reduce the power consumption of display.

Drawings

The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.

FIG. 1 is a diagram illustrating step B1 in step B according to one embodiment of the present invention.

FIG. 2 is a schematic diagram of steps B2-B3 in step B.

FIG. 3 is a schematic diagram of steps B4-B5 in step B.

FIG. 4 is a diagram illustrating step B6 in step B according to the present invention.

FIG. 5 is a diagram illustrating step B7 in step B according to the present invention.

FIG. 6 is a schematic diagram of steps B8-B9 in step B.

FIG. 7 is a diagram illustrating step B10 in step B according to the present invention.

Fig. 8 is a schematic view of turning over the substrate base plate in accordance with an embodiment of the present invention.

FIG. 9 is a schematic diagram of steps C1-C2 in step C.

FIG. 10 is a schematic diagram of steps C3-C4 in step C.

FIG. 11 is a diagram of step C5 in step C.

FIG. 12 is a schematic diagram of steps C6-C7 in step C.

FIG. 13 is a diagram illustrating steps b 8-b 9 in step C according to an embodiment of the present invention.

FIG. 14 is a diagram of step C10 in step C.

FIG. 15 is a diagram illustrating the implementation of step D in accordance with one embodiment of the present invention.

Fig. 16 is a schematic diagram of the implementation of step b11, and steps E to F according to the embodiment of the present invention.

Fig. 17 is a schematic diagram of performing step b11, and steps E to F according to another embodiment of the present invention.

Fig. 18 is a schematic diagram of performing step b11, and steps E to F according to another embodiment of the present invention.

Fig. 19 is a schematic diagram of performing step b11, and steps E to F according to another embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Specifically, referring to fig. 1 to 19, an embodiment of the invention provides a display substrate, which includes: a substrate 100, a driving circuit layer, a display array layer and side wires 400.

As shown in fig. 1 to 19, the substrate base plate 100 has a top surface and a bottom surface opposite to each other and a sidewall joining the top surface and the bottom surface, wherein a surface represents the top surface of the substrate base plate 100, and B surface represents the bottom surface of the substrate base plate 100. The substrate 100 may be a glass substrate.

The driving circuit layer is formed on the bottom surface of the substrate 100 and includes a plurality of circuit units, wherein at least one circuit unit is composed of a low temperature polysilicon thin film transistor 200. The circuit units may include a gate driver circuit (GOA), a demultiplexer circuit (Demux) and a fan-out circuit (fan-out), all formed on the bottom surface of the substrate 100. In an embodiment, the circuit units of the gate driving circuit and the demultiplexer circuit, etc. that implement their functions through thin film transistors may be composed of the low temperature polysilicon thin film transistor 200.

As shown in fig. 1 to 6 and 16 to 19, the low temperature polysilicon thin film transistor 200 is formed on the bottom surface of the substrate 100. The low temperature polysilicon thin film transistor 200 includes a light-shielding layer 201, a first buffer insulating layer 202, a first semiconductor layer 203, a first gate insulating layer 204, a first metal film layer 205, a first dielectric layer 206, a second metal film layer 207 and a first passivation layer 208.

As shown in fig. 1 and 16 to 19, the light-shielding layer 201 is formed on the bottom surface of the base substrate 100. The material of the light-shielding layer 201 may be Mo, a Mo/Al/Mo laminate, a Mo/Cu/IZO laminate, an IZO/Cu/IZO laminate, a Mo/Cu/ITO laminate, a Ni/Cu/Ni laminate, a MoTiNi/Cu/MoTiNi laminate, a NiCr/Cu/NiCr laminate, or CuNb.

As shown in fig. 2 and 16 to 19, the first buffer insulating layer 202 covers the light-shielding layer 201 and the bottom surface of the base substrate 100. The material of the first buffer insulating layer 202 may be SiOx, SiNx, a SiNx/SiOx stack, SiNOx, or the like.

As shown in fig. 2 and 16 to 19, the first semiconductor layer 203 is formed on the first buffer insulating layer 202. The first semiconductor layer 203 is made of polysilicon, and the polysilicon can be obtained by amorphous silicon laser annealing crystallization or other crystallization methods. The first semiconductor layer 203 is subjected to doping treatment, wherein a region connected with a source (such as a first source 2071) and a region connected with a drain (such as a first drain 2072) are predefined on the first semiconductor layer 203, and the doping treatment is to dope phosphorus ions on the region, correspondingly connected with the source and the drain, of the first semiconductor layer 203 to form N-type heavy doping so as to finally form an nMOS transistor; or doping boron ions to form P-type heavy doping to form a pMOS transistor.

As shown in fig. 3 and 16 to 19, the first gate insulating layer 204 covers the first semiconductor layer 203 and the first buffer insulating layer 202. The material of the first gate insulating layer 204 may be SiOx, SiNx, or Al₂O₃a/SiNx/SiOx stack, a SiOx/SiNx/SiOx stack, or the like.

As shown in fig. 3 and 16 to 19, the first metal film layer 205 is formed on the first gate insulating layer 204, and at least a first gate 2051 is formed thereon. In an embodiment, the first metal film 205 is formed with only the first gate electrode 2051 (see fig. 17 and 19). In another embodiment, in addition to forming the first gate 2051, the first metal film layer 205 further forms a second gate 2052 (see fig. 3, 16 and 18), the second gate 2052 is used for connecting with the side wire 400, and the second gate 2052 is formed at the edge (including the vicinity of the edge) of the substrate base plate 100 and is disposed at a side close to the side wire 400. The material of the first metal film layer 205 may be Mo, a Mo/Al stack, a Mo/Cu/IZO stack, an IZO/Cu/IZO stack, a Mo/Cu/ITO stack, a Ni/Cu/Ni stack, a MoTiNi/Cu/MoTiNi stack, a NiCr/Cu/NiCr stack, or CuNb.

As shown in fig. 4 and 16 to 19, the first dielectric layer 206 covers the first metal film layer 205 and the first gate insulating layer 204. Specifically, when the first metal film layer 205 is formed with only the first gate electrode 2051, the first dielectric layer 206 covers the first gate electrode 2051 and the first gate insulating layer 204 (see fig. 17 and 19); when the first metal film layer 205 is further formed with a second gate electrode 2052, the first dielectric layer 206 also covers the second gate electrode 2052 (see fig. 4, 16, and 18). The material of the first dielectric layer 206 may be SiOx, SiNx, SiNOx, or SiOx/SiNx stack. The first dielectric layer 206 is further subjected to hydrogenation and activation, and the present invention does not specifically limit the hydrogenation and activation method, and may adopt the conventional method.

As shown in fig. 5, 16 to 19, the second metal film layer 207 is formed on the first dielectric layer 206, and at least a first source 2071, a first drain 2072, a first bonding pad 2073 and a second source 2074 are formed. The material of the second metal film layer 207 may be: mo, Mo/Al stack, Mo/Cu/IZO stack, IZO/Cu/IZO stack, Mo/Cu/ITO stack, Ni/Cu/Ni stack, MoTiNi/Cu/MoTiNi stack, NiCr/Cu/NiCr stack, CuNb, or the like.

As shown in fig. 5, 16 to 19, the first drain 2072 is connected to the first semiconductor layer 203. The method can be realized by the following steps: as shown in fig. 4, a first via 2061 is formed through the first dielectric layer 206 and the first gate insulating layer 204 and to the first semiconductor layer 203, and the first drain 2072 is connected to the first semiconductor layer 203 through the first via 2061.

As shown in fig. 5, 16 to 19, one end of the first source 2071 is connected to the light-shielding layer 201, and the other end is connected to the first semiconductor layer 203. The method can be realized by the following steps: as shown in fig. 4, a third through hole 2063 is formed through the first dielectric layer 206, the first gate insulating layer 204 and the first buffer insulating layer 202 and leads to the light-shielding layer 201; one end of the first source 2071 is connected to the light-shielding layer 201 through the third through hole 2063. Forming a second via 2062 through the first dielectric layer 206 and the first gate insulating layer 204 and leading to the first semiconductor layer 203; the other end of the first source 2071 is connected to the first semiconductor layer 203 through the second via 2062.

As shown in fig. 5, 16 to 19, the second source 2074 is disposed at the edge (including the edge vicinity) of the substrate base plate 100 and near one side of the side wire 400 for connecting with the side wire 400.

As shown in fig. 5, 16 to 19, the first bonding pad 2073 is used for connection with other elements.

As shown in fig. 6 and 16 to 19, the first passivation layer 208 covers the second metal film layer 207 and the first dielectric layer 206. Specifically, it covers the first dielectric layer 206, the first source 2071, the first drain 2072, the first bond pad 2073 and the second source 2074. The material of the first passivation layer 208 may be SiNx or SiOx.

As shown in fig. 6 and 16 to 19, the low temperature polysilicon thin film transistor 200 further includes a first protection film 209. The first protection film layer 209 is formed on the first passivation layer 208, and at least a first protection layer 2091 and/or a second protection layer 2092 are formed thereon. The material of the protective film layer can be Indium Tin Oxide (ITO) for oxidation resistance. The first protective layer 2091 is connected to the first bonding pad 2073; the second protective layer 2092 is connected to the second source 2074. The connection may be achieved by patterning holes in the first passivation layer 208.

The display array layer is formed on the top surface of the substrate 100 and includes a plurality of pixel units distributed in an array, and each pixel unit includes at least one oxide thin film transistor 300. The oxide thin film transistor 300 may be, for example, an Indium Gallium Zinc Oxide (IGZO) thin film transistor.

As shown in fig. 9 to 19, the oxide thin film transistor 300 is formed on the top surface of the substrate base plate 100. The oxide thin film transistor 300 includes a second buffer insulating layer 301, a second semiconductor layer 302, a gate insulating film 303, a third metal film 304, a second dielectric layer 305, a fourth metal film 306 and a second passivation layer 307.

As shown in fig. 9, 16 to 19, the second buffer insulating layer 301 covers the top surface of the substrate base plate 100. The material of the second buffer insulating layer 301 may be SiOx, SiNx, a SiNx/SiOx stack, SiNOx, or the like.

As shown in fig. 9, 16 to 19, the second semiconductor layer 302 is formed over the second buffer insulating layer 301. The material of the second semiconductor layer 302 may be an oxide semiconductor, such as IGZO, IGTO, IGZO, IGO, IZO, AIZO, ATZO, or the like.

As shown in fig. 10 and 16 to 19, the gate insulating film 303 is formed on the second semiconductor layer 302 and the second buffer insulating layer 301, and at least a second gate insulating layer 3031 is formed on the second semiconductor layer 302. For example: in an embodiment, only the second gate insulating layer 3031 is formed on the gate insulating film layer 303, and the second gate insulating layer 3031 is located on the second semiconductor layer 302. In another embodiment, the gate insulating film layer 303 further forms a third gate insulating layer 3032 in addition to the second gate insulating layer 3031, and the third gate insulating layer 3032 is located on the second buffer insulating layer 301 and is disposed at the edge (including the vicinity of the edge) of the substrate 100 and on the side close to the side wire 400. The gate insulating film 303 may be made of SiOx, SiNx, or Al₂O₃a/SiNx/SiOx stack, a SiOx/SiNx/SiOx stack, or the like.

As shown in fig. 10 and 16 to 19, the third metal film 304 is formed on the gate insulating film 303, and at least a third gate 3041 is formed on the second gate insulating layer 3031. In an embodiment, the third metal film 304 is formed with only a third gate 3041 (see fig. 17 and 19), and the third gate 3041 is located on the second gate insulating layer 3031. In another embodiment, the third metal film 304 further forms a fourth gate 3042 (see fig. 10, 16 and 18) in addition to the third gate 3041, and the fourth gate 3042 is located on the third gate insulating layer 3032. The material of the third metal film layer 304 may be Mo, Mo/Al stack, Mo/Cu/IZO stack, IZO/Cu/IZO stack, Mo/Cu/ITO stack, Ni/Cu/Ni stack, MoTiNi/Cu/MoTiNi stack, NiCr/Cu/NiCr stack, or CuNb, etc.

As shown in fig. 11 and 16 to 19, the second dielectric layer 305 covers the second buffer insulating layer 301, the second semiconductor layer 302, the gate insulating film 303 and the third metal film 304. Specifically, the second dielectric layer 305 covers the second buffer insulating layer 301, the second semiconductor layer 302, the second gate insulating layer 3031, and the third gate electrode 3041 (see fig. 17 and 19); or the second dielectric layer 305 covers the second buffer insulating layer 301, the second semiconductor layer 302, the second gate insulating layer 3031, the third gate insulating layer 3032, the third gate electrode 3041 and the fourth gate electrode 3042 (see fig. 4, 16 and 18). The material of the second dielectric layer 305 may be SiOx, SiNx, SiNOx, or the like.

As shown in fig. 12 and 16 to 19, the fourth metal film layer 306 is formed on the second dielectric layer 305, and at least a second drain 3061, a third source 3062, a second bonding pad 3063 or a common cathode 3065, and a fourth source 3064 are formed. The material of the fourth metal film layer 306 may be Mo, Mo/Al stack, Mo/Cu/IZO stack, IZO/Cu/IZO stack, Mo/Cu/ITO stack, Ni/Cu/Ni stack, MoTiNi/Cu/MoTiNi stack, NiCr/Cu/NiCr stack, CuNb, etc.

As shown in fig. 12, 16 to 19, the drain electrode is connected to the second semiconductor layer 302; the third source 3062 is connected to the second semiconductor layer 302. The method can be realized by the following steps: as shown in fig. 11, a fourth via 3051 and a fifth via 3052 are formed in the second dielectric layer 305; the fourth through hole 3051 and the fifth through hole 3052 are both opened to the second semiconductor layer 302, the drain electrode is connected to the second semiconductor layer 302 through the fourth through hole 3051, and the third source 3062 is connected to the second semiconductor layer 302 through the fifth through hole 3052.

As shown in fig. 12 and 16 to 19, the fourth source 3064 is disposed at the edge of the substrate base 100 (including near the edge) and near one side of the side conductive line 400 for connecting with the side conductive line 400. The second binding pad 3063 or the common cathode 3065 is used for connection with other elements.

As shown in fig. 12 and 16 to 19, the second passivation layer 307 covers the fourth metal film layer 306 and the second dielectric layer 305. Specifically, the second dielectric layer 305, the third source 3062, the second drain 3061, the second binding pad 3063 or common cathode 3065, and the fourth source 3064 are covered. The material of the second passivation layer 307 may beIs SiOx, SiOx/SiNx stack or Al₂O₃a/SiOx stack, etc.

As shown in fig. 13 and 16 to 19, the oxide thin film transistor 300 further includes a pixel electrode layer 308. The pixel electrode layer 308 is formed on the second passivation layer 307, and a first pixel electrode 3081 and a second pixel electrode 3082 are formed. The first pixel electrode 3081 is connected to the second binding pad 3063. The second pixel electrode 3082 is connected to the third source 3062. Likewise, the connection may be achieved by patterning holes formed in the second passivation layer 307. The pixel electrode layer 308 may be made of IZO, ITO, AZO, or the like.

As shown in fig. 13 and 16 to 19, the oxide thin film transistor 300 further includes a third protective layer 309; the third protective layer 309 is formed over the second passivation layer 307 and is connected to the fourth source 3064. Specifically, it is formed above or near the fourth source 3064, i.e., at the edge of the substrate base 100 (including near the edge), and near one side of the side wire 400. The material of the third protective layer 309 may be indium tin oxide for oxidation resistance.

As shown in fig. 16 to 19, each of the pixel units of the display array layer further includes a light emitting device disposed on the top surface of the substrate 100 and connected to the oxide thin film transistor 300. As shown in fig. 16 and 17, the light emitting device may be a micro light emitting diode 500 or an organic light emitting diode 600. Specifically, the micro light emitting diode 500 is connected to the first pixel electrode 3081 and the second pixel electrode 3082, respectively. The micro light emitting diode 500 may be connected to the first pixel electrode 3081 and the second pixel electrode 3082 through a binding adhesive material 501 (e.g., InAg, etc.). Alternatively, as shown in fig. 18 and 19, the organic light emitting diode 600 is connected to the third source 3062 and the common cathode 3065. The light emitting device (such as the micro light emitting diode 500 or the organic diode 600) may be of an existing structure, and the present invention is not particularly limited.

As shown in fig. 15 to 19, the side conductive lines 400 are formed on the sidewalls of the substrate base plate 100, and the circuit units of the driving circuit layer are electrically connected to the display array layer through the side conductive lines 400. Specifically, the side wire 400 is formed on the surface of the substrate 100 where the sidewall is located, and one end of the side wire extends to the surface of the low temperature polysilicon thin film transistor 200 to be connected to the low temperature polysilicon thin film transistor 200, and the other end of the side wire extends to the surface of the oxide thin film transistor 300 to be connected to the oxide thin film transistor 300. The side wires 400 may be formed by a metallization method, such as printing metal traces or other metallization methods, which is simple and robust, and has high reliability, high precision, and high manufacturing efficiency. The material of the side wire 400 may be low melting point metal, such as In, Ag, Ga, Sn, or their alloys with each other.

As shown in fig. 15 to 19, the side wires 400 may be connected to the source or gate of the low temperature polysilicon thin film transistor 200 and the source or gate of the oxide thin film transistor 300. The method specifically comprises the following steps: the side wire 400 is connected with the gate of the low temperature polysilicon thin film transistor 200 and the gate of the oxide thin film transistor 300; the side wire 400 is connected to the source of the low temperature polysilicon thin film transistor 200 and the source of the oxide thin film transistor 300; one end of the side wire 400 is connected to the gate of the low temperature polysilicon thin film transistor 200, and the other end thereof is connected to the source of the oxide thin film transistor 300; alternatively, one end of the side wire 400 is connected to the source of the low temperature polysilicon tft 200, and the other end thereof is connected to the gate of the oxide tft 300. For example, as shown in fig. 17 and 19, one end of the side wire 400 is connected to the fourth source 3064, and the other end is connected to the second source 2074, and the second protective layer 2092 provided between the side wire 400 and the second source 2074 and the third protective layer 309 provided between the side wire 400 and the fourth source 3064 are provided to protect the connection from oxidation, and the actual purpose is to finally connect the side wire 400 to the source of the low temperature polysilicon thin film transistor 200 and the source of the oxide thin film transistor 300. As shown in fig. 16 and 18, the fourth source 3064 is further connected to the fourth gate 3042, and the second source 2074 is further connected to the second gate 2052, which is the actual purpose of the side wire 400 to be finally connected to the gate of the low temperature polysilicon thin film transistor 200 and the gate of the oxide thin film transistor 300.

As shown in fig. 16 to 19, the display substrate further includes a driving chip 800 and a printed circuit board 900.

As shown in fig. 16 to 19, the driver chip 800 is connected to at least one bonding pad of the driver circuit layer; the printed circuit board 900 is connected to the driving chip 800. Specifically, as shown in fig. 16 to 19, the driving Chip 800 may be disposed on the flexible circuit board 700 by a Chip On Film (COF) method, and then connected to at least one bonding pad (e.g., the first bonding pad 2073) of the driving circuit layer through the flexible circuit board 700; the printed circuit board 900 is connected to the flexible wiring board 700. The driver Chip 800 may also be directly bonded to at least one bonding pad (e.g., the first bonding pad 2073) of the driver circuit layer by a Chip On Glass (COG) method, and connected (e.g., connected by an anisotropic conductive film) to the flexible circuit board 700; the printed circuit board 900 is connected to the flexible wiring board 700.

Referring to fig. 1 to 19, an embodiment of the invention further provides a method for manufacturing the display substrate, which includes the following steps:

step a, as shown in fig. 1, providing a substrate base plate 100, where the substrate base plate 100 has a top surface and a bottom surface opposite to each other and a sidewall connecting the top surface and the bottom surface; in the drawing, a plane a indicates the top surface of the substrate base 100, and a plane B indicates the bottom surface of the substrate base 100. The substrate 100 may be a glass substrate.

And step B, preparing a driving circuit layer on the bottom surface of the substrate, wherein the driving circuit layer comprises a plurality of circuit units, and at least one circuit unit is composed of low-temperature polycrystalline silicon thin film transistors. The circuit units include a gate driver circuit (GOA), a demultiplexer circuit (Demux) and a fan-out circuit (fan-out), all formed on the bottom surface of the substrate base 100.

As shown in fig. 1 to 7, the method for manufacturing the low temperature polysilicon thin film transistor 200 includes the following steps:

b1, as shown in fig. 1, a light-shielding layer 201 is formed on the bottom surface of the base substrate 100. Specifically, a metal film layer is plated on the bottom surface of the substrate 100, and the light-shielding layer 201 is obtained by patterning. The material of the light-shielding layer 201 may be Mo, a Mo/Al/Mo laminate, a Mo/Cu/IZO laminate, an IZO/Cu/IZO laminate, a Mo/Cu/ITO laminate, a Ni/Cu/Ni laminate, a MoTiNi/Cu/MoTiNi laminate, a NiCr/Cu/NiCr laminate, or CuNb.

b2, as shown in fig. 2, a first buffer insulating layer 202 is formed so as to cover the light-shielding layer 201 and the base substrate 100. Specifically, a buffer insulating film layer is plated on the bottom surfaces of the light-shielding layer 201 and the substrate 100 to form a first buffer insulating layer 202. The material of the first buffer insulating layer 202 may be SiOx, SiNx, a SiNx/SiOx stack, SiNOx, or the like.

b3, as shown in fig. 2, a first semiconductor layer 203 is formed on the first buffer insulating layer 202. Specifically, a semiconductor film is plated on the first buffer insulating layer 202, and then patterned to obtain a first semiconductor layer 203. The semiconductor material is polysilicon, and the polysilicon can be obtained by amorphous silicon laser annealing crystallization or other crystallization methods.

b4, as shown in fig. 3, a first gate insulating layer 204 is formed over the first semiconductor layer 203 and the first buffer insulating layer 202. Specifically, an insulating film is plated on the first semiconductor layer 203 and the first buffer insulating layer 202 to form a first gate insulating layer 204. The material of the first gate insulating layer 204 may be SiOx, SiNx, or Al₂O₃a/SiNx/SiOx stack, a SiOx/SiNx/SiOx stack, or the like.

b5, as shown in fig. 3, a first metal film 205 is formed on the first gate insulating layer 204, and at least a first gate 2051 is formed on the first metal film 205, and the first semiconductor layer 203 is doped. Specifically, a metal film is plated on the first gate insulating layer 204 to form a first metal film 205, and patterning is performed to obtain a first gate 2051 (see fig. 17 and 19) or a first gate 2051 and a second gate 2052 (see fig. 3, 16, and 18). The second gate 2052 is used for connecting with the side wire 400, wherein the second gate 2052 is formed at the edge (including the vicinity of the edge) of the substrate base plate 100 and is disposed at a side close to the side wire 400. The doping treatment is to dope the first semiconductor with phosphorus ions to form N-type heavy doping so as to finally form an nMOS transistor; or doping boron ions to form P-type heavy doping to finally form the pMOS transistor. The doped region is a region of the first semiconductor correspondingly connected to the first source and drain electrodes 2071 and 2072, and the doping may be a multiple doping process and/or a multiple patterning doping process. The material of the first metal film layer 205 may be Mo, a Mo/Al stack, a Mo/Cu/IZO stack, an IZO/Cu/IZO stack, a Mo/Cu/ITO stack, a Ni/Cu/Ni stack, a MoTiNi/Cu/MoTiNi stack, a NiCr/Cu/NiCr stack, or CuNb.

b6, as shown in fig. 4, forming a first dielectric layer 206 covering the first metal film layer 205 and the first gate insulating layer 204; and the first dielectric layer 206 is hydrogenated and activated. Specifically, a dielectric film is plated on the first metal film 205 and the first gate insulating layer 204, and then hydrogenated and activated, and patterned to obtain the first dielectric layer 206. A first via 2061, a second via 2062, and a third via 2063 may be formed through a patterning process, wherein the first via 2061 penetrates through the first dielectric layer 206 and the first gate insulating layer 204 and leads to the first semiconductor layer 203; the second via 2062 extends through the first dielectric layer 206 and the first gate insulating layer 204 and opens to the first semiconductor layer 203; the third via 2063 penetrates the first dielectric layer 206, the first gate insulating layer 204, and the first buffer insulating layer 202 and is open to the light-shielding layer 201. The material of the first dielectric layer 206 may be SiOx, SiNx, SiNOx, or SiOx/SiNx stack. The hydrogenation and activation treatment method can be realized by adopting the conventional method.

b7, as shown in fig. 5, a second metal film 207 is formed on the first dielectric layer 206, and the second metal film 207 is formed with at least a first source 2071, a first drain 2072, a first bond pad 2073 and a second source 2074. One end of the first source 2071 is connected to the light-shielding layer 201, and the other end is connected to the first semiconductor layer 203; connecting the first drain 2072 with the first semiconductor layer 203; the second source 2074 is disposed at the edge of the substrate base plate 100 (including near the edge) and near one side of the side wire 400 for connecting with the side wire 400. Specifically, a metal film layer is plated on the first dielectric layer 206 to form a second metal film layer 207, and patterning is performed to obtain a first source 2071, a first drain 2072, a first bonding pad 2073 and a second source 2074; and the first drain electrode 2072 is connected to the first semiconductor layer 203 through the first via 2061; one end of the first source 2071 is connected to the light-shielding layer 201 through the third through hole 2063, and the other end is connected to the first semiconductor layer 203 through the second through hole 2062. The first bonding pad 2073 is used for connection with other elements. The material of the second metal film layer 207 may be: mo, Mo/Al stack, Mo/Cu/IZO stack, IZO/Cu/IZO stack, Mo/Cu/ITO stack, Ni/Cu/Ni stack, MoTiNi/Cu/MoTiNi stack, NiCr/Cu/NiCr stack, CuNb, or the like.

b8, as shown in fig. 6, a first passivation layer 208 is formed to cover the second metal film layer 207 and the first dielectric layer 206. Specifically, a passivation layer is plated on the second metal film layer 207 and the first dielectric layer 206 to form a first passivation layer 208, and the first passivation layer 208 covers the first dielectric layer 206, the first source 2071, the first drain 2072, the first bonding pad 2073 and the second source 2074. The material of the first passivation layer 208 may be SiNx or SiOx.

B9, as shown in fig. 6, the step B may further include forming a first protection film layer 209 on the first passivation layer 208, and forming at least a first protection layer 2091 and/or a second protection layer 2092. Specifically, a protective film is coated on the first passivation layer 208, and patterned to obtain the first protective layer 2091 and/or the second protective layer 2092. The first protective layer 2091 is connected to the first bonding pad 2073. The second protective layer 2092 is connected to the second source 2074. The connection may be achieved by patterning holes in the first passivation layer 208. The material of the first protective film layer 209 may be Indium Tin Oxide (ITO) for oxidation resistance.

B10, as shown in fig. 7, in the step B, a bottom protection film 1000 may be further disposed on the first passivation layer 208 and the first protection film 209 to protect the ltps tft 200 from damage and the like in subsequent processes. The material of the bottom protective film layer 1000 may be SiNx, SiOx, or the like.

As shown in fig. 8, after the low temperature polysilicon thin film transistor 200 is manufactured, the substrate 100 is turned over to manufacture the display array layer on the top surface of the substrate 100.

As shown in fig. 16 to 19, each of the pixel units of the display array layer further includes a light emitting device disposed on the top surface of the substrate 100 and connected to the oxide thin film transistor 300. The step B further includes B11, preparing a light emitting device (such as a micro light emitting diode 500 or an organic light emitting diode 600) on the top surface of the substrate 100, and connecting the light emitting device to the oxide thin film transistor 300. For example, as shown in fig. 16 and 17, a micro light emitting diode 500 may be prepared on the top surface of the substrate base plate 100 to be connected to the first pixel electrode 3081 and the second pixel electrode 3082. The micro light emitting diode 500 may be connected to the first pixel electrode 3081 and the second pixel electrode 3082 through a binding adhesive material 501 (e.g., InAg, etc.). As shown in fig. 18 and 19, an organic light emitting diode 600 may be further prepared on the top surface of the substrate base plate 100 to be connected to the third source 3062 and the common cathode 3065. The method for manufacturing the light emitting device (such as the micro light emitting diode 500 or the organic light emitting diode 600) may be the conventional method, and the present invention is not particularly limited.

Step C, preparing a display array layer on the top surface of the substrate 100, where the display array layer includes a plurality of pixel units distributed in an array, and each pixel unit includes at least one oxide thin film transistor 300.

As shown in fig. 9 to 13, the oxide thin film transistor 300 may be an Indium Gallium Zinc Oxide (IGZO) thin film transistor. The method for manufacturing the oxide thin film transistor 300 includes the following steps:

c1, as shown in fig. 9, a second buffer insulating layer 301 is formed so as to cover the top surface of the base substrate 100. Specifically, a buffer insulating film layer is plated on the top surface of the substrate 100 to form a second buffer insulating layer 301. The material of the second buffer insulating layer 301 may be SiOx, SiNx, a SiNx/SiOx stack, SiNOx, or the like.

c2, as shown in fig. 9, a second semiconductor layer 302 is formed over the second buffer insulating layer 301. Specifically, a semiconductor film is plated on the second buffer insulating layer 301, and patterned to obtain a second semiconductor layer 302. The material of the second semiconductor layer 302 may be an oxide semiconductor, such as IGZO, IGTO, IGZO, IGO, IZO, AIZO, ATZO, or the like.

c3, as shown in fig. 10, a gate insulating film 303 is formed on the second semiconductor layer 302 and the second buffer insulating layer 301, and at least a second gate insulating layer 3031 located on the second semiconductor layer 302 is formed. Specifically, an insulating film is plated on the second semiconductor layer 302 and the second buffer insulating layer 301, the gate insulating film 303 is formed, and the gate insulating film is patterned to obtain a second gate insulating layer 3031 (see fig. 17 and 19) or obtain a second gate insulating layer 3031 and a third gate insulating layer 3032 (see fig. 10). The gate insulating film 303 may be made of SiOx, SiNx, or Al₂O₃a/SiNx/SiOx stack, a SiOx/SiNx/SiOx stack, or the like.

c4, as shown in fig. 10, a third metal film 304 is formed on the gate insulating film 303, and at least a third gate 3041 is formed on the second gate insulating layer 3031. Specifically, a metal film is plated on the gate insulating film 303 to form a third metal film 304, and the third metal film is patterned to obtain a third gate 3041 (see fig. 17 and 19) or a third gate 3041 and a fourth gate 3042 (see fig. 10). The material of the third metal film layer 304 may be Mo, Mo/Al stack, Mo/Cu/IZO stack, IZO/Cu/IZO stack, Mo/Cu/ITO stack, Ni/Cu/Ni stack, MoTiNi/Cu/MoTiNi stack, NiCr/Cu/NiCr stack, or CuNb, etc.

c5, as shown in fig. 11, a second dielectric layer 305 is formed to cover the second buffer insulating layer 301, the second semiconductor layer 302, the gate insulating film 303 and the third metal film 304. Specifically, a dielectric film layer is plated to form a second dielectric layer 305, and a fourth via 3051 and a fifth via 3052 are patterned on the second dielectric layer 305, so that the fourth via 3051 and the fifth via 3052 are both open to the second semiconductor layer 302. The material of the second dielectric layer 305 may be SiOx, SiNx, SiNOx, or the like.

c6, as shown in FIG. 12, a fourth metal film layer 306 is formed over the second dielectric layer 305, and the fourth metal film layer 306 is formed with at least a third source 3062, a second drain 3061, a second bond pad 3063 or a common cathode 3065, and a fourth source 3064; wherein the drain electrode is connected to the second semiconductor layer 302; connecting the third source 3062 to the second semiconductor layer 302; the fourth source 3064 is disposed at the edge of the substrate base 100 (including near the edge) near one side of the side wire 400 and the fourth source 3064 is connected to the side wire 400. Specifically, a metal film is plated on the second dielectric layer 305 to obtain a fourth metal film 306, which is patterned to obtain a third source 3062, a second drain 3061, a second bonding pad 3063 or a common cathode 3065, and a fourth source 3064; connecting the drain electrode to the second semiconductor layer 302 through the fourth via 3051; connecting the third source 3062 to the second semiconductor layer 302 through the fifth via 3052; the fourth source 3064 is used for connecting with the side wire 400; the second binding pad 3063 or the common cathode 3065 is used for connection with other elements. The material of the fourth metal film layer 306 may be Mo, Mo/Al stack, Mo/Cu/IZO stack, IZO/Cu/IZO stack, Mo/Cu/ITO stack, Ni/Cu/Ni stack, MoTiNi/Cu/MoTiNi stack, NiCr/Cu/NiCr stack, CuNb, etc.

c7, as shown in fig. 12, a second passivation layer 307 is formed to cover the fourth metal film layer 306 and the second dielectric layer 305. Specifically, a passivation layer is plated on the fourth metal layer 306 and the second dielectric layer 305 to form a second passivation layer 307, which may be patterned as required, such as forming a hole. The material of the second passivation layer 307 may be SiOx, SiOx/SiNx stack, or Al₂O₃a/SiOx stack, etc.

c8, as shown in fig. 13, the step B further includes forming a pixel electrode layer 308 on the second passivation layer 307, and forming a first pixel electrode 3081 and a second pixel electrode 3082. The first pixel electrode 3081 is connected with the second binding pad 3063; the second pixel electrode 3082 is connected to the third source 3062. Specifically, a pixel electrode film layer is plated on the second passivation layer 307 to obtain a pixel electrode layer 308, and the first pixel electrode 3081 and the second pixel electrode 3082 are obtained through patterning, where the first pixel electrode 3081 is connected to the second bonding pad 3063, and the second pixel electrode 3082 is connected to the third source 3062. The connection may be achieved by patterning holes. The pixel electrode layer 308 may be made of IZO, ITO, AZO, or the like.

c9, as shown in fig. 13, the step B further includes forming a third protection layer 309 over the second passivation layer 307, the third protection layer 309 being formed over the second passivation layer 307 and connecting the third protection layer 309 with the fourth source electrode 3064. Specifically, the third protective layer 309 is formed at the edge (including the vicinity of the edge) of the substrate base plate 100, near one side of the side conductive line 400. The material of the third protective layer 309 may be indium tin oxide for oxidation resistance.

c10, as shown in FIG. 14, the bottom surface protective film 1000 on the bottom of the substrate 100 is removed.

Step D, as shown in fig. 15, preparing a side conductive line 400 on the sidewall of the substrate 100, so that the circuit unit of the driving circuit layer is electrically connected to the display array layer through the side conductive line 400. Specifically, a lateral conductive line 400 is formed on a side wall of the substrate 100 by a metallization method (e.g., a printed metal trace or other metallization method), and one end of the lateral conductive line 400 extends to the surface of the low temperature polysilicon thin film transistor 200 to be connected to the low temperature polysilicon thin film transistor 200, and the other end thereof extends to the surface of the oxide thin film transistor 300 to be connected to the oxide thin film transistor 300. The material of the side wire 400 may be low melting point metal, such as In, Ag, Ga, Sn, or their alloys with each other. The method for manufacturing the side wire 400 is simple, and the manufactured side wire 400 is firm, high in reliability, high in precision and high in manufacturing efficiency. As shown in fig. 15, the side wires 400 may be further covered with a side wire protective film 1100 during the processing of the display substrate to prevent damage during the processing.

As shown in fig. 15, the side wires 400 may be connected to the source or gate of the low temperature polysilicon thin film transistor 200 and the source or gate of the oxide thin film transistor 300. For example, as shown in fig. 17 and 19, one end of the side wire 400 is connected to the fourth source 3064, and the other end is connected to the second source 2074, and the second protective layer 2092 provided between the side wire 400 and the second source 2074 and the third protective layer 309 provided between the side wire 400 and the fourth source 3064 are provided to protect the connection from oxidation, and the actual purpose is to finally connect the side wire 400 to the source of the low temperature polysilicon thin film transistor 200 and the source of the oxide thin film transistor 300. As shown in fig. 16 and 18, the fourth source 3064 is further connected to the fourth gate 3042, and the second source 2074 is further connected to the second gate 2052, so that the final purpose is to finally connect the side wire 400 to the gate of the low temperature polysilicon thin film transistor 200 and the gate of the oxide thin film transistor 300.

As shown in fig. 16 to 19, the method for manufacturing a display substrate further includes a step E of connecting a driving chip 800 to at least one bonding pad of the driving circuit layer. And step F, connecting the printed circuit board 900 to the driving chip 800. As shown in fig. 16 to 19, the driving Chip 800 may be disposed on the flexible circuit board 700 by a Chip On Film (COF) method, and then connected to at least one bonding pad (e.g., a first bonding pad 2073) of the driving circuit layer through the flexible circuit board 700; the printed circuit board 900 is connected to the flexible wiring board 700. Specifically, the driving chip 800 is connected to the first bonding pad 2073 of the low temperature polysilicon thin film transistor 200 of the driving circuit layer through the flexible wiring board 700. The driver Chip 800 may also be directly bonded to at least one bonding pad (e.g., the first bonding pad 2073) of the driver circuit layer by a Chip On Glass (COG) method, and connected (e.g., connected by an anisotropic conductive film) to the flexible circuit board 700; the printed circuit board 900 is connected to the flexible wiring board 700.

In the present embodiment, the display array layer is formed on the top surface of the substrate base plate 100, the driving circuit layer is formed on the bottom surface of the substrate base plate 100, and then the driving circuit layer is connected through the side surface wires 400, because the circuit units such as the gate driving circuit, the demultiplexer circuit, and the fan-out circuit are all formed on the bottom surface of the substrate base plate 100, the display area provided by the display array layer on the top surface of the substrate base plate 100 can be maximally extended to the edge of the substrate base plate 100, so the scheme provided by the present embodiment is beneficial to manufacturing the high-resolution frameless display base plate. In addition, the low-temperature polysilicon thin film transistor 200 is adopted in the driving circuit layer, the oxide thin film transistor 300 is adopted in the display array layer, and the low leakage current of the oxide thin film transistor 300 and the high current passing capability of the low-temperature polysilicon thin film transistor 200 can be utilized to reduce the power consumption of the display. In the manufacturing process, the low temperature polysilicon thin film transistor 200 is firstly prepared on the bottom surface of the substrate base plate 100 for forming the driving circuit, and then the oxide thin film transistor 300 is prepared on the top surface of the substrate base plate 100 for displaying, so that the failure caused by the thermal influence of the thin film transistor on the top surface of the substrate base plate 100 when the oxide thin film transistor 300 is used for manufacturing the driving circuit on the bottom surface of the substrate base plate 100 can be avoided.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.