阅读说明：本技术 阵列基板及其制作方法、显示面板 (Array substrate, manufacturing method thereof and display panel ) 是由 张启沛 李世泽 于 2020-12-14 设计创作，主要内容包括：本申请公开了一种阵列基板及其制作方法、显示面板,所述阵列基板在所述非显示区包括层间介电层、第一平坦层、第一金属走线、第二金属走线和第三金属走线,其中所述第一金属走线和所述第二金属走线设置于所述衬底基板和所述层间介电层之间并位于不同的绝缘层上,所述第三金属走线设置于所述第一平坦层上；本申请所述阵列基板及其制作方法、显示面板能避免由于第三金属走线表面凹凸不平导致的显示区边缘显示异色的不良问题。(The application discloses an array substrate, a manufacturing method thereof and a display panel, wherein the array substrate comprises an interlayer dielectric layer, a first flat layer, a first metal wire, a second metal wire and a third metal wire in a non-display area, wherein the first metal wire and the second metal wire are arranged between a substrate and the interlayer dielectric layer and positioned on different insulating layers, and the third metal wire is arranged on the first flat layer; the array substrate, the manufacturing method of the array substrate and the display panel can avoid the problem that the edge of the display area displays different colors due to the fact that the surface of the third metal wiring is uneven.)

1. An array substrate, comprising a substrate, wherein the substrate is divided into a display area and a non-display area, and the array substrate comprises:

a multilayer insulating layer including an interlayer dielectric layer and a first flat layer sequentially stacked on the substrate base; and the number of the first and second groups,

the plurality of metal wires comprise a first metal wire, a second metal wire and a third metal wire, wherein the first metal wire and the second metal wire are arranged between the substrate and the interlayer dielectric layer and positioned on different insulating layers, and the third metal wire is arranged on the first flat layer.

2. The array substrate of claim 1, wherein the second metal traces and the first metal traces are alternately distributed in a plane parallel to the substrate.

3. The array substrate of claim 2, wherein the second metal trace and the first metal trace are spaced apart in a plane parallel to the substrate.

4. The array substrate according to claim 2, wherein the array substrate further has at least a first via hole in the non-display area, the first via hole extending from the first planarization layer to the second metal trace or the first metal trace in a direction toward the substrate and exposing the second metal trace or the first metal trace;

the third metal routing is electrically connected to the second metal routing or the first metal routing through the first via hole.

5. The array substrate of claim 1, wherein the array substrate further comprises a second planarization layer disposed on the third metal trace and covering the third metal trace and the first planarization layer;

the thickness of the first flat layer is smaller than that of the second flat layer.

6. The array substrate of claim 1, wherein the first planarization layer is a photoresist layer.

7. The array substrate of claim 1, wherein the display substrate is provided with at least one thin film transistor in the display region, the thin film transistor comprising a first gate, a second gate, a source and a drain, wherein:

the source electrode and the drain electrode are arranged on the first flat layer;

the second grid and the second metal routing are arranged on the same layer of the insulating layer, and the interlayer dielectric layer covers the second grid;

the first gate and the first metal wire are arranged on the same layer of the insulating layer.

8. The array substrate of claim 7, wherein the multi-layer insulating layer further comprises a first gate insulating layer and a second gate insulating layer, wherein:

the first grid electrode insulating layer covers the substrate base plate, and the first grid electrode and the first metal routing are arranged on the first grid electrode insulating layer;

the second gate insulating layer covers the first gate, the first metal trace and the first gate insulating layer, and the second gate and the second metal trace are disposed on the second gate insulating layer.

9. A manufacturing method of an array substrate is characterized by comprising the following steps:

providing a substrate, wherein the substrate is provided with a display area and a non-display area;

sequentially preparing a first grid electrode insulating layer, a first metal wire, a second grid electrode insulating layer, a second metal wire and an interlayer dielectric layer in a non-display area of the substrate base plate;

a step of preparing a first planarization layer on the interlayer dielectric layer; and the number of the first and second groups,

and preparing a third metal wire on the first flat layer.

10. The method for fabricating the array substrate according to claim 9, wherein the array substrate is provided with a via hole penetrating at least the first planarization layer and the interlayer dielectric layer, the method further comprising:

and patterning the array substrate by using the first flat layer as a light resistance layer to obtain the via hole.

11. A display panel comprising the array substrate according to any one of claims 1 to 8.

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.

Background

The full-face screen is one of the targets of the development of the OLED display technology. And the narrow frame technology can obviously improve the display screen ratio and improve the use experience of users. However, in the narrow bezel technology, the structure and the shape of the film layer around the display area are complicated by compressing the screen bezel.

Fig. 1 is a cross-sectional view of a non-display region of the array substrate of fig. 1. As shown in fig. 1, the array substrate 100 includes, in the non-display region, a substrate base plate 110, a multi-layer insulating layer disposed on the substrate base plate 110, and a plurality of metal traces (131, 132, 133) disposed on the multi-layer insulating layer, where the plurality of metal traces include a first gate layer trace 131, a second gate layer trace 132, and a source drain layer trace 133 that are respectively on the same layer as a first gate, a second gate, and a source drain of the thin film transistor.

As shown in fig. 1, the first gate layer trace 131 and the second gate layer trace 132 are densely distributed, so that the source/drain layer trace 133 has an uneven surface, and incident light generates a grating reflection phenomenon on the surface of the source/drain layer trace 133, which causes the polarizer to not effectively block reflected light, so that the non-display region is close to the edge of the display region to generate a white line, and other defects of displaying different colors are generated. In particular, in a light leakage region not covered with the Cover (Cover Window) ink, a display failure of a different color such as a white line is more likely to occur.

Therefore, it is desirable to provide an array substrate, a method for manufacturing the same, and a display panel to solve the above problems.

Disclosure of Invention

In order to solve the above technical problem, the present application provides an array substrate, a manufacturing method thereof, and a display panel, in which the array substrate is configured to flatten a surface of a third metal trace by additionally providing a first flattening layer on an interlayer dielectric layer, so that a problem that the third metal trace displays different colors at an edge of a display area due to unevenness of the surface can be avoided.

In order to achieve the above purpose, the array substrate, the manufacturing method thereof and the display panel adopt the following technical scheme.

The application provides an array substrate, including a substrate base plate, the substrate base plate is divided into display area and non-display area, the array substrate is in the non-display area includes: a multilayer insulating layer including an interlayer dielectric layer and a first flat layer sequentially stacked on the substrate base; and the metal wires comprise a first metal wire, a second metal wire and a third metal wire, wherein the first metal wire and the second metal wire are arranged between the substrate and the interlayer dielectric layer and positioned on different insulating layers, and the third metal wire is arranged on the first flat layer.

Further, the second metal wirings and the first metal wirings are alternately distributed on a plane parallel to the substrate base plate.

Further, on a plane parallel to the substrate base plate, the second metal routing and the first metal routing which are adjacent to each other are arranged at intervals on the plane parallel to the substrate base plate.

Further, the array substrate is further provided with at least one first via hole in the non-display area, and the first via hole extends from the first flat layer to the second metal routing or the first metal routing in the direction towards the substrate base plate and exposes the second metal routing or the first metal routing; the third metal routing is electrically connected to the second metal routing or the first metal routing through the first via hole.

Further, the array substrate further comprises a second flat layer, wherein the second flat layer is arranged on the third metal routing line and covers the third metal routing line and the first flat layer; the thickness of the first flat layer is smaller than that of the second flat layer.

Further, the display substrate is provided with at least one thin film transistor in the display area, the thin film transistor comprises a first grid, a second grid, a source electrode and a drain electrode, wherein: the source electrode and the drain electrode are arranged on the first flat layer; the second grid and the second metal routing are arranged on the same layer of the insulating layer, and the interlayer dielectric layer covers the second grid; the first gate and the first metal wire are arranged on the same layer of the insulating layer.

Further, the multi-layered insulating layer further includes a first gate insulating layer and a second gate insulating layer, wherein: the first grid electrode insulating layer covers the substrate base plate, and the first grid electrode and the first metal routing are arranged on the first grid electrode insulating layer; the second gate insulating layer covers the first gate, the first metal wire and the first gate insulating layer, and the second gate and the second metal wire are arranged on the second gate insulating layer; and the source electrode and the drain electrode are in contact with the active layer of the thin film transistor through a second via hole which sequentially penetrates through the first flat layer, the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

The application also provides a manufacturing method of the array substrate, which comprises the following steps:

providing a substrate, wherein the substrate is provided with a display area and a non-display area; sequentially preparing a first grid electrode insulating layer, a first metal wire, a second grid electrode insulating layer, a second metal wire and an interlayer dielectric layer in a non-display area of the substrate base plate; a step of preparing a first planarization layer on the interlayer dielectric layer; and preparing a third metal wire on the first flat layer.

Further, the array substrate is provided with a via hole penetrating at least the first flat layer and the interlayer dielectric layer, and the manufacturing method further includes: and patterning the array substrate by using the first flat layer as a light resistance layer to obtain the via hole.

In a preferred implementation, the via includes at least one of a first via or a second via, wherein: the second via hole is used for contacting or electrically connecting the source electrode and the drain electrode with the active layer, and the first via hole is used for contacting or electrically connecting the third metal routing with the first metal routing or the second metal routing.

The application provides a display panel, display panel includes any one the array substrate.

The array substrate, the manufacturing method thereof and the display panel have the following beneficial effects:

according to the array substrate, the first flat layer is additionally arranged on the interlayer dielectric layer, so that the surface of the third metal wiring is flattened, and the problem that the third metal wiring is poor in color display at the edge of the display area due to the fact that the surface of the third metal wiring is uneven can be solved; by making the thickness of the first flat layer smaller than that of the second flat layer, the risk that the third metal routing, the source electrode or the drain electrode is broken due to the fact that the second through holes for connection or contact of the source electrode and the drain electrode and the active layer are deepened due to the fact that the first flat layer is added is reduced, and the risk that the source electrode and the drain electrode are broken when connected with the active layer is reduced.

According to the manufacturing method of the array substrate, the manufacturing process of manufacturing the first flat layer is added after the interlayer dielectric layer manufacturing process is completed, so that the surface of the third metal wiring which is manufactured subsequently can be flattened, and the problem that the edge of a real area displays different colors due to the fact that the surface of an SD film layer is uneven is solved; after the interlayer dielectric layer process is finished, a light resistance layer for manufacturing a via hole is manufactured by utilizing a PLN light resistance material, after the via hole process is finished, the light resistance layer is not stripped, the light resistance layer is reserved, and the first flat layer is obtained, so that Mask for manufacturing the first flat layer is not required to be increased, and the original light resistance layer stripping process is reduced.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a display area of a conventional array substrate;

FIG. 2 is a cross-sectional view of a first embodiment of an array substrate according to the present application;

fig. 3 is a cross-sectional view of a non-display area of a second embodiment of an array substrate according to the present application;

fig. 4 is a cross-sectional view of a first embodiment of a display panel according to the present application.

Fig. 5 is a cross-sectional view of a non-display area of a second embodiment of a display panel according to the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically or electrically connected or may communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

Fig. 2 is a cross-sectional view of a first embodiment of an array substrate according to the present application. As shown in fig. 2, the present application provides an array substrate 100, the array substrate 100 is divided into a display area 11 and a non-display area 12, and the array substrate 100 includes a substrate 110 and a plurality of insulating layers 120, which are sequentially stacked in a thickness direction thereof.

Specifically, the non-display area 12 includes a first non-display sub-area 12a (not shown in the drawings) connected to the display area 11 and a second non-display sub-area 12b (not shown in the drawings) located on a side of the first non-display sub-area 12a away from the display area 11.

Specifically, the first non-display sub-area 12a is a light leakage area not covered by an ink layer of a Cover plate (Cover Window).

As shown in fig. 2, a plurality of metal traces 140 are disposed in the non-display area 12 of the array substrate 100, and the plurality of metal traces 140 include a plurality of first metal traces 141, a plurality of second metal traces 142, and a plurality of third metal traces 143. The first metal trace 141, the second metal trace 142 and the third metal trace 143 are sequentially disposed on different layers of the multi-layer insulating layer 120 along a direction from the multi-layer insulating layer 120 toward the substrate base plate 110.

As shown in fig. 2, the multi-layer insulating layer 120 includes an interlayer dielectric layer 123 and a first flat layer 124, the interlayer dielectric layer 123 is located between the third metal trace 133 and the second metal trace 132 and covers the second metal trace 132 and the insulating layer where the second metal trace 132 is located, and the first flat layer 124 is disposed between the interlayer dielectric layer 123 and the third metal trace 133 and covers the interlayer dielectric layer 123.

By adding the first planarization layer 124 on the interlayer dielectric layer 123, the surface of the third metal trace 143 is planarized, so that the incident light can be prevented from generating a grating reflection phenomenon on the surface of the third metal trace 143, and the problem of poor display color such as white lines generated at the edge of the display region 11 is solved.

As shown in fig. 2, the array substrate 100 includes a substrate 110, a plurality of insulating layers 120 stacked on the substrate 110, a plurality of metal traces 130 formed on the plurality of insulating layers 120, and at least one thin film transistor 130 formed on the plurality of insulating layers 120.

Wherein, the substrate 110 is made of polymer material with light transmission and flexibility. For example, the base substrate 110 may include polyimide, polysiloxane, epoxy-based resin, acrylic resin, polyester, and/or the like. In one embodiment, the base substrate 110 may include polyimide.

As shown in fig. 2, the multi-layer insulating layer 120 is stacked on the substrate 110, and a multi-layer metal trace 140 is disposed in the non-display region 12 of the multi-layer insulating layer 120, and a thin film transistor 130 is disposed in the display region 11 of the multi-layer insulating layer 120.

As shown in fig. 2, the multi-layered insulating layer 120 includes a first gate insulating layer 121, a first gate insulating layer 122, an interlayer dielectric layer 123, a first planarization layer 124, a second planarization layer 125, and a pixel defining layer 126. The thin film transistor 130 includes an active layer 131, a first gate electrode 132, a second gate electrode 133, a drain electrode 134, and a source electrode 135. The multi-layer metal trace 140 includes a first metal trace 141, a second metal trace 142 and a third metal trace 143.

As shown in fig. 2, the active layer 131 is disposed on the substrate base plate 110. Specifically, the active layer 131 includes a channel region and source and drain regions located at the periphery of the channel region. Wherein the channel region may serve as a channel through which charge may move or be transferred, and the source and drain regions are used for source and drain electrical connections or contacts, respectively.

In particular implementations, the active layer 131 may include a silicon compound such as polysilicon. In some embodiments, source and drain regions including p-type or n-type impurities may be formed at both ends of the active layer 131. In some embodiments, the active layer 131 may include an oxide semiconductor, such as Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), Indium Tin Zinc Oxide (ITZO), and/or the like.

As shown in fig. 2, the first gate insulating layer 121 is formed on the active layer 131 and covers the active layer 131 and the base substrate 110.

In particular implementations, the first gate insulating layer 121 may include silicon oxide, silicon nitride, silicon oxynitride, and/or the like. These may be used alone or in combination thereof.

As shown in fig. 2, the first gate electrode 132 is disposed on the first gate insulating layer 121. Specifically, the first gate electrode 132 is stacked in a region of the first gate insulating layer 121 corresponding to the channel region.

As shown in fig. 2, a plurality of first metal traces 141 are disposed on the first gate insulating layer 121 at intervals and located in the non-display region 12.

The first metal trace 141 and the first gate 132 may be prepared from the same metal film layer. By such design, the first metal trace 141 and the first gate 132 can be formed simultaneously through a one-step composition process, so that the process steps for manufacturing the display panel or the array substrate and the number of used mask plates are reduced, the time for manufacturing the display panel can be saved, and the cost can be saved.

As shown in fig. 2, the second gate insulating layer 122 is disposed on the first gate 132 and covers the first gate 132, the first metal trace 141 and the first gate insulating layer 121.

As shown in fig. 2, the second gate electrode 133 is disposed on the second gate insulating layer 122, and specifically, the second gate electrode 133 is stacked in a region of the second gate layer 122 corresponding to the first gate electrode 132.

Referring to fig. 2, a plurality of second metal traces 142 are disposed on the second gate insulating layer 122 at intervals and located in the non-display region 12.

Wherein the second metal trace 142 and the second gate layer 133 are obtained from the same film layer. By such design, the second metal routing 142 and the second gate layer 133 can be formed simultaneously through a one-step composition process, so that the process steps for manufacturing the display panel or the array substrate and the number of used mask plates are reduced, the time for manufacturing the display panel can be saved, and the cost can be saved.

As shown in fig. 2, the second metal traces 142 and the first metal traces 141 are alternately distributed on a plane parallel to the substrate 110. Further, on the plane parallel to the substrate base plate 110, the adjacent second metal traces 142 and the first metal traces 141 are spaced from each other. In other words, the orthographic projections of the second metal trace 142 and the first metal trace 141 on the array substrate 100 are not overlapped and spaced from each other.

For example, in a specific implementation, on the plane parallel to the substrate base plate 110, a distance between adjacent second metal traces 142 and the first metal trace 141 is less than 3 um.

As shown in fig. 2, the interlayer dielectric layer 123 is disposed on the second gate 133 and covers the second gate 133, the second metal trace 142 and the second gate insulating layer 122.

As shown in fig. 2, the first flat layer 124 is disposed on and covers the interlayer dielectric layer 123, and the first flat layer 124 covers the non-display region 12 and the display region 11 of the interlayer dielectric layer 123.

As shown in fig. 2, by disposing the first planarization layer 124, the planarization layer can planarize a step caused by a film layer structure between the first planarization layer 124 and the substrate 110, so as to planarize a concave-convex structure formed by the first metal traces 141 and the second metal traces 142 alternately.

Specifically, the thickness of the first planarization layer 124 is smaller than the thickness of the second planarization layer 125. By making the thickness of the first flat layer 124 smaller than that of the second flat layer 125, the risk that the second via 102 for connection or contact of the source and drain electrodes with the active layer due to the addition of the first flat layer 124 is deepened, which may cause the third metal routing 143, the source 135 or the drain 124 to be disconnected, is reduced, and the risk of disconnection when the source 135 or the drain 124 is connected with the active layer 141 is reduced.

Specifically, the first planarization layer 124 is made of PLN photoresist. That is, the first planarization layer 124 can function as a planarization layer and also as a photoresist layer.

As shown in fig. 2, a first via 101 is formed on the array substrate 100, the first via 101 extends from the first planarization layer 124 to the second metal trace 142 or the first metal trace 141 in a direction toward the substrate 110 and exposes the second metal trace 142 or the first metal trace 141, and the first via 101 is used for electrically connecting or contacting a subsequent third metal trace 143 with the first metal trace 141 or the second metal trace 142.

As shown in fig. 2, a second via hole 102 is formed in a region of the array substrate 100 corresponding to a source region or a drain region of the active layer 131. The second via hole 102 extends from the first planarization layer 124 to the active layer 131 in a direction toward the substrate 110, and the second via hole 102 exposes a source region and a drain region of the active layer 131 respectively for making contact or electrical connection between the source 135 and the drain 134 and the active layer 141.

Referring to fig. 2, the drain electrode 134 and the source electrode 135 are disposed on the first planar layer 124, and the drain electrode 134 and the source electrode 135 are electrically connected or contacted with the source region and the drain region through the second via 102, respectively.

Referring to fig. 2, the third metal trace 143 is disposed on the first planarization layer 124 and located in the non-display area 12.

With reference to fig. 2, by disposing the third metal trace 143, the drain 134 and the source 135 on the first planarization layer 124, the third metal trace 143, the drain 134 and the source 135 all have a planarized surface, so as to avoid the problem of displaying different colors at the edge of the display area 11 due to the unevenness of the surface of the third metal trace 143.

Specifically, the third metal trace 143 can be electrically connected or contacted with the second metal trace 142 or the first metal trace 141 through the first via 101.

For example, as shown in fig. 2, in the present embodiment, a plurality of the third metal traces 143 are disposed at intervals. The third metal trace 143 is electrically connected or contacted with the second metal trace 141 of the second metal trace 142 through a first via hole 101 penetrating from the first planarization layer 124 to the second metal trace 141. At this time, the first via 101 sequentially penetrates through the first planarization layer 124 and the interlayer dielectric layer 123.

In other embodiments, the third metal trace 143 can be electrically connected or contacted with the first metal trace 141 through a first via 101 penetrating from the first planarization layer 124 to the first metal trace 141. At this time, the first via 101 sequentially penetrates through the first planar layer 124, the interlayer dielectric layer 123 and the second gate insulating layer 122 to expose the third metal trace 143.

With reference to fig. 2, the second planarization layer 125 is disposed on the drain electrode 134 and the source electrode 135, and the second planarization layer 125 covers the drain electrode 134, the source electrode 135, the third metal trace 143, and the first planarization layer 124.

By disposing the second planarization layer 125, the step of the array substrate 100 can be planarized, so as to facilitate the subsequent fabrication of the light emitting device.

With continued reference to fig. 2, a third via hole 103 is disposed in a region of the second planar layer 125 corresponding to the drain 134. The third via hole 103 penetrates through the second planarization layer 125 to the drain 134 in a direction toward the substrate 110. The third via 103 exposes the drain 134 for electrical connection or contact between the drain 134 and the subsequent first electrode 150.

For example, in the present embodiment, the third via 103 penetrates through the thickness of the second planar layer 125.

With reference to fig. 2, a first electrode 150 is further disposed on the second planar layer 125, and the first electrode 150 is electrically connected to the drain 134 through a third via 103 penetrating through the second planar layer 125.

Specifically, the first electrode 150 may be an anode for subsequently forming a light emitting device.

With reference to fig. 2, a pixel defining layer 126 is disposed on the second flat layer 125, the pixel defining layer 126 covers a peripheral portion or an edge portion of the first electrode 150, and has a pixel opening 104 exposing the first electrode 150, and the pixel opening 104 is used for defining a light emitting device or a pixel region.

As shown in fig. 2, in the present embodiment, the first gate insulating layer 121, the second gate insulating layer 122, the interlayer dielectric layer 123, the first planarization layer 124, the second planarization layer 125 and the pixel definition layer 126 all cover the display area 11 and the display area 102 of the array substrate 100.

It should be noted that the present application does not limit the arrangement, thickness, material or coverage area of each insulating layer of the multi-layer insulating layer 120 except for the first planarization layer 124. For example, the layers of the multi-layered insulating layer 120 can be independently arranged, for example, can be arranged in a continuous manner or can be arranged in a broken manner. One or more of the insulating layers 120 can be patterned according to actual design requirements, for example, forming via holes, openings, or hollow areas, and a coverage area can be separately provided for each insulating layer. In other embodiments, the multi-layered insulating layer 120 may further include one or more of a buffer layer, an organic barrier layer, an inorganic barrier layer, or a passivation layer.

In specific implementations, the first gate 132, the second gate 133, the drain 134, and the source 135 may each independently include a metal, an alloy, or a metal nitride. For example, the gate electrode 132 may include a metal such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and neodymium (Nd), an alloy thereof, and/or a nitride thereof. These may be used alone or in combination thereof. The first gate 132 and the second gate 133 may each independently include at least two metal layers having different physical and/or chemical properties.

In a specific implementation, the first electrode 150 may be made of a transparent material. The transparent material may be, but is not limited to, indium tin oxide, indium zinc oxide, or indium oxide. In specific implementation, the first electrode 150 is prepared by a sputtering method.

In implementation, for example, a photosensitive organic material such as a polyimide resin or an acrylic resin may be coated, and then an exposure process and a developing process may be performed to form the pixel defining layer 126. In some embodiments, the pixel defining layer 126 may be formed of a polymer material or an inorganic material through a printing process (e.g., an inkjet printing process).

It should be further noted that the arrangement, size, structure or configuration of the thin film transistor 130 in the present application is not limited to the embodiments listed in the above embodiments of the present invention. As long as the specific configuration of the thin film transistor 130 is suitable, it can be used for switching or driving.

Fig. 3 is a cross-sectional view of a non-display area of a second embodiment of an array substrate according to the present application. Compared with the embodiment shown in fig. 2, the embodiment shown in fig. 3 has the most distinctive features that: the array substrate 100 is not provided with the first via hole 101 in the non-display area 12.

Specifically, the array substrate 100 is not provided with the first via hole 101 in the first non-display sub-area 12a and the non-display area 12.

The application also provides a manufacturing method of the array substrate, which comprises the following steps:

providing a substrate, wherein the substrate is provided with a display area and a non-display area;

sequentially preparing a first grid electrode insulating layer, a first metal wire, a second grid electrode insulating layer, a second metal wire and an interlayer dielectric layer in a non-display area of the substrate base plate;

a step of preparing a first planarization layer on the interlayer dielectric layer; and the number of the first and second groups,

and preparing a third metal wire on the first flat layer.

According to the manufacturing method of the array substrate, the manufacturing process of the first flat layer 124 is added after the interlayer dielectric layer 123 is completed, so that a flat surface is provided for a subsequent film layer for preparing the third metal wire 143, and the subsequently manufactured third metal wire 143 obtains the flat surface, so that the problem that the edge of the display area 11 area displays different colors due to the fact that the surface of the SD film layer is uneven in the existing array substrate is solved.

Further, the array substrate is provided with a via hole penetrating at least the first flat layer and the interlayer dielectric layer, and the manufacturing method further comprises the following steps:

and patterning the array substrate by using the first flat layer as a light resistance layer to obtain the via hole.

In this step, the photoresist material capable of forming a flat layer is used to fabricate the hole photoresist layer (i.e., the first flat layer 124) on the interlayer dielectric layer 123, and after the via hole process is completed, the photoresist layer is not stripped, and the photoresist layer is retained, so that the first flat layer 124 is obtained, thereby eliminating the need to increase Mask for fabricating the first flat layer 124, and reducing the photoresist layer stripping process in the prior art. The via may be at least one of a via 101 or a second via 102.

Preferably, in the case that the array substrate 100 has a barrier layer or a buffer layer, the barrier layer or the buffer layer is formed before the first metal routing layer 141 is formed. Of course, it is understood that the barrier layer, the buffer layer, etc. may be fabricated by those skilled in the art without the need for any additional process. In specific implementation, the photoresist material capable of forming the planarization layer may be, but is not limited to, polyimide or polyamic acid.

Fig. 4 is a cross-sectional view of the display panel of the application. As shown in fig. 4, the present application also provides a display panel including the array substrate 100 of the present application. For a specific structure of the array substrate 100, reference is made to the above, and details are not repeated here.

As shown in fig. 4, the display panel further includes an organic light emitting layer 160 and a second electrode 170.

As shown in fig. 4, the organic light emitting layer 160 is disposed on the first electrode 150 exposed by the pixel opening 104. The organic light emitting layer 160 is formed of an organic light emitting material for generating red, blue or green light.

In some embodiments, the HTL may be formed using the above-described hole transport material before forming the organic emission layer 160. The ETL, HTL, and ETL may also be formed on the organic light emitting layer 160 using the above-described electron transport material, and the HTL and ETL may be patterned for each pixel through a process substantially the same as or similar to that for the organic light emitting layer.

As shown in fig. 4, the second electrode 170 is formed on the surface of the organic light emitting layer 160, and the edge of the second electrode 170 covers the pixel defining layer 126 at the periphery of the pixel opening 104.

The first electrode 150, the second electrode 170, and the organic light emitting layer 160 together form a light emitting device, which can be used for displaying or emitting light.

Specifically, the second electrode 170 may be made of a transparent material or a semitransparent material. The transparent material may be, but is not limited to, indium tin oxide, indium zinc oxide, or indium oxide.

Fig. 5 is a cross-sectional view of a non-display area of a second embodiment of a display panel according to the present application. Compared with the display panel shown in fig. 4, the most distinctive feature of the embodiment shown in fig. 5 is that: the array substrate 100 is not provided with the first via hole 101 in the non-display area 12.

As shown in fig. 5, the display panel further includes an encapsulation layer 180, and the encapsulation layer 180 is disposed on the second electrode 170 and covers the array substrate 100 and the light emitting device, so as to prevent moisture or other external contaminants from penetrating into the array substrate 100 and the light emitting device.

Specifically, the encapsulation layer 180 may include a plurality of inorganic encapsulation layers and organic encapsulation layers stacked in an alternating manner.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The array substrate, the manufacturing method thereof, and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied in the description to explain the principle and the implementation of the present application, and the description of the embodiments above is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.