阅读说明：本技术 一种用于三维封装的soi有源转接板及其制备方法 (SOI active adapter plate for three-dimensional packaging and preparation method thereof ) 是由 朱宝 陈琳 孙清清 张卫 于 2020-06-30 设计创作，主要内容包括：本发明公开一种用于三维封装的SOI有源转接板及其制备方法。采用SOI作为基底,在SOI的顶层硅上采用标准集成电路制造工艺制备CMOS反相器,可以抑制短沟道效应以及闩锁效应。在CMOS反相器的PMOS和NMOS晶体管之间的SOI基底上刻蚀出通孔结构,该通孔结构一方面可以作为连接垂直方向芯片之间的导电通道,另一方面可以作为PMOS和NMOS晶体管之间的电学隔离层。(The invention discloses an SOI active adapter plate for three-dimensional packaging and a preparation method thereof. The SOI is used as a substrate, and the CMOS inverter is prepared on the top silicon of the SOI by adopting a standard integrated circuit manufacturing process, so that the short channel effect and the latch-up effect can be inhibited. A through hole structure is etched on an SOI substrate between a PMOS transistor and an NMOS transistor of a CMOS phase inverter, and the through hole structure can be used as a conductive channel for connecting chips in the vertical direction on one hand and can be used as an electric isolation layer between the PMOS transistor and the NMOS transistor on the other hand.)

1. An SOI active adapter plate for three-dimensional packaging is characterized in that,

the method comprises the following steps:

an SOI substrate;

a CMOS inverter including a PMOS transistor (203) and an NMOS transistor (204) formed on the SOI substrate;

an SOI via hole formed between the PMOS transistor (203) and the NMOS transistor (204) and penetrating through the SOI substrate;

a first insulating medium (205) encapsulating the PMOS transistor (203) and the NMOS transistor (204);

a second insulating medium (206) formed on the SOI through hole side wall and the surface of the first insulating medium (205);

source drain gate through holes formed in the source, drain and gate of the PMOS transistor (203) and the NMOS transistor (204), respectively, penetrating through the first insulating medium (205) and the second insulating medium (206);

a copper diffusion barrier layer (207) and a seed layer (208) are formed on the side wall of the SOI through hole, copper (209) is filled in the SOI through hole, an adhesion layer/seed layer laminated film (210) and a micro bump (211) are formed at the top, and an adhesion layer/seed layer laminated film (212) and a C4 bump (213) are formed at the bottom;

and a copper diffusion barrier layer (207) and a seed crystal layer (208) are formed at the bottom and the side wall of the source-drain gate through hole, copper (209) is filled in the source-drain gate through hole, and an adhesion layer/seed layer laminated film (210) and a micro bump (211) are formed at the top of the source-drain gate through hole.

2. The SOI active interposer for three-dimensional packaging according to claim 1,

the first insulating medium (205) and the second insulating medium (206) are silicon dioxide, silicon nitride, SiOCH or SiOCFH.

3. The SOI active interposer for three-dimensional packaging according to claim 1,

the copper diffusion impervious layer (207) is TaN, TiN, ZrN, MnSiO₃At least one of (1).

4. The SOI active interposer for three-dimensional packaging according to claim 1,

the seed layer (208) is at least one of Cu, Co, and Ru.

5. A method for preparing an SOI active adapter plate for three-dimensional packaging is characterized in that,

the method comprises the following steps:

providing an SOI substrate comprising a silicon substrate (200), silicon dioxide (201) and top silicon (202);

preparing a CMOS inverter on the surface of the SOI substrate, wherein the CMOS inverter comprises a PMOS transistor (203) and an NMOS transistor (204);

forming a first insulating dielectric (205) to encapsulate the PMOS transistor (203) and the NMOS transistor (204);

photoetching and etching the area between the PMOS transistor (203) and the NMOS transistor (204) until part of the silicon substrate (200) is etched;

forming a second insulating dielectric (206) over the structure;

photoetching and etching to remove the first insulating medium (205) and the second insulating medium (206) on the source electrode, the drain electrode and the grid electrode of the PMOS transistor (203) and the NMOS transistor (204) so as to form a source-drain grid through hole;

forming a copper diffusion barrier layer (207), a seed layer (208) and copper (209), and removing the copper (209), the seed layer (208) and the copper diffusion barrier layer (207) above the second insulating medium (206) by adopting a chemical mechanical polishing process;

forming a top adhesion layer/seed layer laminated film (210) and a micro bump (211);

the silicon substrate (200) on the back side of the SOI base is thinned by a combined process of mechanical grinding and chemical mechanical polishing, so that the bottom of the copper (209) is exposed, and a bottom adhesion layer/seed layer laminated film (212) and a C4 bump (213) are formed.

6. The method for manufacturing an SOI active interposer for three-dimensional packaging according to claim 5,

the first insulating medium (205) and the second insulating medium (206) are silicon dioxide, silicon nitride, SiOCH or SiOCFH.

7. The method for manufacturing an SOI active interposer for three-dimensional packaging according to claim 5,

the copper diffusion impervious layer (207) is TaN, TiN, ZrN, MnSiO₃At least one of (1).

8. The method for manufacturing an SOI active interposer for three-dimensional packaging according to claim 5,

the seed layer (208) is at least one of Cu, Co, and Ru.

Technical Field

The invention belongs to the field of integrated circuit packaging, and particularly relates to an SOI (silicon on insulator) active adapter plate for three-dimensional packaging and a preparation method thereof.

Background

With the rapid development of integrated circuit technology, microelectronic packaging technology is becoming a major factor that restricts the development of semiconductor technology. In order to achieve high density of electronic packages, better performance and lower overall cost, the skilled person has developed a series of advanced packaging techniques. The three-dimensional system-in-package technology has good electrical performance and high reliability, can realize high packaging density, and is widely applied to various high-speed circuits and miniaturized systems.

The Through Silicon Via (TSV) interposer technology is a new technology for realizing interconnection of stacked chips in a three-dimensional integrated circuit, and a plurality of vertical interconnection vias and subsequent Redistribution Layer (RDL) are manufactured on a Silicon wafer to realize electrical interconnection between different chips. In addition, the TSV interposer technology is divided into an active interposer and a passive interposer, wherein the active interposer has active devices, and the passive interposer lacks active devices. The TSV adapter plate technology can enable the stacking density of chips in the three-dimensional direction to be maximum, the interconnection line between the chips to be shortest, the overall dimension to be minimum, the chip speed and the performance of low power consumption to be greatly improved, and the TSV adapter plate technology is the most attractive technology in the electronic packaging technology at present. However, when a CMOS device, such as a CMOS inverter, is fabricated on a silicon-based interposer, short channel effects and latch-up are likely to occur, thereby affecting device performance.

Disclosure of Invention

In order to solve the above problems, the present invention discloses an SOI active interposer for three-dimensional packaging, comprising: an SOI substrate; a CMOS inverter including a PMOS transistor and an NMOS transistor formed on the SOI substrate; an SOI through hole formed between the PMOS transistor and the NMOS transistor and penetrating through the SOI substrate; the first insulating medium covers the PMOS transistor and the NMOS transistor; the second insulating medium is formed on the side wall of the SOI through hole and the surface of the first insulating medium; source drain gate through holes which are respectively formed on the source electrodes, the drain electrodes and the grid electrodes of the PMOS transistor and the NMOS transistor and penetrate through the first insulating medium and the second insulating medium; a copper diffusion barrier layer and a seed crystal layer are formed on the side wall of the SOI through hole, copper is filled in the SOI through hole, an adhesion layer/seed layer laminated film and a micro bump are formed at the top of the SOI through hole, and an adhesion layer/seed layer laminated film and a C4 bump are formed at the bottom of the SOI through hole; and a copper diffusion barrier layer and a seed crystal layer are formed at the bottom and the side wall of the source-drain gate through hole, copper is filled in the source-drain gate through hole, and an adhesion layer/seed layer laminated film and a micro bump are formed at the top of the source-drain gate through hole.

In the SOI active interposer for three-dimensional packaging according to the present invention, preferably, the first insulating medium and the second insulating medium are silicon dioxide, silicon nitride, SiOCH, or SiOCFH.

In the SOI active interposer for three-dimensional packaging of the present invention, preferably, the copper diffusion barrier layer is TaN, TiN, ZrN, MnSiO₃At least one of (1).

In the SOI active interposer for three-dimensional packaging according to the present invention, preferably, the seed layer is at least one of Cu, Co, and Ru.

The invention also discloses a preparation method of the SOI active adapter plate for three-dimensional packaging, which comprises the following steps: providing an SOI substrate comprising a silicon substrate, silicon dioxide and top silicon; preparing a CMOS inverter on the surface of the SOI substrate, wherein the CMOS inverter comprises a PMOS transistor and an NMOS transistor; forming a first insulating medium to cover the PMOS transistor and the NMOS transistor; photoetching and etching the region between the PMOS transistor and the NMOS transistor until part of the silicon substrate is etched; forming a second insulating medium on the structure; photoetching and etching to remove the first insulating medium and the second insulating medium on the source electrode, the drain electrode and the grid electrode of the PMOS transistor and the NMOS transistor so as to form a source-drain grid through hole; forming a copper diffusion barrier layer, a seed crystal layer and copper, and removing the copper material, the seed crystal layer and the copper diffusion barrier layer above the second insulating medium by adopting a chemical mechanical polishing process; forming an adhesive layer/seed layer laminated film and a micro bump on the top; and thinning the silicon substrate on the back of the SOI base by adopting a combined process of mechanical grinding and chemical mechanical polishing to expose the bottom of copper and form the adhesive layer/seed layer laminated film on the bottom and a C4 bump.

In the method for manufacturing an SOI active interposer for three-dimensional packaging according to the present invention, preferably, the first insulating medium and the second insulating medium are silicon dioxide, silicon nitride, SiOCH, or SiOCFH.

In the preparation method of the SOI active adapter plate for three-dimensional packaging, the copper diffusion barrier layer is preferably TaN, TiN, ZrN or MnSiO₃At least one of (1).

In the method for manufacturing the SOI active interposer for three-dimensional packaging according to the present invention, preferably, the seed layer is at least one of Cu, Co, and Ru.

The invention adopts SOI as the substrate for preparing the active adapter plate and prepares the CMOS inverter on the top silicon of the SOI, thereby being capable of inhibiting the short channel effect and the latch-up effect. In addition, a through hole structure is formed on the SOI substrate between the PMOS transistor and the NMOS transistor of the CMOS inverter in an etching mode, and the through hole structure can be used as a conductive channel for connecting chips in the vertical direction on one hand and can be used as an electric isolation layer between the PMOS transistor and the NMOS transistor on the other hand to play a role similar to Short Trench Isolation (STI).

Drawings

Fig. 1 is a flow chart of a method for fabricating an SOI active interposer for three-dimensional packaging.

Fig. 2 to 13 are schematic structural diagrams of steps of a method for manufacturing an SOI active interposer for three-dimensional packaging.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.

The technical scheme of the invention is further explained by combining the attached figures 1-13 and the embodiment. Fig. 1 is a flowchart of a method for manufacturing an SOI active interposer for three-dimensional packaging, and fig. 2 to 13 are schematic structural diagrams illustrating steps of the method for manufacturing the SOI active interposer for three-dimensional packaging. As shown in fig. 1, the preparation method comprises the following specific steps:

step S1: and preparing a CMOS inverter on the surface of the SOI substrate. A single crystal silicon substrate 200 and a top layer single crystal silicon 202 are both selected as p-type doped SOI as a base, and the resulting structure is shown in fig. 2. The material between the silicon substrate 200 and the top silicon 202 is silicon dioxide 201, and the thickness of the top silicon 202 is 100-400 nm. Next, a CMOS inverter is fabricated on the surface of the top silicon 202 by using integrated circuit standard processes such as photolithography, etching, ion implantation, sputtering, and the like, and the resulting structure is shown in fig. 3. The device structure enclosed by the dotted line is a PMOS transistor 203 and an NMOS transistor 204, and the PMOS transistor 203 and the NMOS transistor 204 form a CMOS inverter. In this embodiment, both the silicon substrate and the top layer silicon are doped p-type, but the present invention is not limited thereto, and n-type doping may be used. The SOI is used as a substrate for preparing the active adapter plate, and the CMOS inverter is prepared on the top silicon of the SOI, so that the short channel effect and the latch-up effect can be inhibited.

Step S2: and etching the SOI substrate to form an SOI through hole structure. First, a layer of silicon dioxide is grown on the surface of the structure by using a chemical vapor deposition process to serve as a first insulating medium 205, and the structure can completely cover the CMOS inverter, and the structure is shown in fig. 4. And then, spin-coating photoresist and defining the pattern of the SOI through hole structure through exposure and development processes. Next, a deep plasma etch (DRIE) process is used to etch the SOI region between the PMOS and NMOS transistors until a portion of the silicon substrate 200 is etched away. Finally, the photoresist is dissolved or ashed away in a solvent, and the resulting structure is shown in FIG. 5. The through hole structure can be used as a conductive channel for connecting chips in the vertical direction on one hand, and can be used as an electrical isolation layer between a PMOS transistor and an NMOS transistor on the other hand, and the through hole structure plays a role similar to Short Trench Isolation (STI). Wherein CF may be selected as the plasma used for etching the silicon dioxide 202 and the first insulating medium 205₄、CHF₃、CF₄/CHF₃、CF₄/O₂Or CHF₃/O₂CF may be selected for etching the top silicon 203 and the silicon substrate 200₄、SF₆At least one of (1).

Step S3: and forming a through hole structure on the source electrode, the drain electrode and the grid electrode of the CMOS inverter. Firstly, a layer of silicon dioxide is grown on the surface of the structure by adopting a chemical vapor deposition process to serve as a second insulating medium 206, the thickness range is 200-500 nm, and thus the surface of the SOI through hole is covered with a layer of the second insulating medium 206. The layer of second insulating medium may serve as an isolation layer between the PMOS transistor and the NMOS transistor, or may serve as an isolation layer between the CMOS inverter, the silicon substrate, and the metal interconnection line, and the resulting structure is shown in fig. 6. And then, spin-coating photoresist and defining a through hole pattern of a source electrode, a drain electrode and a grid electrode of the CMOS inverter through exposure and development processes. Next, the first insulating dielectric 205 and the second insulating dielectric 206 are etched by DRIE process until the source, drain and gate electrodes are exposed, and the resulting structure is shown in fig. 7. In the present invention, silicon dioxide is used as the insulating dielectric, but the present invention is not limited thereto, and silicon dioxide, silicon nitride, low dielectric constant materials (e.g., SiOCH, SiOCFH), and the like may be selected.

Step S4: depositing a copper diffusion barrier layer, a seed layer, and electroplating copper. Firstly, a TaN film and a Cu film are sequentially grown in the SOI through hole and the source-drain gate through hole by adopting a physical vapor deposition method to respectively serve as a copper diffusion barrier layer 207 and a seed crystal layer 208, and the obtained structure is shown in figure 8. Then, a copper film is used as a seed crystal layer, a copper material 209 is electroplated on the seed crystal layer by adopting an electroplating process, the SOI through hole and the source-drain gate through hole are completely filled with the copper material 209, and the obtained structure is shown in FIG. 9. Finally, a chemical mechanical polishing process is used to remove the copper material 209, the Cu seed layer 208 and the TaN copper diffusion barrier layer 207 above the second insulating medium 206, and the resulting structure is shown in fig. 10. In the present embodiment, TaN is used as the copper diffusion barrier layer and Cu is used as the seed layer, but the present invention is not limited thereto, and TaN, TiN, ZrN, and MnSiO may be selected₃At least one of Cu, Co and Ru is selected as a seed crystal layer; the copper diffusion barrier layer and the seed layer may be grown in a manner selected from at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

Step S5: and carrying out metal wiring and manufacturing a contact bump. First, a laminated film 210 composed of a Ti thin film and a Cu thin film is grown on the surface of the above structure by a physical vapor deposition method. Wherein, the Ti film and the Cu film are respectively used as an adhesion layer and a seed layer. Then, a metal laminate composed of a Cu material and a Sn material is plated on the surface of the adhesive layer/seed layer laminate film 210 by an electroplating method to form the micro-bump 211. Next, the unnecessary adhesion layer/seed layer stack film 210 is removed by photolithography and etching processes to ensure that there is no conduction between adjacent micro-bumps, and the resulting structure is shown in fig. 11. Subsequently, the silicon substrate on the back side of the SOI base is thinned by a combined process of mechanical grinding and chemical mechanical polishing, so that the bottom of the copper material 209 is exposed, and the resulting structure is shown in fig. 12. Finally, the same process as that for making the micro-bumps 211 is used to sequentially make an adhesion layer/seed layer laminated film 212 and C4 bumps 213 on the bottom of the copper material 209, and the resulting structure is shown in fig. 13.

As shown in fig. 13, the SOI active interposer for three-dimensional packaging of the present invention includes: an SOI substrate; a CMOS inverter including a PMOS transistor 203 and an NMOS transistor 204 formed on an SOI substrate; an SOI through hole formed between the PMOS transistor 203 and the NMOS transistor 204, penetrating the SOI substrate; a first insulating medium 205 covering the PMOS transistor 203 and the NMOS transistor 204; a second insulating medium 206 formed on the sidewall of the SOI through hole and the surface of the first insulating medium 205; source drain gate vias formed on the source, drain and gate electrodes of the PMOS transistor 203 and the NMOS transistor 204, respectively, through the first insulating medium 205 and the second insulating medium 206; a copper diffusion barrier layer 207 and a seed layer 208 are formed on the side wall of the SOI through hole, copper 209 is filled in the SOI through hole, an adhesion layer/seed layer laminated film 210 and a micro bump 211 are formed on the top, and an adhesion layer/seed layer laminated film 212 and a C4 bump 213 are formed on the bottom; a copper diffusion barrier layer 207 and a seed layer 208 are formed at the bottom and the side wall of the source-drain gate through hole, the inside of the source-drain gate through hole is filled with copper 209, and an adhesion layer/seed layer laminated film 210 and a micro bump 211 are formed at the top of the source-drain gate through hole.

Preferably, the first insulating medium and the second insulating medium are silicon dioxide, silicon nitride, SiOCH, SiOCFH, etc. Preferably, the copper diffusion barrier layer is TaN, TiN, ZrN, MnSiO₃At least one of (1). Preferably, the seed layer is at least one of Cu, Co and Ru.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.