阅读说明：本技术 非易失性半导体存储装置 (Nonvolatile semiconductor memory device ) 是由 吉井谦一郎 菅野伸一 于 2019-08-26 设计创作，主要内容包括：实施方式实现一种能够减轻控制器侧的处理负担的非易失性半导体存储装置。能够与控制器连接的非易失性半导体存储装置包含具有多个块的单元阵列和控制电路。所述控制电路按预定的编程顺序执行对所述多个块中通过所述控制器选择的写入目的地块所包含的多个页的编程动作。所述控制电路将对所述写入目的地块的下一个编程动作所对应的页地址向所述控制器通知。(Embodiments realize a nonvolatile semiconductor memory device capable of reducing a processing load on a controller side. A nonvolatile semiconductor memory device capable of being connected to a controller includes a cell array having a plurality of blocks and a control circuit. The control circuit performs a program operation for a plurality of pages included in a write destination block selected by the controller among the plurality of blocks in a predetermined program order. The control circuit notifies the controller of a page address corresponding to a next program operation for the write destination block.)

1. A nonvolatile semiconductor memory device is connectable to a controller, and includes:

a cell array including a plurality of blocks; and

a control circuit configured to execute a program operation for a plurality of pages included in a write destination block selected by the controller among the plurality of blocks in a predetermined program order,

the control circuit is configured to notify the controller of a page address corresponding to a next program operation for the write destination block.

2. The non-volatile semiconductor memory device according to claim 1,

the control circuit is configured to, when a 1st process request for selecting one of the blocks as the write destination block is received from the controller, notify the controller of a page address indicating a page corresponding to a first program sequence number among the pages included in the write destination block as the page address corresponding to the next program operation for the write destination block.

3. The nonvolatile semiconductor memory device according to claim 2,

the control circuit is configured to control the operation of the electronic device,

when a program request specifying the page address of the page corresponding to the earliest program sequence number is received from the controller, and data to be written to the page corresponding to the earliest program sequence number is received, the controller is notified of a page address indicating a page corresponding to a next program sequence number from among the plurality of pages included in the write destination block, as the page address corresponding to the next program operation for the write destination block.

4. The non-volatile semiconductor memory device according to claim 1,

further comprising a buffer that holds data transferred from the controller,

a plurality of word lines belonging to the write destination block each include a plurality of pages,

the control circuit is configured to execute a plurality of programming operations for each word line in the write-destination block,

the programming order is determined such that programming actions for adjacent respective word lines are performed alternately with each other,

the control circuit is configured to, when a programming operation for a page address designated by a programming request received from the controller is a 2nd or subsequent programming operation for a 1st word line in the write destination block, read data used in a previous programming operation for the 1st word line from the buffer, and execute the programming operation for the 1st word line using the read data and data to be written to the designated page address transferred from the controller.

5. The non-volatile semiconductor memory device according to claim 1,

the control circuit is configured to, after receiving a program request for specifying the notified page address and data corresponding to a page having the specified page address from the controller, notify the controller of a case where the data corresponding to the page is not needed in a program operation for any page of the write destination block.

6. The non-volatile semiconductor memory device according to claim 1,

further comprising a buffer that holds data transferred from the controller,

the control circuit is configured to control the operation of the electronic device,

when a program request specifying another page address different from the notified page address and data corresponding to the another page address are received from the controller, the received data is saved in the cache without executing a program operation for a page having the another page address.

7. The non-volatile semiconductor memory device according to claim 6,

the control circuit is configured to control the operation of the electronic device,

performing a programming action on the page having the page address notified in a case where a programming request specifying the page address notified and data corresponding to the page having the page address notified are received from the controller,

after the program action for the page having the notified page address is performed, in a case where data corresponding to a next page in the write destination block in which a next program action should be performed exists in the cache, the program action for the next page is performed.

8. The non-volatile semiconductor memory device according to claim 7,

the control circuit is configured to release an area in the buffer memory that stores data that is no longer necessary for a program operation for any page of the write destination block.

9. The non-volatile semiconductor memory device according to claim 1,

the control circuit is configured to, when a copy request specifying the notified page address as a copy destination location and specifying a copy source location is received from the controller, read data stored at the copy source location from the cell array to a buffer existing in the nonvolatile semiconductor memory device, and execute a program operation of writing the data from the buffer to the copy destination location.

10. The non-volatile semiconductor memory device according to claim 1,

and an error-correcting code decoder is also provided,

the control circuit is configured to, when instructed by the controller that the ECC decoder should be enabled, perform, using the ECC decoder: error correction decoding processing of encoded data containing data and an error correction code read out from the cell array in accordance with a processing request from the controller.

11. The nonvolatile semiconductor memory device according to claim 9,

and an error-correcting code decoder is also provided,

the control circuit is configured to, when instructed by the controller that the ECC decoder should be enabled, perform, using the ECC decoder: error correction decoding processing of encoded data containing data and an error correction code read out from the copy source location of the cell array in accordance with the copy request from the controller.

12. The non-volatile semiconductor memory device according to claim 1,

and an error-correcting code encoder is also provided,

the control circuit is configured to, when instructed by the controller that the ECC encoder should be enabled, perform, using the ECC encoder: and an error correction encoding process of adding an error correction code to the data written in the write destination block.

13. The nonvolatile semiconductor memory device according to claim 11,

and an error-correcting code encoder is also provided,

the control circuit is configured to execute a programming operation of writing data, which has been error-corrected by the error correction decoding process, to the copy destination position when the controller instructs that the error correction code encoder should be enabled.

14. The non-volatile semiconductor memory device according to claim 1,

and an error-suppressing code decoder for decoding data encoded by an error-suppressing encoding process for converting a data pattern of original data into a data pattern in which errors are hard to occur and restoring the decoded data to the original data,

the control circuit is configured to, when instructed by the controller that the error suppression code decoder should be enabled, perform, using the error suppression code decoder: error-suppressing decoding processing of restoring data, which is read out from the cell array in accordance with a processing request from the controller and encoded by error-suppressing encoding processing, to original data.

15. The non-volatile semiconductor memory device according to claim 1,

an error-suppressing code encoder for performing an error-suppressing encoding process for converting a data pattern of original data into a data pattern in which errors are suppressed,

the control circuit is configured to encode data to be written to the write destination block by the error-suppressing encoding process using the error-suppressing code encoder when the controller instructs that the error-correcting code encoder should be enabled.

16. The nonvolatile semiconductor memory device according to claim 1, further comprising:

an error correction code decoder; and

an error-suppressing code decoder for decoding data encoded by an error-suppressing encoding process for converting a data pattern of original data into an error-suppressed data pattern and restoring the decoded data to the original data,

the control circuit is configured to, when the controller instructs that the error correction code decoder and the error suppression code decoder should be enabled, perform error correction decoding processing of encoded data including data and an error correction code, which is read from the cell array in response to a processing request from the controller, using the error correction code decoder, and perform error suppression decoding processing of restoring error-corrected data to original data using the error suppression code decoder.

17. The nonvolatile semiconductor memory device according to claim 1, further comprising:

an error correction code encoder; and

an error-suppressing code encoder for performing an error-suppressing encoding process for converting a data pattern of original data into a data pattern in which an error is suppressed,

the control circuit is configured to, when the controller instructs that the error correction code encoder and the error suppression code encoder should be enabled, encode data written to the write destination block by the error suppression encoding process using the error suppression code encoder, and perform an error correction encoding process of adding an error correction code to the data encoded by the error suppression encoding process using the error correction code encoder.

18. The non-volatile semiconductor memory device according to claim 1,

and an error-correcting code decoder is also provided,

the control circuit is configured to, when receiving a processing request from the controller, the processing request instructing checking of the number of error bits of data stored in a 1st block among the plurality of blocks, check the number of error bits included in the data stored in the 1st block using an error correction code decoder, and return a check result regarding the number of error bits to the controller.

19. The non-volatile semiconductor memory device according to claim 18,

the check result indicates whether the number of error bits checked is greater than or equal to a threshold value.

20. The non-volatile semiconductor memory device according to claim 18,

the check result indicates success or failure of error correction of the data held in the 1st block.

21. The non-volatile semiconductor memory device according to claim 18,

the control circuit is configured to check at least the number of error bits included in the 1st data stored in the 1st block and the number of error bits included in the 2nd data stored in the 1st block, and return the maximum number of error bits to the controller as the check result.

22. The non-volatile semiconductor memory device according to claim 1,

and an error-correcting code decoder is also provided,

the control circuit is configured to, when receiving a processing request from the controller to instruct adjustment of a read voltage level used for reading data from the cell array, repeat an operation of reading data from a plurality of memory cells connected to a read-target word line and an operation of checking the number of error bits of the read data using the error correction code decoder while changing the read voltage level applied to the read-target word line, thereby determining a new read voltage level at which the number of error bits is minimized.

23. The non-volatile semiconductor memory device according to claim 22,

the control circuit is configured to, when the processing request for instructing adjustment of the read voltage level designates a block address of a 1st block among the plurality of blocks, repeat an operation of reading data from a plurality of memory cells connected to a read-target word line among word lines belonging to the 1st block and an operation of checking the number of error bits of the read data using the error correction code decoder while changing the read voltage level applied to the read-target word line, thereby determining a new read voltage level at which the number of error bits is the minimum as the read voltage level for reading data from the 1st block.

24. The non-volatile semiconductor memory device according to any one of claims 1 to 23,

the nonvolatile semiconductor memory device includes: a plurality of memory cores operating independently of each other; and a plurality of memory core control circuits respectively controlling the plurality of memory cores,

the plurality of memory cores each operate as the cell array,

the plurality of memory core control circuits are each configured to operate as the control circuit.

25. A nonvolatile semiconductor memory device is connectable to a 1st semiconductor element and is configured,

comprising a plurality of blocks, said blocks comprising a plurality of memory cells,

transmitting a 2nd address signal selected based on the 1st address signal to the 1st semiconductor element with respect to a 1st address signal indicating one block selected from the plurality of blocks and received from the 1st semiconductor element,

the 1st data is programmed to the memory cell corresponding to the 1st address based on the 1st address signal and the 2nd address signal, for a command received from the 1st semiconductor element specifying the 1st address signal, the 2nd address signal, and the 1st data.

26. The non-volatile semiconductor memory device according to claim 25,

the 1st semiconductor element is connectable to a host device, and the 1st semiconductor element generates the 1st address signal and the 2nd address signal based on the 2nd address and the 1st data based on the 2nd data when receiving a write request specifying the 2nd address and the 2nd data from the host device.

27. The non-volatile semiconductor memory device according to claim 26,

the 1st semiconductor element associates the 2nd address with a physical address corresponding to the 1st address signal and the 2nd address signal.

Technical Field

Embodiments of the present invention relate to a nonvolatile semiconductor memory device such as a NAND flash memory.

Background

In recent years, various nonvolatile semiconductor memory devices have been used. As a typical example of the nonvolatile semiconductor memory device, a NAND-type flash memory is known.

As an Interface standard between a NAND-type Flash memory and a controller for controlling the memory, for example, Open NAND Flash Interface (ONFi) is widely used. Communication between the NAND-type flash memory and the controller is generally performed as follows.

For example, in a data write operation (program operation), the controller determines a page to be accessed, and transfers a program request (program command), an address, and data to the NAND-type flash memory. The NAND-type flash memory writes data received from the controller to a page specified by an address received from the controller, and returns the processing result to the controller.

Disclosure of Invention

Embodiments of the present invention provide a nonvolatile semiconductor memory device capable of reducing the processing load on the controller side.

According to an embodiment, a nonvolatile semiconductor memory device connectable to a controller includes a cell array including a plurality of blocks, and a control circuit configured to execute a program operation for a plurality of pages included in a write destination block selected by the controller among the plurality of blocks in a predetermined program order. The control circuit is configured to notify the controller of a page address corresponding to a next program operation to the write destination block.

Drawings

Fig. 1 is a block diagram showing an example of the configuration of a memory system including a nonvolatile semiconductor memory device (nonvolatile memory) and a controller that controls the nonvolatile semiconductor memory device.

Fig. 2 is a block diagram showing an example of the configuration of a controller in the memory system of fig. 1.

Fig. 3A is a block diagram showing an example of the configuration of the nonvolatile memory.

Fig. 3B is a block diagram showing an example of the configuration of a cell array included in the nonvolatile memory.

Fig. 3C is a circuit diagram showing an example of the configuration of each block included in the cell array.

Fig. 4 is a diagram showing an example of a program sequence table in which a program sequence rule applied to a flash memory (TLC) in which 3-bit data is stored in each memory cell is defined.

Fig. 5 is a diagram showing an example of the configuration of a cache management table maintained and managed by a cache control unit in the nonvolatile memory.

Fig. 6 is a diagram showing an example of the configuration of a block write state management table maintained and managed by a data processing unit in the nonvolatile memory.

Fig. 7A is a timing chart showing a part of the steps of the data writing process performed by the controller and the nonvolatile memory.

Fig. 7B is a subsequent timing chart showing steps of the data writing process performed by the controller and the nonvolatile memory.

Fig. 8 is a diagram showing the contents of the cache management table at a certain time point during execution of the data write processing.

Fig. 9 is a diagram showing the contents of the block write state management table at a certain time point during execution of the data write processing.

Fig. 10 is a timing chart showing other steps of the data writing process performed by the controller and the nonvolatile memory.

Fig. 11 is a diagram showing the contents of the buffer management table at a certain time point during execution of the data write processing of fig. 10.

Fig. 12 is a flowchart showing a procedure of processing executed by the nonvolatile memory in a case where start of the write processing to the block is notified from the controller.

Fig. 13 is a flowchart showing steps of a process performed by the nonvolatile memory in the case where a program request and write data are received from the controller.

Fig. 14 is a flowchart showing steps of processing executed by the nonvolatile memory when the program operation for a certain page is completed.

Fig. 15 is a diagram for explaining data copy processing executed inside the nonvolatile memory.

Fig. 16 is a sequence diagram showing steps of the data copy processing executed by the controller and the nonvolatile memory.

Fig. 17 is a block diagram showing an ECC processing section and an EMC processing section provided in a memory core control section of a nonvolatile memory.

Fig. 18 is a sequence diagram showing other steps of the data copy processing executed by the controller and the nonvolatile memory.

Fig. 19 is a timing chart showing other steps of the data writing process executed by the controller and the nonvolatile memory.

Fig. 20 is a sequence diagram showing the procedure of the error bit number checking process executed by the controller and the nonvolatile memory.

Fig. 21 is a diagram showing a relationship between 8 threshold voltage distributions corresponding to 3-bit data values stored in respective memory cells and 7 read voltage levels used when data is read from the respective memory cells.

Fig. 22 is a diagram showing a state in which each threshold voltage distribution of the memory cell is shifted (shift) to a low value with the passage of time after programming.

Fig. 23 is a diagram for explaining a process of determining an optimum read level corresponding to a threshold voltage distribution after conversion.

Fig. 24 is a timing chart showing the procedure of the optimum read level determination process executed by the controller and the nonvolatile memory.

Fig. 25 shows an example of a configuration of a nonvolatile memory including a plurality of memory cores and a plurality of memory core control units for controlling the memory cores.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings.

(embodiment 1)

Fig. 1 shows an example of a configuration of a memory system including the nonvolatile memory 1 according to embodiment 1.

The nonvolatile memory 1 is a nonvolatile semiconductor memory device such as a NAND flash memory. The nonvolatile memory 1 may be a 2-dimensional flash memory or a 3-dimensional flash memory.

The memory system includes a nonvolatile memory 1 and a controller 2 that controls the nonvolatile memory 1. The controller 2 is also referred to as the 1st semiconductor element. In addition, the nonvolatile memory 1 is also referred to as a 2nd semiconductor element. The memory system also includes a host interface 3, a memory controller communication line 4, and a power line 5.

The memory system may also be implemented as a Solid State Disk (SSD), for example. In this case, the SSD is used as a data storage of various information processing apparatuses such as a server computer, a personal computer, and a mobile device which function as a host system (host apparatus). Alternatively, the memory system may be implemented as a Removable storage device (Removable storage device) such as a memory card or a USB memory, or may be implemented as an embedded storage device.

The memory controller communication line 4 is a signal line used for communication between the controller 2 and the nonvolatile memory 1. A plurality of signals are defined in the memory controller communication line 4. These signals may be, for example, signals complying with the ONFI standard. These signals include a chip valid signal CEn, a write valid signal WEn, a read valid signal REN, a command latch valid signal CLE, an address latch valid signal ALE, a write protect signal WPn, a write valid signal WEn, I/O signals < 7: 0 >, ready/busy signal RBn. Here, "n" at the end of the name of a signal means that the signal is a signal of negative logic.

The nonvolatile memory 1 is implemented as a semiconductor memory chip such as a NAND flash memory chip. The nonvolatile memory 1 has a chip enable signal CEn, a write enable signal WEn, a read enable signal REn, a command latch enable signal CLE, an address latch enable signal ALE, a write protect signal WPn, a write enable signal WEn, an I/O signal < 7: the signal pins 0 >, and the ready/busy signal RBn correspond to, respectively, and can be connected to the controller 2 via these signal pins and the memory controller communication line 4.

The chip enable signal CEn is a signal for selecting the nonvolatile memory 1 (for example, a NAND-type flash memory chip).

The command latch valid signal CLE controls the introduction (latching) of commands, addresses, input data on the data bus (I/O signals < 7: 0 >).

The read enable signal REn enables serial data output to the data bus (I/O signal < 7: 0 >).

The command latch valid signal CLE is used to inform the nonvolatile memory 1 that the current bus cycle type on the data bus (I/O signals < 7: 0 >) is a command.

The address latch valid signal ALE is used to inform the nonvolatile memory 1 that the current bus cycle type on the data bus (I/O signal < 7: 0 >) is an address.

The write protect signal WPn is used to disable (disable) the program operation and the erase operation. The ready/busy signal RBn indicates the current state (ready state or busy state) of the nonvolatile memory 1.

Fig. 2 is a block diagram depicting the interior of the controller 2 of fig. 1 in more detail.

The controller 2 controls writing of data into the nonvolatile memory 1 in response to a data write request (write command) from a host system (host apparatus) such as a CPU in the information processing apparatus, or controls reading of data from the nonvolatile memory 1 in response to a data read request (read command) from the host system (host apparatus).

The controller 2 includes a host interface control unit 201, a command control unit 202, a buffer control unit 203, a data allocation management unit 204, a memory control unit 205, a buffer memory 206, an error correction code processing unit (ECC unit) 207, and a memory interface control unit 208.

The host interface control section 201 communicates with a host system (host device) via the host interface 3. The host interface control unit 201 executes processing for receiving a request (command) and data from a host system (host device) and processing for transmitting the processing result and data to the host system (host device) in accordance with an instruction from the command control unit 202.

Specific examples of the host interface 3 include Non-Volatile Memory Express (NVME) (registered trademark), Serial ATA (SATA), Serial Attached SCSI (SAS), and Universal Flash Storage (UFS).

The command control unit 202 interprets a command received from a host system (host device) via the host interface control unit 201, and controls other functional blocks in the controller 2 to execute processing in accordance with the contents of the command.

The cache control unit 203 manages the cache memory 206, and stores write data (user data) received from a host system (host device) and data read from the nonvolatile memory 1 in an appropriate position in the cache memory 206.

The data allocation management unit 204 manages which page of which block in the nonvolatile memory 1 the user data received from the host system (host device) is allocated. Here, the block is a unit of an erase operation, and the page is a unit of a program operation and a read operation.

The controller 2 receives, from the host system (host apparatus), user data associated with a data write request (write command) received from the host system (host apparatus). By the write command, an address (e.g., logical address) corresponding to the user data and the user data are specified. Specifically, the write command specifies a logical address (start logical address), a length, a data pointer, and the like. The start logical address indicates the first logical address in the logical address range corresponding to the user data. The length indicates the length of the user data. The data pointer indicates the location where the user data exists within the host memory (memory within the host system (host device)).

The block to which the user data is to be allocated and the page in the block are determined by the data allocation management unit 204. That is, the data allocation management unit 204 determines a block address and a page address to be allocated to user data specified by a write command received from a host system (host apparatus), and allocates the determined block address and the determined page address to a logical address specified by the received write command.

Further, the controller 2 generates write data (e.g., encoded data such as ECC encoded data) to be actually written to the nonvolatile memory 1 based on user data received from a host system (host device). The physical address indicating the physical storage location in the nonvolatile memory 1 to which the write data is to be written is determined based on a combination of a block address and a page address assigned to a logical address of user data corresponding to the write data.

In addition, the controller 2 manages mapping information indicating the correspondence between each logical address designated by the host system (host device) and each physical address of the nonvolatile memory 1 using a logical-physical address conversion table in order to access the memory system. Each physical address is represented by a combination of a block address and a page address, or a combination of a block address, a page address, and an offset (offset) within a page. The controller 2 updates the logical-physical address conversion table to associate a physical address (block address, page address) with an address (logical address) specified by a write command received from the host system (host apparatus).

When a read request (read command) is received from a host system (host device), the controller 2 can refer to the logical-physical address conversion table and acquire a physical address corresponding to the logical address specified by the read command from the logical-physical address conversion table.

The memory control unit 205 controls the memory interface control unit 208 in accordance with the instruction from the instruction control unit 202. Specifically, the memory control unit 205 controls the memory interface control unit 208 to read data from the nonvolatile memory 1 and write data to the nonvolatile memory 1. The act of writing data to the non-volatile memory 1 is also referred to as a programming act.

The cache memory 206 is an area for temporarily storing data and the like exchanged between the host system (host apparatus) and the nonvolatile memory 1. The cache memory 206 is often composed of a volatile memory such as a DRAM or an SRAM.

An Error Correction Code (ECC) processing unit 207 performs error correction encoding processing to which an error correction code is added on user data to be transferred from the cache memory 206 to the nonvolatile memory 1 via the memory interface control unit 208 in accordance with an instruction from the command control unit 202. The error correction encoding process is an encoding process of encoding user data and generating encoded data including the user data and an Error Correction Code (ECC) capable of correcting an error of the user data. Further, the Error Correction Code (ECC) processing section 207 performs error correction decoding processing for correcting an error of read data transferred from the nonvolatile memory 1 through the memory interface control section 208 in accordance with an instruction from the command control section 202. The error correction decoding process is a decoding process of decoding encoded data including data and ECC and correcting errors included in the data.

The memory interface control unit 208 electrically operates a physical signal line between the nonvolatile memory 1 and the controller 2 in accordance with an instruction from the memory control unit 205, and causes the nonvolatile memory 1 to perform a desired operation.

Fig. 3A is a block diagram depicting the interior of the non-volatile memory 1 of fig. 1 in more detail.

The nonvolatile memory 1 includes a memory core 11, a memory core control unit 12, and an input/output unit 13.

The memory core 11 includes a cell array 101. The cell array 101 includes a large number of nonvolatile memory elements (memory cells) regularly arranged.

The input/output unit 13 includes input buffers 112 and 114 and output buffers 113 and 115.

The input buffers 112 and 114 temporarily hold signals received from the controller 2 via signal lines for transferring signals from the controller 2 to the nonvolatile memory 1. The output buffers 113 and 115 temporarily store signals to be transmitted to the controller 2 via the signal lines for transferring signals from the nonvolatile memory 1 to the controller 2.

The memory core control unit 12 functions as a control circuit configured to control writing of data to the cell array 101 and reading of data from the cell array 101.

The memory core control unit 12 includes a row decoder 102, a column decoder, a buffer sense amplifier 103, a buffer 104, a memory core power supply control unit 105, a memory core operation unit 106, a command decoder 107, a command queue 108, a command execution control unit 109, a data processing unit 110, and a buffer control unit 111.

The row decoder 102 specifies a row (row) to be operated in the cell array 101. The column decoder buffer sense amplifier 103 performs transfer of data to a set of memory cells belonging to a row designated and/or selected by the row decoder 102, readout (sense) of data belonging to a set of memory cells belonging to a row designated and/or selected by the row decoder 102, selection of a column (column) in the buffer, and the like.

The buffer 104 is a temporary storage location for data to be written into the cell array 101 or data read out from the cell array 101. Here, a case where M +1 caches are provided as the cache 104 is exemplified.

The memory core power supply control unit 105 generates a voltage and/or a current required for the memory core 11 from a power supply voltage VCC supplied from the outside in accordance with an instruction from the memory core operation unit 106.

The memory core operation unit 106 controls the memory core power supply control unit 105 to generate a voltage and/or a current necessary for the operation of the cell array 101, and also controls a programming operation of writing data into the cell array 101 and a reading operation of reading data from the cell array 101, in accordance with an instruction from the instruction execution control unit 109.

In the programming operation, the memory core operation unit 106 causes the row decoder 102 to select a row to be operated, and instructs the cache sense amplifier 103 to write data (program) to the cell array 101. In the read operation, the memory core operation unit 106 causes the row decoder 10 to select a row to be operated, and instructs the buffer sense amplifier 103 to read data from the cell array 101.

The command decoder 107 interprets the contents of the command received from the controller 2 via the input buffer 114, stores the command in the command queue 108, and notifies the command execution control unit 109 of the reception of the command.

The command queue 108 is an area for temporarily holding commands received by the command decoder 107. The commands stored in the command queue 108 are acquired and executed by the command execution control unit 109. And if execution of the command is complete, the command is removed from the command queue 108.

When receiving a notification indicating that a command has been received from the command decoder 107, the command execution control unit 109 acquires the command from the command queue 108, and executes the command by controlling the memory core operation unit 106, the data processing unit 110, and the output buffer 113.

The data processing unit 110 performs an operation on the data in the buffer 104 in accordance with an instruction from the instruction execution control unit 109. The data processing unit 110 instructs the buffer control unit 111 to operate on the data in the buffer 104.

The buffer control unit 111 performs operations and management of the data in the buffer 104 in accordance with instructions from the data processing unit 110. The management of validity and invalidation of each cache used as the cache 104 is also the responsibility of the cache control unit 111.

Fig. 3B shows an example of the structure of the cell array 101.

The cell array 101 includes a plurality of memory cells arranged in a matrix. As shown in fig. 3B, the cell array 101 includes a plurality of blocks (physical blocks) BLK0 to BLK (j-1). The blocks BLK0 to BLK (j-1) function as a unit of an erase operation.

The blocks BLK 0-BLK (j-1) contain a plurality of pages. That is, the blocks BLK0 to BLK (j-1) include pages P0, P1, and … P (k-1), respectively. Reading of data and writing of data are performed in units of pages.

The nonvolatile memory 1 may be a single-level cell (SLC) -flash memory that stores 1 bit of data in one memory cell, a multi-level cell (MLC) -flash memory that stores 2 bits of data in one memory cell, a triple-level cell (TLC) -flash memory that stores 3 bits of data in one memory cell, or a quad-level cell (QLC) -flash memory that stores 4 bits of data in one memory cell.

In the SLC, a set of a plurality of memory cells connected to the same word line in a block functions as one page.

In the MLC, a set of a plurality of memory cells connected to the same word line functions as 2 pages (referred to as an upper page and a lower page).

In TLC, a set of a plurality of memory cells connected to the same word line functions as 3 pages (referred to as an upper page, a middle page, and a lower page).

Fig. 3C shows an example of the configuration of each block included in the cell array 101.

A block BLK includes a plurality of word lines WL0, WL1, WL2, WL3, WL4, …. A plurality of memory cells (memory cell transistors) MT0, MT1, …, MTN are connected to each word line WL.

For example, in TLC that stores 3-bit data for each memory cell, each memory cell transistor is set to any one of 8 states having different threshold voltages from each other. Each state corresponds to any one of 8 data values ("000", "001", "010", "011", "100", "101", "110", and "111").

Each word line WL is allocated with 3 pages (upper page, middle page, lower page). The 3 bits held by each memory cell transistor belong to different 3 pages (upper page, middle page, and lower page).

For example, page 0 (upper page), page 1 (middle page), and page 2 (lower page) are assigned to a set of memory cell transistors connected to word line WL 0. Similarly, page 3 (upper page), page 4 (middle page), and page 5 (lower page) are assigned to the set of memory cell transistors connected to word line WL1, and page 6 (upper page), page 7 (middle page), and page 8 (lower page) are assigned to the set of memory cell transistors connected to word line WL 2.

Fig. 4 shows an example of a program sequence table for specifying a program sequence rule to be applied to the nonvolatile memory 1.

The programming order represented by the programming order rule represents the order of pages required to write data to the blocks. In the case where a plurality of pages are allocated to each word line, the program order may indicate the order of word lines necessary for writing data to each block.

Hereinafter, a flash memory (TLC) is exemplified, and an example of the program sequence is described.

The program sequence table of fig. 4 shows the correspondence relationship between the program sequence numbers (program sequence number 0, program sequence number 1, program sequence number 2, …,) which are the sequence in which the plurality of word lines WL belonging to the same block are programmed, and the page addresses indicating the pages corresponding to the program sequence number 0, program sequence number 1, program sequence number 2, …, respectively.

For example, the first (program sequence No. 0) programming operation is a 1st programming operation for the word line WL0 (i.e., a programming operation for the page address 0). Page address 0 corresponds to the upper page of word line WL 0.

The next (program sequence No. 1) programming operation is a 1st programming operation for the word line WL1 (i.e., a programming operation for the page address 3). Page address 3 corresponds to the upper page of word line WL 1.

The next (program sequence No. 2) program operation is a 2nd program operation for the word line WL0 (i.e., a program operation for page address 1). Page address 1 corresponds to the middle page of word line WL 0.

The next (program sequence No. 3) program operation is a 1st program operation for the word line WL2 (i.e., a program operation for the page address 6). Page address 6 corresponds to the upper page of word line WL 2.

The next (program sequence No. 4) program action is a 2nd program action for the word line WL1 (the program action for page address 4). Page address 4 corresponds to the middle page of word line WL 1.

The next (programming sequence No. 5) programming action is a 3rd programming action for word line WL0 (i.e., a programming action for page address 2). Page address 2 corresponds to the lower page of word line WL 0.

In this way, in the nonvolatile memory 1, a program order indicating the order of pages necessary for writing data to each block is determined. In the example of fig. 4, the program sequence is determined such that the program actions for adjacent several word lines are performed alternately with each other.

That is, the program operation for each word line WL is performed by 3 different program operations including the 1st program operation, the 2nd program operation, and the 3rd program operation. The 2nd programming action for word line WL0 begins after the 1st programming action for word line WL1 is completed. The 2nd programming action for word line WL1 begins after the 1st programming action for word line WL2 is completed.

The 3rd programming action to word line WL0 begins after the 2nd programming action to word line WL1 is completed. The 3rd programming action to word line WL1 begins after the 2nd programming action to word line WL2 is completed.

The memory core control unit 12 of the nonvolatile memory 1 executes a program operation for a plurality of pages included in a write destination block selected from the plurality of blocks by the controller 2 in a program order indicating an order of pages necessary for writing data to the write destination block.

In the example of fig. 4, in order to write data to the write-destination block, the memory core control unit 12 needs to execute the program operation for the plurality of pages included in the write-destination block in the order of the program operation for the page address 0, the program operation for the page address 3, the program operation for the page address 1, the program operation for the page address 6, the program operation for the page address 4, the program operation for the page address 2, and the program operation for the page address ….

Fig. 5 is a cache management table maintained and managed by the cache control unit 111.

The cache management table is a table for managing the caches 104 in the nonvolatile memory 1, and includes a plurality of columns corresponding to each of a plurality of caches used as the caches 104. Each column stores a buffer number 51, a valid/invalid flag 52, a block address 53, a page address 54, and a data necessary period 55.

In each column of the cache management table, the cache number 51 indicates a cache number for identifying the cache corresponding to the column. Valid-invalid flag 52 indicates whether the contents of the cache to which the column corresponds are valid or invalid. The block address 53 indicates a block address identifying a block to which the content of the cache corresponding to the column belongs. Page address 54 represents a page address identifying a page corresponding to the contents of the cache to which the column corresponds. The data necessary period 55 indicates a period during which the data is required to be held in the cache memory in order to execute a program operation using the data held in the cache memory corresponding to the column.

Specifically, as the value of the data necessary period 55 corresponding to a certain data, a program sequence number corresponding to the 3rd program operation for the word line to be programmed using the data is used.

For example, in the cache storing the data to be written in page address 0, the programming sequence number (═ 5) corresponding to the 3rd programming operation of word line WL0 is the data necessary period corresponding to the data stored in the cache.

Similarly, for the buffer storing the data to be written to page address 1 or 2, the programming sequence number (═ 5) corresponding to the 3rd programming operation of word line WL0 becomes the data-required period corresponding to the data stored in the buffer.

In the buffer storing the data to be written to page address 3, the programming sequence number (═ 8) corresponding to the 3rd programming operation of word line WL1 becomes the data-requiring period corresponding to the data stored in the buffer.

Similarly, for the buffer storing the data to be written to page address 4 or 5, the programming sequence number (═ 8) corresponding to the 3rd programming operation of word line WL1 becomes the data-required period corresponding to the data stored in the buffer.

Fig. 6 shows a block write state management table maintained and managed by the data processing unit 110.

The block write state management table is a table for managing the write states of a plurality of blocks in the nonvolatile memory 1, and includes a plurality of columns to which the plurality of blocks correspond. Each column stores a block address 61, a write flag 62, a next program order number 63, and a completed program order number 64.

In each column of the block write state management table, the block address 61 indicates a block address for identifying a block corresponding to the column. The in-write flag 62 indicates whether or not the block corresponding to the column is in use as a write destination block (open block). The next program sequence number 63 indicates a program sequence number corresponding to a next program action to be performed on the block corresponding to the column (hereinafter, referred to as "next program sequence number"). The completed program order number 64 indicates the program order number of the program action completed in the block corresponding to the column.

Specifically, as each of the value of the next program order number 63 and the value of the completed program order number 64, the value of the program order 41 explained in fig. 4 is used.

When a block is selected as a write-destination block, the next program sequence number corresponding to the block is program sequence number 0. When the first (program sequence number 0) program operation (1st program operation of word line WL 0) is completed, the completed program sequence number corresponding to the block becomes program sequence number 0, and the next program sequence number corresponding to the block becomes program sequence number 1.

Returning to the description of fig. 4.

The programming sequence shown in fig. 4 shows that 3 programming operations (1st programming operation, 2nd programming operation, and 3rd programming operation) are required to store 3 bits of data (8 states) in each memory cell of one word line.

For example, in order to program each memory cell connected to the word line WL0 to a desired threshold voltage level corresponding to any one of the 8 states, it is necessary to perform the 1st program operation on the word line WL0 with the program sequence number 0, perform the 2nd program operation on the word line WL0 with the program sequence number 2, and perform the 3rd program operation on the word line WL0 with the program sequence number 5.

Similarly, in order to program each memory cell connected to the word line WL1 to a desired threshold voltage level corresponding to any one of the 8 states, it is necessary to perform the 1st program operation on the word line WL1 with the program sequence number 1, perform the 2nd program operation on the word line WL1 with the program sequence number 4, and perform the 3rd program operation on the word line WL1 with the program sequence number 8.

In this way, the data writing process for the plurality of memory cells connected to each word line is divided into 3 different programming operations (1st programming operation, 2nd programming operation, 3rd programming operation).

The 2nd programming action for a word line WLn is performed after the 1st programming action for the adjacent word line WLn + 1. Likewise, the 2nd programming action of word line WLn +2 is performed after the 1st programming action of the adjacent word line WLn + 2. Also, the 3rd program action for word line WLn is performed after the 2nd program action for word line WLn + 1.

In this way, the data writing process to the memory cells connected to the respective word lines is executed so that the programming operations to the adjacent word lines are staggered. This is because, in the nonvolatile memory 1 such as a NAND flash memory, it is necessary to write data to the memory cells of each word line while correcting the threshold voltage of the memory cells of each word line in accordance with the state of the adjacent word line. By interleaving the programming operations for several adjacent word lines, program disturb due to intercell interference can be reduced.

The program sequence rule necessary for the data write processing to each block changes depending on the generation of the nonvolatile memory 1 or the data write method.

However, in the conventional communication between the NAND flash memory and the controller, the controller itself needs to determine a write destination page to which data is to be written. That is, conventional communication between the NAND-type flash memory and the controller is premised on the controller side grasping the programming order (that is, the order of pages necessary to write data to a block) applied to the NAND-type flash memory.

Therefore, in order to make the program sequence to be used compatible with various nonvolatile memories, it is necessary to develop a controller compatible with various writing methods (that is, various program sequences) in advance, or to develop a new controller every time the generations of the nonvolatile memories are alternated.

However, in order to manufacture a controller capable of coping with various writing methods, it is necessary to add a plurality of circuits coping with the plurality of writing methods, which increases the cost accordingly. In addition, when a controller capable of coping with various writing methods is realized by software installation, the performance may be degraded due to a delay in processing caused by the software.

In addition, re-developing a new controller every time the generations of the nonvolatile memory 1 are alternated causes a huge increase in cost.

Therefore, the present embodiment provides a technique capable of reducing the processing load on the controller 2 side required for controlling the nonvolatile memory 1. Specifically, the present embodiment provides a technique that enables the controller 2 to cope with various writing methods, and further, with various generations of NAND flash memories.

Furthermore, in the data write operation, data in the previous program operation for the same word line is required even in the 2nd and 3rd program operations for each word line.

For example, in the 2nd programming operation (2nd programming operation) of the word line WL0, in order to determine the target threshold voltage (any one of the 4 states) of each memory cell of the word line WL0, not only data to be written in the 2nd programming operation (data corresponding to the middle page) but also data used in the 1st programming operation (1st programming operation) of the word line WL0 (data corresponding to the upper page) are required.

In the 3rd programming operation (3rd programming operation) of the word line WL0, in order to determine the final target threshold voltage (any of the 8 states) of each memory cell, not only data to be written in the 3rd programming operation (data corresponding to the lower page) but also data used in the 1st programming operation (1st programming operation) of the word line WL0 (data corresponding to the upper page) and data used in the 2nd programming operation (2nd programming operation) of the word line WL0 (data corresponding to the middle page) are required.

In this case, in the conventional inter-memory-controller interface standard, for example, at the time of the 2nd programming operation, not only data necessary for the 2nd programming operation but also data used in the 1st programming operation need to be transferred from the controller 2 to the nonvolatile memory 1. Similarly, for example, in the 3rd programming operation, not only the data necessary for the 3rd programming operation but also the data used in the 1st programming operation and the data used in the 2nd programming operation need to be transferred from the controller 2 to the nonvolatile memory 1. Thus, the number of communications between the controller 2 and the nonvolatile memory 1 becomes large.

When the number of times of communication increases, not only is it impossible to use the time taken for communication in the communication path within the controller 2 and the communication path between the memory controllers for other processing, but also power consumption due to communication increases.

Therefore, the present embodiment also provides a technique capable of suppressing an increase in the number of communications between memory controllers.

Hereinafter, specific communication contents between the nonvolatile memory 1 and the controller 2 will be described.

Fig. 7A and 7B show steps of data writing processing executed by the controller 2 and the nonvolatile memory 1.

The procedure of the data writing process according to embodiment 1 will be described with reference to fig. 7A and 7B.

As shown in fig. 7A, first, the controller 2 designates a block address to the nonvolatile memory 1, and notifies the nonvolatile memory 1 that the write process to the block is started (step S701).

In step S701, the controller 2 may transmit a request (Block open request) for selecting one of a plurality of blocks (free blocks) in the nonvolatile memory 1 as a write destination Block to the nonvolatile memory 1. For example, if the selected write destination Block is a Block having a Block address 0, the controller 2 transmits Block open (0) to the nonvolatile memory 1. Here, (0) of Block open (0) represents a Block address 0.

In other words, in this step S701, the controller 2 transmits a block address indicating one block selected from a plurality of blocks (free blocks) within the nonvolatile memory 1 to the nonvolatile memory 1. Here, the block address is also referred to as a 1st address signal.

When the memory core control unit 12 of the nonvolatile memory 1 receives the Block address, which is a request (Block open (0)) for selecting a write destination Block, from the controller 2, the memory core control unit 12 updates the Block write state management table of fig. 6, and sets the write flag corresponding to the designated Block 0 (Block having the Block address 0) to Y (yes) (step S702).

Further, the memory core control unit 12 updates the block write state management table of fig. 6, and initializes the value of the next program order number 63 corresponding to the designated block 0 (block having the block address 0) to 0 (step S703).

Then, the memory core control unit 12 of the nonvolatile memory 1 notifies the controller 2 that the data necessary for the next programming operation for the block 0 is the data of the page 0 (step S704). In other words, in step S704, the memory core control section 12 transmits the page address selected based on the block address to the controller 2 for the block address received from the controller 2. Here, the page address is also referred to as a 2nd address signal.

That is, in step S704, the memory core control unit 12 notifies the controller 2 of the page address corresponding to the next program operation performed on the block 0.

The next program sequence number corresponding to the next program operation is the value of the next program sequence number 63 (here, 0), and as can be seen from the table in fig. 4, the page address of the page required for the program operation of the next program sequence number 0 is 0. Similarly, the memory core control unit 12 obtains the next program sequence number from the block write state management table of fig. 6, and obtains the page address of the page necessary for the program operation indicating the next program sequence number from the table of fig. 4.

In this way, in step S704, the memory core control unit 12 of the nonvolatile memory 1 notifies the controller 2 of the page address indicating the page required for the next programming operation, that is, the page address of the "next page" (Notify next page 0, 0)). (0,0) of Notify next page (0,0) indicates a block address 0 of a write destination block and a page address 0 of a next write destination page in the write destination block. Notify next page (0,0) may also be accessed via a transport interface for transport I/O signal < 7: the data bus of 0 > is sent from the nonvolatile memory 1 to the controller 2.

In this way, by notifying the controller 2 of the pair of the block address of the write-destination block and the page address of the write-destination page in the write-destination block, even when a plurality of write-destination blocks are simultaneously opened (open), the memory core control unit 12 of the nonvolatile memory 1 can accurately notify the controller 2 of the page address indicating the page necessary for the next programming operation for each write-destination block.

Note that it is not necessary to notify both the write-destination block address and the page address from the nonvolatile memory 1 to the controller 2, and the notification of the write-destination block address may be omitted, and only the page address may be notified from the nonvolatile memory 1 to the controller 2.

When the controller 2 receives the page address 0 of the "next page" from the nonvolatile memory 1, the controller 2 transfers a program request (Write (0,0)) specifying the page address 0 and data to be written to the page having the page address 0 (also referred to as data of the page 0) to the nonvolatile memory 1 (step S705). (0,0) of Write (0,0) indicates a Write destination block address 0 and a page address 0. In addition, the program request may not necessarily specify both the write destination block address and the page address, and a program request specifying only the page address may be used.

Specifically, in step S705, first, a program command, a write destination block address, and a page address are transferred from the controller 2 to the nonvolatile memory 1, and then, data of page 0 is transferred from the controller 2 to the nonvolatile memory 1.

When the memory core control unit 12 of the nonvolatile memory 1 receives the program request (Write (0,0)) and the data of page 0 from the controller 2, the memory core control unit 12 stores the received data of page 0 in the cache 104, and registers the management data in the cache management table of fig. 5 (step S706).

For example, when the data is stored in the buffer of the buffer number 0, the memory core control unit 12 sets the valid/invalid flag 52 of the column associated with the buffer number 0 in the buffer management table (fig. 5) to a value indicating valid, sets the block address 51 of the column to 0, sets the page address 54 of the column to 0, and sets the data necessary period 55 of the column to 5. The value of the data necessary period (here, 5) is determined by referring to the table of fig. 4.

That is, as can be seen by referring to the table of fig. 4, the data of page 0 is the data of word line WL0, and the 3rd programming operation of this word line WL0 is the program sequence No. 5. Therefore, it can be seen that the data of page 0 is necessary until the program operation of program sequence number 5 is completed. From this, it is understood that the value of the data necessary period 55 set for the data of page 0 is 5. Thereafter, similarly, the data necessary period corresponding to the data of each page is acquired from the table of fig. 4.

Returning to the description of fig. 7A.

The memory core control unit 12 that acquired the data of the page 0 necessary for the next programming operation to write the destination block 0 updates the value of the next programming order number 63 associated with the block 0 in the block writing state management table (fig. 6) to 1, and notifies the controller 2 that the page address of the data necessary for the next programming operation to write the destination block 0 is 3 (step S707).

In this way, in step S707, the memory core control unit 12 notifies the controller 2 of the page address 3 corresponding to the next program operation for the write destination block 0 (Notifynext page (0, 3)). (0,3) of Notify next page (0,3) indicates a block address 0 of a write destination block and a page address 3 of a write destination page in the write destination block. Then, the memory core control section 12 performs a programming operation of writing the data of page 0 received from the controller 2 into page 0 of block 0 (step S708). In other words, in step S708, the memory core control unit 12 programs the data of page 0 to the memory cell corresponding to the address (physical address) based on the write destination block address and the page address, in response to the command (program command) received from the controller 2 and specifying the write destination block address, the page address, and the data of page 0.

When the programming of the data of page 0 is completed, the memory core control unit 12 sets the value of the completed programming order number 64 associated with block 0 of the block write status management table (fig. 6) to 0.

When the controller 2 receives the page address 3 of the "next page" from the nonvolatile memory 1, the controller 2 transfers a program request (Write (0,3)) specifying the page address 3 and data to be written to the page having the page address 3 (also referred to as data of the page 3) to the nonvolatile memory 1 (step S709).

When the memory core control unit 12 of the nonvolatile memory 1 receives the program request (Write (0,3)) and the data of page 3 from the controller 2, the memory core control unit 12 stores the data of page 3 in the cache 104 and registers the management data in the cache management table of fig. 5 (step S710). For example, when the data of the page 3 is stored in the cache of the cache number 1, the memory core control unit 12 sets the valid/invalid flag 52 of the column associated with the cache number 1 in the cache management table (fig. 5) to a value indicating valid, sets the block address 51 of the column to 0, sets the page address 54 of the column to 3, and sets the data necessary period 55 of the column to 8. The value of the data necessary period (here, 8) is determined by referring to the table of fig. 4.

The memory core control unit 12 that has acquired the data of the page 3 necessary for the next programming operation to write the destination block 0 updates the value of the next programming order number 63 associated with the block 0 in the block writing state management table (fig. 6) to 1, and notifies the controller 2 that the page address of the data necessary for the next programming operation to write the destination block 0 is 1 (step S711).

In this way, in step S711, the memory core control unit 12 notifies the controller 2 of the page address 1 corresponding to the next program operation for the write-destination block (Notify next page (0, 1)). (0,1) of Notify next page (0,1) indicates a block address 0 of a write destination block and a page address 1 of a write destination page in the write destination block. Then, the memory core control section 12 performs a programming operation of writing the data of page 3 received from the controller 2 into page 3 of block 0 (step S712).

When the controller 2 receives the page address 1 of the "next page" from the nonvolatile memory 1, the controller 2 transfers a program request (Write (0,1)) specifying the page address 1 and data to be written to the page having the page address 1 (also referred to as data of the page 1) to the nonvolatile memory 1 (step S713).

When the memory core control unit 12 of the nonvolatile memory 1 receives the program request (Write (0,1)) and the data of page 1 from the controller 2, the memory core control unit 12 stores the data of page 1 in the cache 104 and registers the management data in the cache management table of fig. 5 (step S714). For example, when the data of the page 1 is stored in the cache of the cache number 2, the memory core control unit 12 sets the valid/invalid flag 52 of the column associated with the cache number 2 in the cache management table (fig. 5) to a value indicating valid, sets the block address 51 of the column to 0, sets the page address 54 of the column to 1, and sets the data necessary period 55 of the column to 5. The value of the data necessary period (here, 5) is determined by referring to the table of fig. 4.

The memory core control unit 12 that has acquired the data of the page 1 necessary for the next programming operation to write the destination block 0 updates the value of the next programming order number 63 associated with the block 0 in the block writing state management table (fig. 6) to 6, and notifies the controller 2 that the page address of the data necessary for the next programming operation to write the destination block 0 is 6 (step S715).

In this way, in step S715, the memory core control unit 12 notifies the controller 2 of the page address 6 corresponding to the next program operation for the write destination block 0 (Notify next page (0, 6)). (0,6) of Notify next page (0,6) indicates a block address 0 of a write destination block and a page address 6 of a write destination page in the write destination block. Then, the memory core control unit 12 reads the data of page 1 from the buffer 104, and performs a program operation for page 1 of block 0 using the data of page 1 read from the buffer 104 and the data of page 3 received from the controller 2 (step S716).

In this way, when the program operation for the page designated by the program request received from the controller 2 is the 2nd program operation of the word line WL0, the memory core control unit 12 reads data (data of page 0) used in the 1st program operation for the word line WL0 from the buffer 104, and performs the program operation for the page 1 using the read data of page 0 and the data of page 1 transferred from the controller 2. Both the data of page 0 and the data of page 1 are used to determine the target threshold voltage level of each memory cell of word line WL 0. The target threshold voltage level is any one of 4 threshold voltage levels corresponding to 4 data values corresponding to 2 bits.

Thereafter, the same communication and processing are performed between the controller 2 and the nonvolatile memory 1 (step S713 of fig. 7A to step S728 of fig. 7B).

In step S728 of fig. 7B, the memory core control unit 12 reads both the data of page 0 and the data of page 1 from the buffer 104, and performs a program operation for page 2 of block 0 using the data of page 0 and the data of page 1 read from the buffer 104 and the data of page 2 received from the controller 2. The data of page 0, the data of page 1, and the data of page 2 are used to determine the final target threshold voltage level of each memory cell of word line WL 0. The final target threshold voltage level is any one of 8 threshold voltage levels corresponding to 8 data values corresponding to 3 bits.

When the programming of the data of page 2 is completed, the memory core control unit 12 sets the value of the completed programming order number 64 for block 0 in the block write state management table (fig. 6) to 5.

Specifically, the contents of the block write state management table (fig. 6) at this point in time are as shown in fig. 9. Fig. 8 shows the contents of the cache management table (fig. 5) at this point in time.

Therefore, the memory core control unit 12 refers to the cache management table of fig. 5 to search for a cache in which the value of the data necessary period 55 is 5. Then, the memory core control unit 12 detects that the value of the data-necessary period 55 corresponding to the buffer of the buffer number 0, the buffer of the buffer number 2, and the buffer of the buffer number 5 becomes 5, and identifies the value of the page address 54 corresponding to the data held in these buffers (here, the page addresses 0,1, and 2) as the data of the page that is no longer necessary in the program operation for any page of the write-destination block 0. Then, in step S729, the memory core control unit 12 notifies the controller 2 of the unnecessary data notification indicating that the data corresponding to the page addresses 0,1, and 2 is not necessary (Notify free data (0,1, 2)). (0,1,2) of Notifyfree data (0,1,2) indicates page addresses 0,1, 2.

In addition, not only the page addresses of the data that are no longer needed, but also the block addresses of the blocks to which these pages belong may be notified from the nonvolatile memory 1 to the controller 2.

Further, in step S729, the memory core control unit 12 also executes a process of releasing the cache (the area in the cache 104) in which the data corresponding to the page addresses 0,1, and 2 are stored.

Upon receiving the data unnecessary notification, the controller 2 determines that the specified data stored in the cache memory 206 in the controller 2 is unnecessary. Then, the controller 2 frees the area in the cache memory 206 in which the specified data is stored, and reuses the freed area for storage of other data or the like.

As described above, the memory core control unit 12 of the nonvolatile memory 1 executes the program operation for the plurality of pages included in the write-destination block in the predetermined program order. The predetermined program order indicates an order of pages required to write data to the write destination block. Then, the memory core control unit 12 notifies the controller 2 of the page address corresponding to the next program operation for the write destination block.

Therefore, the controller 2 only needs to perform a process of transferring data to be written to the page address indicated by the nonvolatile memory 1 to the nonvolatile memory 1, and therefore, it is not necessary to know whether or not the nonvolatile memory 1 is a memory in which the pages need to be programmed in what programming order. That is, even if the write mode of the nonvolatile memory 1 to be controlled is changed, the controller 2 can execute an accurate data write operation by performing a process of transferring data corresponding to the page address indicated by the nonvolatile memory 1 to the nonvolatile memory 1.

Therefore, even if the write method of the nonvolatile memory 1 is changed, there is no need to develop a new controller that can control the nonvolatile memory 1 in the correct program order corresponding to the changed write method, and the controller 2 can be continuously used.

Generally, the generation of the NAND flash memory used as the nonvolatile memory 1 changes every year, for example. Therefore, if a new controller is developed every time the generation of the NAND-type flash memory changes, a huge cost increase is caused.

In the present embodiment, when receiving a block address indicating one block selected from a plurality of blocks from the controller 2, the nonvolatile memory 2 transmits a page address selected based on the block address to the controller 2. This makes it possible to provide a communication interface standard in which the nonvolatile memory 1 notifies the controller 2 of the page address corresponding to the next program operation for writing to the destination block. Therefore, the processing load on the controller 2 side required for controlling the nonvolatile memory 1 can be reduced, and thus a memory system capable of coping with NAND-type flash memories of a plurality of generations can be realized at low cost.

In the present embodiment, as described in step S704 of fig. 7A, when receiving a processing request (Block open request) for selecting one of a plurality of blocks as a write-destination Block from the controller 2, the memory core control unit 12 notifies the controller 2 of a page address (for example, page address 0) indicating a page corresponding to a first programming sequence number (programming sequence number 0) among a plurality of pages included in the write-destination Block, as a page address indicating a page necessary for executing a next programming operation for the write-destination Block.

In the present embodiment, as described in step S707 in fig. 7A, when receiving a program request from the controller 2 to specify a page address (for example, page address 0) of a page corresponding to the first program sequence number (program sequence number 0) and data to be written to the page address 0, the memory core control unit 12 notifies the controller 2 of a page address (for example, page address 3) indicating a page corresponding to the next program sequence number (program sequence number 1) among a plurality of pages included in the write-destination block as a page address indicating a page necessary for performing the next program operation for the write-destination block.

In this way, as a reply to the Block open request or the program request, the page address indicating the page necessary for the next program operation is notified from the nonvolatile memory 1 to the controller 2.

Therefore, each time a Block open request or a program request is issued, the controller 2 can easily know a page address indicating a page necessary for the next program operation.

In addition, the controller 2 can recognize unnecessary data by receiving an unnecessary notification from the nonvolatile memory 1. Therefore, the controller 2 can easily delete data that is no longer necessary for the data write processing of the write destination block from the buffer memory 206, without knowing the number of pages assigned to each word line, the program order, the write method, and the like.

Further, in the present embodiment, each of the plurality of word lines belonging to the write-destination block includes a plurality of pages, and the memory core control unit 12 performs a multi-pass programming operation on each word line in the write-destination block. The program sequence is determined such that the program operations for the adjacent respective word lines are performed alternately with each other.

As described with reference to fig. 3A, the memory core control unit 12 includes a buffer 104 that holds data transferred from the controller 2. When the program operation for the page address designated by the program request received from the controller 2 is, for example, the 2nd or later program operation for the word line WL0, the memory core control unit 12 reads data used in the previous program operation for the word line WL0 from the buffer 104, and executes the program operation for the word line WL0 using the read data and the data to be written to the designated page address transmitted from the controller 2.

Therefore, the controller 2 needs to transmit only the data of the page instructed by the nonvolatile memory 1 to the nonvolatile memory 1, and even when a write scheme requiring a plurality of page data for writing data to each word line is applied to the nonvolatile memory 1, the controller 2 does not know the write scheme, and therefore the number of communications and/or the communication time between the nonvolatile memory 1 and the controller 2 can be reduced.

Specifically, even when a write method in which the number of page data required for data writing changes depending on which of the upper page, the middle page, and the lower page is the write target page is applied to the nonvolatile memory 1, the controller 2 only needs to perform a process of transferring, to the nonvolatile memory 1, 1 page of write data that specifies a page address that is known by the nonvolatile memory 1 and that is to be written to the page address, without considering which of the upper page, the middle page, and the lower page is the write target page.

Fig. 12 is a flowchart showing the steps of processing executed by the nonvolatile memory 1 when the start of the write processing to a block is notified from the controller 2, and fig. 13 is a flowchart showing the steps of processing executed by the nonvolatile memory 1 when a program request and write data are received from the controller 2. Details of these steps will be described in embodiment 2 described later.

(embodiment 2)

Next, embodiment 2 will be explained.

The configuration of each of the nonvolatile memory 1 and the controller 2 according to embodiment 2 is the same as the configuration of each of the nonvolatile memory 1 and the controller 2 according to embodiment 1.

In embodiment 1, the controller 2 transfers data corresponding to a page address designated by the nonvolatile memory 1 to the nonvolatile memory 1.

However, depending on the situation of the controller 2, it is also conceivable that the controller 2 cannot transfer data corresponding to the page address specified by the nonvolatile memory 1 to the nonvolatile memory 1. Fig. 10 shows the processing contents in such a case.

Since the processing of steps S1001 to S1008 of fig. 10 is the same as the processing of steps S701 to S708 of fig. 7A, the description of the processing of steps S1001 to S1008 of fig. 10 is omitted.

Here, although the nonvolatile memory 1 notifies the controller 2 of 3 as the page address of the data necessary for the next programming operation for the block 0 in step S1007, a case is considered in which the controller 2 transfers the data (data of page 1) to be written to the page address 1 of the block 0 in the programming request specifying the page address 1 of the block 0 to the nonvolatile memory 1 (step S1009).

At this time, the memory core control unit 12 of the nonvolatile memory 1 stores the data of the page 1 received from the controller 2 in the buffer 104, and registers the management data in the buffer management table of fig. 5 (step S1010). The data necessary period of the data of page 1 is 5.

Next, the memory core control unit 12 notifies the controller 2 that the page address of the data necessary for the next program operation for the block 0 is 3 again (step S1011).

Then, since the data (data of page address 3) necessary for the next programming operation of block 0 does not exist, the memory core control section 12 does not perform the programming operation for page address 3 of block 0.

Further, when the controller 2 transfers the program request specifying the page address 2 and the data to be written to the page address 2 (data of the page 2) to the nonvolatile memory 1, the memory core control unit 12 also performs the same processing as that performed when the program request specifying the page address 1 of the block 0 and the data (data of the page 1) to be written to the page address 1 of the block 0 are received (step S1013, step S1014). The data necessary period of the data of page 2 is 5.

After that, when the controller 2 transfers a program request specifying the page address 3 of the block 0 and data (data of the page 3) to be written to the page address 3 of the block 0 to the nonvolatile memory 1 (step S1015), the memory core control unit 12 stores the data of the page 3 received from the controller 2 in the cache 104 and registers management data in the cache management table of fig. 5 (step S1016). The data necessary period of the data of page 3 is 8.

The memory core control section 12 notifies the controller 2 that the data required for the next program operation for the block 0 is the data of the page address 6 (step S1017).

Then, the memory core control unit 12 performs a programming operation of writing the data of page 3 that has been received last (just) into page 3 of block 0 (step S1018). Then, the memory core control unit 12 updates the value of the next program order number 63 related to the block 0 of the block write state management table (fig. 6) to 2, and updates the value of the completed program order number 64 related to the block 0 to 1.

At this time, the contents of the cache management table of fig. 5 are as shown in fig. 11.

Then, the memory core control unit 12 recognizes that the next program sequence number is 2, and that the data required for programming the page 1 corresponding to the program sequence number 2 is both the data corresponding to the page address 0 and the data corresponding to the page address 1, and that both the data corresponding to the page address 0 and the data corresponding to the page address 1 are already present in the cache memory 104.

Therefore, after the programming of page 3 is completed, the memory core control unit 12 reads both the data corresponding to page address 0 and the data corresponding to page address 1 from the buffer 104, and performs the programming operation for page 1 using both the read data corresponding to page address 0 and the read data corresponding to page address 1 (step S1019).

In this way, when data of a page that is not necessary for the next programming operation is transferred from the controller 2, the memory core control unit 12 of the nonvolatile memory 1 stores the data in the buffer 104, and when the next programming sequence number is a programming sequence number that requires the stored data, the memory core control unit automatically executes the programming operation for the page corresponding to the programming sequence number without waiting for an instruction from the controller 1.

As described above, fig. 12, 13, and 14 show the processing contents described in fig. 7A, 7B, and 10 in flowcharts.

The contents of fig. 12, 13, and 14 will be described below.

Fig. 12 shows a procedure of processing executed by the nonvolatile memory 1 when the controller 2 notifies the nonvolatile memory 1 of the start of the write processing to the block (S701, S1001).

When the controller 2 notifies the nonvolatile memory 1 of the start of the write process to a block having a certain block address, the memory core control unit 12 of the nonvolatile memory 1 initializes a column related to the block in the block write state management table (fig. 6) (step S1201).

The initialization here means that the write flag 62 is set to Y, and the value of the next program sequence number 63, that is, the next program sequence number, is set to 0.

Next, the memory core control unit 12 of the nonvolatile memory 1 returns the page address 0 corresponding to the next program sequence number 0 to the controller 2 (step S1202). The page address corresponding to the next program sequence number 0 can be taken from the table of fig. 4.

Fig. 13 is explained next.

Fig. 13 shows steps of processing performed by the nonvolatile memory 1 when a program request and write data are transferred from the controller 2 to the nonvolatile memory 1.

The memory core control unit 12 of the nonvolatile memory 1 which received the program request from the controller 2 refers to the block write state management table (fig. 6) to determine whether or not the block specified by the received program request is a block under write (an open block) (step S1301).

If the block is not a block being written (no in step S1301), the memory core control unit 12 returns an error indicating that the block has not received a notification of the start of the writing process to the controller 2 (step S1302), and ends the process.

If the block specified by the received program request is a block being written (yes in step S1301), the memory core control unit 12 determines whether or not the page address specified by the received program request matches the page address corresponding to the value of the next program order number 63 in the block writing status management table (fig. 6) by referring to the table of fig. 4 (step S1303).

When the page address specified by the received program request matches the page address corresponding to the value of the next program order number 63 (yes in step S1303), the memory core control unit 12 stores the data received from the controller 2 in the cache 104 (step S1304), and updates the cache management table in fig. 5 (step S1305).

In the process of updating the cache management table of fig. 5, the memory core control unit 12 sets the valid/invalid flag 52 to a value indicating validity, the block address 53 to be written, the page address 54 to be written, and the data necessary period 55 to the program sequence number acquired with reference to the table of fig. 4, for the column in the cache management table corresponding to the cache number in which the data is stored.

When the update of the cache management table in fig. 5 is completed, the memory core control unit 12 updates the value of the next program order number 63 in the block write state management table in fig. 6 (step S1306). For example, when a program request and data corresponding to the program sequence number 0 are transferred from the controller 2 to the nonvolatile memory 1, the value of the next program sequence number 63, that is, the next program sequence number is updated to 1.

Then, the memory core control unit 12 returns the page address corresponding to the updated value of the next program order number 63 for the block to the controller 2 (step S1307). For example, if the value of the next program sequence number 63 (program sequence number) is updated to 1, the page address corresponding to the updated program sequence number 1 is determined to be 3 according to fig. 4, and the page address 3 is returned to the controller 2.

Then, the memory core control unit 12 starts the program operation for the page specified by the program request received from the controller 2, using the data stored in the buffer memory 104 in step S1304 (step S1308).

If the page address of the data received from the controller 2 is not the page address corresponding to the value of the next programming order number 63 (no in step S1303), the memory core control unit 12 checks whether or not there is a free area (margin) in the buffer 104 in which the data of the page necessary for the next programming operation can be stored, even if the data other than the data of the page necessary for the next programming operation is stored in the buffer 104 (step S1309).

In step S1309, the memory core control unit 12 may check whether or not the buffer memory 104 has a free area other than the free area for data corresponding to the next program sequence number, for example. That is, the memory core control unit 12 may check whether or not the buffer 104 has 2 or more free areas (2 or more free buffers), and determine that the buffer 104 has a margin if the buffer 104 has 2 or more free areas (2 or more free buffers).

When the buffer 104 has no free space (margin) for holding data other than the data of the page necessary for the next programming operation as much as possible (no in step S1309), the memory core control unit 12 returns an error indicating that the buffer 104 has no free space (margin) to the controller 2 (step S1312).

On the other hand, when the buffer 104 has a free space (margin) for storing data other than the data of the page necessary for the next programming operation as much as possible (yes in step S1309), the memory core control unit 12 stores the data received from the controller 2 in the buffer 104 (step S1310), and updates the buffer management table of fig. 5 (step S1311).

After the processing in steps S1311 and S1312, in any case, the memory core control unit 12 returns the page address corresponding to the value of the next program order number 63 of the block to the controller 2 (step S1313), and the processing is completed.

Fig. 14 shows a procedure of processing executed by the memory core control unit 12 when the programming operation started in step S1308 in fig. 13 is completed.

When detecting that the program operation for a certain page of a certain write destination block is completed, the memory core control unit 12 first updates the value of the completed program sequence number 64, that is, the completed program sequence number, for the block in question in the block write status management table (fig. 6) (step S1401).

Next, the memory core control unit 12 refers to the cache management table of fig. 5, and checks whether or not there is a cache in which the completed program sequence number is set in the data necessary period 55 (step S1402). The data held in the buffer memory in which the completed program sequence number is set in the data necessary period 55 is data (unnecessary data) which is not necessary in the program operation for any page of the write destination block.

If there is no cache in which the completed program order number is set in the data necessary period 55 (no in step S1402), the memory core control unit 12 ends the process.

If there is one or more buffers in which the completed program sequence number is set in the data necessary period 55 (yes in step S1402), the memory core control unit 12 releases the buffers (the area in the buffer 104), and returns a response to the controller 2 indicating that data of the page address corresponding to the buffers is not necessary (step S1403). This is processing corresponding to step S729 of fig. 7.

Thereafter, the memory core control unit 12 refers to the cache management table of fig. 5, and checks whether all data necessary for executing the program operation for the page corresponding to the next program sequence number of the completed program sequence numbers, that is, the next program operation, is already present in the cache 104 (step S1404). All data required for the next program operation are, for example, (1) data of page 0 and data of page 1 in the case where the next program operation corresponds to the 2nd program operation (2nd program operation) of the word line WL0, (2) data of page 0, data of page 1 and data of page 2 in the case where the next program operation corresponds to the 3rd program operation (3rd program operation) of the word line WL0, and (3) data of page 3 in the case where the next program operation corresponds to the 1st program operation (1st program operation) of the word line WL 1.

Therefore, for example, when the next program operation corresponds to the 2nd program operation (2nd program operation) of the word line WL0, the memory core control unit 12 checks whether or not all data necessary for executing the next program operation is present in the buffer 104 based on whether or not both of the data of page 0 and the data of page 1 are present in the buffer 104.

If all the data necessary for the next programming operation is not present in the cache memory 104 (no in step S1404), the memory core control unit 12 ends the processing.

On the other hand, when all the data necessary for the next programming operation is present in the cache memory 104 (yes in step S1404), the memory core control unit 12 automatically starts the next programming operation using the data in the cache memory 104 (step S1405). Where a series of processes is completed.

When the programming operation started in step S1405 is completed, the processing from step S1401 is performed again.

As described above, in embodiment 2, when receiving a program request for designating another page address different from the page address notified to the controller 2 and data corresponding to the other page address from the controller 2, the memory core control unit 12 does not execute a program operation for the page having the other page address and stores the received data in the buffer 104. Thus, even if the controller 2 transmits data of a page different from the page designated by the nonvolatile memory 1 to the nonvolatile memory 1, the data can be held in the cache memory 104 in the nonvolatile memory 1 without discarding.

When receiving a program request for specifying a notified page address and data corresponding to a page having the notified page address from the controller 2, the memory core control unit 12 executes a program operation for the page having the notified page address. After the programming operation for the page having the notified page address is executed, if data corresponding to the next page to be executed in the next programming operation exists in the buffer 104, the memory core control unit 12 automatically executes the programming operation for the next page.

Therefore, even if the controller 2 transmits data corresponding to a page different from the page designated by the nonvolatile memory 1 to the nonvolatile memory 1, the data corresponding to the page different from the page designated by the nonvolatile memory 1 can be written in the write destination block in the correct program order without increasing the number of communications between the controller 2 and the nonvolatile memory 1.

(embodiment 3)

Next, as embodiment 3, a configuration in which the nonvolatile memory 1 copies data from a certain block to another block in response to an instruction from the controller 2 will be described.

The configuration of each of the nonvolatile memory 1 and the controller 2 according to embodiment 3 is the same as the configuration of each of the nonvolatile memory 1 and the controller 2 according to embodiment 1 and 2.

The term "copy" as used herein refers to the following process.

For example, as shown in fig. 15, there are block a and block b, and it is set that: of the data stored in block a, 4 data stored in each of 4 storage positions a10, a13, a20, and a21 are valid data, and of the data stored in block b, 4 data stored in each of 4 storage positions b00, b01, b02, and b10 are valid data.

a10 indicates block address a, page address 1, offset 0. Similarly, b00 represents block address b, page address 0, offset 0.

The case where the valid data of block a and the valid data of block b in fig. 15 are copied to block c, which is another block, is referred to as copy processing. The copy processing is executed inside the nonvolatile memory 1. That is, the memory core control unit 12 reads data (valid data) held at the copy source position of the cell array 101 from the cell array 101 to the buffer memory 104, and then executes a programming operation of writing the data (valid data) from the buffer memory 104 to the copy destination position (write destination page) of the cell array 101.

Such processing is called garbage collection (garpage collection).

Here, the valid data refers to data associated with any one of logical addresses used by the host to access the memory system. The data associated with a logical address is data that is likely to be accessed later by the host. Invalid data refers to data that is not associated with any logical address.

The controller 2 manages an address conversion table for managing mapping between each logical address and each physical address indicating a storage location in the nonvolatile memory 1 in which data corresponding to the logical address is stored. The update data corresponding to a certain logical address is written to a location different from the storage location of the nonvolatile memory 1 in which the previous data corresponding to the logical address is stored. The controller 2 updates the address conversion table so that a physical address indicating a memory location to which the update data is written is associated with the logical address. The data held at the latest physical address corresponding to each logical address is valid data.

The contents of communication between the nonvolatile memory 1 and the controller 2 relating to the copy processing are as shown in fig. 16.

Similarly to the normal write processing, the controller 2 first notifies the memory 1 of the start of writing to a block (step S1601). Here, a write start notification is performed for the block c. In step S1601, the controller 2 may transmit a request (Block open request) to the nonvolatile memory 1 to select one of a plurality of blocks (free blocks) in the nonvolatile memory 1 as a write destination Block (also referred to as a copy destination Block herein). If the selected write destination Block is a Block c having a Block address c, the controller 2 transmits a Block open (c) to the nonvolatile memory 1. Here, (c) of Block open (c) denotes a Block address c.

The memory core control unit 12 of the nonvolatile memory 1 that receives the notification of the start of writing to the block c initializes the column of the block c in the block writing state management table (fig. 6) (step S1602), and notifies the controller 2 that the data necessary for the next programming operation to the block c is the data of page 0 (step S1603).

In step S1603, the memory core control unit 12 notifies the controller 2 of the page address 0 corresponding to the next program sequence number of the block c (Notify next page (c, 0)).

Then, the controller 2 sends a Copy request (Copy (c,0, a10, a13, a20, a21)) specifying the write-destination block number (c here), the write-destination page address (0 here), and the location information of the Copy-source data, to the nonvolatile memory 1 (step S1604).

In the example of fig. 15, since valid data exists at 4 locations of a10, a13, a20, a21 of block a, the controller 2 transmits these locations to the nonvolatile memory 1 as location information of copy source data.

In step S1604, specifically, the copy command, the write destination block address, the write destination page address, and the location information of the copy source data are transferred from the controller 2 to the nonvolatile memory 1.

The memory core control unit 12 of the nonvolatile memory 1 that has received the Copy request (Copy (c,0, a10, a13, a20, a21)) reads out the data held at the Copy source location specified by the Copy request to the cache 104(S1605), and updates the cache management table (fig. 5) (S1606).

For example, when the data is stored in the cache of the cache number 0, the memory core control unit 12 sets the valid/invalid flag 52 of the column associated with the cache number 0 in the cache management table (fig. 5) to a value indicating valid, sets the block address 51 of the column to c, sets the page address 54 of the column to 0, and sets the data necessary period 55 of the column to 5.

Then, the memory core control unit 12 notifies the controller 2 that the data required for the next programming operation for the block c is the data of the page 3 (step S1607).

In step S1607, the memory core control unit 12 notifies the controller 2 of the page address 3 corresponding to the next program sequence number 1 of the block c (Notify next page (c, 3)).

After that, the memory core control unit 12 starts the programming operation for page 0 of block c using the data read to the cache 104 (step S1608). Then, the memory core control unit 12 also updates the contents of the block write state management table (fig. 6) relating to the block c.

Next, the controller 2 transmits a Copy request (Copy (c,3, b00, b01, b02, b10)) specifying the write-destination block number (c here), the write-destination page address (3 here), and the location information of the Copy-source data to the nonvolatile memory 1 (step S16009).

In the example of fig. 15, since valid data exists at 4 locations of b00, b01, b02, b10 of block b, the controller 2 transmits these locations to the nonvolatile memory 1 as location information of copy source data.

The memory core controller 12 of the nonvolatile memory 1 that received the Copy request (Copy (c,3, b00, b01, b02, b10)) reads data stored at the designated Copy source location to the cache 104(S1610), and updates the cache management table (fig. 5) (S1611).

For example, when the data is stored in the cache of the cache number 1, the memory core control unit 12 sets the valid/invalid flag 52 of the column associated with the cache number 1 in the cache management table (fig. 5) to a value indicating valid, sets the block address 51 of the column to c, sets the page address 54 of the column to 3, and sets the data necessary period 55 of the column to 8.

Then, the memory core control unit 12 notifies the controller 2 that the data required for the next program operation for the block c is the data of page 1 (step S1612).

Thereafter, the memory core control unit 12 starts the program operation for page 3 of the block c using the data read to the cache memory 104 (step S1613). The contents of the block write status management table (fig. 6) relating to the block c are also updated.

By doing so, the data in the nonvolatile memory 1 can be copied without transmitting and receiving actual data between the nonvolatile memory 1 and the controller 2, and thus, reduction in processing time and reduction in power consumption due to simplification of communication contents can be achieved.

(embodiment 4)

Next, embodiment 4 will be explained.

The nonvolatile memory 1 and the controller 2 according to embodiment 4 are different from the nonvolatile memory 1 and the controller 2 according to embodiments 1 to 3 in that the memory core control unit 12 of the nonvolatile memory 1 includes an Error Correction Code (ECC) processing unit 116 and an error suppression code (EMC) processing unit 117, as shown in fig. 17. That is, in embodiment 4, an Error Correction Code (ECC) processing section 116 and an error suppression code (EMC) processing section 117 are provided in the memory core control section 12 of the nonvolatile memory 1.

In fig. 17, for convenience of illustration, only some elements within the memory core control unit 12 are illustrated, but the memory core control unit 12 according to embodiment 4 may include all the elements described in fig. 3A, an Error Correction Code (ECC) processing unit 116, and an error suppression code (EMC) processing unit 117.

The Error Correction Code (ECC) processing section 116 includes an ECC encoder 116a and an ECC decoder 116 b. The ECC encoder 116a performs error correction encoding processing of encoding data (user data) written to the write destination block and adding an error correction code to the data. The ECC decoder 116b performs error correction decoding processing of decoding data (encoded data including user data and ECC) read out from the cell array 101 and correcting errors included in the data.

As the error correction coding process, rs (reed solomon) coding, bch (bose chaudhurichocqueenghem) coding, or the like can be used.

The error suppression code (EMC) processing section 117 includes an EMC encoder 117a and an EMC decoder 117 b. The EMC encoder 117a performs error-suppressing encoding processing for converting a data pattern (also referred to as a bit pattern) of original data into a data pattern in which errors are hard to occur, that is, a data pattern in which errors are suppressed. The EMC decoder 117b performs error-suppressing decoding processing of decoding the data encoded by the error-suppressing encoding processing to restore the data to the original data.

For example, the EMC encoder 117a performs encoding for generating a code word whose occurrence frequency of '0' or '1' is offset. In the present description, such a code is referred to as an error suppression code (EMC), and a symbol used in the error suppression code is referred to as an error suppression code (EMC).

Here, the frequency of occurrence of '0' refers to the number of times (frequency) of occurrence of '0' in the bit sequence constituting the code word. The frequency of occurrence of '1' refers to the number of times (frequency) of occurrence of '1' in the bit sequence constituting the code word. Therefore, a codeword in which the occurrence frequency of '0' or '1' is biased means a codeword in which the number of '0's (the number of occurrences) and the number of '1's (the number of occurrences) are different.

As the code for generating such a code word, there are a scheme of generating a code word having a fixed bit length by encoding data having a fixed bit length, a scheme of generating a code word having a variable bit length by encoding data having a fixed bit length, and a scheme of generating a code word having a fixed bit length by encoding data having a variable bit length. Hereinafter, a method of encoding data of a fixed length to generate a codeword of a fixed length is referred to as a fixed length method. A variable length scheme is referred to as a scheme in which data having a fixed bit length is encoded to generate a code word having a variable bit length, a scheme in which data having a variable bit length is encoded to generate a code word having a fixed bit length, and a scheme in which data having a variable bit length is encoded to generate a code word having a variable bit length.

The variable length system can make the difference between the frequency of 0 and 1 larger than the fixed length system. Therefore, the EMC encoder 117a can encode the data in a variable length manner.

As the variable length coding, entropy coding such as Reverse Huffman coding, Reverse turn transform coding, or Reverse turn transform Huffman coding can be exemplified. Reverse Huffman coding is coding that is the inverse of Huffman coding. Reverse turn tune Huffman coding is coding that is the inverse of turn tune Huffman coding. Reverse Tunstall coding is coding that is the inverse of Tunstall coding. Huffman coding and Tunstall coding are coding used in data compression and the like. The tunstatus Huffman coding is coding in which the result obtained by the tunstatus coding is further subjected to Huffman coding.

As another encoding that can be used for the error-suppressing encoding process, inter-cell interference-suppressing encoding (ICI) that encodes data to be written such that a data pattern written in a memory cell becomes a data pattern that suppresses inter-cell interference, endurance encoding (end encoding) that encodes data to be written such that a data pattern written in a memory cell becomes a data pattern that reduces wear of a memory cell, asymmetric encoding (asymmetric encoding) that can change a ratio of 1 to 0 in data (i.e., a codeword) written in a memory cell, and the like can be exemplified.

For example, in TLC, each memory cell is programmed to any one of 8 states having different threshold voltages, but encoding processing for reducing the number of memory cells that are programmed to a state corresponding to the highest threshold voltage, which is a state in which errors are likely to occur, may be used as error-suppressing encoding processing.

In the data writing process, the memory core control unit 12 can encode data to be written in the write destination block by the error suppression encoding process using the EMC encoder 117a, and can perform a programming operation of writing the data encoded by the error suppression encoding process in the write destination page of the write destination block.

Furthermore, the memory core control unit 12 may further perform an error correction coding process of adding ECC to the data coded by the error suppression coding process using the ECC encoder 116a, and perform a programming operation of writing the data obtained by the error correction coding process (coded data + ECC obtained by the error suppression coding process) to the write destination page of the write destination block.

In the data reading processing, the memory core control section 12 first performs error correction decoding processing on the data read from the cell array 101 using the ECC decoder 116 b. Then, the memory core control section 12 performs error-suppressing decoding processing of restoring the error-corrected data to the original data using the EMC decoder 117 b.

In addition, data stored in the cell array 101 may be read with an error due to a lapse of time or the like.

Therefore, in particular, when data is copied in the nonvolatile memory 1 as in embodiment 3, it is effective to perform error correction decoding processing on data read from the cell array 101 using the ECC decoder 116b in the nonvolatile memory 1, and to write the error-corrected data into a write destination block (copy destination block) by reducing the number of errors included in the read data.

In addition, since the tendency of an error of data written to the cell array 101 of the nonvolatile memory 1 is known in advance from the characteristics of the memory core 11 (the characteristics of the cell array 101), it is also effective to operate on data so that such an error is difficult to occur. This "operating data so that an error is difficult to occur" is the responsibility of the EMC processing section 117 described above.

For example, in the sequence of the copy processing in fig. 16, when a processing request from the controller 2 to the nonvolatile memory 1 is made in S1601, S1604, or S1609, the controller 2 instructs the nonvolatile memory 1 to apply or not to apply the error correction processing using the ECC processing unit 116 and to apply or not to apply the error suppression processing using the EMC processing unit 117, so that at least one of the error correction decoding processing and the error suppression decoding processing can be performed in the nonvolatile memory 1 at the time of data reading in S1605 or S1610 in fig. 16, and at least one of the error correction encoding processing and the error suppression encoding processing can be performed in the nonvolatile memory 1 at the time of programming in S1608 or S1613 in fig. 16.

In the data write processing sequence of fig. 7A, when a processing request from the controller 2 to the nonvolatile memory 1 is made in S701, S705, or S709, the application or non-application of the error correction processing using the ECC processing unit 116 and the application or non-application of the error suppression processing using the EMC processing unit 117 are instructed, and thus at least one of the error correction coding processing and the error suppression coding processing can be performed in the nonvolatile memory 1 at the time of programming in S708 or S712 of fig. 7A.

Specifically, when the controller 2 instructs that the ECC decoder 116b should be enabled, the memory core control unit 12 performs error correction decoding processing using the ECC decoder 116b on data (encoded data including user data and ECC) read from the cell array 101 in response to a processing request (for example, a read request or a copy request) from the controller 2.

When the controller 2 instructs that the ECC encoder 116a should be enabled, the memory core control unit 12 performs error correction encoding processing for adding an error correction code to data written in the write destination block using the ECC encoder 116 a. The memory core control unit 12 performs a programming operation of writing data to which an error correction code is added, that is, encoded data including the data and the ECC, to a write destination page of the write destination block.

In addition, when the controller 2 instructs that the EMC decoder 117b should be enabled, the memory core control unit 12 performs: error-resilient decoding processing of restoring data encoded by error-resilient encoding processing, which is read out from the cell array 101 in accordance with a processing request (e.g., a read request, or a copy request) from the controller 2, to the original data.

When the controller 2 instructs that the EMC encoder 117a should be enabled, the memory core control unit 12 encodes the data to be written to the write destination block by error suppression encoding processing using the EMC encoder 117 a. Then, the memory core control unit 12 performs a programming operation of writing the data obtained by the error-suppressing encoding process into the write destination page of the write destination block.

Further, when the controller 2 instructs that both the ECC decoder 116b and the EMC decoder 117b should be enabled, the memory core control unit 12 performs: error correction decoding processing of encoded data including data and ECC read out from the cell array 101 in accordance with a processing request (for example, a read request, or a copy request) from the controller 2, and error suppression decoding processing of restoring error-corrected data to original data are performed using the EMC decoder 117 b.

Further, when the controller 2 instructs that both the ECC encoder 116a and the EMC encoder 117a should be enabled, the memory core control unit 12 encodes the data to be written into the write destination block by the error suppression encoding process using the EMC encoder 117a, and performs the error correction encoding process of adding the error correction code to the data encoded by the error suppression encoding process using the ECC encoder 116 a. Then, the memory core control unit 12 executes a programming operation of writing the data obtained by the error correction coding process (the coded data + ECC obtained by the error suppression coding process) into the write destination page of the write destination block.

Further, for example, in the data writing process, in a case where the controller 2 transmits the encoded data (encoded data including the user data and the ECC) generated using the ECC unit 207 inside the controller 2 to the nonvolatile memory 1 as write data, the controller 2 may instruct the nonvolatile memory 1 so that the error correction encoding process inside the nonvolatile memory 1 is not applied to the write data and the ECC encoder 116a inside the nonvolatile memory 1 is disabled. In addition, at the time of the copy processing or the read processing, the controller 2 may instruct the nonvolatile memory 1 so that the error correction coding processing inside the nonvolatile memory 1 is applied to the read data so that the ECC encoder 116a inside the nonvolatile memory 1 is enabled. In the copy process, the controller 2 may also instruct the nonvolatile memory 1 to validate both the ECC encoder 116a and the ECC decoder 116b in the nonvolatile memory 1.

Fig. 18 shows a sequence of data copying processing by the ECC processing section 116 and the EMC processing section 117.

The data copy processing in fig. 18 is different from the data copy processing described with reference to fig. 16 only in that the processing in S1604, S1605, S1608, S1609, S1610, and S1613 in fig. 16 is replaced with the processing in S1604, S1605 ', S1608 ', S1609 ', S1610 ', and S1613 '. The processing in S1601 to S1603, S1606 to S1607, and S1611 to S1612 in fig. 18 is the same as the processing described in S1601 to S1603, S1606 to S1607, and S1611 to S1612 in fig. 16, and therefore, the description thereof is omitted.

Hereinafter, it is assumed that both the ECC decoder 116b and the EMC decoder 117b are enabled at the time of reading, and both the ECC encoder 116a and the EMC encoder 117a are enabled at the time of writing.

S1604': the controller 2 transmits a Copy request (Copy (c,0, a10, a13, a20, a21)) specifying the write-destination block number (c here), the write-destination page address (0 here), and the location information of the Copy source data to the nonvolatile memory 1, and indicates to the nonvolatile memory 1 that both the ECC decoder 116b and the EMC decoder 117b should be validated.

S1605': the memory core control unit 12 reads data (encoded data including user data and ECC) held at the copy source location designated by the copy request, performs error correction decoding processing on the read encoded data using the ECC decoder 116b, and performs error suppression decoding processing for restoring error-corrected data (data encoded by error suppression encoding processing) to the original data using the EMC decoder 117 b. The memory core control unit 12 stores the original data obtained by the error-suppressing decoding process in the buffer 104. The memory core control unit 12 may read data (encoded data including user data and ECC) stored at the copy source location to the buffer 104, and perform error correction decoding processing and error suppression decoding processing on the data in the buffer 104.

S1608': the memory core control unit 12 encodes the data (data on which the error correction decoding process and the error suppression decoding process have been performed) in the buffer 104 by the error suppression encoding process using the EMC encoder 117a, and performs the error correction encoding process of adding the error correction code to the data encoded by the error suppression encoding process using the ECC encoder 116 a. Then, the memory core control unit 12 executes a programming operation of writing the data obtained by the error correction coding process (the coded data + ECC obtained by the error suppression coding process) to the write destination page 0 of the write destination block c.

In S1609 ', S1610', S1613 ', the same processing as in S1604', S1605 ', S1608' is also executed.

Fig. 19 shows a sequence of data writing processing by the ECC processing section 116 and the EMC processing section 117.

The data writing process of fig. 19 is different from the data writing process described with reference to fig. 7A only in that the processes of S705 ', S708', S709 ', and S712' are executed instead of the processes of S705, S708, S709, and S712 of fig. 7A. The processing of S701 to S704, S706 to S707, and S710 to S711 in fig. 19 is the same as the processing described in S701 to S704, S706 to S707, and S710 to S711 in fig. 7A, and therefore, the description thereof is omitted.

Hereinafter, it is assumed that both the ECC encoder 116a and the EMC encoder 117a are enabled at the time of writing.

S705': the controller 2, which has received the page address 0 of the "next page" from the nonvolatile memory 1, transmits a program request (Write (0,0)) specifying the page address 0 and data (data of page 0) to be written to the page having the page address 0 to the nonvolatile memory 1, and indicates to the nonvolatile memory 1 that both the ECC encoder 116a and the EMC encoder 117a should be enabled.

S708': the memory core control unit 12 of the nonvolatile memory 1 encodes the data of page 0 by the error suppression encoding process using the EMC encoder 117a, and performs the error correction encoding process of adding the error correction code to the data encoded by the error suppression encoding process using the ECC encoder 116 a. Then, the memory core control unit 12 executes a programming operation of writing data obtained by the error correction coding process (coded data + ECC obtained by the error suppression coding process) into page 0 of the write-destination block 0.

S709': the controller 2, which has received the page address 3 of the "next page" from the nonvolatile memory 1, transmits a program request (Write (0,3)) specifying the page address 3 and data (data of the page 3) to be written to the page having the page address 3 to the nonvolatile memory 1, and indicates to the nonvolatile memory 1 that both the ECC encoder 116a and the EMC encoder 117a should be enabled.

S712': the memory core control unit 12 of the nonvolatile memory 1 encodes the data of page 3 by error suppression encoding processing using the EMC encoder 117a, and performs error correction encoding processing of adding an error correction code to the data encoded by the error suppression encoding processing using the ECC encoder 116 a. Then, the memory core control unit 12 executes a programming operation of writing data obtained by the error correction coding process (coded data + ECC obtained by the error suppression coding process) to the page 3 of the write destination block 0.

(embodiment 5)

Next, embodiment 5 will be described.

The nonvolatile memory 1 and the controller 2 according to embodiment 5 are substantially the same in configuration as the nonvolatile memory 1 and the controller 2 according to embodiment 4. However, the nonvolatile memory 1 according to embodiment 5 may not necessarily include both the ECC processing unit 116 and the EMC processing unit 117, and may have a configuration including the ECC processing unit 116 and not including the EMC processing unit 117.

In embodiment 5, the nonvolatile memory 1 performs a process of checking the number of error bits of data stored in a block designated by the controller 2.

Fig. 20 shows the procedure of the error bit number checking process executed by the controller 2 and the nonvolatile memory 1.

First, the controller 2 designates a block address to the nonvolatile memory 1, and requests the nonvolatile memory 1 to check the number of error bits of data stored in the block (step S2001).

In step S2001, for example, the controller 2 may transmit a Block check request (Block check (1)) specifying a Block address (for example, Block address 1) of one Block in the Block in which data is written to all pages to the nonvolatile memory 1. Block check (1) is a processing request for indicating to the controller 2 that the number of error bits of data held in a specific Block should be checked. (1) of Block check (1) represents a Block address 1.

When the nonvolatile memory 1 receives the Block check request (Block check (1)), the memory core control unit 12 of the nonvolatile memory 1 checks the number of error bits included in the data stored in the Block 1 having the Block address 1 by using the ECC decoder 116b in the nonvolatile memory 1 (step S2002).

In step S2002, the memory core control unit 12 reads data from block 1, and performs error correction decoding processing on the read data using the ECC decoder 116b to check the number of error bits included in the data. Here, the number of error bits of the data is the number of error bits before the data is corrected.

In the error correction decoding process, error correction may not be possible. This is because the maximum number of error bits that can be corrected by the ECC decoder 116b is fixed to a certain upper limit.

Which page in the read block checks the number of error bits, how to read, the method of error correction processing, and the like may be determined by the nonvolatile memory 1, or may be set in advance in the nonvolatile memory 1 by the controller 2. For example, when a page in which an error is likely to accumulate in each block or a word line in which an error is likely to accumulate in each block is known in advance, data may be read from the page, or data may be read from each of several pages corresponding to the word line.

Then, the memory core control unit 12 determines a check result such as whether the number of error bits is within the allowable range based on the result of the error correction decoding process (step S2003), and returns the check result regarding the number of error bits to the controller 2 (step S2004).

In step S2004, the memory core control unit 12 may Notify the controller 2 of the result of the check indicating the success (pass) or failure (fail) of the error correction of the data stored in the block 1 (pass/fail)). Alternatively, the memory core controller 12 may notify the controller 2 of a check result indicating whether or not the number of error bits of the data stored in the block 1 is equal to or greater than a threshold value.

Alternatively, when data is read from each of several pages of block 0, the memory core control unit 12 performs error correction decoding processing on the 1st data read from a certain page, thereby examining the number of error bits included in the 1st data. Further, the memory core control unit 12 performs error correction decoding processing on the 2nd data read from the other page, thereby examining the number of error bits included in the 2nd data. The memory core controller 12 notifies the controller 2 of the largest number of error bits among the checked numbers of error bits as a check result.

In this way, it is possible to check in the nonvolatile memory 1 what the number of error bits of the data stored in the nonvolatile memory 1 is, and it is possible to reduce the number of communications between the nonvolatile memory 1 and the controller 2, and to reduce the amount of communication data, thereby reducing power consumption.

Further, since the controller 2 can specify a block having a relatively large number of error bits based on the check result notified from the nonvolatile memory 1, the controller 2 may transmit a request to copy data in the specified block to another block to the nonvolatile memory 1.

(embodiment 6)

Next, embodiment 6 will be described.

The nonvolatile memory 1 and the controller 2 according to embodiment 6 are substantially the same in configuration as the nonvolatile memory 1 and the controller 2 according to embodiment 4. However, the nonvolatile memory 1 according to embodiment 6 may not necessarily include both the ECC processing unit 116 and the EMC processing unit 117, and may have a configuration including the ECC processing unit 116 and not including the EMC processing unit 117.

In embodiment 6, the controller 2 requests the nonvolatile memory 1 to set an optimum read voltage level (also referred to as an optimum read level) when reading data from the cell array 101. That is, the controller 2 sends a processing request to the nonvolatile memory 1 instructing adjustment of the read voltage level used in reading data from the cell array 101.

When the nonvolatile memory 1 receives the processing request, the memory core control unit 12 of the nonvolatile memory 1 repeats an operation of reading data from a plurality of memory cells connected to a certain word line (read target word line) and an operation of checking the number of error bits of the read data by using the ECC decoder 116b in the nonvolatile memory 1 while changing the read voltage level applied to the word line, thereby determining a new read voltage level having the smallest number of error bits as the optimum read voltage level.

The adjustment of the optimum read voltage level may also be done on a block basis. In this case, the controller 2 may specify a block address of a block whose optimum read voltage level should be adjusted, to the nonvolatile memory 1. This makes it possible to determine an optimum read voltage level for each block in the nonvolatile memory 1.

Hereinafter, a process of adjusting a read voltage level used for reading data from the cell array 101 will be described with reference to fig. 21 to 22.

The readout voltage level adjustment processing will be described below by exemplifying TLC, but the readout voltage level adjustment processing of the present embodiment may be applied to SLC, MLC, or QLC.

Fig. 21 shows the relationship between the threshold voltage distribution of the memory cell immediately after programming and 7 read voltage levels.

In TLC, each memory cell to which 3-bit data is written is set to any one of 8 states (one state and 7 programmed states). These 8 states are referred to as an "ER" state, an "a" state, a "B" state, a "C" state, a "D" state, an "E" state, an "F" state, and a "G" state. These "ER", "a", "B", "C", "D", "E", "F", "G" states have threshold voltage levels that are different from each other. The threshold voltage levels increase in the order of "ER", "a", "B", "C", "D", "E", "F", and "G" states.

The read voltage level for reading data from the cell array 101 is set to, for example, the intersection of 2 adjacent threshold voltage distributions.

That is, in the data reading process, any one of 7 threshold voltages Vth0, Vth1, Vth2, Vth3, Vth4, Vth5, and Vth6 for separating the "ER", "a", "B", "C", "D", "E", "F", and "G" states from each other is used as the read voltage level. The read voltage level is a voltage applied to a word line (read target word line) to which a set of memory cells to be read is connected.

Vth0 is a voltage corresponding to an intersection of a threshold voltage distribution corresponding to the "ER" state and a threshold voltage distribution corresponding to the "a" state. Vth1 is set to a voltage corresponding to an intersection of the threshold voltage distribution corresponding to the "a" state and the threshold voltage distribution corresponding to the "B" state. Vth2 is set to a voltage corresponding to an intersection of a threshold voltage distribution corresponding to the "B" state and a threshold voltage distribution corresponding to the "C" state. Vth3 is set to a voltage corresponding to an intersection of a threshold voltage distribution corresponding to the "C" state and a threshold voltage distribution corresponding to the "D" state. Vth4 is set to a voltage corresponding to an intersection of the threshold voltage distribution corresponding to the "D" state and the threshold voltage distribution corresponding to the "E" state. Vth5 is set to a voltage corresponding to an intersection of a threshold voltage distribution corresponding to the "E" state and a threshold voltage distribution corresponding to the "F" state. Vth6 is set to a voltage corresponding to an intersection of a threshold voltage distribution corresponding to the "F" state and a threshold voltage distribution corresponding to the "G" state.

Fig. 22 shows threshold voltage distributions of the memory cells when a certain time has elapsed since the programming of the memory cells.

In fig. 22, the threshold voltage distribution immediately after programming is indicated by a one-dot chain line, and the current threshold voltage distribution is indicated by a solid line. The threshold voltage distribution of each memory cell when the time has elapsed from the start of programming is converted to a voltage lower than the threshold voltage distribution immediately after programming. Therefore, the threshold voltages Vth0, Vth1, Vth2, Vth3, Vth4, Vth5, and Vth6 immediately after programming are not optimal as read voltage levels.

In a block in which the number of program/erase cycles increases, the threshold voltage distribution of each memory cell may be set to a low value as indicated by the solid line in fig. 22 immediately after the program is performed.

Fig. 23 shows an example of the optimum read voltage level corresponding to the threshold voltage division distribution after the conversion of fig. 22.

In the present embodiment, a read voltage level suitable for the threshold voltage division distribution after the conversion is determined in the nonvolatile memory 1. Here, the threshold voltages Vth0 ', Vth1 ', Vth2 ', Vth3 ', Vth4 ', Vth5 ', and Vth6 ' represent the optimum readout voltage levels.

The threshold voltages Vth0 ', Vth1 ', Vth2 ', Vth3 ', Vth4 ', Vth5 ', and Vth6 ' for a certain block may be determined based on, for example, the number of program/erase cycles of the block, or may be determined based on the elapsed time from the start of programming the block.

Alternatively, for example, an optimum threshold voltage may be selected as the optimum read voltage level from among several predetermined threshold voltage candidates.

In this case, the optimal threshold voltage set may be selected from several threshold voltage sets (sets) corresponding to the number of program/erase cycles (or elapsed time from the start of programming) (in the case of TLC, each threshold voltage set includes 6 threshold voltage candidates).

Fig. 24 shows a process of determining an optimum read level.

In step S3401, the controller 2 transmits a process request for setting an optimum read voltage level to the nonvolatile memory 1 (Set optimum read level (1)). (1) of the Set optimal read level (1) indicates the block address of the block for which the optimal read voltage level should be Set.

The memory core control unit 12 of the nonvolatile memory 1 that has received the processing request repeats an operation of reading data from a plurality of memory cells connected to the read target word line and an operation of checking the number of error bits of the read data using the ECC decoder 116b of the nonvolatile memory 1 while changing the read voltage level applied to the read target word line among the word lines belonging to the block 1 having the block address 1 (step S2402). Thus, the memory core control unit 12 determines the new read voltage level with the smallest number of error bits as the optimum read voltage level for reading data from the block 1.

Then, the memory core control unit 12 records the determined optimum read voltage level in the register or the cell array 101 in the nonvolatile memory 1 (step S2403), and notifies the controller 2 that the optimization processing is completed (step S2404).

In this way, the controller 2 can adjust the read voltage level so that the data retention capability of the nonvolatile memory 1 becomes maximum without knowing how the nonvolatile memory 1 is configured.

(7 th embodiment)

In embodiment 7, the nonvolatile memory 1 includes a plurality of memory cores 11, and the nonvolatile memory 1 can operate the plurality of memory cores 11 independently.

Fig. 25 shows a structure of the nonvolatile memory 1 according to embodiment 7.

As shown in fig. 25, the nonvolatile memory 1 according to embodiment 7 includes memory cores 11a, 11b, and 11c that can operate independently of each other. Each of these memory cores 11a, 11b, and 11c has the same structure as the memory core 11 described with reference to fig. 3A, and includes a cell array having a plurality of blocks.

Further, the nonvolatile memory 1 includes memory core control units 12a, 12b, and 12 c. The memory core controllers 12a, 12b, and 12c are connected to the memory cores 11a, 11b, and 11c, respectively.

The memory core control unit 12a functions as a memory core control circuit configured to control writing of data to the cell array in the memory core 11a and reading of data from the cell array in the memory core 11 a.

The pair of the memory core control unit 12a and the memory core 11a can perform the same operation as the pair of the memory core 11 and the memory core control unit 12 described with reference to fig. 3A. That is, the memory core control unit 12a has the same configuration and capability as the memory core control unit 12 described in embodiments 1 to 6. The pair of the memory core control section 12a and the memory core 11a may be realized by 1 chip (die).

The memory core control unit 12b functions as a memory core control circuit configured to control writing of data to the cell array in the memory core 11b and reading of data from the cell array in the memory core 11 b.

The pair of the memory core control unit 12b and the memory core 11b can also perform the same operation as the pair of the memory core 11 and the memory core control unit 12 described with reference to fig. 3A. That is, the memory core control unit 12b has the same configuration and capability as the memory core control unit 12 described in embodiments 1 to 6. The pair of the memory core control unit 12b and the memory core 11b may be implemented by 1 chip (die).

The memory core control unit 12c functions as a memory core control circuit configured to control writing of data to the cell array in the memory core 11c and reading of data from the cell array in the memory core 11 c.

The pair of the memory core control unit 12c and the memory core 11c can also perform the same operation as the pair of the memory core 11 and the memory core control unit 12 described with reference to fig. 3A. That is, the memory core control unit 12c has the same configuration and capability as the memory core control unit 12 described in embodiments 1 to 6. The pair of the memory core control unit 12b and the memory core 11b may be implemented by 1 chip (die).

The memory core control units 12a, 12b, and 12c perform communication with the controller 2 via the input/output unit 13 included in the nonvolatile memory 1. The memory controller communication lines may also contain 3 chip valid signals CE0n-CE2n, a write valid signal WEn, a read valid signal REn, a command latch valid signal CLE, an address latch valid signal ALE, a write protect signal WPn, a write valid signal WEn, I/O signals < 7: 0 >, 3 ready/busy signals RB0n-RB2 n.

In the nonvolatile memory 1 according to embodiment 7, a pair of the memory core control unit 12a and the memory core 11a, a pair of the memory core control unit 12b and the memory core 11b, and a pair of the memory core control unit 12c and the memory core 11c can operate independently of each other. Therefore, the operations described in embodiments 1 to 6 can be executed in parallel in these pairs, and the write and read performance of the memory system can be sufficiently improved.

In embodiments 1 to 7, a NAND flash memory is exemplified as a nonvolatile memory. However, the functions of the embodiments can be applied to various other nonvolatile memories such as MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Access Memory), and FeRAM (Ferroelectric Random Access Memory).

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope equivalent to the invention described in the claims.