阅读说明：本技术 一种半导体器件的制造方法 (Method for manufacturing semiconductor device ) 是由 彭翔 陈昊瑜 王奇伟 于 2020-06-02 设计创作，主要内容包括：本发明提供了一种半导体器件的制造方法,具体包括：提供衬底,存储区域的衬底上形成有存储晶体管的栅极结构,外围区域的衬底上形成有用以构成外围晶体管的栅极结构的第一层；以上述第一层为上述外围区域的掩膜,对上述存储晶体管的栅极结构两侧的存储区域的衬底上部进行轻掺杂漏的离子注入；以及对上述第一层进行刻蚀,以形成上述外围晶体管的栅极结构。根据本发明所提供的半导体器件,通过将存储区域的轻掺杂漏离子注入的步骤提前,能够有效地增加存储区域源漏极的离子扩散程度,在不增加额外热预算的前提下,提升存储单元器件的均匀性。(The invention provides a manufacturing method of a semiconductor device, which specifically comprises the following steps: providing a substrate, wherein a gate structure of a storage transistor is formed on the substrate of a storage area, and a first layer used for forming the gate structure of the peripheral transistor is formed on the substrate of a peripheral area; performing ion implantation of a lightly doped drain on the upper part of the substrate of the storage region at two sides of the gate structure of the storage transistor by taking the first layer as a mask of the peripheral region; and etching the first layer to form the gate structure of the peripheral transistor. According to the semiconductor device provided by the invention, the ion diffusion degree of the source electrode and the drain electrode of the storage region can be effectively increased by advancing the step of lightly doped drain ion implantation of the storage region, and the uniformity of the storage unit device is improved on the premise of not increasing extra thermal budget.)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a gate structure of a storage transistor is formed on the substrate of a storage area, and a first layer used for forming the gate structure of the peripheral transistor is formed on the substrate of a peripheral area;

performing lightly doped drain ion implantation on the upper part of the substrate of the storage region at two sides of the gate structure of the storage transistor by taking the first layer as a mask of the peripheral region; and

and etching the first layer to form a gate structure of the peripheral transistor.

2. The method of manufacturing of claim 1, further comprising:

performing gate reoxidation treatment on the gate structures of the storage transistor and the peripheral transistor; wherein

The implanted lightly doped drain ions are heat treated in the gate reoxidation process.

3. The method of manufacturing of claim 1, further comprising:

performing a self-aligned source process on the upper part of the substrate of the storage region corresponding to the source electrode of the storage transistor to form the source electrode of the storage transistor; wherein

The implanted lightly doped drain ions are heat treated in the self-aligned source process.

4. The method of manufacturing of claim 3, wherein the self-aligned source process further comprises:

self-aligned source electrode etching, self-aligned source electrode ion implantation and self-aligned source electrode annealing; wherein

The implanted lightly doped drain ions are heat treated in the self-aligned source anneal.

5. The method of manufacturing of claim 1, wherein providing a substrate formed with a gate structure of the memory transistor further comprises:

providing a substrate with a stacked gate layer of a storage transistor formed on the upper surface; and

and etching the stacked gate layer to form a gate structure of the storage transistor.

6. The method of manufacturing of claim 5, wherein providing a substrate having a stacked gate layer of a memory transistor formed on an upper surface further comprises:

and sequentially depositing a grid dielectric layer, a floating grid layer, an interlayer dielectric layer and a control grid layer on the upper surface of the substrate of the storage region from bottom to top.

7. The method of manufacturing of claim 6, wherein providing the substrate with the first layer formed further comprises:

and sequentially depositing a grid dielectric layer and a grid layer on the upper surface of the substrate of the peripheral area from bottom to top to form the first layer.

8. The manufacturing method according to claim 7, wherein the gate dielectric layer of the peripheral region and the gate dielectric layer of the storage region are formed in the same step.

9. The manufacturing method according to claim 7, wherein the gate layer of the peripheral region and the control gate layer of the storage region are formed in the same step.

10. The method of manufacturing of claim 7, wherein the gate layer of the peripheral region and the control gate layer of the storage region are polysilicon.

Technical Field

The invention relates to the field of manufacturing of semiconductor devices, in particular to a manufacturing method of a flash memory device.

Background

Flash memories (Flash memories) are widely used in various fields including consumer electronics, network communication devices, industrial instrumentation embedded systems, automotive devices, etc. because of their non-volatility, easy programming and erasing, long service life, and low cost.

The existing Flash memory structure, taking NOR Flash structure as an example, has three different gates:

1. a Floating Gate (FG) of a memory transistor in the memory region, which is a basic data memory cell;

2. a Control Gate (CG) of the memory transistor in the storage region is located above the floating Gate, an insulator is located between the floating Gate and the Control Gate, and the Control Gate controls erasing, writing, and reading of data in the floating Gate;

3. the gates (Poly Gate, hereinafter abbreviated as PG) of various devices in the peripheral logic control region, it is understood that various devices in the peripheral logic control region may include a high voltage P-type MOS transistor (HVPMOS), a high voltage N-type MOS transistor (HVNMOS), a low voltage P-type MOS transistor (LVPMOS), a low voltage N-type MOS transistor (LVNMOS), and the like.

Disclosure of Invention

The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

As described above, in order to improve the problem of poor uniformity of ion implantation into the lightly doped drain of the memory cell of the flash memory in the prior art and improve the problem of poor electrical uniformity between the memory cells, the present invention provides a method for manufacturing a semiconductor device, which specifically comprises: providing a substrate, wherein a gate structure of a storage transistor is formed on the substrate of a storage area, and a first layer used for forming the gate structure of the peripheral transistor is formed on the substrate of a peripheral area;

performing ion implantation of a lightly doped drain on the upper part of the substrate of the storage region at two sides of the gate structure of the storage transistor by taking the first layer as a mask of the peripheral region; and

and etching the first layer to form the gate structure of the peripheral transistor.

In an embodiment of the above manufacturing method, optionally, the manufacturing method further includes:

performing gate reoxidation treatment on the gate structures of the memory transistor and the peripheral transistor; wherein

The implanted lightly doped drain ions are heat treated in the gate reoxidation process described above.

In an embodiment of the above manufacturing method, optionally, the manufacturing method further includes:

performing a self-aligned source process on an upper portion of the substrate corresponding to a storage region of the source of the memory transistor to form a source of the memory transistor; wherein

The implanted lightly doped drain ions are heat treated in the self-aligned source process described above.

In an embodiment of the manufacturing method, optionally, the self-aligned source process further includes:

self-aligned source electrode etching, self-aligned source electrode ion implantation and self-aligned source electrode annealing; wherein

The implanted lightly doped drain ions are heat treated in the self-aligned source anneal described above.

In an embodiment of the above manufacturing method, optionally, providing the substrate on which the gate structure of the memory transistor is formed further includes:

providing a substrate with a stacked gate layer of a storage transistor formed on the upper surface; and

and etching the stacked gate layer to form the gate structure of the storage transistor.

In an embodiment of the foregoing manufacturing method, optionally, providing the substrate with the stacked gate layer of the memory transistor formed on the upper surface further includes:

and sequentially depositing a grid dielectric layer, a floating grid layer, an interlayer dielectric layer and a control grid layer on the upper surface of the substrate of the storage region from bottom to top.

In an embodiment of the above manufacturing method, optionally, providing the substrate formed with the first layer further includes:

and depositing a grid dielectric layer and a grid layer on the upper surface of the substrate of the peripheral area from bottom to top in sequence to form the first layer.

In an embodiment of the manufacturing method, optionally, the gate dielectric layer of the peripheral region and the gate dielectric layer of the storage region are formed in the same step.

In an embodiment of the manufacturing method, optionally, the gate layer of the peripheral region and the control gate layer of the storage region are formed in the same step.

In an embodiment of the manufacturing method, optionally, the gate layer of the peripheral region and the control gate layer of the storage region are polysilicon.

According to the manufacturing method of the semiconductor device provided by the invention, aiming at two short plates of the existing Cell LDD implantation process, the step of lightly doped drain ion implantation of a storage area is advanced, and on the premise of not changing the structure and design of the original device and not adjusting the existing ion implantation conditions, on one hand, the physical structure before implantation is more single, the possibility that the implanted ions are blocked by defects is reduced, on the other hand, the damage caused by ion implantation is repaired by means of the thermal budget of the subsequent process, and simultaneously, the ion diffusion is more uniform. Finally, the effect of improving the electrical uniformity of the storage unit is achieved, and the yield and the erasing performance of the flash memory storage unit are effectively improved. In addition, according to the manufacturing method of the semiconductor device provided by the invention, when ion implantation of the lightly doped drain is carried out on the storage region, a photoresist does not need to be additionally formed in the peripheral device region, so that a layer of photomask can be saved, and the manufacturing cost can be reduced.

Drawings

The above features and advantages of the present disclosure will be better understood upon reading the detailed description of embodiments of the disclosure in conjunction with the following drawings. In the drawings, components are not necessarily drawn to scale, and components having similar relative characteristics or features may have the same or similar reference numerals.

Fig. 1 shows a schematic diagram of a device structure after forming a control gate CG and a peripheral device gate PG in the prior art.

Fig. 2 is a schematic diagram illustrating a step of ion implantation of lightly doped drain to a memory region in the prior art.

Fig. 3 shows a schematic flow chart of a manufacturing method provided according to the present invention.

Fig. 4 shows a schematic structural diagram of the control gate of the memory region after etching according to the manufacturing method provided by the invention.

Fig. 5 is a schematic diagram illustrating a step of ion implantation of a lightly doped drain into a memory region according to a manufacturing method provided by the present invention.

Reference numerals

100 substrate

110 shallow trench isolation STI

200 gate dielectric layer

300 floating gate

400 control gate

500 peripheral device gate

520 Gate layer

600 photo resist

700 memory cell lightly doped drain ion CLDD

800 self-aligned source SAS

Detailed Description

The invention is described in detail below with reference to the figures and specific embodiments. It is noted that the aspects described below in connection with the figures and the specific embodiments are only exemplary and should not be construed as imposing any limitation on the scope of the present invention.

The present invention relates to a manufacturing process of a semiconductor device. According to the manufacturing method of the semiconductor device provided by the invention, aiming at two short plates of the existing Cell LDD implantation process, the step of lightly doped drain ion implantation of a storage area is advanced, and on the premise of not changing the structure and design of the original device and not adjusting the existing ion implantation conditions, on one hand, the physical structure before implantation is more single, the possibility that the implanted ions are blocked by defects is reduced, on the other hand, the damage caused by ion implantation is repaired by means of the thermal budget of the subsequent process, and simultaneously, the ion diffusion is more uniform. Finally, the effect of improving the electrical uniformity of the storage unit is achieved, and the yield and the erasing performance of the flash memory storage unit are effectively improved. In addition, according to the manufacturing method of the semiconductor device provided by the invention, when ion implantation of the lightly doped drain is carried out on the storage region, a photoresist does not need to be additionally formed in the peripheral device region, so that a layer of photomask can be saved, and the manufacturing cost can be reduced.

The following description is presented to enable any person skilled in the art to make and use the invention and is incorporated in the context of a particular application. Various modifications, as well as various uses in different applications will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the practice of the invention may not necessarily be limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Note that where used, the designations left, right, front, back, top, bottom, positive, negative, clockwise, and counterclockwise are used for convenience only and do not imply any particular fixed orientation. In fact, they are used to reflect the relative position and/or orientation between the various parts of the object.

The terms "over.," under., "" between., "(between)," and ". on.," as used herein refer to the relative position of this layer with respect to other layers. Likewise, for example, a layer deposited or placed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Further, a layer deposited or placed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in contact with the second layer. In addition, the relative position of one layer with respect to the other layers is provided (assuming deposition, modification and removal of the thin film operations with respect to the starting substrate without regard to the absolute orientation of the substrate).

As described above, in order to improve the problem of poor uniformity of ion implantation into the lightly doped drain of the memory cell of the flash memory in the prior art and improve the problem of poor electrical uniformity between memory cells, the present invention provides a method for manufacturing a semiconductor device, and fig. 3 shows a flow chart of the manufacturing method. As shown in fig. 3, the manufacturing method provided by the present invention specifically includes step S110: providing a substrate, wherein a gate structure of a storage transistor is formed on the substrate of a storage area, and a first layer used for forming the gate structure of the peripheral transistor is formed on the substrate of a peripheral area; step S120: performing ion implantation of a lightly doped drain on the upper part of the substrate of the storage region at two sides of the gate structure of the storage transistor by taking the first layer as a mask of the peripheral region; and step S130: and etching the first layer to form the gate structure of the peripheral transistor.

It can be seen that, according to the manufacturing method of the semiconductor device provided by the present invention, aiming at the problems existing in the existing Cell LDD implantation process, by advancing the step of lightly doped drain ion implantation in the storage region, on the premise of not changing the structure and design of the original device and not adjusting the existing ion implantation conditions, on one hand, the physical structure before implantation is more single, the possibility that the implanted ions are blocked by the defects is reduced, the electrical uniformity of the storage unit can be effectively improved, and the yield and the erasing performance of the flash memory storage unit can be effectively improved.

In addition, according to the manufacturing method of the semiconductor device provided by the invention, when ion implantation of the lightly doped drain is carried out on the storage region, a photoresist does not need to be additionally formed in the peripheral device region, so that a layer of photomask can be saved, and the manufacturing cost can be reduced.

It should be noted that, a person skilled in the art may adjust the relevant parameters of the lightly doped drain ion implantation according to the actual situation of the device, and the above-mentioned lightly doped drain ion implantation may be implemented by using the existing or future processes. The parameters and specific implementation manners related to the lightly doped drain ion implantation should not unduly limit the scope of the present invention.

In an embodiment, the manufacturing method provided by the present invention further includes: and carrying out gate reoxidation treatment on the gate structures of the memory transistor and the peripheral transistor. Through the gate reoxidation treatment, not only an oxide layer can be formed on the surface of the gate structure for protection, but also the implanted lightly doped drain ions can be subjected to heat treatment in the gate reoxidation treatment. By carrying out heat treatment on the lightly doped drain ions in the storage region in the gate reoxidation treatment, the diffusion uniformity of the lightly doped drain ions in the storage region can be improved without additionally increasing the thermal budget, and the damage caused by ion implantation of the lightly doped drain can be repaired.

It should be noted that, in the above embodiments, a person skilled in the art may use the existing or future semiconductor process to implement the gate reoxidation process, and the specific implementation manner during the gate reoxidation process should not unduly limit the scope of the present invention.

In another embodiment, the manufacturing method provided by the present invention further includes: and carrying out a self-aligned source electrode process on the upper part of the substrate of the storage region corresponding to the source electrode of the storage transistor so as to form the source electrode of the storage transistor.

In the above embodiment, the self-aligned source process may further include: self-aligned source etching, self-aligned source ion implantation and self-aligned source annealing. It will be appreciated that the common source of the memory transistor described above may be formed using existing or future self-aligned source processes by those skilled in the art. The implementation method of the specific steps of the self-aligned source process and the interrelationship between the various steps should not unduly limit the scope of the present invention.

Since the annealing step is included in the self-aligned source process, the implanted lightly doped drain ions may be heat treated by the self-aligned source process. By carrying out heat treatment on the ions of the lightly doped drain in the storage region in the step of forming the self-aligned common source, the diffusion uniformity of the ions of the lightly doped drain in the storage region can be improved without additionally increasing the thermal budget, and the damage caused by ion implantation of the lightly doped drain can be repaired.

Further, it is understood that in the present invention, the ion implantation of the lightly doped drain of the memory region is performed after the gate formation of the memory transistor of the memory region and before the gate formation of the associated peripheral device of the peripheral control region.

In another aspect of the manufacturing method provided by the invention, the method further comprises forming a gate of a memory transistor of the memory region and a gate of an associated peripheral device of the peripheral control region. Specifically, before the ion implantation of the lightly doped drain of the storage region is performed, the manufacturing method provided by the invention further comprises the step of forming a gate electrode of the storage transistor of the storage region.

Forming the gate of the memory transistor of the memory region further comprises: and forming a stacked gate layer on the upper surface of the substrate of the storage area, and etching the stacked gate layer to form a gate structure of the storage transistor.

The stacked gate layer specifically comprises a gate dielectric layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are stacked from bottom to top on the upper surface of the substrate. The gate dielectric layer may be formed of any conventional or future gate dielectric material, including but not limited to oxide or high-K dielectric material. The floating gate layer may be formed using polysilicon. The interlayer dielectric layer is an insulator and may include, but is not limited to, an ONO stack, i.e., an oxide-nitride-oxide stack. The control gate layer may be formed using polysilicon.

Forming a gate of an associated peripheral device of the peripheral control region further comprises: and forming a first layer for forming a grid electrode of the peripheral device on the upper surface of the substrate of the peripheral control area, and etching the first layer to form a grid electrode structure of the relevant peripheral device.

The first layer specifically includes a gate dielectric layer and a gate electrode layer stacked in this order from bottom to top on the upper surface of the substrate. It is understood that the gate dielectric layer may be formed of any existing or future gate dielectric material, including but not limited to oxide or high-K dielectric materials. The gate layer may be formed using polysilicon.

In one embodiment, it is understood that the memory transistors of the memory region and the associated peripheral devices of the peripheral control region are formed on the same substrate. The substrate may comprise an elemental semiconductor comprising silicon or germanium in a crystalline, polycrystalline or amorphous structure; a compound semiconductor including silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), and indium antimonide (indium antimonide); an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GalnP, and GalnAsP; any other suitable material, or combination of the foregoing.

In one embodiment, the gate dielectric layers of the memory region and the peripheral control region may be formed on the upper surface of the substrate of the memory region and the peripheral control region simultaneously. In addition, the control gate layer of the memory region and the gate layer of the peripheral control region may also be formed in the same step.

In the manufacturing method provided by the invention, the ion implantation of the lightly doped drain of the storage region is performed after the step of etching and forming the grid electrode of the storage transistor of the storage region and before the step of etching and forming the grid electrode of the peripheral device related to the peripheral control region. When ion implantation of the lightly doped drain of the storage region is performed, the first layer of the peripheral control region can be used as a barrier layer of the peripheral control region, so that a photoresist does not need to be additionally formed in the peripheral device region to be used as the barrier layer, a layer of photomask can be saved, and the manufacturing cost can be reduced.

Please refer to fig. 4 and 5 to understand the manufacturing method provided by the present invention. Fig. 4 shows a schematic structural diagram of the control gate of the memory region after etching according to the manufacturing method provided by the invention. As shown in fig. 4, a memory area a and a peripheral logic control area B are predefined on a substrate 100. The memory region a is used to form memory transistors, and the peripheral logic control region B is used to form various peripheral logic control transistors, as shown in fig. 4, including but not limited to high voltage P-type MOS transistor (HVPMOS), high voltage N-type MOS transistor (HVNMOS), low voltage P-type MOS transistor (LVPMOS), and low voltage N-type MOS transistor (LVNMOS). The structure of the memory transistor is illustrated in fig. 4 from the X-direction parallel to the gate of the memory transistor and the Y-direction exposing the cross section of the gate of the memory transistor, respectively.

As can be seen in fig. 4, a shallow trench isolation STI110 is also formed in the substrate 100 to define each memory cell and associated peripheral devices, and to electrically isolate each memory cell from each other and from each other peripheral device.

The upper surface of the substrate 100 of the memory area a and the peripheral logic control area B are formed with a gate dielectric layer 200. In one embodiment, the gate dielectric layer 200 of the memory region a and the peripheral logic control region B are formed in the same step.

The floating gate 300 of the memory transistor is formed on the upper surface of the gate dielectric layer 200 of the memory region a, the control gate 400 of the memory transistor is formed above the floating gate 300, and the floating gate 300 and the control gate 400 are isolated by an interlayer dielectric layer.

Gate dielectric layer 200 of peripheral logic control region B has a gate layer 520 formed on its upper surface to form the gate of the associated peripheral control device, and as described above, gate layer 520 and control gate layer 400 may be deposited in the same step. In one embodiment, the control gate 400 and the gate layer 520 of the storage region a may be made of polysilicon.

As can be seen in the Y direction of fig. 4, the stacked gate layers of the memory region have been etched, thereby forming the gate structure of the memory transistor. For the peripheral logic control region B, the gate layer 520 has not been etched, and the gates of the related peripheral devices are not formed.

Subsequently, the manufacturing method provided by the present invention performs ion implantation of lightly doped drain on the storage region a on the basis of fig. 4. As shown in fig. 5, after the memory cell gate etching and before the peripheral gate etching, a lightly doped drain implantation is performed in the memory region a using the gate layer 520 of the peripheral logic control region as a mask. Therefore, in the step of performing the lightly doped drain implantation of the memory region a, no extra photoresist is required to be formed, and the manufacturing cost can be reduced.

As shown in fig. 5, after the lightly doped drain implantation of the memory region a is performed, memory cell lightly doped drain ions CLDD700 are formed at an upper portion of the substrate 100 at both sides of the gate of the memory transistor of the memory region a.

After the lightly doped drain implantation of the memory region a is performed, the manufacturing method provided by the present invention further includes etching the gate layer 520 in the peripheral logic control region B to form various peripheral device gates 500 as shown in fig. 1 and 2.

In another embodiment, after the peripheral device gate 500 is formed by etching, the manufacturing method provided by the present invention further includes: and carrying out gate reoxidation treatment on the gate structures of the memory transistor and the peripheral transistor. Through the gate reoxidation treatment, not only an oxide layer can be formed on the surface of the gate structure for protection, but also the implanted lightly doped drain ions can be subjected to heat treatment in the gate reoxidation treatment. By carrying out heat treatment on the lightly doped drain ions in the storage region in the gate reoxidation treatment, the diffusion uniformity of the lightly doped drain ions in the storage region can be improved without additionally increasing the thermal budget, and the damage caused by ion implantation of the lightly doped drain can be repaired.

It should be noted that, in the above embodiments, a person skilled in the art may use the existing or future semiconductor process to implement the gate reoxidation process, and the specific implementation manner during the gate reoxidation process should not unduly limit the scope of the present invention.

In another embodiment, the manufacturing method provided by the present invention further includes: and carrying out a self-aligned source electrode process on the upper part of the substrate of the storage region corresponding to the source electrode of the storage transistor so as to form the source electrode of the storage transistor.

In the above embodiment, the self-aligned source process may further include: self-aligned source etching, self-aligned source ion implantation and self-aligned source annealing. It will be appreciated that the common source of the memory transistor described above may be formed using existing or future self-aligned source processes by those skilled in the art. The implementation method of the specific steps of the self-aligned source process and the interrelationship between the various steps should not unduly limit the scope of the present invention.

Since the annealing step is included in the self-aligned source process, the implanted lightly doped drain ions may be heat treated by the self-aligned source process. By carrying out heat treatment on the ions of the lightly doped drain in the storage region in the step of forming the self-aligned common source, the diffusion uniformity of the ions of the lightly doped drain in the storage region can be improved without additionally increasing the thermal budget, and the damage caused by ion implantation of the lightly doped drain can be repaired.

It is to be understood that since the lightly doped drain ion implantation of the storage region a has been completed in the previous process, no additional lightly doped drain ion implantation of the storage region a is performed in the self-aligned common source SAS formed by the self-aligned source process described above.

According to the manufacturing method of the semiconductor device provided by the invention, aiming at two short plates of the existing Cell LDD implantation process, the step of lightly doped drain ion implantation of a storage area is advanced, and on the premise of not changing the structure and design of the original device and not adjusting the existing ion implantation conditions, on one hand, the physical structure before implantation is more single, the possibility that the implanted ions are blocked by defects is reduced, on the other hand, the damage caused by ion implantation is repaired by means of the thermal budget of the subsequent process, and simultaneously, the ion diffusion is more uniform. Finally, the effect of improving the electrical uniformity of the storage unit is achieved, and the yield and the erasing performance of the flash memory storage unit are effectively improved. In addition, according to the manufacturing method of the semiconductor device provided by the invention, when ion implantation of the lightly doped drain is carried out on the storage region, a photoresist does not need to be additionally formed in the peripheral device region, so that a layer of photomask can be saved, and the manufacturing cost can be reduced. Although the present disclosure has been described with respect to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Reference in the specification to one embodiment or an embodiment is intended to include within at least one embodiment of a circuit or method a particular feature, structure, or characteristic described in connection with the embodiment. The appearances of the phrase one embodiment in various places in the specification are not necessarily all referring to the same embodiment.