阅读说明：本技术 一种阵列基板及其制备方法以及显示面板 (Array substrate, preparation method thereof and display panel ) 是由 张明 杨杰 于 2020-05-09 设计创作，主要内容包括：本揭示提供一种阵列基板及其制备方法以及显示面板。阵列基板的显示区和屏下摄像头区的薄膜晶体管同时制备,且显示区的多条第一信号线和薄膜晶体管在同一工艺下制备。屏下摄像头区的多条第二信号线采用银纤维材料制备在像素电极层,并通过过孔与显示区的多条第一信号线连接。以提高屏下摄像头区穿透度的同时,提升屏下摄像头区信号线的机械可靠性。(The disclosure provides an array substrate, a preparation method thereof and a display panel. The thin film transistors in the display area of the array substrate and the camera area under the screen are simultaneously prepared, and the plurality of first signal lines and the thin film transistors in the display area are prepared in the same process. A plurality of second signal wires of the camera area under the screen are prepared on the pixel electrode layer by adopting silver fiber materials and are connected with a plurality of first signal wires of the display area through via holes. The mechanical reliability of the signal line of the camera area under the screen is improved while the penetration degree of the camera area under the screen is improved.)

1. The utility model provides an array substrate, its characterized in that divides into display area and under-screen camera area, under-screen camera area is located in the display area, wherein array substrate includes:

a substrate base plate;

the first thin film transistor is arranged on the substrate base plate and is positioned in the display area;

a plurality of first signal lines disposed in the display area;

the second thin film transistor is arranged on the same layer as the first thin film transistor and is positioned in the camera area under the screen;

the planarization layer is arranged on the first thin film transistor and the second thin film transistor, and a plurality of first through holes and a plurality of second through holes are formed in the planarization layer;

a plurality of pixel electrodes disposed on the planarization layer; and

the plurality of second signal lines are arranged on the same layer as the pixel electrodes and are positioned in the under-screen camera area;

the pixel electrode of the display area is connected with the first thin film transistor through the first through hole, and the pixel electrode of the under-screen camera area is connected with the second thin film transistor through the other first through hole; the plurality of second signal lines are respectively connected with the plurality of corresponding first signal lines through the plurality of second via holes.

2. The array substrate of claim 1, wherein the material of the second signal lines comprises silver fibers.

3. The array substrate of claim 2, wherein a film thickness of the second signal lines is greater than 100 nm.

4. The array substrate of claim 3, further comprising a pixel defining layer disposed on the planarization layer and the second signal lines, wherein a film thickness of the second signal lines is smaller than a film thickness of the pixel defining layer.

5. The array substrate of claim 1, wherein the first signal lines and the second signal lines each comprise a gate scan line and a data line.

6. The preparation method of the array substrate is characterized by comprising the following steps:

step S10, providing a substrate, dividing the substrate into a display area and a camera area under a screen, and fabricating a first thin film transistor and a second thin film transistor on the substrate, wherein the first thin film transistor is located in the display area, the second thin film transistor is located in the camera area under the screen, and a plurality of first signal lines are fabricated while the first thin film transistor is fabricated in the display area;

step S20, preparing a planarization layer on the first thin film transistor and the second thin film transistor, and disposing a plurality of first via holes and a plurality of second via holes on the planarization layer;

step S30, preparing a plurality of pixel electrodes on the planarization layer, wherein the pixel electrodes are respectively connected to the first thin film transistor and the second thin film transistor through the first via holes; and

step S40, preparing a plurality of second signal lines on the planarization layer where the pixel electrodes are not disposed in the under-screen camera area, where the plurality of second signal lines are connected to the plurality of corresponding first signal lines through the plurality of second via holes, respectively.

7. The method of claim 6, wherein the step of preparing the plurality of second signal lines in step S40 comprises the steps of:

depositing an entire silver thin film on the plurality of pixel electrodes and the planarization layer;

performing transparentization treatment on the silver film to form a transparent silver fiber film layer; and

and carrying out a yellow light process on the transparent silver fiber film layer to form the plurality of second signal lines.

8. The method for preparing the array substrate of claim 7, wherein the thickness of the silver fiber film layer is greater than 100 nanometers.

9. The method for preparing the array substrate according to claim 8, further comprising the steps of:

step S50, preparing a pixel defining layer on the planarization layer and the plurality of second signal lines, wherein the film thickness of the plurality of second signal lines is smaller than the film thickness of the pixel defining layer.

10. A display panel comprising the array substrate according to any one of claims 1 to 5.

Technical Field

The disclosure relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.

Background

With the wide development and deep application of OLED (Organic Light emitting diode) technology, the pursuit of a high-screen-ratio (even full-screen) Display screen with better visual experience has become one of the trends of the development of current Display technology. In order to realize full-screen display, the space occupied by the camera in the screen is particularly important. The emergence of the Under-screen Camera (CUP) technology has greatly promoted the screen occupation ratio of display screens. The screen camera technology does not damage the integrity of the screen while realizing full screen display. And the camera area under the screen can also display, the self-luminescence of the OLED screen is mainly utilized, and the characteristic of transparency can be made, and the imaging is realized through gaps among pixel points of the OLED screen. In the area of the front camera, the display panel is a small transparent screen, and when the camera does not take a picture, the display panel can normally display the content of the screen; when photographed, it became a transparent film. Therefore, it is important to improve the penetration of the under-screen camera area. The commonly used method for improving the penetration of the area of the camera under the screen at present comprises the following steps: thinning the flexible substrate, thinning the polaroid, reducing the number of pixels, avoiding and laminating the polaroid and the like. However, the complicated process easily causes brittle wire breakage, which degrades product reliability. Metals or metal oxides used in a common Thin Film Transistor (TFT) process, including molybdenum, titanium, aluminum, silver, Indium Tin Oxide (ITO), etc., have the disadvantages of low transmittance, brittle Film quality, and poor flexibility.

Therefore, the problem that the existing metal wiring in the camera area under the screen cannot meet the requirements of high penetration and good flexibility at the same time needs to be solved.

Disclosure of Invention

The invention provides an array substrate, a preparation method thereof and a display panel, which are used for solving the technical problem that metal wiring in the area of a traditional under-screen camera cannot meet high penetration and better flexibility at the same time.

In order to solve the above problems, the technical solution provided by the present disclosure is as follows:

the embodiment of the disclosure provides an array substrate, which is divided into a display area and a camera area under a screen, wherein the camera area under the screen is located in the display area, and the array substrate comprises a substrate, a first thin film transistor, a plurality of first signal lines, a second thin film transistor, a planarization layer, a plurality of pixel electrodes and a plurality of second signal lines. The first thin film transistor is arranged on the substrate base plate and is positioned in the display area. The plurality of first signal lines are arranged in the display area. The second thin film transistor is arranged on the same layer as the first thin film transistor and is positioned in the camera area under the screen. The planarization layer is arranged on the first thin film transistor and the second thin film transistor, and a plurality of first via holes and a plurality of second via holes are formed in the planarization layer. The pixel electrodes are arranged on the planarization layer. The plurality of second signal lines are arranged on the same layer as the pixel electrodes and are positioned in the under-screen camera area. The pixel electrode of the display area is connected with the first thin film transistor through the first through hole, and the pixel electrode of the under-screen camera area is connected with the second thin film transistor through the other first through hole; the plurality of second signal lines are respectively connected with the plurality of corresponding first signal lines through the plurality of second via holes.

In the array substrate provided by the embodiment of the present disclosure, a material of the plurality of second signal lines includes silver fibers.

In the array substrate provided by the embodiment of the present disclosure, the film thickness of the plurality of second signal lines is greater than 100 nanometers.

In the array substrate provided by the embodiment of the present disclosure, the array substrate further includes a pixel defining layer, the pixel defining layer is disposed on the planarization layer and the plurality of second signal lines, and a film thickness of the plurality of second signal lines is smaller than a film thickness of the pixel defining layer.

In the array substrate provided by the embodiment of the present disclosure, each of the plurality of first signal lines and the plurality of second signal lines includes a gate scan line and a data line.

The embodiment of the disclosure also provides a preparation method of the array substrate, which includes the following steps: step S10, providing a substrate, dividing the substrate into a display area and a camera area under the screen, and fabricating a first thin film transistor and a second thin film transistor on the substrate, where the first thin film transistor is located in the display area, the second thin film transistor is located in the camera area under the screen, and a plurality of first signal lines are fabricated while fabricating the first thin film transistor in the display area. Step S20, preparing a planarization layer on the first thin film transistor and the second thin film transistor, and disposing a plurality of first via holes and a plurality of second via holes on the planarization layer. Step S30, preparing a plurality of pixel electrodes on the planarization layer, where the pixel electrodes are respectively connected to the first thin film transistor and the second thin film transistor through the first via holes. Step S40, preparing a plurality of second signal lines on the planarization layer where the pixel electrodes are not disposed in the under-screen camera area, where the plurality of second signal lines are connected to the plurality of corresponding first signal lines through the plurality of second via holes, respectively.

In the array substrate manufacturing method provided by the embodiment of the present disclosure, in step S40, the manufacturing the plurality of second signal lines includes: depositing an entire silver thin film on the plurality of pixel electrodes and the planarization layer. And carrying out transparentizing treatment on the silver film to form a transparent silver fiber film layer. And carrying out a yellow light process on the transparent silver fiber film layer to form the plurality of second signal lines.

In the preparation method of the array substrate provided by the embodiment of the disclosure, the thickness of the silver fiber film layer is greater than 100 nanometers.

In the method for preparing the array substrate provided by the embodiment of the disclosure, the method further includes the following steps: step S50, preparing a pixel defining layer on the planarization layer and the plurality of second signal lines, wherein the film thickness of the plurality of second signal lines is smaller than the film thickness of the pixel defining layer.

The embodiment of the disclosure provides a display panel, which includes the array substrate of one of the foregoing embodiments.

The beneficial effects of this revelation do: in the array substrate, the preparation method thereof and the display panel provided by the disclosure, the plurality of second signal lines in the under-screen camera area are prepared by using silver fiber materials and are connected with the plurality of first signal lines in the display area through the via holes. The silver fiber material has the high conductivity, high ductility characteristics of silver and high penetration. Adopt the signal line in camera district under the silver-colored fibre preparation screen, improved the penetrability in camera district under the screen, and then promoted the effect of shooing and the user experience of leading camera. Meanwhile, the high ductility of the silver fibers improves the mechanical reliability of the signal lines of the camera area under the screen, and the reliability of the product is improved.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic bottom view of an array substrate according to an embodiment of the disclosure;

FIG. 2 is a schematic side view of a film structure of an array substrate according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram illustrating a side view of a film structure of a first TFT according to an embodiment of the disclosure;

fig. 4 is a schematic bottom view of a second signal line routing path according to an embodiment of the disclosure;

fig. 5 to 10 are schematic views illustrating structures of films manufactured in various steps of a method for manufacturing an array substrate according to an embodiment of the disclosure.

Detailed Description

The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in this disclosure, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure. In the drawings, elements having similar structures are denoted by the same reference numerals.

In an embodiment, an array substrate 100 is provided, as shown in fig. 1, which is divided into a display area AA and a sub-screen camera area CUP, where the sub-screen camera area CUP is located in the display area AA. As shown in fig. 2, the array substrate 100 includes a substrate 10, a first thin film transistor 20, a plurality of first signal lines 222, a second thin film transistor 30, a planarization layer 40, a plurality of pixel electrodes 50, and a plurality of second signal lines 60. The first thin film transistor 20 is disposed on the substrate 10 and located in the display area AA. The plurality of first signal lines 222 are disposed in the display area AA and are fabricated simultaneously with the first thin film transistors 20. The second thin film transistor 30 is disposed on the same layer as the first thin film transistor 20, and is located in the under-screen camera area CUP. The planarization layer 40 is disposed on the first thin film transistor 20 and the second thin film transistor 30, and a plurality of first via holes 41 and a plurality of second via holes 42 are disposed on the planarization layer 40. The plurality of pixel electrodes 50 are disposed on the planarization layer 40. The plurality of second signal lines 60 are disposed on the same layer as the pixel electrodes 50, and are located in the under-screen camera area CUP. The pixel electrode 50 of the display area AA is connected to the first thin film transistor 20 through the first via hole (not shown), and the pixel electrode 50 of the under-screen camera area CUP is connected to the second thin film transistor 30 through another first via hole 41; the second signal line 60 is connected to the corresponding first signal line 222 through the second via 42.

Specifically, the base substrate 10 includes a glass substrate, a Polyimide (PI) flexible substrate, or the like.

Further, the first thin film transistor 20 and the second thin film transistor 30 each include an active layer, a gate layer, and a source/drain layer. Taking the first thin film transistor 20 as an example, as shown in fig. 3, the active layer 21 is disposed on the substrate 10, the gate layer 22 is disposed above the active layer 21, and the source/drain layer 23 is disposed above the gate layer 22. The active layer 21 includes a doped region 211 and a channel region 212. The gate layer 22 includes a gate electrode 221 and a first signal line 222. The source-drain layer 23 includes a source electrode 231 and a drain electrode 232, and the source electrode 231 and the drain electrode 232 are connected to the doped region 211 of the active layer 21. Certainly, the array substrate further includes a barrier layer and a buffer layer disposed between the substrate and the thin film transistor, and an insulating layer between the active layer, the gate layer, and the source/drain layer of the thin film transistor, which will not be described in detail herein.

Note that the thin film transistor of the present disclosure is not limited to the top-gate single-gate structure shown in fig. 2 or 3, and the thin film transistor of the present disclosure may also be a bottom-gate structure or a double-gate structure.

Further, when the first thin film transistor 20 of the display area AA is manufactured, the plurality of first signal lines 222 are simultaneously manufactured. The plurality of first signal lines 222 include gate scan lines, data lines, and the like, and the first signal lines 222 shown in fig. 2 and 3 are the gate scan lines. And the grid scanning line and the grid are prepared at the same layer and are used for driving the thin film transistor. And the data line and the source electrode and the drain electrode of the source and drain electrode layers are prepared in the same layer and used for providing data signals for the thin film transistor.

Specifically, the metal material used for the first thin film transistor 20, the second thin film transistor 30, and the plurality of first signal lines 222 includes copper, aluminum, molybdenum, titanium, or the like, or an alloy thereof.

Further, the pixel density (the number of pixels per unit area) of the under-screen camera area CUP of the array substrate of the present disclosure may be the same as the pixel density of the display area AA.

Further, in conjunction with fig. 2 and 3, a planarization layer 40 is formed on the first thin film transistor 20 and the second thin film transistor 30. And performing a yellow light process on the planarization layer 40 to form a plurality of first via holes 41 and a plurality of second via holes 42. The plurality of first via holes 41 penetrate the planarization layer 40 to expose the source or drain of the first thin film transistor 20 and the source or drain of the second thin film transistor 30. The second via holes 42 penetrate through the planarization layer 40 and a portion of the insulating layer of the first thin film transistor 20 to expose a portion of the first signal lines 222.

Further, a plurality of pixel electrodes 50 are prepared on the planarization layer 40. The plurality of pixel electrodes 50 are connected to the source or drain of the first thin film transistor 20 and the source or drain of the second thin film transistor 30 through the plurality of first via holes 41, respectively.

Specifically, the material of the pixel electrode includes a transparent conductive electrode material such as indium tin oxide.

Further, a plurality of second signal lines 60 are prepared on the planarization layer 40 where the pixel electrodes 50 are not disposed in the under-screen camera area CUP. The plurality of second signal lines 60 are respectively connected to the plurality of corresponding first signal lines 222 through the plurality of second vias 42, as shown in fig. 2 by way of example, which shows a portion of the second signal lines 60 and the first signal lines 222.

Specifically, the material of the second signal lines 60 includes a transparent flexible conductive material such as silver fiber.

Specifically, the plurality of second signal lines also include gate scan lines, data lines, and the like. The plurality of second signal lines are respectively connected with the plurality of corresponding first signal lines through the second via holes, that is, the gate scan line of the under-screen camera area CUP is connected with the gate scan line of the display area AA through the second via holes (as shown in fig. 2), and the data line of the under-screen camera area CUP is connected with the data line of the display area AA through the second via holes (not shown in the figure).

Specifically, the plurality of second signal lines 60 and the pixel electrode 50 of the under-screen camera area CUP adopt an avoidance design, that is, the plurality of second signal lines 60 and the pixel electrode 50 are not in contact.

Further, the line widths of the plurality of second signal lines may be the same as the line widths of the corresponding first signal lines. And the routing paths of the plurality of second signal lines are not limited to those exemplarily shown in fig. 4 of the present disclosure. In fig. 4, the plurality of second signal lines 60 of the off-screen camera area CUP pass through the gap between two adjacent rows of sub-pixels 110, and are connected to the plurality of first signal lines 222 of the display area AA through the second via holes 42.

Further, the thickness of the plurality of second signal lines 60 is greater than 100 nm to reduce contact resistance and horizontal transfer resistance, thereby reducing voltage drop.

Further, the array substrate 100 further includes a pixel defining layer 70, the pixel defining layer 70 is disposed on the planarization layer 40 and the plurality of second signal lines 60, and a film thickness of the plurality of second signal lines 60 is smaller than a film thickness of the pixel defining layer 70.

In this embodiment, the plurality of second signal lines of the under-screen camera area are prepared by using silver fibers and connected to the plurality of first signal lines of the display area through via holes. The penetration degree of the camera area under the screen and the mechanical reliability of the signal line are improved while the display of the camera area under the screen is realized.

In one embodiment, a method for manufacturing an array substrate is provided, which includes the steps of:

step S10, providing a substrate 10, dividing the substrate 10 into a display area AA and a camera area CUP under the screen, fabricating a first thin film transistor 20 and a second thin film transistor 30 on the substrate 10, where the first thin film transistor 20 is located in the display area AA, the second thin film transistor 30 is located in the camera area CUP under the screen, and fabricating a plurality of first signal lines 222 at the same time of fabricating the first thin film transistor 20 in the display area AA, as shown in fig. 5.

Specifically, the base substrate 10 includes a glass substrate, a polyimide flexible substrate, or the like.

Furthermore, according to the actual installation position requirement of the product camera, a display area AA and a camera area CUP under the screen are defined on the substrate base plate, so that the subsequent process is facilitated.

Further, a barrier layer 11 and a buffer layer 12 are prepared on the substrate base plate 10, and the buffer layer 12 is disposed on the barrier layer 11.

Further, the first thin film transistor 20 and the second thin film transistor 30 are prepared on the buffer layer 12. The first thin film transistor 20 is located in the display area AA, and the second thin film transistor 30 is located in the under-screen camera area CUP. The first thin film transistor 20 and the second thin film transistor 30 each include an active layer, a gate layer, a source drain layer, and an insulating layer between the active layer, the gate layer, and the source drain layer.

Further, a plurality of first signal lines 222 are formed at the same time when the first thin film transistors 30 are formed in the display area AA.

Specifically, taking the preparation of the first thin film transistor as an example, as shown in fig. 6, an active layer 21 is prepared on the buffer layer 12, and both sides of the active layer 21 are ion-doped to form doped regions 211, and a channel region 212 of the active layer 21 is located between the doped regions 211 at both ends.

Further, a gate insulating layer 24 is formed on the active layer 21 and the buffer layer 12, and a gate electrode layer 22 is formed on the gate insulating layer 24.

Further, a yellow light process is performed on the gate layer 22 to form other signal lines such as a gate 221 and a plurality of first signal lines 222 in the display area AA, where the first signal lines 222 are gate scan lines as shown in fig. 6. And forming a grid in the camera area under the screen.

Further, an interlayer insulating layer 25 is formed on the gate electrode layer 22 and the gate insulating layer 24, and a source drain layer 23 is formed on the interlayer insulating layer 25.

Further, the source/drain layer 23 is subjected to a yellow process to form other signal lines such as a source 231, a drain 232, and a data line (not shown) in the display region. The source electrode 231 and the drain electrode 232 are connected to the doped region 211 of the active layer 21 through vias, respectively. And forming a source electrode and a drain electrode in the camera area under the screen, wherein the source electrode and the drain electrode are respectively connected with the doped area of the active layer through via holes.

Specifically, the plurality of first signal lines include other signal lines such as a gate scan line and a data line.

Step S20 is to prepare a planarization layer 40 on the first thin film transistor 20 and the second thin film transistor 30, and to dispose a plurality of first via holes 41 and a plurality of second via holes 42 on the planarization layer 40, as shown in fig. 7.

Specifically, a yellow light process is performed on the planarization layer 40 to form a plurality of first vias 41 and a plurality of second vias 42.

Step S30, preparing a plurality of pixel electrodes 50 on the planarization layer 40, where the plurality of pixel electrodes 50 are respectively connected to the first thin film transistor 20 and the second thin film transistor 30 through the plurality of first vias 41, as shown in fig. 8.

Specifically, the pixel electrode 50 in the display area AA is connected to the source or the drain of the first thin film transistor 20 through the first via hole (not shown in fig. 8). The pixel electrode 50 of the under-screen camera area CUP is connected to the source or the drain of the second thin film transistor 30 through another first via hole 41.

Step S40, preparing a plurality of second signal lines 60 on the planarization layer 40 where the pixel electrode 50 is not disposed in the under-screen camera area CUP, where the plurality of second signal lines 60 are respectively connected to the plurality of corresponding first signal lines 222 through the plurality of second via holes 42, as shown in fig. 9.

Specifically, a whole silver thin film is deposited on the plurality of pixel electrodes and the planarization layer.

Further, the silver film is subjected to transparentization treatment to form a transparent silver fiber film layer.

Specifically, the polystyrene fiber is prepared on the silver film by adopting an electrostatic spinning process. The silver thin film not covered with the polystyrene fiber was subjected to plasma treatment using oxygen, and then wet etching was performed using hydrogen peroxide. Finally, removing the polystyrene fiber to form a transparent silver fiber film layer. The silver fiber film layer has high transmittance and better ductility.

Further, a yellow light process is carried out on the transparent silver fiber film layer to form the plurality of second signal lines.

Specifically, the plurality of second signal lines 60 also include gate scan lines, data lines, and the like. The plurality of second signal lines are respectively connected with the plurality of corresponding first signal lines through the second through holes, namely, the grid scanning lines of the camera area under the screen are connected with the grid scanning lines of the display area through the second through holes, and the data lines of the camera area under the screen are connected with the data lines of the display area through the second through holes.

Specifically, the plurality of second signal lines and the pixel electrodes of the under-screen camera area are in an avoidance design, that is, the plurality of second signal lines and the pixel electrodes are not in contact.

Further, the line widths of the plurality of second signal lines may be the same as the line widths of the corresponding first signal lines.

Further, the thickness of the second signal lines is larger than 100 nanometers, so that contact resistance and horizontal transmission resistance are reduced, and voltage drop is reduced.

Step S50 is to prepare a pixel defining layer 70 on the planarization layer 40 and the plurality of second signal lines 60, wherein the film thickness of the plurality of second signal lines 60 is smaller than the film thickness of the pixel defining layer 70, as shown in fig. 10.

Specifically, a pixel defining layer 70 is formed on the planarization layer 40 and the plurality of second signal lines 60 to expose the plurality of pixel electrodes 50. Meanwhile, the thickness of the pixel defining layer 70 is greater than that of the second signal lines 60, so as to cover the second signal lines 60.

In one embodiment, a display panel is provided, which includes the array substrate of the above embodiments.

Specifically, taking a top-emitting OLED display panel as an example, when a pixel electrode of an array substrate is prepared, a total-reflection type pixel electrode is prepared, and a semi-reflection and semi-transmission cathode is matched, so that the light utilization rate of light emission of the OLED can be improved.

According to the above embodiments:

the invention provides an array substrate, a preparation method thereof and a display panel. A plurality of second signal wires of the camera area under the screen are prepared on the pixel electrode layer by adopting silver fiber materials and are connected with a plurality of first signal wires of the display area through via holes. The silver fiber material has the high conductivity, high ductility characteristics of silver and high penetration. Adopt the signal line in camera district under the silver-colored fibre preparation screen, improved the penetrability in camera district under the screen, and then promoted the effect of shooing and the user experience of leading camera. Meanwhile, the high ductility of the silver fibers improves the mechanical reliability of the signal lines of the camera area under the screen, and the reliability of the product is improved.

In summary, although the present disclosure has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present disclosure, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so that the scope of the present disclosure is defined by the appended claims.