阅读说明：本技术 一种具有内嵌肖特基二极管的rc-ligbt器件 (RC-L IGBT device with embedded Schottky diode ) 是由 易波 赵青 蔺佳 杨瑞丰 侯云如 黄东 于 2020-03-02 设计创作，主要内容包括：本发明属于功率半导体技术领域,涉及高压横向半导体器件,具体为一种具有内嵌肖特基二极管的RC-LIGBT器件。本发明中,通过在集电极一侧引入N型欧姆接触区、浮空电极以及P型肖特基二极管,在反向工作状态下形成由两个串联二极管组成的载流子流通路径,使得器件具有反向导通的能力；同时,当器件工作在正向状态时,P型肖特基二极管不会开启,从而消除了电压折回现象。更重要的是,本发明在实现反向导通和消除电压折回现象的同时缩短了器件的长度,从而大幅度的提升了器件的性能：增强了器件的反向恢复特性、使得器件具有更短的反向恢时间,减小了器件的导通压降、优化了IGBT器件导通压降和关断损耗之间的矛盾关系。(The invention belongs to the technical field of power semiconductors, and relates to a high-voltage transverse semiconductor device, in particular to an RC-L IGBT device with an embedded Schottky diode, wherein an N-type ohmic contact region, a floating electrode and a P-type Schottky diode are introduced at one side of a collector, and a carrier flow path consisting of two diodes connected in series is formed in a reverse working state, so that the device has reverse conduction capability, and meanwhile, when the device works in a forward state, the P-type Schottky diode is not turned on, so that a voltage folding-back phenomenon is eliminated.)

1. An RC-L IGBT device with a built-in schottky diode, comprising:

the semiconductor device comprises a semiconductor substrate 1, a buried oxide layer region 2 located above the semiconductor substrate and a semiconductor layer located on the buried oxide layer;

the semiconductor layer includes: the semiconductor device comprises a P-type semiconductor base region 4, a gate region, a surface voltage-withstanding region 3, an N-type semiconductor buffer region 12, a P-type collector region 18 and a series diode region, wherein the P-type semiconductor base region 4 and the gate region are positioned on one side of a semiconductor layer, the N-type semiconductor buffer region 12 is positioned on the other side of the semiconductor layer, the surface voltage-withstanding region 3 is positioned between the P-type semiconductor base region 4 and the N-type semiconductor buffer region 12, and the surface voltage-withstanding region 3 is covered with field oxide 20;

a P-type buried layer region 5, a heavily doped P-type semiconductor region 6 and a heavily doped N-type semiconductor region 7 are arranged in the P-type semiconductor base region 4, and the heavily doped N-type semiconductor region 7 and the heavily doped P-type semiconductor region 6 are covered with emitter metal 8;

a P-type collector region 18 and a series diode region are arranged in the N-type semiconductor buffer region 12; the P-type collector region 18 is covered with a collector metal 17; the series diode region comprises an N-type ohmic contact region 13, a P-type ohmic contact region 14 and a P-type semiconductor region 16 which are adjacent in sequence, the N-type ohmic contact region 13 and the P-type ohmic contact region 14 are in short circuit through a floating electrode 15, a collector metal 17 covers the P-type semiconductor region 16, and the P-type ohmic contact region 14, the P-type semiconductor region 16 and the collector metal 17 form a Schottky diode.

2. An RC-L IGBT device with embedded schottky diode according to claim 1, characterized in that an isolation trench 19 is further provided between the P-type collector region 18 and the N-type ohmic contact region 13, the isolation trench being made of silicon dioxide filling or of polysilicon filled with silicon dioxide.

3. The RC-L IGBT device with embedded Schottky diode according to claim 1, wherein the gate region is a planar gate region, is positioned on the P-type semiconductor base region 4 and covers a part of the heavily doped N-type semiconductor region 7 and a part of the surface voltage-resistant region 3, and the planar gate region is composed of a gate dielectric layer 11, an N-type polysilicon gate region 10 and a gate metal 9 which are sequentially arranged from bottom to top.

Technical Field

The invention belongs to the technical field of power semiconductors, relates to a high-voltage transverse semiconductor device, and particularly relates to a novel RC-L IGBT device with an embedded Schottky diode.

Background

Miniaturization and integration of power electronic systems are important research directions of power semiconductor devices. The intelligent Power Integrated Circuit (SPIC) or the High Voltage Integrated Circuit (HVIC) integrates low voltage circuits such as protection, control, detection, drive and the like and High voltage Power devices on the same chip, so that the system volume is reduced, and the system reliability is improved; meanwhile, in a working occasion with higher frequency, the requirement of the buffering and protecting circuit can be obviously reduced due to the reduction of the inductance of the lead wire of the system.

A lateral Insulated-Gate Bipolar Transistor (L) is one of important power devices of an SPIC (passive-active-Transistor) and an HVIC (high voltage integrated circuit), a L IGBT based on an SOI (silicon on insulator) technology is widely applied due to excellent isolation characteristics, and as a Bipolar power device, the L IGBT has the characteristics of high input impedance of an MOSFET (metal-oxide-semiconductor field effect Transistor) and high current density of the BJT (Bipolar junction Transistor). A large number of unbalanced electron-hole pairs gathered in a drift region during conduction enhance the conductance modulation effect of the device, so that the device has lower conduction voltage drop, however, the existence of a large number of unbalanced carriers increases the carrier extraction time and the Turn-off loss of the device during Turn-off, so the Turn-off loss (Turn-off: E-Bipolar Transistor) of the device is optimized_off) And an On-state voltage drop (On-state voltage drop: v_on) On the other hand, metal and semiconductor contacts can form ohmic contacts and Schottky contacts, a Schottky Barrier Diode (SBD) forms Schottky contacts through the metal and the semiconductor, the Schottky diode has unidirectional conduction characteristic, the N-type Schottky diode is conducted when forward voltage is applied between the metal and the N-type base region, and the metal and the P-type Schottky diode are conducted when forward voltage is applied between the metal and the N-type base regionWhen a negative voltage is applied between the regions, the P-type Schottky diode is conducted.

As shown in FIG. 7, the traditional RC-L IGBT structure is that J.H.Chul et al in the article of A fast-switching SOI SA-L IGBT with out NDR region in 2000, electrons in a drift region can be rapidly extracted by a newly introduced N + collector in the turn-off process of the device with the structure, so that the turn-off time and the turn-off loss are obviously reduced, but the introduction of the N + collector not only can cause the hole injection efficiency of an anode to be reduced, but also can cause a P +/N type buffer layer to start to be conducted at a higher Voltage, so that the device is converted from a unipolar conduction mode to a conduction mode, the on-resistance of the device is increased, and the turn-off Voltage characteristic curve (delta Voltage) of a bipolar type conduction mode is caused, and the turn-off Voltage characteristic curve (delta Voltage V) of the device is folded back Voltage_SB) For the conventional structure RC-L IGBT as shown in FIG. 7, when the distance between the P + collector and the N + collector is increased (L)_B) Therefore, how to solve the voltage folding-back effect is one of the key points of the RC-L IGBT device design.

Disclosure of Invention

The invention aims to solve the technical problems and provide an RC-L IGBT device with a built-in Schottky diode, and the device can eliminate the voltage folding phenomenon and simultaneously enable the device to have better compromise relationship between turn-off loss and turn-on voltage drop.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

an RC-L IGBT device with elimination of voltage foldback phenomenon, comprising:

the semiconductor device comprises a semiconductor substrate 1, a buried oxide layer region 2 located above the semiconductor substrate and a semiconductor layer located on the buried oxide layer;

the semiconductor layer includes: the semiconductor device comprises a P-type semiconductor base region 4, a gate region, a surface voltage-withstanding region 3, an N-type semiconductor buffer region 12, a P-type collector region 18 and a series diode region, wherein the P-type semiconductor base region 4 and the gate region are positioned on one side of a semiconductor layer, the N-type semiconductor buffer region 12 is positioned on the other side of the semiconductor layer, the surface voltage-withstanding region 3 is positioned between the P-type semiconductor base region 4 and the N-type semiconductor buffer region 12, and the surface voltage-withstanding region 3 is covered with field oxide 20;

a P-type buried layer region 5, a heavily doped P-type semiconductor region 6 and a heavily doped N-type semiconductor region 7 are arranged in the P-type semiconductor base region 4, and the heavily doped N-type semiconductor region 7 and the heavily doped P-type semiconductor region 6 are covered with emitter metal 8;

a P-type collector region 18 and a series diode region are arranged in the N-type semiconductor buffer region 12; the P-type collector region 18 is covered with a collector metal 17; the series diode region comprises an N-type ohmic contact region 13, a P-type ohmic contact region 14 and a P-type semiconductor region 16 which are adjacent in sequence, the N-type ohmic contact region 13 and the P-type ohmic contact region 14 are in short circuit through a floating electrode 15, a collector metal 17 covers the P-type semiconductor region 16, and the P-type ohmic contact region 14, the P-type semiconductor region 16 and the collector metal 17 form a Schottky diode.

Further, an isolation trench 19 is further disposed between the P-type collector region 18 and the N-type ohmic contact region 13, and the isolation trench may be filled with silicon dioxide or filled with polysilicon.

Furthermore, the gate region is a planar gate region, is positioned on the P-type semiconductor base region 4 and covers a part of the heavily doped N-type semiconductor region 7 and a part of the surface voltage-resisting region 3; the planar gate region is composed of a gate dielectric layer 11, an N-type polycrystalline silicon gate region 10 and a gate metal 9 which are sequentially arranged from bottom to top.

Obviously, on the basis of the present invention, the RC-L IGBT formed by the planar gate structure used in the first active region of the present invention can be replaced by the common trench gate structure, and the same effect will be obtained.

The invention has the beneficial effects that:

the invention provides an RC-L IGBT for eliminating voltage folding effect and reducing turn-off loss, which is characterized in that an N-type ohmic contact area, a floating electrode and a P-type Schottky diode are introduced at one side of a collector, a carrier flow path consisting of two diodes connected in series is formed in a reverse working state, so that the device has reverse conduction capability, meanwhile, the Schottky diode has a one-way rectification characteristic, when the device works in a forward state, the P-type Schottky diode cannot be started, so that a voltage folding phenomenon introduced by the traditional RC-L IGBT is eliminated, the newly introduced structure realizes reverse conduction and eliminates the voltage folding phenomenon, and simultaneously, the length of the device is shortened, so that the performance of the device is greatly improved.

Drawings

Fig. 1 is a schematic structural diagram of an RC-L IGBT device with a built-in schottky diode according to embodiment 1 of the present invention;

fig. 2 is a schematic structural diagram of an RC-L IGBT device with a built-in schottky diode according to embodiment 2 of the present invention;

fig. 3 is a schematic structural diagram of an RC-L IGBT device with a built-in schottky diode according to embodiment 3 of the present invention;

in the figure, 1 is a P-type substrate, 2 is a buried oxide layer region, 3 is a surface voltage-resistant region, 4 is a P-type semiconductor base region, 5 is a P-type buried layer region, 6 is a heavily doped P-type semiconductor region, 7 is a heavily doped N-type semiconductor region, 8 is emitter metal, 9 is gate metal, 10 is an N-type polysilicon gate region, 11 is a gate oxide layer, 12 is an N-type semiconductor buffer layer, 13 is an N-type ohmic contact region, 14 is a P-type ohmic contact region, 15 is a floating electrode, 16 is a P-type region, 17 is collector metal, 18 is a P-type collector region, 19 is an isolation groove, and 20 is field oxide.

FIG. 4 is a graph comparing I-V relationships obtained from simulation of example 1 of the present invention and conventional RC-L IGBT.

Fig. 5 is a comparison graph of reverse recovery relationship obtained by simulation of the embodiment 1 of the present invention and the conventional RC-L IGBT.

FIG. 6 shows V simulated by example 1 of the present invention and a conventional RC-L IGBT_on-E_offThe relationship is compared to the graph.

Fig. 7 is a structural schematic diagram of a conventional RC-L IGBT device.

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings.